module IntXbar( // @[:freechips.rocketchip.system.TinyConfig.fir@3.2] input auto_int_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@6.4] input auto_int_in_1, // @[:freechips.rocketchip.system.TinyConfig.fir@6.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@6.4] output auto_int_out_1 // @[:freechips.rocketchip.system.TinyConfig.fir@6.4] ); assign auto_int_out_0 = auto_int_in_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@15.4] assign auto_int_out_1 = auto_int_in_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@15.4] endmodule module TLMonitor( // @[:freechips.rocketchip.system.TinyConfig.fir@28.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@29.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@30.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@31.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@1491.4] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47.6] wire _T_8; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@52.6] wire [26:0] _T_10; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@54.6] wire [11:0] _T_11; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@55.6] wire [11:0] _T_12; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@56.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57.6] wire [31:0] _T_13; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57.6] wire _T_14; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@58.6] wire _T_16; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@60.6] wire [1:0] _T_17; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@61.6] wire [1:0] _T_19; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@63.6] wire _T_20; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@64.6] wire _T_21; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65.6] wire _T_22; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66.6] wire _T_23; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@67.6] wire _T_25; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@69.6] wire _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@70.6] wire _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@72.6] wire _T_29; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@73.6] wire _T_30; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@74.6] wire _T_31; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@75.6] wire _T_32; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@76.6] wire _T_33; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@77.6] wire _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@78.6] wire _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@79.6] wire _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@80.6] wire _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@81.6] wire _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@82.6] wire _T_39; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@83.6] wire _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@84.6] wire _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@85.6] wire _T_42; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@86.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@87.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@88.6] wire [3:0] _T_47; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@91.6] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@95.6] wire _T_68; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@116.6] wire [31:0] _T_70; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@119.8] wire [32:0] _T_71; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@120.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@121.8] wire [32:0] _T_73; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@122.8] wire _T_74; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@123.8] wire [31:0] _T_75; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@124.8] wire [32:0] _T_76; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@125.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126.8] wire [32:0] _T_78; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@127.8] wire _T_79; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128.8] wire [31:0] _T_80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@129.8] wire [32:0] _T_81; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@130.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@131.8] wire [32:0] _T_83; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@132.8] wire _T_84; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@133.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@136.8] wire [32:0] _T_88; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@137.8] wire _T_89; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@138.8] wire [31:0] _T_90; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@139.8] wire [32:0] _T_91; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@140.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@141.8] wire [32:0] _T_93; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@142.8] wire _T_94; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@143.8] wire [31:0] _T_95; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@144.8] wire [32:0] _T_96; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@145.8] wire [32:0] _T_97; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@146.8] wire [32:0] _T_98; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@147.8] wire _T_99; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@148.8] wire [31:0] _T_100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@149.8] wire [32:0] _T_101; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@150.8] wire [32:0] _T_102; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@151.8] wire [32:0] _T_103; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@152.8] wire _T_104; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@153.8] wire _T_105; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@154.8] wire _T_106; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@155.8] wire _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@156.8] wire _T_108; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@157.8] wire _T_115; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@164.8] wire _T_120; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@177.8] wire _T_121; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@178.8] wire _T_124; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@185.8] wire _T_125; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@186.8] wire _T_127; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@192.8] wire _T_128; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@193.8] wire _T_129; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@198.8] wire _T_131; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@200.8] wire _T_132; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@201.8] wire [3:0] _T_133; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@206.8] wire _T_134; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@207.8] wire _T_136; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@209.8] wire _T_137; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@210.8] wire _T_138; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@215.8] wire _T_140; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@217.8] wire _T_141; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@218.8] wire _T_142; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@224.6] wire _T_207; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@314.8] wire _T_209; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@316.8] wire _T_210; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@317.8] wire _T_220; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@340.6] wire _T_222; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@343.8] wire _T_230; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@351.8] wire _T_232; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@353.8] wire _T_265; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@386.8] wire _T_266; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@387.8] wire _T_267; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@388.8] wire _T_268; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@389.8] wire _T_269; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@390.8] wire _T_270; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@391.8] wire _T_272; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@393.8] wire _T_274; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@395.8] wire _T_275; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@396.8] wire _T_282; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@415.8] wire _T_284; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@417.8] wire _T_285; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@418.8] wire _T_286; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@423.8] wire _T_288; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@425.8] wire _T_289; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@426.8] wire _T_294; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@440.6] wire _T_332; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@479.8] wire _T_341; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@488.8] wire _T_349; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@496.8] wire _T_351; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@498.8] wire _T_353; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@500.8] wire _T_355; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@502.8] wire _T_356; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@503.8] wire _T_371; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@539.6] wire [3:0] _T_444; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@629.8] wire [3:0] _T_445; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@630.8] wire _T_446; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@631.8] wire _T_448; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@633.8] wire _T_449; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@634.8] wire _T_450; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@640.6] wire _T_452; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@643.8] wire _T_484; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@675.8] wire _T_501; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@692.8] wire _T_502; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@693.8] wire _T_509; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@712.8] wire _T_511; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@714.8] wire _T_512; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@715.8] wire _T_517; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@729.6] wire _T_576; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@801.8] wire _T_578; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@803.8] wire _T_579; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@804.8] wire _T_584; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@818.6] wire _T_635; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@870.8] wire _T_636; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@871.8] wire _T_651; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@909.6] wire _T_653; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@911.6] wire _T_654; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@912.6] wire _T_656; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@918.6] wire _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@923.6] wire _T_660; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@925.6] wire _T_662; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@928.8] wire _T_663; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@929.8] wire _T_664; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@934.8] wire _T_666; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@936.8] wire _T_667; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@937.8] wire _T_668; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@942.8] wire _T_670; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@944.8] wire _T_671; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@945.8] wire _T_672; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@950.8] wire _T_674; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@952.8] wire _T_675; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@953.8] wire _T_676; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@958.8] wire _T_678; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@960.8] wire _T_679; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@961.8] wire _T_680; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@967.6] wire _T_691; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@991.8] wire _T_693; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@993.8] wire _T_694; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@994.8] wire _T_695; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@999.8] wire _T_697; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1001.8] wire _T_698; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1002.8] wire _T_708; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@1025.6] wire _T_728; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@1066.8] wire _T_730; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1068.8] wire _T_731; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1069.8] wire _T_737; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@1084.6] wire _T_754; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@1119.6] wire _T_772; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@1155.6] wire _T_801; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@1215.4] wire [9:0] _T_806; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@1220.4] wire _T_807; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@1221.4] wire _T_808; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@1222.4] reg [9:0] _T_810; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@1224.4] reg [31:0] _RAND_0; wire [9:0] _T_812; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1226.4] wire _T_813; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1227.4] reg [2:0] _T_821; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@1238.4] reg [31:0] _RAND_1; reg [2:0] _T_822; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@1239.4] reg [31:0] _RAND_2; reg [3:0] _T_823; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@1240.4] reg [31:0] _RAND_3; reg _T_824; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@1241.4] reg [31:0] _RAND_4; reg [31:0] _T_825; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@1242.4] reg [31:0] _RAND_5; wire _T_826; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@1243.4] wire _T_827; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@1244.4] wire _T_828; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@1246.6] wire _T_830; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1248.6] wire _T_831; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1249.6] wire _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@1254.6] wire _T_834; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1256.6] wire _T_835; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1257.6] wire _T_836; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@1262.6] wire _T_838; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1264.6] wire _T_839; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1265.6] wire _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@1270.6] wire _T_842; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1272.6] wire _T_843; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1273.6] wire _T_844; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@1278.6] wire _T_846; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1280.6] wire _T_847; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1281.6] wire _T_849; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@1288.4] wire _T_850; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@1296.4] wire [26:0] _T_852; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@1298.4] wire [11:0] _T_853; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@1299.4] wire [11:0] _T_854; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@1300.4] wire [9:0] _T_855; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@1301.4] wire _T_856; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@1302.4] reg [9:0] _T_858; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@1304.4] reg [31:0] _RAND_6; wire [9:0] _T_860; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1306.4] wire _T_861; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1307.4] reg [2:0] _T_869; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@1318.4] reg [31:0] _RAND_7; reg [1:0] _T_870; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@1319.4] reg [31:0] _RAND_8; reg [3:0] _T_871; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@1320.4] reg [31:0] _RAND_9; reg _T_872; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@1321.4] reg [31:0] _RAND_10; reg _T_873; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@1322.4] reg [31:0] _RAND_11; reg _T_874; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@1323.4] reg [31:0] _RAND_12; wire _T_875; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@1324.4] wire _T_876; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@1325.4] wire _T_877; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@1327.6] wire _T_879; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1329.6] wire _T_880; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1330.6] wire _T_881; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@1335.6] wire _T_883; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1337.6] wire _T_884; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1338.6] wire _T_885; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@1343.6] wire _T_887; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1345.6] wire _T_888; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1346.6] wire _T_889; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@1351.6] wire _T_891; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1353.6] wire _T_892; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1354.6] wire _T_893; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@1359.6] wire _T_895; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1361.6] wire _T_896; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1362.6] wire _T_897; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@1367.6] wire _T_899; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1369.6] wire _T_900; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1370.6] wire _T_902; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@1377.4] reg [1:0] _T_903; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@1386.4] reg [31:0] _RAND_13; reg [9:0] _T_913; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@1396.4] reg [31:0] _RAND_14; wire [9:0] _T_915; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1398.4] wire _T_916; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1399.4] reg [9:0] _T_932; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@1418.4] reg [31:0] _RAND_15; wire [9:0] _T_934; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1420.4] wire _T_935; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1421.4] wire _T_945; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@1436.4] wire [1:0] _T_947; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@1439.6] wire [1:0] _T_948; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@1441.6] wire _T_949; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@1442.6] wire _T_950; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@1443.6] wire _T_952; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1445.6] wire _T_953; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1446.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@1438.4] wire _T_957; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@1457.4] wire _T_959; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@1459.4] wire _T_960; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@1460.4] wire [1:0] _T_961; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@1462.6] wire [1:0] _T_962; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@1464.6] wire [1:0] _T_963; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@1465.6] wire _T_964; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@1466.6] wire _T_966; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1468.6] wire _T_967; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1469.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@1461.4] wire _T_968; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@1475.4] wire _T_969; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@1476.4] wire _T_970; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@1477.4] wire _T_971; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@1478.4] wire _T_973; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1480.4] wire _T_974; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1481.4] wire [1:0] _T_975; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@1486.4] wire [1:0] _T_976; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@1487.4] wire [1:0] _T_977; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@1488.4] reg [31:0] _T_978; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@1490.4] reg [31:0] _RAND_16; wire _T_979; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@1493.4] wire _T_980; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@1494.4] wire _T_981; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@1495.4] wire _T_982; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@1496.4] wire _T_983; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@1497.4] wire _T_984; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@1498.4] wire _T_986; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1500.4] wire _T_987; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1501.4] wire [31:0] _T_989; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@1507.4] wire _T_992; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@1511.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@166.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@274.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@398.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@505.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@604.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@695.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@784.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@873.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@931.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@973.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@1031.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@1090.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@1125.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@1161.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@1491.4] .out(plusarg_reader_out) ); assign _T_6 = io_in_a_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47.6] assign _T_8 = io_in_a_bits_source | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@52.6] assign _T_10 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@54.6] assign _T_11 = _T_10[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@55.6] assign _T_12 = ~ _T_11; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@56.6] assign _GEN_18 = {{20'd0}, _T_12}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57.6] assign _T_13 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57.6] assign _T_14 = _T_13 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@58.6] assign _T_16 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@60.6] assign _T_17 = 2'h1 << _T_16; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@61.6] assign _T_19 = _T_17 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@63.6] assign _T_20 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@64.6] assign _T_21 = _T_19[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65.6] assign _T_22 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66.6] assign _T_23 = _T_22 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@67.6] assign _T_25 = _T_21 & _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@69.6] assign _T_26 = _T_20 | _T_25; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@70.6] assign _T_28 = _T_21 & _T_22; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@72.6] assign _T_29 = _T_20 | _T_28; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@73.6] assign _T_30 = _T_19[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@74.6] assign _T_31 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@75.6] assign _T_32 = _T_31 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@76.6] assign _T_33 = _T_23 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@77.6] assign _T_34 = _T_30 & _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@78.6] assign _T_35 = _T_26 | _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@79.6] assign _T_36 = _T_23 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@80.6] assign _T_37 = _T_30 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@81.6] assign _T_38 = _T_26 | _T_37; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@82.6] assign _T_39 = _T_22 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@83.6] assign _T_40 = _T_30 & _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@84.6] assign _T_41 = _T_29 | _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@85.6] assign _T_42 = _T_22 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@86.6] assign _T_43 = _T_30 & _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@87.6] assign _T_44 = _T_29 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@88.6] assign _T_47 = {_T_44,_T_41,_T_38,_T_35}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@91.6] assign _T_51 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@95.6] assign _T_68 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@116.6] assign _T_70 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@119.8] assign _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@120.8] assign _T_72 = $signed(_T_71) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@121.8] assign _T_73 = $signed(_T_72); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@122.8] assign _T_74 = $signed(_T_73) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@123.8] assign _T_75 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@124.8] assign _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@125.8] assign _T_77 = $signed(_T_76) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126.8] assign _T_78 = $signed(_T_77); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@127.8] assign _T_79 = $signed(_T_78) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128.8] assign _T_80 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@129.8] assign _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@130.8] assign _T_82 = $signed(_T_81) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@131.8] assign _T_83 = $signed(_T_82); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@132.8] assign _T_84 = $signed(_T_83) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@133.8] assign _T_87 = $signed(_T_51) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@136.8] assign _T_88 = $signed(_T_87); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@137.8] assign _T_89 = $signed(_T_88) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@138.8] assign _T_90 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@139.8] assign _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@140.8] assign _T_92 = $signed(_T_91) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@141.8] assign _T_93 = $signed(_T_92); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@142.8] assign _T_94 = $signed(_T_93) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@143.8] assign _T_95 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@144.8] assign _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@145.8] assign _T_97 = $signed(_T_96) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@146.8] assign _T_98 = $signed(_T_97); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@147.8] assign _T_99 = $signed(_T_98) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@148.8] assign _T_100 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@149.8] assign _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@150.8] assign _T_102 = $signed(_T_101) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@151.8] assign _T_103 = $signed(_T_102); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@152.8] assign _T_104 = $signed(_T_103) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@153.8] assign _T_105 = _T_74 | _T_79; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@154.8] assign _T_106 = _T_105 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@155.8] assign _T_107 = _T_106 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@156.8] assign _T_108 = _T_107 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@157.8] assign _T_115 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@164.8] assign _T_120 = _T_8 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@177.8] assign _T_121 = _T_120 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@178.8] assign _T_124 = _T_20 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@185.8] assign _T_125 = _T_124 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@186.8] assign _T_127 = _T_14 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@192.8] assign _T_128 = _T_127 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@193.8] assign _T_129 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@198.8] assign _T_131 = _T_129 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@200.8] assign _T_132 = _T_131 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@201.8] assign _T_133 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@206.8] assign _T_134 = _T_133 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@207.8] assign _T_136 = _T_134 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@209.8] assign _T_137 = _T_136 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@210.8] assign _T_138 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@215.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@217.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@218.8] assign _T_142 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@224.6] assign _T_207 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@314.8] assign _T_209 = _T_207 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@316.8] assign _T_210 = _T_209 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@317.8] assign _T_220 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@340.6] assign _T_222 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@343.8] assign _T_230 = _T_222 & _T_74; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@351.8] assign _T_232 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@353.8] assign _T_265 = _T_79 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@386.8] assign _T_266 = _T_265 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@387.8] assign _T_267 = _T_266 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@388.8] assign _T_268 = _T_267 | _T_99; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@389.8] assign _T_269 = _T_268 | _T_104; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@390.8] assign _T_270 = _T_232 & _T_269; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@391.8] assign _T_272 = _T_230 | _T_270; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@393.8] assign _T_274 = _T_272 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@395.8] assign _T_275 = _T_274 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@396.8] assign _T_282 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@415.8] assign _T_284 = _T_282 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@417.8] assign _T_285 = _T_284 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@418.8] assign _T_286 = io_in_a_bits_mask == _T_47; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@423.8] assign _T_288 = _T_286 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@425.8] assign _T_289 = _T_288 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@426.8] assign _T_294 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@440.6] assign _T_332 = _T_232 & _T_267; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@479.8] assign _T_341 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@488.8] assign _T_349 = _T_341 & _T_104; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@496.8] assign _T_351 = _T_230 | _T_332; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@498.8] assign _T_353 = _T_351 | _T_349; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@500.8] assign _T_355 = _T_353 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@502.8] assign _T_356 = _T_355 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@503.8] assign _T_371 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@539.6] assign _T_444 = ~ _T_47; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@629.8] assign _T_445 = io_in_a_bits_mask & _T_444; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@630.8] assign _T_446 = _T_445 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@631.8] assign _T_448 = _T_446 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@633.8] assign _T_449 = _T_448 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@634.8] assign _T_450 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@640.6] assign _T_452 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@643.8] assign _T_484 = _T_452 & _T_108; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@675.8] assign _T_501 = _T_484 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@692.8] assign _T_502 = _T_501 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@693.8] assign _T_509 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@712.8] assign _T_511 = _T_509 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@714.8] assign _T_512 = _T_511 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@715.8] assign _T_517 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@729.6] assign _T_576 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@801.8] assign _T_578 = _T_576 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@803.8] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@804.8] assign _T_584 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@818.6] assign _T_635 = _T_230 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@870.8] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@871.8] assign _T_651 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@909.6] assign _T_653 = _T_651 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@911.6] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@912.6] assign _T_656 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@918.6] assign _T_658 = io_in_d_bits_source | _T_656; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@923.6] assign _T_660 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@925.6] assign _T_662 = _T_658 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@928.8] assign _T_663 = _T_662 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@929.8] assign _T_664 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@934.8] assign _T_666 = _T_664 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@936.8] assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@937.8] assign _T_668 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@942.8] assign _T_670 = _T_668 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@944.8] assign _T_671 = _T_670 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@945.8] assign _T_672 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@950.8] assign _T_674 = _T_672 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@952.8] assign _T_675 = _T_674 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@953.8] assign _T_676 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@958.8] assign _T_678 = _T_676 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@960.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@961.8] assign _T_680 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@967.6] assign _T_691 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@991.8] assign _T_693 = _T_691 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@993.8] assign _T_694 = _T_693 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@994.8] assign _T_695 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@999.8] assign _T_697 = _T_695 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1001.8] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1002.8] assign _T_708 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@1025.6] assign _T_728 = _T_676 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@1066.8] assign _T_730 = _T_728 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1068.8] assign _T_731 = _T_730 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1069.8] assign _T_737 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@1084.6] assign _T_754 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@1119.6] assign _T_772 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@1155.6] assign _T_801 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@1215.4] assign _T_806 = _T_12[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@1220.4] assign _T_807 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@1221.4] assign _T_808 = _T_807 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@1222.4] assign _T_812 = _T_810 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1226.4] assign _T_813 = _T_810 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1227.4] assign _T_826 = _T_813 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@1243.4] assign _T_827 = io_in_a_valid & _T_826; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@1244.4] assign _T_828 = io_in_a_bits_opcode == _T_821; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@1246.6] assign _T_830 = _T_828 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1248.6] assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1249.6] assign _T_832 = io_in_a_bits_param == _T_822; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@1254.6] assign _T_834 = _T_832 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1256.6] assign _T_835 = _T_834 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1257.6] assign _T_836 = io_in_a_bits_size == _T_823; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@1262.6] assign _T_838 = _T_836 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1264.6] assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1265.6] assign _T_840 = io_in_a_bits_source == _T_824; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@1270.6] assign _T_842 = _T_840 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1272.6] assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1273.6] assign _T_844 = io_in_a_bits_address == _T_825; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@1278.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1280.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1281.6] assign _T_849 = _T_801 & _T_813; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@1288.4] assign _T_850 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@1296.4] assign _T_852 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@1298.4] assign _T_853 = _T_852[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@1299.4] assign _T_854 = ~ _T_853; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@1300.4] assign _T_855 = _T_854[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@1301.4] assign _T_856 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@1302.4] assign _T_860 = _T_858 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1306.4] assign _T_861 = _T_858 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1307.4] assign _T_875 = _T_861 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@1324.4] assign _T_876 = io_in_d_valid & _T_875; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@1325.4] assign _T_877 = io_in_d_bits_opcode == _T_869; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@1327.6] assign _T_879 = _T_877 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1329.6] assign _T_880 = _T_879 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1330.6] assign _T_881 = io_in_d_bits_param == _T_870; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@1335.6] assign _T_883 = _T_881 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1337.6] assign _T_884 = _T_883 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1338.6] assign _T_885 = io_in_d_bits_size == _T_871; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@1343.6] assign _T_887 = _T_885 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1345.6] assign _T_888 = _T_887 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1346.6] assign _T_889 = io_in_d_bits_source == _T_872; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@1351.6] assign _T_891 = _T_889 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1353.6] assign _T_892 = _T_891 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1354.6] assign _T_893 = io_in_d_bits_sink == _T_873; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@1359.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1361.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1362.6] assign _T_897 = io_in_d_bits_denied == _T_874; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@1367.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1369.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1370.6] assign _T_902 = _T_850 & _T_861; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@1377.4] assign _T_915 = _T_913 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1398.4] assign _T_916 = _T_913 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1399.4] assign _T_934 = _T_932 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@1420.4] assign _T_935 = _T_932 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@1421.4] assign _T_945 = _T_801 & _T_916; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@1436.4] assign _T_947 = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@1439.6] assign _T_948 = _T_903 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@1441.6] assign _T_949 = _T_948[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@1442.6] assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@1443.6] assign _T_952 = _T_950 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1445.6] assign _T_953 = _T_952 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1446.6] assign _GEN_15 = _T_945 ? _T_947 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@1438.4] assign _T_957 = _T_850 & _T_935; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@1457.4] assign _T_959 = _T_660 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@1459.4] assign _T_960 = _T_957 & _T_959; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@1460.4] assign _T_961 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@1462.6] assign _T_962 = _GEN_15 | _T_903; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@1464.6] assign _T_963 = _T_962 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@1465.6] assign _T_964 = _T_963[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@1466.6] assign _T_966 = _T_964 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1468.6] assign _T_967 = _T_966 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1469.6] assign _GEN_16 = _T_960 ? _T_961 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@1461.4] assign _T_968 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@1475.4] assign _T_969 = _GEN_15 != 2'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@1476.4] assign _T_970 = _T_969 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@1477.4] assign _T_971 = _T_968 | _T_970; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@1478.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1480.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1481.4] assign _T_975 = _T_903 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@1486.4] assign _T_976 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@1487.4] assign _T_977 = _T_975 & _T_976; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@1488.4] assign _T_979 = _T_903 != 2'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@1493.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@1494.4] assign _T_981 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@1495.4] assign _T_982 = _T_980 | _T_981; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@1496.4] assign _T_983 = _T_978 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@1497.4] assign _T_984 = _T_982 | _T_983; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@1498.4] assign _T_986 = _T_984 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1500.4] assign _T_987 = _T_986 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1501.4] assign _T_989 = _T_978 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@1507.4] assign _T_992 = _T_801 | _T_850; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@1511.4] assign _GEN_19 = io_in_a_valid & _T_68; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@166.10] assign _GEN_35 = io_in_a_valid & _T_142; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@274.10] assign _GEN_53 = io_in_a_valid & _T_220; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@398.10] assign _GEN_65 = io_in_a_valid & _T_294; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@505.10] assign _GEN_75 = io_in_a_valid & _T_371; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@604.10] assign _GEN_85 = io_in_a_valid & _T_450; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@695.10] assign _GEN_95 = io_in_a_valid & _T_517; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@784.10] assign _GEN_105 = io_in_a_valid & _T_584; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@873.10] assign _GEN_115 = io_in_d_valid & _T_660; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@931.10] assign _GEN_125 = io_in_d_valid & _T_680; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@973.10] assign _GEN_137 = io_in_d_valid & _T_708; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@1031.10] assign _GEN_149 = io_in_d_valid & _T_737; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@1090.10] assign _GEN_155 = io_in_d_valid & _T_754; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@1125.10] assign _GEN_161 = io_in_d_valid & _T_772; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@1161.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_810 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_821 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_822 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_823 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_824 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_825 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_858 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_869 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_870 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_871 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_872 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_873 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_874 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_903 = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_913 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_932 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_978 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_810 <= 10'h0; end else begin if (_T_801) begin if (_T_813) begin if (_T_808) begin _T_810 <= _T_806; end else begin _T_810 <= 10'h0; end end else begin _T_810 <= _T_812; end end end if (_T_849) begin _T_821 <= io_in_a_bits_opcode; end if (_T_849) begin _T_822 <= io_in_a_bits_param; end if (_T_849) begin _T_823 <= io_in_a_bits_size; end if (_T_849) begin _T_824 <= io_in_a_bits_source; end if (_T_849) begin _T_825 <= io_in_a_bits_address; end if (reset) begin _T_858 <= 10'h0; end else begin if (_T_850) begin if (_T_861) begin if (_T_856) begin _T_858 <= _T_855; end else begin _T_858 <= 10'h0; end end else begin _T_858 <= _T_860; end end end if (_T_902) begin _T_869 <= io_in_d_bits_opcode; end if (_T_902) begin _T_870 <= io_in_d_bits_param; end if (_T_902) begin _T_871 <= io_in_d_bits_size; end if (_T_902) begin _T_872 <= io_in_d_bits_source; end if (_T_902) begin _T_873 <= io_in_d_bits_sink; end if (_T_902) begin _T_874 <= io_in_d_bits_denied; end if (reset) begin _T_903 <= 2'h0; end else begin _T_903 <= _T_977; end if (reset) begin _T_913 <= 10'h0; end else begin if (_T_801) begin if (_T_916) begin if (_T_808) begin _T_913 <= _T_806; end else begin _T_913 <= 10'h0; end end else begin _T_913 <= _T_915; end end end if (reset) begin _T_932 <= 10'h0; end else begin if (_T_850) begin if (_T_935) begin if (_T_856) begin _T_932 <= _T_855; end else begin _T_932 <= 10'h0; end end else begin _T_932 <= _T_934; end end end if (reset) begin _T_978 <= 32'h0; end else begin if (_T_992) begin _T_978 <= 32'h0; end else begin _T_978 <= _T_989; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:37:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@173.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@174.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@180.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_121) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@181.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:37:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@188.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_125) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@189.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@195.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_128) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@196.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:37:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_132) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@212.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_137) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@213.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@220.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_141) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@221.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@274.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@275.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:37:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@281.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@282.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@288.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_121) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@289.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:37:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@296.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_125) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@297.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@303.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_128) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@304.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:37:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@311.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_132) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@312.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_210) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:37:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@319.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_210) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@320.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@328.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_137) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@329.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@336.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@337.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_275) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@398.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_275) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@399.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@405.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_121) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@406.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@412.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_128) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@413.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@420.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_285) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@421.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@428.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_289) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@429.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@436.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_141) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@437.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@505.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_356) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@506.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@512.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_121) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@513.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@519.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_128) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@520.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@527.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_285) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@528.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@535.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_289) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@536.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@604.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_356) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@605.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@611.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_121) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@612.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@618.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_128) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@619.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@626.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_285) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@627.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_449) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@636.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_449) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@637.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@695.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_502) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@696.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@702.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_121) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@703.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@709.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_128) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@710.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_512) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:37:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@717.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_512) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@718.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@725.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_289) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@726.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@784.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_502) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@785.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@791.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_121) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@792.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_128) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:37:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@806.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_579) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@807.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@814.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_289) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@815.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:37:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@873.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_636) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@874.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@880.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_121) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@881.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:37:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@887.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_128) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@888.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:37:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@895.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_289) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@896.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@903.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_141) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@904.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:37:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@914.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_654) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@915.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@931.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_663) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@932.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:37:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@939.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_667) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@940.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@947.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_671) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@948.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@955.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_675) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@956.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:37:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@963.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@964.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@973.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_663) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@974.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@980.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_115) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@981.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:37:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@988.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_667) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@989.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:37:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@996.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_694) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@997.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:37:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1004.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_698) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@1005.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@1012.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_675) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@1013.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@1031.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_663) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@1032.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@1038.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_115) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@1039.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:37:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@1046.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_667) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@1047.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:37:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@1054.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_694) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@1055.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:37:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@1062.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_698) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@1063.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1071.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_731) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@1072.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@1090.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_663) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@1091.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@1098.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_671) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@1099.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@1106.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_675) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@1107.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@1125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_663) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@1126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@1133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_671) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@1134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@1142.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_731) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@1143.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@1161.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_663) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@1162.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:37:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@1169.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_671) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@1170.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:37:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@1177.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_675) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@1178.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_831) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1251.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_831) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@1252.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_835) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1259.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_835) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@1260.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_839) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1267.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_839) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@1268.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_843) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1275.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_843) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@1276.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1283.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_847) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@1284.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_880) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1332.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_880) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@1333.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_884) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1340.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_884) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@1341.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_888) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1348.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_888) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@1349.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_892) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1356.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_892) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@1357.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1364.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_896) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@1365.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:37:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1372.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_900) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@1373.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_945 & _T_953) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:37:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1448.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_945 & _T_953) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@1449.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_960 & _T_967) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:37:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1471.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_960 & _T_967) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@1472.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:37:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1483.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@1484.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:37:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1503.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@1504.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_1( // @[:freechips.rocketchip.system.TinyConfig.fir@1524.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@1525.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@1526.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@1527.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@3029.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@1544.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@1545.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@1562.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@1564.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@1565.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@1566.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@1567.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@1567.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@1568.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@1570.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@1571.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@1573.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@1574.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@1575.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@1576.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@1577.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1579.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1580.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1582.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1583.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@1584.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@1585.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@1586.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1587.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1588.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1589.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1590.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1591.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1592.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1593.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1594.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1595.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1596.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1597.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1598.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@1601.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1612.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@1640.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1643.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1644.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1645.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1646.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1647.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1648.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1649.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1650.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1651.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1652.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1653.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1654.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1655.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1656.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1657.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1660.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1661.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1662.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1663.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1664.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1665.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1666.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1667.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1668.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1669.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1670.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1671.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1672.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1673.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1674.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1675.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1676.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1677.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1678.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1679.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1680.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1681.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1688.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1701.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1702.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1709.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1710.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1716.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1717.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@1722.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1724.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1725.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@1730.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@1731.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1733.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1734.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@1739.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1741.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1742.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@1748.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@1838.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1840.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1841.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@1864.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@1867.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@1875.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@1877.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1910.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1911.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1912.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1913.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1914.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@1915.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@1917.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1919.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1920.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@1939.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1941.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1942.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@1947.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1949.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1950.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@1964.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2003.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@2012.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2020.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@2022.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@2024.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2026.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2027.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@2063.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@2153.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@2154.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@2155.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2157.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2158.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@2164.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@2167.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2199.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2216.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2217.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@2236.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2238.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2239.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@2253.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@2325.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2327.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2328.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@2342.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2394.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2395.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@2433.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2435.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2436.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@2443.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@2444.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@2461.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@2463.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2466.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2467.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@2472.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2474.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2475.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@2480.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2482.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2483.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@2488.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2490.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2491.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@2496.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2498.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2499.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@2505.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@2529.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2531.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2532.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@2537.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2539.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2540.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@2563.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@2604.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2606.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2607.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@2622.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@2657.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@2693.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@2753.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@2758.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@2759.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@2760.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@2762.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2764.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2765.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@2776.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@2777.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@2778.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@2779.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@2780.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@2781.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@2782.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@2784.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2786.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2787.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@2792.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2794.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2795.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@2800.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2802.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2803.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@2808.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2810.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2811.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@2816.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2818.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2819.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@2826.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@2834.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@2836.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@2837.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@2838.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@2839.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@2840.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@2842.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2844.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2845.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@2856.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@2857.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@2858.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@2859.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@2860.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@2861.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@2862.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@2863.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@2865.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2867.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2868.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@2873.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2875.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2876.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@2881.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2883.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2884.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@2889.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2891.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2892.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@2897.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2899.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2900.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@2905.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2907.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2908.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@2915.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@2924.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@2934.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2936.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2937.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@2956.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2958.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2959.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@2974.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@2977.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@2979.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@2980.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@2981.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2983.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2984.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@2976.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@2995.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@2997.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@2998.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@3000.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@3002.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@3003.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@3004.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3006.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3007.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@2999.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@3013.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@3014.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@3015.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@3016.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3018.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3019.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@3024.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@3025.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@3026.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@3028.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@3031.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@3032.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@3033.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@3034.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@3035.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@3036.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3038.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3039.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@3045.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@3049.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1690.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@1798.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1922.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2029.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@2128.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2219.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@2308.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2397.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2469.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@2511.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@2569.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@2628.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@2663.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@2699.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@3029.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@1544.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@1545.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@1562.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@1564.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@1565.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@1566.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@1567.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@1567.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@1568.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@1570.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@1571.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@1573.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@1574.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@1575.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@1576.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@1577.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1579.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1580.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1582.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1583.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@1584.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@1585.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@1586.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1587.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1588.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1589.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1590.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1591.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1592.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1593.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1594.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1595.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@1596.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@1597.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@1598.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@1601.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1612.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@1640.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1643.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1644.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1645.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1646.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1647.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1648.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1649.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1650.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1651.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1652.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1653.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1654.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1655.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1656.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1657.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1660.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1661.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1662.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1663.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1664.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1665.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1666.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1667.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1668.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1669.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1670.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1671.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1672.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@1673.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@1674.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1675.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@1676.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@1677.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1678.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1679.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1680.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1681.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1688.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1701.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1702.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1709.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1710.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1716.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1717.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@1722.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1724.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1725.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@1730.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@1731.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1733.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1734.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@1739.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1741.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1742.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@1748.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@1838.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1840.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1841.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@1864.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@1867.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@1875.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@1877.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1910.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1911.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1912.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1913.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@1914.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@1915.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@1917.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1919.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1920.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@1939.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1941.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1942.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@1947.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1949.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1950.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@1964.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2003.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@2012.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2020.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@2022.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@2024.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2026.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2027.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@2063.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@2153.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@2154.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@2155.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2157.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2158.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@2164.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@2167.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@2199.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2216.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2217.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@2236.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2238.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2239.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@2253.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@2325.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2327.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2328.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@2342.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2394.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2395.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@2433.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2435.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2436.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@2443.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@2444.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@2461.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@2463.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2466.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2467.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@2472.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2474.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2475.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@2480.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2482.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2483.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@2488.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2490.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2491.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@2496.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2498.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2499.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@2505.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@2529.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2531.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2532.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@2537.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2539.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2540.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@2563.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@2604.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2606.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2607.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@2622.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@2657.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@2693.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@2753.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@2758.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@2759.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@2760.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2764.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2765.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@2781.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@2782.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@2784.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2786.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2787.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@2792.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2794.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2795.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@2800.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2802.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2803.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@2808.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2810.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2811.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@2816.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2818.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2819.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@2826.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@2834.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@2836.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@2837.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@2838.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@2839.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@2840.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2844.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2845.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@2862.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@2863.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@2865.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2867.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2868.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@2873.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2875.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2876.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@2881.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2883.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2884.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@2889.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2891.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2892.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@2897.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2899.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2900.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@2905.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2907.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2908.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@2915.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2936.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2937.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@2958.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@2959.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@2974.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@2977.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@2979.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@2980.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@2981.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2983.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2984.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@2976.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@2995.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@2997.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@2998.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@3000.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@3002.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@3003.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@3004.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3006.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3007.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@2999.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@3013.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@3014.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@3015.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@3016.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3018.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3019.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@3024.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@3025.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@3026.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@3031.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@3032.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@3033.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@3034.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@3035.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@3036.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3038.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3039.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@3045.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@3049.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1690.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@1798.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1922.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2029.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@2128.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2219.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@2308.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2397.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2469.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@2511.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@2569.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@2628.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@2663.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@2699.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1690.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@1691.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:62:9)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@1697.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@1698.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1704.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@1705.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1712.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@1713.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1719.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@1720.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1727.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@1728.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@1737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@1745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@1798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@1799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:62:9)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@1805.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@1806.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@1812.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@1813.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@1820.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@1821.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@1827.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@1828.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@1835.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@1836.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:62:9)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1843.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@1844.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@1852.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@1853.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@1860.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@1861.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1922.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@1923.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@1929.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@1930.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@1936.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@1937.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1944.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@1945.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@1953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@1960.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@1961.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@2030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@2036.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@2037.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@2043.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@2044.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@2051.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@2052.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@2059.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@2060.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@2128.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@2129.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@2135.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@2136.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@2142.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@2143.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@2150.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@2151.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2160.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@2161.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2219.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@2220.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@2226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@2227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@2233.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@2234.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2241.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@2242.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@2249.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@2250.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@2308.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@2309.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@2315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@2316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@2322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@2323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2330.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@2331.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@2338.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@2339.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2397.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@2398.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@2404.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@2405.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@2411.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@2412.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@2419.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@2420.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@2427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@2428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:62:9)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2438.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@2439.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@2470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2477.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@2478.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2485.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@2486.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@2494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2501.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@2502.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@2511.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@2512.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@2518.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@2519.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@2526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@2527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2534.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@2535.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2542.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@2543.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@2550.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@2551.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@2569.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@2570.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@2576.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@2577.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@2584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@2585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@2592.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@2593.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@2600.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@2601.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2609.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@2610.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@2628.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@2629.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@2636.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@2637.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@2644.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@2645.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@2663.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@2664.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@2671.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@2672.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@2680.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@2681.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@2699.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@2700.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@2707.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@2708.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@2715.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@2716.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2789.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@2790.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2797.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@2798.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2805.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@2806.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2813.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@2814.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2821.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@2822.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2870.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@2871.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2878.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@2879.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2886.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@2887.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2894.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@2895.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2902.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@2903.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2910.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@2911.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2986.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@2987.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:62:9)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3009.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@3010.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:62:9)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3021.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@3022.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:62:9)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3041.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@3042.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar( // @[:freechips.rocketchip.system.TinyConfig.fir@3054.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@3055.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@3056.4] output auto_in_1_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_1_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_in_1_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_in_1_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_in_1_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_in_1_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_in_1_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_in_1_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_in_1_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_1_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_1_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_1_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_in_1_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [1:0] auto_in_1_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_in_1_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_in_1_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_1_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_1_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [31:0] auto_in_1_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_1_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_0_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_in_0_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_in_0_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_in_0_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_0_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_in_0_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_in_0_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_in_0_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_0_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_in_0_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_in_0_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [1:0] auto_in_0_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_in_0_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [31:0] auto_in_0_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_in_0_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_1_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_1_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_out_1_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_out_1_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [4:0] auto_out_1_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [30:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [31:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_1_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_1_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_1_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_out_1_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [4:0] auto_out_1_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_1_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_1_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_0_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_0_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [2:0] auto_out_0_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_out_0_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [4:0] auto_out_0_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [31:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [3:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output [31:0] auto_out_0_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_0_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] output auto_out_0_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_0_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [1:0] auto_out_0_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [3:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [4:0] auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_0_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input [31:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@3057.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] wire TLMonitor_1_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [2:0] TLMonitor_1_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [2:0] TLMonitor_1_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [3:0] TLMonitor_1_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [3:0] TLMonitor_1_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [31:0] TLMonitor_1_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [3:0] TLMonitor_1_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [2:0] TLMonitor_1_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [1:0] TLMonitor_1_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [3:0] TLMonitor_1_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [3:0] TLMonitor_1_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire TLMonitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] wire [4:0] _GEN_4; // @[Xbar.scala 115:55:freechips.rocketchip.system.TinyConfig.fir@3175.4] wire [4:0] in_0_a_bits_source; // @[Xbar.scala 115:55:freechips.rocketchip.system.TinyConfig.fir@3175.4] reg [9:0] _T_525; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@3945.4] reg [31:0] _RAND_0; wire _T_526; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3946.4] wire [3:0] _T_144; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3378.4] wire requestDOI_1_0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3379.4] wire _T_287; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3596.4] wire [3:0] _T_130; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3362.4] wire requestDOI_0_0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3363.4] wire _T_278; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3580.4] wire [1:0] _T_528; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3948.4] reg [1:0] _T_535; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@3959.4] reg [31:0] _RAND_1; wire [1:0] _T_536; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3960.4] wire [1:0] _T_537; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3961.4] wire [3:0] _T_538; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3962.4] wire [2:0] _T_539; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3963.4] wire [3:0] _GEN_5; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3964.4] wire [3:0] _T_540; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3964.4] wire [2:0] _T_542; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3966.4] wire [3:0] _T_543; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3967.4] wire [3:0] _GEN_6; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3968.4] wire [3:0] _T_544; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3968.4] wire [1:0] _T_545; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3969.4] wire [1:0] _T_546; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3970.4] wire [1:0] _T_547; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3971.4] wire [1:0] _T_548; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3972.4] wire _T_557; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3984.4] wire _T_560; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3990.4] reg _T_590_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@4035.4] reg [31:0] _RAND_2; wire _T_591_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4036.4] wire [48:0] _T_607; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4057.4] wire [48:0] _T_608; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4058.4] wire _T_558; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3985.4] wire _T_561; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3991.4] reg _T_590_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@4035.4] reg [31:0] _RAND_3; wire _T_591_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4036.4] wire [48:0] _T_615; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4065.4] wire [48:0] _T_616; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4066.4] wire [48:0] _T_617; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4067.4] wire [4:0] in_0_d_bits_source; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4079.4] reg [9:0] _T_629; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@4091.4] reg [31:0] _RAND_4; wire _T_630; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@4092.4] wire _T_151; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3386.4] wire requestDOI_1_1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3387.4] wire _T_289; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3600.4] wire _T_137; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3370.4] wire requestDOI_0_1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3371.4] wire _T_280; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3584.4] wire [1:0] _T_632; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4094.4] reg [1:0] _T_639; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@4105.4] reg [31:0] _RAND_5; wire [1:0] _T_640; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@4106.4] wire [1:0] _T_641; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@4107.4] wire [3:0] _T_642; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4108.4] wire [2:0] _T_643; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@4109.4] wire [3:0] _GEN_7; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@4110.4] wire [3:0] _T_644; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@4110.4] wire [2:0] _T_646; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@4112.4] wire [3:0] _T_647; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@4113.4] wire [3:0] _GEN_8; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@4114.4] wire [3:0] _T_648; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@4114.4] wire [1:0] _T_649; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@4115.4] wire [1:0] _T_650; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@4116.4] wire [1:0] _T_651; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@4117.4] wire [1:0] _T_652; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@4118.4] wire _T_661; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@4130.4] wire _T_664; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@4136.4] reg _T_694_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@4181.4] reg [31:0] _RAND_6; wire _T_695_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4182.4] wire [48:0] _T_712; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4204.4] wire _T_662; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@4131.4] wire _T_665; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@4137.4] reg _T_694_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@4181.4] reg [31:0] _RAND_7; wire _T_695_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4182.4] wire [48:0] _T_720; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4212.4] wire [48:0] _T_721; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4213.4] wire [4:0] in_1_d_bits_source; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4225.4] wire [32:0] _T_57; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3273.4] wire [32:0] _T_58; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3274.4] wire [32:0] _T_59; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3275.4] wire requestAIO_0_0; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3276.4] wire [31:0] _T_61; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@3278.4] wire [32:0] _T_62; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3279.4] wire [32:0] _T_63; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3280.4] wire [32:0] _T_64; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3281.4] wire requestAIO_0_1; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3282.4] wire [32:0] _T_67; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3285.4] wire [32:0] _T_68; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3286.4] wire [32:0] _T_69; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3287.4] wire requestAIO_1_0; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3288.4] wire [31:0] _T_71; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@3290.4] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3291.4] wire [32:0] _T_73; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3292.4] wire [32:0] _T_74; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3293.4] wire requestAIO_1_1; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3294.4] wire [26:0] _T_161; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3401.4] wire [11:0] _T_162; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3402.4] wire [11:0] _T_163; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3403.4] wire [9:0] _T_164; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3404.4] wire _T_165; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@3405.4] wire _T_166; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@3406.4] wire [9:0] beatsAI_0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3407.4] wire [26:0] _T_168; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3409.4] wire [11:0] _T_169; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3410.4] wire [11:0] _T_170; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3411.4] wire [9:0] _T_171; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3412.4] wire _T_172; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@3413.4] wire _T_173; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@3414.4] wire [9:0] beatsAI_1; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3415.4] wire [26:0] _T_205; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3455.4] wire [11:0] _T_206; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3456.4] wire [11:0] _T_207; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3457.4] wire [9:0] _T_208; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3458.4] wire _T_209; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@3459.4] wire [9:0] beatsDO_0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3460.4] wire [22:0] _T_211; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3462.4] wire [7:0] _T_212; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3463.4] wire [7:0] _T_213; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3464.4] wire [5:0] _T_214; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3465.4] wire _T_215; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@3466.4] wire [5:0] beatsDO_1; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3467.4] wire _T_220; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3476.4] wire _T_222; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3480.4] reg [9:0] _T_314; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@3644.4] reg [31:0] _RAND_8; wire _T_315; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3645.4] wire _T_229; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3492.4] wire [1:0] _T_317; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3647.4] reg [1:0] _T_324; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@3658.4] reg [31:0] _RAND_9; wire [1:0] _T_325; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3659.4] wire [1:0] _T_326; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3660.4] wire [3:0] _T_327; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3661.4] wire [2:0] _T_328; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3662.4] wire [3:0] _GEN_9; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3663.4] wire [3:0] _T_329; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3663.4] wire [2:0] _T_331; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3665.4] wire [3:0] _T_332; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3666.4] wire [3:0] _GEN_10; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3667.4] wire [3:0] _T_333; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3667.4] wire [1:0] _T_334; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3668.4] wire [1:0] _T_335; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3669.4] wire [1:0] _T_336; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3670.4] wire [1:0] _T_337; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3671.4] wire _T_346; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3683.4] reg _T_379_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@3734.4] reg [31:0] _RAND_10; wire _T_381_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3737.4] wire _T_382; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3738.4] wire _T_223; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3482.4] reg [9:0] _T_419; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@3793.4] reg [31:0] _RAND_11; wire _T_420; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3794.4] wire _T_231; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3496.4] wire [1:0] _T_422; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3796.4] reg [1:0] _T_429; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@3807.4] reg [31:0] _RAND_12; wire [1:0] _T_430; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3808.4] wire [1:0] _T_431; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3809.4] wire [3:0] _T_432; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3810.4] wire [2:0] _T_433; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3811.4] wire [3:0] _GEN_11; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3812.4] wire [3:0] _T_434; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3812.4] wire [2:0] _T_436; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3814.4] wire [3:0] _T_437; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3815.4] wire [3:0] _GEN_12; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3816.4] wire [3:0] _T_438; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3816.4] wire [1:0] _T_439; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3817.4] wire [1:0] _T_440; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3818.4] wire [1:0] _T_441; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3819.4] wire [1:0] _T_442; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3820.4] wire _T_451; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3832.4] reg _T_484_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@3883.4] reg [31:0] _RAND_13; wire _T_486_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3886.4] wire _T_487; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3887.4] wire _T_224; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3483.4] wire _T_347; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3684.4] reg _T_379_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@3734.4] reg [31:0] _RAND_14; wire _T_381_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3737.4] wire _T_383; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3740.4] wire _T_232; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3498.4] wire _T_452; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3833.4] reg _T_484_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@3883.4] reg [31:0] _RAND_15; wire _T_486_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3886.4] wire _T_488; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3889.4] wire _T_233; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3499.4] wire _T_592_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4038.4] wire _T_593; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4039.4] wire _T_281; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3586.4] wire _T_696_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4184.4] wire _T_697; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4185.4] wire _T_282; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3587.4] wire _T_592_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4038.4] wire _T_594; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4041.4] wire _T_290; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3602.4] wire _T_696_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4184.4] wire _T_698; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4187.4] wire _T_291; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3603.4] wire _T_316; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3646.4] wire _T_319; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3649.4] wire _T_321; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3651.4] wire _T_322; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3652.4] wire _T_338; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3672.4] wire _T_339; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3673.4] wire [1:0] _T_340; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3675.6] wire [2:0] _T_341; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3676.6] wire [1:0] _T_342; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3677.6] wire [1:0] _T_343; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3678.6] wire _T_349; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3689.4] wire _T_350; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3690.4] wire _T_353; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3696.4] wire _T_355; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3698.4] wire _T_358; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3701.4] wire _T_359; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@3702.4] wire _T_362; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3705.4] wire _T_363; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3706.4] wire _T_364; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@3711.4] wire _T_365; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@3712.4] wire _T_367; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@3714.4] wire _T_369; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3716.4] wire _T_370; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3717.4] wire [9:0] _T_371; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3722.4] wire [9:0] _T_372; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3723.4] wire [9:0] _T_373; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@3724.4] wire _T_385; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3743.4] wire _T_386; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3744.4] wire _T_387; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3745.4] wire out_0_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@3748.4] wire _T_374; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@3725.4] wire [9:0] _GEN_13; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3726.4] wire [9:0] _T_376; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3727.4] wire _T_380_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3735.4] wire _T_380_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3735.4] wire [83:0] _T_396; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3756.4] wire [83:0] _T_397; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3757.4] wire [4:0] in_1_a_bits_source; // @[Xbar.scala 109:18:freechips.rocketchip.system.TinyConfig.fir@3172.4 Xbar.scala 114:17:freechips.rocketchip.system.TinyConfig.fir@3198.4 Xbar.scala 115:29:freechips.rocketchip.system.TinyConfig.fir@3200.4] wire [83:0] _T_404; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3764.4] wire [83:0] _T_405; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3765.4] wire [83:0] _T_406; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3766.4] wire _T_421; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3795.4] wire _T_424; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3798.4] wire _T_426; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3800.4] wire _T_427; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3801.4] wire _T_443; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3821.4] wire _T_444; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3822.4] wire [1:0] _T_445; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3824.6] wire [2:0] _T_446; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3825.6] wire [1:0] _T_447; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3826.6] wire [1:0] _T_448; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3827.6] wire _T_454; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3838.4] wire _T_455; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3839.4] wire _T_458; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3845.4] wire _T_460; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3847.4] wire _T_463; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3850.4] wire _T_464; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@3851.4] wire _T_467; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3854.4] wire _T_468; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3855.4] wire _T_469; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@3860.4] wire _T_470; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@3861.4] wire _T_472; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@3863.4] wire _T_474; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3865.4] wire _T_475; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3866.4] wire [9:0] _T_476; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3871.4] wire [9:0] _T_477; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3872.4] wire [9:0] _T_478; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@3873.4] wire _T_490; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3892.4] wire _T_491; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3893.4] wire _T_492; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3894.4] wire out_1_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@3897.4] wire _T_479; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@3874.4] wire [9:0] _GEN_14; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3875.4] wire [9:0] _T_481; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3876.4] wire _T_485_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3884.4] wire _T_485_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3884.4] wire [83:0] _T_502; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3906.4] wire [83:0] _T_510; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3914.4] wire [83:0] _T_511; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3915.4] wire [31:0] out_1_a_bits_address; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3925.4] wire _T_527; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3947.4] wire _T_530; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3950.4] wire _T_532; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3952.4] wire _T_533; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3953.4] wire _T_549; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3973.4] wire _T_550; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3974.4] wire [1:0] _T_551; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3976.6] wire [2:0] _T_552; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3977.6] wire [1:0] _T_553; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3978.6] wire [1:0] _T_554; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3979.6] wire _T_564; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3997.4] wire _T_566; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3999.4] wire _T_569; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4002.4] wire _T_570; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@4003.4] wire _T_573; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4006.4] wire _T_574; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4007.4] wire _T_575; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@4012.4] wire _T_576; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@4013.4] wire _T_578; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@4015.4] wire _T_580; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4017.4] wire _T_581; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4018.4] wire [9:0] _T_582; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4023.4] wire [5:0] _T_583; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4024.4] wire [9:0] _GEN_15; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4025.4] wire [9:0] _T_584; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4025.4] wire _T_596; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4044.4] wire _T_597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4045.4] wire _T_598; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4046.4] wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@4049.4] wire _T_585; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@4026.4] wire [9:0] _GEN_16; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4027.4] wire [9:0] _T_587; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4028.4] wire _T_631; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@4093.4] wire _T_634; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@4096.4] wire _T_636; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4098.4] wire _T_637; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4099.4] wire _T_653; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@4119.4] wire _T_654; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@4120.4] wire [1:0] _T_655; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@4122.6] wire [2:0] _T_656; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@4123.6] wire [1:0] _T_657; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@4124.6] wire [1:0] _T_658; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@4125.6] wire _T_668; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@4143.4] wire _T_670; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4145.4] wire _T_673; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4148.4] wire _T_674; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@4149.4] wire _T_677; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4152.4] wire _T_678; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4153.4] wire _T_679; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@4158.4] wire _T_680; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@4159.4] wire _T_682; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@4161.4] wire _T_684; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4163.4] wire _T_685; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4164.4] wire [9:0] _T_686; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4169.4] wire [5:0] _T_687; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4170.4] wire [9:0] _GEN_17; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4171.4] wire [9:0] _T_688; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4171.4] wire _T_700; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4190.4] wire _T_701; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4191.4] wire _T_702; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4192.4] wire in_1_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@4195.4] wire _T_689; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@4172.4] wire [9:0] _GEN_18; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4173.4] wire [9:0] _T_691; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4174.4] TLMonitor TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3066.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); TLMonitor_1 TLMonitor_1 ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@3115.4] .clock(TLMonitor_1_clock), .reset(TLMonitor_1_reset), .io_in_a_ready(TLMonitor_1_io_in_a_ready), .io_in_a_valid(TLMonitor_1_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_1_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_1_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_1_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_1_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_1_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_1_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_1_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_1_io_in_d_ready), .io_in_d_valid(TLMonitor_1_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_1_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_1_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_1_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_1_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_1_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_1_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_1_io_in_d_bits_corrupt) ); assign _GEN_4 = {{4'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 115:55:freechips.rocketchip.system.TinyConfig.fir@3175.4] assign in_0_a_bits_source = _GEN_4 | 5'h10; // @[Xbar.scala 115:55:freechips.rocketchip.system.TinyConfig.fir@3175.4] assign _T_526 = _T_525 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3946.4] assign _T_144 = auto_out_1_d_bits_source[4:1]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3378.4] assign requestDOI_1_0 = _T_144 == 4'h8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3379.4] assign _T_287 = auto_out_1_d_valid & requestDOI_1_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3596.4] assign _T_130 = auto_out_0_d_bits_source[4:1]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3362.4] assign requestDOI_0_0 = _T_130 == 4'h8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3363.4] assign _T_278 = auto_out_0_d_valid & requestDOI_0_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3580.4] assign _T_528 = {_T_287,_T_278}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3948.4] assign _T_536 = ~ _T_535; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3960.4] assign _T_537 = _T_528 & _T_536; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3961.4] assign _T_538 = {_T_537,_T_287,_T_278}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3962.4] assign _T_539 = _T_538[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3963.4] assign _GEN_5 = {{1'd0}, _T_539}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3964.4] assign _T_540 = _T_538 | _GEN_5; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3964.4] assign _T_542 = _T_540[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3966.4] assign _T_543 = {_T_535, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3967.4] assign _GEN_6 = {{1'd0}, _T_542}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3968.4] assign _T_544 = _GEN_6 | _T_543; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3968.4] assign _T_545 = _T_544[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3969.4] assign _T_546 = _T_544[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3970.4] assign _T_547 = _T_545 & _T_546; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3971.4] assign _T_548 = ~ _T_547; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3972.4] assign _T_557 = _T_548[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3984.4] assign _T_560 = _T_557 & _T_278; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3990.4] assign _T_591_0 = _T_526 ? _T_560 : _T_590_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4036.4] assign _T_607 = {auto_out_0_d_bits_opcode,auto_out_0_d_bits_param,auto_out_0_d_bits_size,auto_out_0_d_bits_source,auto_out_0_d_bits_sink,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4057.4] assign _T_608 = _T_591_0 ? _T_607 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4058.4] assign _T_558 = _T_548[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3985.4] assign _T_561 = _T_558 & _T_287; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3991.4] assign _T_591_1 = _T_526 ? _T_561 : _T_590_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4036.4] assign _T_615 = {auto_out_1_d_bits_opcode,2'h0,auto_out_1_d_bits_size,auto_out_1_d_bits_source,1'h0,auto_out_1_d_bits_denied,auto_out_1_d_bits_data,auto_out_1_d_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4065.4] assign _T_616 = _T_591_1 ? _T_615 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4066.4] assign _T_617 = _T_608 | _T_616; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4067.4] assign in_0_d_bits_source = _T_617[39:35]; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4079.4] assign _T_630 = _T_629 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@4092.4] assign _T_151 = auto_out_1_d_bits_source[4:4]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3386.4] assign requestDOI_1_1 = _T_151 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3387.4] assign _T_289 = auto_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3600.4] assign _T_137 = auto_out_0_d_bits_source[4:4]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@3370.4] assign requestDOI_0_1 = _T_137 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@3371.4] assign _T_280 = auto_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3584.4] assign _T_632 = {_T_289,_T_280}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4094.4] assign _T_640 = ~ _T_639; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@4106.4] assign _T_641 = _T_632 & _T_640; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@4107.4] assign _T_642 = {_T_641,_T_289,_T_280}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4108.4] assign _T_643 = _T_642[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@4109.4] assign _GEN_7 = {{1'd0}, _T_643}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@4110.4] assign _T_644 = _T_642 | _GEN_7; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@4110.4] assign _T_646 = _T_644[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@4112.4] assign _T_647 = {_T_639, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@4113.4] assign _GEN_8 = {{1'd0}, _T_646}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@4114.4] assign _T_648 = _GEN_8 | _T_647; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@4114.4] assign _T_649 = _T_648[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@4115.4] assign _T_650 = _T_648[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@4116.4] assign _T_651 = _T_649 & _T_650; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@4117.4] assign _T_652 = ~ _T_651; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@4118.4] assign _T_661 = _T_652[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@4130.4] assign _T_664 = _T_661 & _T_280; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@4136.4] assign _T_695_0 = _T_630 ? _T_664 : _T_694_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4182.4] assign _T_712 = _T_695_0 ? _T_607 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4204.4] assign _T_662 = _T_652[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@4131.4] assign _T_665 = _T_662 & _T_289; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@4137.4] assign _T_695_1 = _T_630 ? _T_665 : _T_694_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@4182.4] assign _T_720 = _T_695_1 ? _T_615 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4212.4] assign _T_721 = _T_712 | _T_720; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4213.4] assign in_1_d_bits_source = _T_721[39:35]; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4225.4] assign _T_57 = {1'b0,$signed(auto_in_0_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3273.4] assign _T_58 = $signed(_T_57) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3274.4] assign _T_59 = $signed(_T_58); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3275.4] assign requestAIO_0_0 = $signed(_T_59) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3276.4] assign _T_61 = auto_in_0_a_bits_address ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@3278.4] assign _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3279.4] assign _T_63 = $signed(_T_62) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3280.4] assign _T_64 = $signed(_T_63); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3281.4] assign requestAIO_0_1 = $signed(_T_64) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3282.4] assign _T_67 = {1'b0,$signed(auto_in_1_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3285.4] assign _T_68 = $signed(_T_67) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3286.4] assign _T_69 = $signed(_T_68); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3287.4] assign requestAIO_1_0 = $signed(_T_69) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3288.4] assign _T_71 = auto_in_1_a_bits_address ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@3290.4] assign _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@3291.4] assign _T_73 = $signed(_T_72) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3292.4] assign _T_74 = $signed(_T_73); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@3293.4] assign requestAIO_1_1 = $signed(_T_74) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@3294.4] assign _T_161 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3401.4] assign _T_162 = _T_161[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3402.4] assign _T_163 = ~ _T_162; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3403.4] assign _T_164 = _T_163[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3404.4] assign _T_165 = auto_in_0_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@3405.4] assign _T_166 = _T_165 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@3406.4] assign beatsAI_0 = _T_166 ? _T_164 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3407.4] assign _T_168 = 27'hfff << auto_in_1_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3409.4] assign _T_169 = _T_168[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3410.4] assign _T_170 = ~ _T_169; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3411.4] assign _T_171 = _T_170[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3412.4] assign _T_172 = auto_in_1_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@3413.4] assign _T_173 = _T_172 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@3414.4] assign beatsAI_1 = _T_173 ? _T_171 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3415.4] assign _T_205 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3455.4] assign _T_206 = _T_205[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3456.4] assign _T_207 = ~ _T_206; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3457.4] assign _T_208 = _T_207[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3458.4] assign _T_209 = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@3459.4] assign beatsDO_0 = _T_209 ? _T_208 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3460.4] assign _T_211 = 23'hff << auto_out_1_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@3462.4] assign _T_212 = _T_211[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@3463.4] assign _T_213 = ~ _T_212; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@3464.4] assign _T_214 = _T_213[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@3465.4] assign _T_215 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@3466.4] assign beatsDO_1 = _T_215 ? _T_214 : 6'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@3467.4] assign _T_220 = auto_in_0_a_valid & requestAIO_0_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3476.4] assign _T_222 = auto_in_0_a_valid & requestAIO_0_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3480.4] assign _T_315 = _T_314 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3645.4] assign _T_229 = auto_in_1_a_valid & requestAIO_1_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3492.4] assign _T_317 = {_T_229,_T_220}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3647.4] assign _T_325 = ~ _T_324; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3659.4] assign _T_326 = _T_317 & _T_325; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3660.4] assign _T_327 = {_T_326,_T_229,_T_220}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3661.4] assign _T_328 = _T_327[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3662.4] assign _GEN_9 = {{1'd0}, _T_328}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3663.4] assign _T_329 = _T_327 | _GEN_9; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3663.4] assign _T_331 = _T_329[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3665.4] assign _T_332 = {_T_324, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3666.4] assign _GEN_10 = {{1'd0}, _T_331}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3667.4] assign _T_333 = _GEN_10 | _T_332; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3667.4] assign _T_334 = _T_333[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3668.4] assign _T_335 = _T_333[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3669.4] assign _T_336 = _T_334 & _T_335; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3670.4] assign _T_337 = ~ _T_336; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3671.4] assign _T_346 = _T_337[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3683.4] assign _T_381_0 = _T_315 ? _T_346 : _T_379_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3737.4] assign _T_382 = auto_out_0_a_ready & _T_381_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3738.4] assign _T_223 = requestAIO_0_0 ? _T_382 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3482.4] assign _T_420 = _T_419 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@3794.4] assign _T_231 = auto_in_1_a_valid & requestAIO_1_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.TinyConfig.fir@3496.4] assign _T_422 = {_T_231,_T_222}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3796.4] assign _T_430 = ~ _T_429; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@3808.4] assign _T_431 = _T_422 & _T_430; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@3809.4] assign _T_432 = {_T_431,_T_231,_T_222}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@3810.4] assign _T_433 = _T_432[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@3811.4] assign _GEN_11 = {{1'd0}, _T_433}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3812.4] assign _T_434 = _T_432 | _GEN_11; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@3812.4] assign _T_436 = _T_434[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@3814.4] assign _T_437 = {_T_429, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@3815.4] assign _GEN_12 = {{1'd0}, _T_436}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3816.4] assign _T_438 = _GEN_12 | _T_437; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@3816.4] assign _T_439 = _T_438[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@3817.4] assign _T_440 = _T_438[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@3818.4] assign _T_441 = _T_439 & _T_440; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@3819.4] assign _T_442 = ~ _T_441; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@3820.4] assign _T_451 = _T_442[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3832.4] assign _T_486_0 = _T_420 ? _T_451 : _T_484_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3886.4] assign _T_487 = auto_out_1_a_ready & _T_486_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3887.4] assign _T_224 = requestAIO_0_1 ? _T_487 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3483.4] assign _T_347 = _T_337[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3684.4] assign _T_381_1 = _T_315 ? _T_347 : _T_379_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3737.4] assign _T_383 = auto_out_0_a_ready & _T_381_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3740.4] assign _T_232 = requestAIO_1_0 ? _T_383 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3498.4] assign _T_452 = _T_442[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@3833.4] assign _T_486_1 = _T_420 ? _T_452 : _T_484_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@3886.4] assign _T_488 = auto_out_1_a_ready & _T_486_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@3889.4] assign _T_233 = requestAIO_1_1 ? _T_488 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3499.4] assign _T_592_0 = _T_526 ? _T_557 : _T_590_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4038.4] assign _T_593 = auto_in_0_d_ready & _T_592_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4039.4] assign _T_281 = requestDOI_0_0 ? _T_593 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3586.4] assign _T_696_0 = _T_630 ? _T_661 : _T_694_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4184.4] assign _T_697 = auto_in_1_d_ready & _T_696_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4185.4] assign _T_282 = requestDOI_0_1 ? _T_697 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3587.4] assign _T_592_1 = _T_526 ? _T_558 : _T_590_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4038.4] assign _T_594 = auto_in_0_d_ready & _T_592_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4041.4] assign _T_290 = requestDOI_1_0 ? _T_594 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3602.4] assign _T_696_1 = _T_630 ? _T_662 : _T_694_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@4184.4] assign _T_698 = auto_in_1_d_ready & _T_696_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@4187.4] assign _T_291 = requestDOI_1_1 ? _T_698 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3603.4] assign _T_316 = _T_315 & auto_out_0_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3646.4] assign _T_319 = _T_317 == _T_317; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3649.4] assign _T_321 = _T_319 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3651.4] assign _T_322 = _T_321 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3652.4] assign _T_338 = _T_317 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3672.4] assign _T_339 = _T_316 & _T_338; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3673.4] assign _T_340 = _T_337 & _T_317; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3675.6] assign _T_341 = {_T_340, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3676.6] assign _T_342 = _T_341[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3677.6] assign _T_343 = _T_340 | _T_342; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3678.6] assign _T_349 = _T_346 & _T_220; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3689.4] assign _T_350 = _T_347 & _T_229; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3690.4] assign _T_353 = _T_349 | _T_350; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3696.4] assign _T_355 = _T_349 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3698.4] assign _T_358 = _T_350 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3701.4] assign _T_359 = _T_355 | _T_358; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@3702.4] assign _T_362 = _T_359 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3705.4] assign _T_363 = _T_362 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3706.4] assign _T_364 = _T_220 | _T_229; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@3711.4] assign _T_365 = _T_364 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@3712.4] assign _T_367 = _T_365 | _T_353; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@3714.4] assign _T_369 = _T_367 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3716.4] assign _T_370 = _T_369 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3717.4] assign _T_371 = _T_349 ? beatsAI_0 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3722.4] assign _T_372 = _T_350 ? beatsAI_1 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3723.4] assign _T_373 = _T_371 | _T_372; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@3724.4] assign _T_385 = _T_379_0 ? _T_220 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3743.4] assign _T_386 = _T_379_1 ? _T_229 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3744.4] assign _T_387 = _T_385 | _T_386; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3745.4] assign out_0_a_valid = _T_315 ? _T_364 : _T_387; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@3748.4] assign _T_374 = auto_out_0_a_ready & out_0_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@3725.4] assign _GEN_13 = {{9'd0}, _T_374}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3726.4] assign _T_376 = _T_314 - _GEN_13; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3727.4] assign _T_380_0 = _T_315 ? _T_349 : _T_379_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3735.4] assign _T_380_1 = _T_315 ? _T_350 : _T_379_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3735.4] assign _T_396 = {auto_in_0_a_bits_opcode,auto_in_0_a_bits_param,auto_in_0_a_bits_size,in_0_a_bits_source,auto_in_0_a_bits_address,auto_in_0_a_bits_mask,auto_in_0_a_bits_data,auto_in_0_a_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3756.4] assign _T_397 = _T_380_0 ? _T_396 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3757.4] assign in_1_a_bits_source = {{1'd0}, auto_in_1_a_bits_source}; // @[Xbar.scala 109:18:freechips.rocketchip.system.TinyConfig.fir@3172.4 Xbar.scala 114:17:freechips.rocketchip.system.TinyConfig.fir@3198.4 Xbar.scala 115:29:freechips.rocketchip.system.TinyConfig.fir@3200.4] assign _T_404 = {auto_in_1_a_bits_opcode,auto_in_1_a_bits_param,auto_in_1_a_bits_size,in_1_a_bits_source,auto_in_1_a_bits_address,auto_in_1_a_bits_mask,auto_in_1_a_bits_data,auto_in_1_a_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3764.4] assign _T_405 = _T_380_1 ? _T_404 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3765.4] assign _T_406 = _T_397 | _T_405; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3766.4] assign _T_421 = _T_420 & auto_out_1_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3795.4] assign _T_424 = _T_422 == _T_422; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3798.4] assign _T_426 = _T_424 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3800.4] assign _T_427 = _T_426 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3801.4] assign _T_443 = _T_422 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3821.4] assign _T_444 = _T_421 & _T_443; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3822.4] assign _T_445 = _T_442 & _T_422; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3824.6] assign _T_446 = {_T_445, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3825.6] assign _T_447 = _T_446[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3826.6] assign _T_448 = _T_445 | _T_447; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3827.6] assign _T_454 = _T_451 & _T_222; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3838.4] assign _T_455 = _T_452 & _T_231; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@3839.4] assign _T_458 = _T_454 | _T_455; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3845.4] assign _T_460 = _T_454 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3847.4] assign _T_463 = _T_455 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3850.4] assign _T_464 = _T_460 | _T_463; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@3851.4] assign _T_467 = _T_464 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3854.4] assign _T_468 = _T_467 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3855.4] assign _T_469 = _T_222 | _T_231; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@3860.4] assign _T_470 = _T_469 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@3861.4] assign _T_472 = _T_470 | _T_458; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@3863.4] assign _T_474 = _T_472 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3865.4] assign _T_475 = _T_474 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3866.4] assign _T_476 = _T_454 ? beatsAI_0 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3871.4] assign _T_477 = _T_455 ? beatsAI_1 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@3872.4] assign _T_478 = _T_476 | _T_477; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@3873.4] assign _T_490 = _T_484_0 ? _T_222 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3892.4] assign _T_491 = _T_484_1 ? _T_231 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3893.4] assign _T_492 = _T_490 | _T_491; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3894.4] assign out_1_a_valid = _T_420 ? _T_469 : _T_492; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@3897.4] assign _T_479 = auto_out_1_a_ready & out_1_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@3874.4] assign _GEN_14 = {{9'd0}, _T_479}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3875.4] assign _T_481 = _T_419 - _GEN_14; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@3876.4] assign _T_485_0 = _T_420 ? _T_454 : _T_484_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3884.4] assign _T_485_1 = _T_420 ? _T_455 : _T_484_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@3884.4] assign _T_502 = _T_485_0 ? _T_396 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3906.4] assign _T_510 = _T_485_1 ? _T_404 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3914.4] assign _T_511 = _T_502 | _T_510; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3915.4] assign out_1_a_bits_address = _T_511[68:37]; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@3925.4] assign _T_527 = _T_526 & auto_in_0_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@3947.4] assign _T_530 = _T_528 == _T_528; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@3950.4] assign _T_532 = _T_530 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3952.4] assign _T_533 = _T_532 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3953.4] assign _T_549 = _T_528 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@3973.4] assign _T_550 = _T_527 & _T_549; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@3974.4] assign _T_551 = _T_548 & _T_528; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@3976.6] assign _T_552 = {_T_551, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@3977.6] assign _T_553 = _T_552[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@3978.6] assign _T_554 = _T_551 | _T_553; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@3979.6] assign _T_564 = _T_560 | _T_561; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@3997.4] assign _T_566 = _T_560 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@3999.4] assign _T_569 = _T_561 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4002.4] assign _T_570 = _T_566 | _T_569; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@4003.4] assign _T_573 = _T_570 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4006.4] assign _T_574 = _T_573 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4007.4] assign _T_575 = _T_278 | _T_287; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@4012.4] assign _T_576 = _T_575 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@4013.4] assign _T_578 = _T_576 | _T_564; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@4015.4] assign _T_580 = _T_578 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4017.4] assign _T_581 = _T_580 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4018.4] assign _T_582 = _T_560 ? beatsDO_0 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4023.4] assign _T_583 = _T_561 ? beatsDO_1 : 6'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4024.4] assign _GEN_15 = {{4'd0}, _T_583}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4025.4] assign _T_584 = _T_582 | _GEN_15; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4025.4] assign _T_596 = _T_590_0 ? _T_278 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4044.4] assign _T_597 = _T_590_1 ? _T_287 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4045.4] assign _T_598 = _T_596 | _T_597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4046.4] assign in_0_d_valid = _T_526 ? _T_575 : _T_598; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@4049.4] assign _T_585 = auto_in_0_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@4026.4] assign _GEN_16 = {{9'd0}, _T_585}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4027.4] assign _T_587 = _T_525 - _GEN_16; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4028.4] assign _T_631 = _T_630 & auto_in_1_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@4093.4] assign _T_634 = _T_632 == _T_632; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@4096.4] assign _T_636 = _T_634 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4098.4] assign _T_637 = _T_636 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4099.4] assign _T_653 = _T_632 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@4119.4] assign _T_654 = _T_631 & _T_653; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@4120.4] assign _T_655 = _T_652 & _T_632; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@4122.6] assign _T_656 = {_T_655, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@4123.6] assign _T_657 = _T_656[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@4124.6] assign _T_658 = _T_655 | _T_657; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@4125.6] assign _T_668 = _T_664 | _T_665; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@4143.4] assign _T_670 = _T_664 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4145.4] assign _T_673 = _T_665 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@4148.4] assign _T_674 = _T_670 | _T_673; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@4149.4] assign _T_677 = _T_674 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4152.4] assign _T_678 = _T_677 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4153.4] assign _T_679 = _T_280 | _T_289; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@4158.4] assign _T_680 = _T_679 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@4159.4] assign _T_682 = _T_680 | _T_668; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@4161.4] assign _T_684 = _T_682 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4163.4] assign _T_685 = _T_684 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4164.4] assign _T_686 = _T_664 ? beatsDO_0 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4169.4] assign _T_687 = _T_665 ? beatsDO_1 : 6'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@4170.4] assign _GEN_17 = {{4'd0}, _T_687}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4171.4] assign _T_688 = _T_686 | _GEN_17; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@4171.4] assign _T_700 = _T_694_0 ? _T_280 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4190.4] assign _T_701 = _T_694_1 ? _T_289 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4191.4] assign _T_702 = _T_700 | _T_701; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@4192.4] assign in_1_d_valid = _T_630 ? _T_679 : _T_702; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@4195.4] assign _T_689 = auto_in_1_d_ready & in_1_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@4172.4] assign _GEN_18 = {{9'd0}, _T_689}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4173.4] assign _T_691 = _T_629 - _GEN_18; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@4174.4] assign auto_in_1_a_ready = _T_232 | _T_233; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_valid = _T_630 ? _T_679 : _T_702; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_opcode = _T_721[48:46]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_param = _T_721[45:44]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_size = _T_721[43:40]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_source = in_1_d_bits_source[3:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_sink = _T_721[34]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_denied = _T_721[33]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_data = _T_721[32:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_1_d_bits_corrupt = _T_721[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3171.4] assign auto_in_0_a_ready = _T_223 | _T_224; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_valid = _T_526 ? _T_575 : _T_598; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_opcode = _T_617[48:46]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_param = _T_617[45:44]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_size = _T_617[43:40]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_source = in_0_d_bits_source[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_sink = _T_617[34]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_denied = _T_617[33]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_data = _T_617[32:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_in_0_d_bits_corrupt = _T_617[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@3170.4] assign auto_out_1_a_valid = _T_420 ? _T_469 : _T_492; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_opcode = _T_511[83:81]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_param = _T_511[80:78]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_size = _T_511[77:74]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_source = _T_511[73:69]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_address = out_1_a_bits_address[30:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_mask = _T_511[36:33]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_data = _T_511[32:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_a_bits_corrupt = _T_511[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_1_d_ready = _T_290 | _T_291; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3169.4] assign auto_out_0_a_valid = _T_315 ? _T_364 : _T_387; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_opcode = _T_406[83:81]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_param = _T_406[80:78]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_size = _T_406[77:74]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_source = _T_406[73:69]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_address = _T_406[68:37]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_mask = _T_406[36:33]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_data = _T_406[32:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_a_bits_corrupt = _T_406[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign auto_out_0_d_ready = _T_281 | _T_282; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@3168.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@3068.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@3069.4] assign TLMonitor_io_in_a_ready = _T_223 | _T_224; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_valid = _T_526 ? _T_575 : _T_598; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_opcode = _T_617[48:46]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_param = _T_617[45:44]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_size = _T_617[43:40]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_source = in_0_d_bits_source[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_sink = _T_617[34]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_denied = _T_617[33]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_io_in_d_bits_corrupt = _T_617[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3114.4] assign TLMonitor_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@3117.4] assign TLMonitor_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@3118.4] assign TLMonitor_1_io_in_a_ready = _T_232 | _T_233; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_valid = _T_630 ? _T_679 : _T_702; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_opcode = _T_721[48:46]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_param = _T_721[45:44]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_size = _T_721[43:40]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_source = in_1_d_bits_source[3:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_sink = _T_721[34]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_denied = _T_721[33]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] assign TLMonitor_1_io_in_d_bits_corrupt = _T_721[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@3163.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_525 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_535 = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_590_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_590_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_629 = _RAND_4[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_639 = _RAND_5[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_694_0 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_694_1 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_314 = _RAND_8[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_324 = _RAND_9[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_379_0 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_419 = _RAND_11[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_429 = _RAND_12[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_484_0 = _RAND_13[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_379_1 = _RAND_14[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_484_1 = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_525 <= 10'h0; end else begin if (_T_527) begin _T_525 <= _T_584; end else begin _T_525 <= _T_587; end end if (reset) begin _T_535 <= 2'h3; end else begin if (_T_550) begin _T_535 <= _T_554; end end if (reset) begin _T_590_0 <= 1'h0; end else begin if (_T_526) begin _T_590_0 <= _T_560; end end if (reset) begin _T_590_1 <= 1'h0; end else begin if (_T_526) begin _T_590_1 <= _T_561; end end if (reset) begin _T_629 <= 10'h0; end else begin if (_T_631) begin _T_629 <= _T_688; end else begin _T_629 <= _T_691; end end if (reset) begin _T_639 <= 2'h3; end else begin if (_T_654) begin _T_639 <= _T_658; end end if (reset) begin _T_694_0 <= 1'h0; end else begin if (_T_630) begin _T_694_0 <= _T_664; end end if (reset) begin _T_694_1 <= 1'h0; end else begin if (_T_630) begin _T_694_1 <= _T_665; end end if (reset) begin _T_314 <= 10'h0; end else begin if (_T_316) begin _T_314 <= _T_373; end else begin _T_314 <= _T_376; end end if (reset) begin _T_324 <= 2'h3; end else begin if (_T_339) begin _T_324 <= _T_343; end end if (reset) begin _T_379_0 <= 1'h0; end else begin if (_T_315) begin _T_379_0 <= _T_349; end end if (reset) begin _T_419 <= 10'h0; end else begin if (_T_421) begin _T_419 <= _T_478; end else begin _T_419 <= _T_481; end end if (reset) begin _T_429 <= 2'h3; end else begin if (_T_444) begin _T_429 <= _T_448; end end if (reset) begin _T_484_0 <= 1'h0; end else begin if (_T_420) begin _T_484_0 <= _T_454; end end if (reset) begin _T_379_1 <= 1'h0; end else begin if (_T_315) begin _T_379_1 <= _T_350; end end if (reset) begin _T_484_1 <= 1'h0; end else begin if (_T_420) begin _T_484_1 <= _T_455; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_322) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3654.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_322) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3655.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_363) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3708.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_363) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3709.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_370) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3719.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_370) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3720.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_427) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3803.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_427) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3804.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_468) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3857.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_468) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@3858.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_475) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3868.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_475) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@3869.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_533) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3955.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_533) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@3956.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_574) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4009.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_574) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4010.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_581) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4020.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_581) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4021.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_637) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4101.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_637) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@4102.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_678) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4155.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_678) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@4156.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_685) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4166.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_685) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@4167.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_2( // @[:freechips.rocketchip.system.TinyConfig.fir@4243.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@4244.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@4245.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@4246.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@5706.4] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@4262.6] wire _T_8; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@4267.6] wire [26:0] _T_10; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@4269.6] wire [11:0] _T_11; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@4270.6] wire [11:0] _T_12; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@4271.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@4272.6] wire [31:0] _T_13; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@4272.6] wire _T_14; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@4273.6] wire _T_16; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@4275.6] wire [1:0] _T_17; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@4276.6] wire [1:0] _T_19; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@4278.6] wire _T_20; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@4279.6] wire _T_21; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@4280.6] wire _T_22; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@4281.6] wire _T_23; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@4282.6] wire _T_25; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4284.6] wire _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4285.6] wire _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4287.6] wire _T_29; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4288.6] wire _T_30; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@4289.6] wire _T_31; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@4290.6] wire _T_32; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@4291.6] wire _T_33; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4292.6] wire _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4293.6] wire _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4294.6] wire _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4295.6] wire _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4296.6] wire _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4297.6] wire _T_39; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4298.6] wire _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4299.6] wire _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4300.6] wire _T_42; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4301.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4302.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4303.6] wire [3:0] _T_47; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4306.6] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4310.6] wire _T_68; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@4331.6] wire [31:0] _T_70; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4334.8] wire [32:0] _T_71; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4335.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4336.8] wire [32:0] _T_73; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4337.8] wire _T_74; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4338.8] wire [31:0] _T_75; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4339.8] wire [32:0] _T_76; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4340.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4341.8] wire [32:0] _T_78; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4342.8] wire _T_79; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4343.8] wire [31:0] _T_80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4344.8] wire [32:0] _T_81; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4345.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4346.8] wire [32:0] _T_83; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4347.8] wire _T_84; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4348.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4351.8] wire [32:0] _T_88; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4352.8] wire _T_89; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4353.8] wire [31:0] _T_90; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4354.8] wire [32:0] _T_91; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4355.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4356.8] wire [32:0] _T_93; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4357.8] wire _T_94; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4358.8] wire [31:0] _T_95; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4359.8] wire [32:0] _T_96; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4360.8] wire [32:0] _T_97; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4361.8] wire [32:0] _T_98; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4362.8] wire _T_99; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4363.8] wire [31:0] _T_100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4364.8] wire [32:0] _T_101; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4365.8] wire [32:0] _T_102; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4366.8] wire [32:0] _T_103; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4367.8] wire _T_104; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4368.8] wire _T_105; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4369.8] wire _T_106; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4370.8] wire _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4371.8] wire _T_108; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4372.8] wire _T_115; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4379.8] wire _T_120; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4392.8] wire _T_121; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4393.8] wire _T_124; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4400.8] wire _T_125; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4401.8] wire _T_127; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4407.8] wire _T_128; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4408.8] wire _T_129; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@4413.8] wire _T_131; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4415.8] wire _T_132; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4416.8] wire [3:0] _T_133; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@4421.8] wire _T_134; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@4422.8] wire _T_136; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4424.8] wire _T_137; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4425.8] wire _T_138; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@4430.8] wire _T_140; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4432.8] wire _T_141; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4433.8] wire _T_142; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@4439.6] wire _T_207; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@4529.8] wire _T_209; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4531.8] wire _T_210; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4532.8] wire _T_220; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@4555.6] wire _T_222; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4558.8] wire _T_230; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4566.8] wire _T_232; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4568.8] wire _T_265; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4601.8] wire _T_266; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4602.8] wire _T_267; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4603.8] wire _T_268; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4604.8] wire _T_269; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4605.8] wire _T_270; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4606.8] wire _T_272; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4608.8] wire _T_274; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4610.8] wire _T_275; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4611.8] wire _T_282; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@4630.8] wire _T_284; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4632.8] wire _T_285; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4633.8] wire _T_286; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@4638.8] wire _T_288; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4640.8] wire _T_289; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4641.8] wire _T_294; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@4655.6] wire _T_332; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4694.8] wire _T_341; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4703.8] wire _T_349; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4711.8] wire _T_351; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4713.8] wire _T_353; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4715.8] wire _T_355; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4717.8] wire _T_356; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4718.8] wire _T_371; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@4754.6] wire [3:0] _T_444; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@4844.8] wire [3:0] _T_445; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@4845.8] wire _T_446; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@4846.8] wire _T_448; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4848.8] wire _T_449; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4849.8] wire _T_450; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@4855.6] wire _T_452; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4858.8] wire _T_484; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4890.8] wire _T_501; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4907.8] wire _T_502; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4908.8] wire _T_509; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@4927.8] wire _T_511; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4929.8] wire _T_512; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4930.8] wire _T_517; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@4944.6] wire _T_576; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@5016.8] wire _T_578; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5018.8] wire _T_579; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5019.8] wire _T_584; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@5033.6] wire _T_635; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5085.8] wire _T_636; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5086.8] wire _T_651; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@5124.6] wire _T_653; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5126.6] wire _T_654; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5127.6] wire _T_656; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@5133.6] wire _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@5138.6] wire _T_660; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@5140.6] wire _T_662; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5143.8] wire _T_663; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5144.8] wire _T_664; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@5149.8] wire _T_666; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5151.8] wire _T_667; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5152.8] wire _T_668; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@5157.8] wire _T_670; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5159.8] wire _T_671; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5160.8] wire _T_672; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@5165.8] wire _T_674; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5167.8] wire _T_675; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5168.8] wire _T_676; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@5173.8] wire _T_678; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5175.8] wire _T_679; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5176.8] wire _T_680; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@5182.6] wire _T_691; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@5206.8] wire _T_693; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5208.8] wire _T_694; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5209.8] wire _T_695; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@5214.8] wire _T_697; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5216.8] wire _T_698; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5217.8] wire _T_708; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@5240.6] wire _T_728; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@5281.8] wire _T_730; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5283.8] wire _T_731; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5284.8] wire _T_737; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@5299.6] wire _T_754; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@5334.6] wire _T_772; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@5370.6] wire _T_801; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@5430.4] wire [9:0] _T_806; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@5435.4] wire _T_807; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@5436.4] wire _T_808; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@5437.4] reg [9:0] _T_810; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@5439.4] reg [31:0] _RAND_0; wire [9:0] _T_812; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5441.4] wire _T_813; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5442.4] reg [2:0] _T_821; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@5453.4] reg [31:0] _RAND_1; reg [2:0] _T_822; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@5454.4] reg [31:0] _RAND_2; reg [3:0] _T_823; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@5455.4] reg [31:0] _RAND_3; reg _T_824; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@5456.4] reg [31:0] _RAND_4; reg [31:0] _T_825; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@5457.4] reg [31:0] _RAND_5; wire _T_826; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@5458.4] wire _T_827; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@5459.4] wire _T_828; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@5461.6] wire _T_830; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5463.6] wire _T_831; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5464.6] wire _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@5469.6] wire _T_834; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5471.6] wire _T_835; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5472.6] wire _T_836; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@5477.6] wire _T_838; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5479.6] wire _T_839; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5480.6] wire _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@5485.6] wire _T_842; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5487.6] wire _T_843; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5488.6] wire _T_844; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@5493.6] wire _T_846; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5495.6] wire _T_847; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5496.6] wire _T_849; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@5503.4] wire _T_850; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@5511.4] wire [26:0] _T_852; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@5513.4] wire [11:0] _T_853; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@5514.4] wire [11:0] _T_854; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@5515.4] wire [9:0] _T_855; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@5516.4] wire _T_856; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@5517.4] reg [9:0] _T_858; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@5519.4] reg [31:0] _RAND_6; wire [9:0] _T_860; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5521.4] wire _T_861; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5522.4] reg [2:0] _T_869; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@5533.4] reg [31:0] _RAND_7; reg [1:0] _T_870; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@5534.4] reg [31:0] _RAND_8; reg [3:0] _T_871; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@5535.4] reg [31:0] _RAND_9; reg _T_872; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@5536.4] reg [31:0] _RAND_10; reg _T_873; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@5537.4] reg [31:0] _RAND_11; reg _T_874; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@5538.4] reg [31:0] _RAND_12; wire _T_875; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@5539.4] wire _T_876; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@5540.4] wire _T_877; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@5542.6] wire _T_879; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5544.6] wire _T_880; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5545.6] wire _T_881; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@5550.6] wire _T_883; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5552.6] wire _T_884; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5553.6] wire _T_885; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@5558.6] wire _T_887; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5560.6] wire _T_888; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5561.6] wire _T_889; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@5566.6] wire _T_891; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5568.6] wire _T_892; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5569.6] wire _T_893; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@5574.6] wire _T_895; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5576.6] wire _T_896; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5577.6] wire _T_897; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@5582.6] wire _T_899; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5584.6] wire _T_900; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5585.6] wire _T_902; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@5592.4] reg [1:0] _T_903; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@5601.4] reg [31:0] _RAND_13; reg [9:0] _T_913; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@5611.4] reg [31:0] _RAND_14; wire [9:0] _T_915; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5613.4] wire _T_916; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5614.4] reg [9:0] _T_932; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@5633.4] reg [31:0] _RAND_15; wire [9:0] _T_934; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5635.4] wire _T_935; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5636.4] wire _T_945; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@5651.4] wire [1:0] _T_947; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@5654.6] wire [1:0] _T_948; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@5656.6] wire _T_949; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@5657.6] wire _T_950; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@5658.6] wire _T_952; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5660.6] wire _T_953; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5661.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@5653.4] wire _T_957; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@5672.4] wire _T_959; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@5674.4] wire _T_960; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@5675.4] wire [1:0] _T_961; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@5677.6] wire [1:0] _T_962; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@5679.6] wire [1:0] _T_963; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@5680.6] wire _T_964; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@5681.6] wire _T_966; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5683.6] wire _T_967; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5684.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@5676.4] wire _T_968; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@5690.4] wire _T_969; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@5691.4] wire _T_970; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@5692.4] wire _T_971; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@5693.4] wire _T_973; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5695.4] wire _T_974; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5696.4] wire [1:0] _T_975; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@5701.4] wire [1:0] _T_976; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@5702.4] wire [1:0] _T_977; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@5703.4] reg [31:0] _T_978; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@5705.4] reg [31:0] _RAND_16; wire _T_979; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@5708.4] wire _T_980; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@5709.4] wire _T_981; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@5710.4] wire _T_982; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@5711.4] wire _T_983; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@5712.4] wire _T_984; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@5713.4] wire _T_986; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5715.4] wire _T_987; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5716.4] wire [31:0] _T_989; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@5722.4] wire _T_992; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@5726.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4381.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@4489.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4613.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4720.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@4819.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4910.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@4999.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5088.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5146.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@5188.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@5246.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@5305.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@5340.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@5376.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@5706.4] .out(plusarg_reader_out) ); assign _T_6 = io_in_a_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@4262.6] assign _T_8 = io_in_a_bits_source | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@4267.6] assign _T_10 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@4269.6] assign _T_11 = _T_10[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@4270.6] assign _T_12 = ~ _T_11; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@4271.6] assign _GEN_18 = {{20'd0}, _T_12}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@4272.6] assign _T_13 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@4272.6] assign _T_14 = _T_13 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@4273.6] assign _T_16 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@4275.6] assign _T_17 = 2'h1 << _T_16; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@4276.6] assign _T_19 = _T_17 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@4278.6] assign _T_20 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@4279.6] assign _T_21 = _T_19[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@4280.6] assign _T_22 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@4281.6] assign _T_23 = _T_22 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@4282.6] assign _T_25 = _T_21 & _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4284.6] assign _T_26 = _T_20 | _T_25; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4285.6] assign _T_28 = _T_21 & _T_22; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4287.6] assign _T_29 = _T_20 | _T_28; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4288.6] assign _T_30 = _T_19[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@4289.6] assign _T_31 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@4290.6] assign _T_32 = _T_31 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@4291.6] assign _T_33 = _T_23 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4292.6] assign _T_34 = _T_30 & _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4293.6] assign _T_35 = _T_26 | _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4294.6] assign _T_36 = _T_23 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4295.6] assign _T_37 = _T_30 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4296.6] assign _T_38 = _T_26 | _T_37; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4297.6] assign _T_39 = _T_22 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4298.6] assign _T_40 = _T_30 & _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4299.6] assign _T_41 = _T_29 | _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4300.6] assign _T_42 = _T_22 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@4301.6] assign _T_43 = _T_30 & _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@4302.6] assign _T_44 = _T_29 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@4303.6] assign _T_47 = {_T_44,_T_41,_T_38,_T_35}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@4306.6] assign _T_51 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4310.6] assign _T_68 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@4331.6] assign _T_70 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4334.8] assign _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4335.8] assign _T_72 = $signed(_T_71) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4336.8] assign _T_73 = $signed(_T_72); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4337.8] assign _T_74 = $signed(_T_73) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4338.8] assign _T_75 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4339.8] assign _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4340.8] assign _T_77 = $signed(_T_76) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4341.8] assign _T_78 = $signed(_T_77); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4342.8] assign _T_79 = $signed(_T_78) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4343.8] assign _T_80 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4344.8] assign _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4345.8] assign _T_82 = $signed(_T_81) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4346.8] assign _T_83 = $signed(_T_82); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4347.8] assign _T_84 = $signed(_T_83) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4348.8] assign _T_87 = $signed(_T_51) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4351.8] assign _T_88 = $signed(_T_87); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4352.8] assign _T_89 = $signed(_T_88) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4353.8] assign _T_90 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4354.8] assign _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4355.8] assign _T_92 = $signed(_T_91) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4356.8] assign _T_93 = $signed(_T_92); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4357.8] assign _T_94 = $signed(_T_93) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4358.8] assign _T_95 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4359.8] assign _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4360.8] assign _T_97 = $signed(_T_96) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4361.8] assign _T_98 = $signed(_T_97); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4362.8] assign _T_99 = $signed(_T_98) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4363.8] assign _T_100 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@4364.8] assign _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@4365.8] assign _T_102 = $signed(_T_101) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4366.8] assign _T_103 = $signed(_T_102); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@4367.8] assign _T_104 = $signed(_T_103) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@4368.8] assign _T_105 = _T_74 | _T_79; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4369.8] assign _T_106 = _T_105 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4370.8] assign _T_107 = _T_106 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4371.8] assign _T_108 = _T_107 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4372.8] assign _T_115 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4379.8] assign _T_120 = _T_8 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4392.8] assign _T_121 = _T_120 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4393.8] assign _T_124 = _T_20 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4400.8] assign _T_125 = _T_124 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4401.8] assign _T_127 = _T_14 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4407.8] assign _T_128 = _T_127 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4408.8] assign _T_129 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@4413.8] assign _T_131 = _T_129 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4415.8] assign _T_132 = _T_131 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4416.8] assign _T_133 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@4421.8] assign _T_134 = _T_133 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@4422.8] assign _T_136 = _T_134 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4424.8] assign _T_137 = _T_136 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4425.8] assign _T_138 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@4430.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4432.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4433.8] assign _T_142 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@4439.6] assign _T_207 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@4529.8] assign _T_209 = _T_207 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4531.8] assign _T_210 = _T_209 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4532.8] assign _T_220 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@4555.6] assign _T_222 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4558.8] assign _T_230 = _T_222 & _T_74; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4566.8] assign _T_232 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4568.8] assign _T_265 = _T_79 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4601.8] assign _T_266 = _T_265 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4602.8] assign _T_267 = _T_266 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4603.8] assign _T_268 = _T_267 | _T_99; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4604.8] assign _T_269 = _T_268 | _T_104; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@4605.8] assign _T_270 = _T_232 & _T_269; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4606.8] assign _T_272 = _T_230 | _T_270; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4608.8] assign _T_274 = _T_272 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4610.8] assign _T_275 = _T_274 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4611.8] assign _T_282 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@4630.8] assign _T_284 = _T_282 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4632.8] assign _T_285 = _T_284 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4633.8] assign _T_286 = io_in_a_bits_mask == _T_47; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@4638.8] assign _T_288 = _T_286 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4640.8] assign _T_289 = _T_288 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4641.8] assign _T_294 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@4655.6] assign _T_332 = _T_232 & _T_267; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4694.8] assign _T_341 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4703.8] assign _T_349 = _T_341 & _T_104; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4711.8] assign _T_351 = _T_230 | _T_332; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4713.8] assign _T_353 = _T_351 | _T_349; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@4715.8] assign _T_355 = _T_353 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4717.8] assign _T_356 = _T_355 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4718.8] assign _T_371 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@4754.6] assign _T_444 = ~ _T_47; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@4844.8] assign _T_445 = io_in_a_bits_mask & _T_444; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@4845.8] assign _T_446 = _T_445 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@4846.8] assign _T_448 = _T_446 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4848.8] assign _T_449 = _T_448 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4849.8] assign _T_450 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@4855.6] assign _T_452 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@4858.8] assign _T_484 = _T_452 & _T_108; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@4890.8] assign _T_501 = _T_484 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4907.8] assign _T_502 = _T_501 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4908.8] assign _T_509 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@4927.8] assign _T_511 = _T_509 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4929.8] assign _T_512 = _T_511 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4930.8] assign _T_517 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@4944.6] assign _T_576 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@5016.8] assign _T_578 = _T_576 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5018.8] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5019.8] assign _T_584 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@5033.6] assign _T_635 = _T_230 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5085.8] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5086.8] assign _T_651 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@5124.6] assign _T_653 = _T_651 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5126.6] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5127.6] assign _T_656 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@5133.6] assign _T_658 = io_in_d_bits_source | _T_656; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@5138.6] assign _T_660 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@5140.6] assign _T_662 = _T_658 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5143.8] assign _T_663 = _T_662 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5144.8] assign _T_664 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@5149.8] assign _T_666 = _T_664 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5151.8] assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5152.8] assign _T_668 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@5157.8] assign _T_670 = _T_668 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5159.8] assign _T_671 = _T_670 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5160.8] assign _T_672 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@5165.8] assign _T_674 = _T_672 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5167.8] assign _T_675 = _T_674 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5168.8] assign _T_676 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@5173.8] assign _T_678 = _T_676 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5175.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5176.8] assign _T_680 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@5182.6] assign _T_691 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@5206.8] assign _T_693 = _T_691 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5208.8] assign _T_694 = _T_693 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5209.8] assign _T_695 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@5214.8] assign _T_697 = _T_695 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5216.8] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5217.8] assign _T_708 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@5240.6] assign _T_728 = _T_676 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@5281.8] assign _T_730 = _T_728 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5283.8] assign _T_731 = _T_730 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5284.8] assign _T_737 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@5299.6] assign _T_754 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@5334.6] assign _T_772 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@5370.6] assign _T_801 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@5430.4] assign _T_806 = _T_12[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@5435.4] assign _T_807 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@5436.4] assign _T_808 = _T_807 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@5437.4] assign _T_812 = _T_810 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5441.4] assign _T_813 = _T_810 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5442.4] assign _T_826 = _T_813 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@5458.4] assign _T_827 = io_in_a_valid & _T_826; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@5459.4] assign _T_828 = io_in_a_bits_opcode == _T_821; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@5461.6] assign _T_830 = _T_828 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5463.6] assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5464.6] assign _T_832 = io_in_a_bits_param == _T_822; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@5469.6] assign _T_834 = _T_832 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5471.6] assign _T_835 = _T_834 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5472.6] assign _T_836 = io_in_a_bits_size == _T_823; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@5477.6] assign _T_838 = _T_836 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5479.6] assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5480.6] assign _T_840 = io_in_a_bits_source == _T_824; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@5485.6] assign _T_842 = _T_840 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5487.6] assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5488.6] assign _T_844 = io_in_a_bits_address == _T_825; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@5493.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5495.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5496.6] assign _T_849 = _T_801 & _T_813; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@5503.4] assign _T_850 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@5511.4] assign _T_852 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@5513.4] assign _T_853 = _T_852[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@5514.4] assign _T_854 = ~ _T_853; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@5515.4] assign _T_855 = _T_854[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@5516.4] assign _T_856 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@5517.4] assign _T_860 = _T_858 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5521.4] assign _T_861 = _T_858 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5522.4] assign _T_875 = _T_861 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@5539.4] assign _T_876 = io_in_d_valid & _T_875; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@5540.4] assign _T_877 = io_in_d_bits_opcode == _T_869; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@5542.6] assign _T_879 = _T_877 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5544.6] assign _T_880 = _T_879 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5545.6] assign _T_881 = io_in_d_bits_param == _T_870; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@5550.6] assign _T_883 = _T_881 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5552.6] assign _T_884 = _T_883 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5553.6] assign _T_885 = io_in_d_bits_size == _T_871; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@5558.6] assign _T_887 = _T_885 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5560.6] assign _T_888 = _T_887 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5561.6] assign _T_889 = io_in_d_bits_source == _T_872; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@5566.6] assign _T_891 = _T_889 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5568.6] assign _T_892 = _T_891 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5569.6] assign _T_893 = io_in_d_bits_sink == _T_873; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@5574.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5576.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5577.6] assign _T_897 = io_in_d_bits_denied == _T_874; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@5582.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5584.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5585.6] assign _T_902 = _T_850 & _T_861; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@5592.4] assign _T_915 = _T_913 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5613.4] assign _T_916 = _T_913 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5614.4] assign _T_934 = _T_932 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@5635.4] assign _T_935 = _T_932 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@5636.4] assign _T_945 = _T_801 & _T_916; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@5651.4] assign _T_947 = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@5654.6] assign _T_948 = _T_903 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@5656.6] assign _T_949 = _T_948[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@5657.6] assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@5658.6] assign _T_952 = _T_950 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5660.6] assign _T_953 = _T_952 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5661.6] assign _GEN_15 = _T_945 ? _T_947 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@5653.4] assign _T_957 = _T_850 & _T_935; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@5672.4] assign _T_959 = _T_660 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@5674.4] assign _T_960 = _T_957 & _T_959; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@5675.4] assign _T_961 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@5677.6] assign _T_962 = _GEN_15 | _T_903; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@5679.6] assign _T_963 = _T_962 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@5680.6] assign _T_964 = _T_963[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@5681.6] assign _T_966 = _T_964 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5683.6] assign _T_967 = _T_966 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5684.6] assign _GEN_16 = _T_960 ? _T_961 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@5676.4] assign _T_968 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@5690.4] assign _T_969 = _GEN_15 != 2'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@5691.4] assign _T_970 = _T_969 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@5692.4] assign _T_971 = _T_968 | _T_970; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@5693.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5695.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5696.4] assign _T_975 = _T_903 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@5701.4] assign _T_976 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@5702.4] assign _T_977 = _T_975 & _T_976; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@5703.4] assign _T_979 = _T_903 != 2'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@5708.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@5709.4] assign _T_981 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@5710.4] assign _T_982 = _T_980 | _T_981; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@5711.4] assign _T_983 = _T_978 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@5712.4] assign _T_984 = _T_982 | _T_983; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@5713.4] assign _T_986 = _T_984 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5715.4] assign _T_987 = _T_986 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5716.4] assign _T_989 = _T_978 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@5722.4] assign _T_992 = _T_801 | _T_850; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@5726.4] assign _GEN_19 = io_in_a_valid & _T_68; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4381.10] assign _GEN_35 = io_in_a_valid & _T_142; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@4489.10] assign _GEN_53 = io_in_a_valid & _T_220; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4613.10] assign _GEN_65 = io_in_a_valid & _T_294; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4720.10] assign _GEN_75 = io_in_a_valid & _T_371; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@4819.10] assign _GEN_85 = io_in_a_valid & _T_450; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4910.10] assign _GEN_95 = io_in_a_valid & _T_517; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@4999.10] assign _GEN_105 = io_in_a_valid & _T_584; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5088.10] assign _GEN_115 = io_in_d_valid & _T_660; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5146.10] assign _GEN_125 = io_in_d_valid & _T_680; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@5188.10] assign _GEN_137 = io_in_d_valid & _T_708; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@5246.10] assign _GEN_149 = io_in_d_valid & _T_737; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@5305.10] assign _GEN_155 = io_in_d_valid & _T_754; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@5340.10] assign _GEN_161 = io_in_d_valid & _T_772; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@5376.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_810 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_821 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_822 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_823 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_824 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_825 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_858 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_869 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_870 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_871 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_872 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_873 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_874 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_903 = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_913 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_932 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_978 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_810 <= 10'h0; end else begin if (_T_801) begin if (_T_813) begin if (_T_808) begin _T_810 <= _T_806; end else begin _T_810 <= 10'h0; end end else begin _T_810 <= _T_812; end end end if (_T_849) begin _T_821 <= io_in_a_bits_opcode; end if (_T_849) begin _T_822 <= io_in_a_bits_param; end if (_T_849) begin _T_823 <= io_in_a_bits_size; end if (_T_849) begin _T_824 <= io_in_a_bits_source; end if (_T_849) begin _T_825 <= io_in_a_bits_address; end if (reset) begin _T_858 <= 10'h0; end else begin if (_T_850) begin if (_T_861) begin if (_T_856) begin _T_858 <= _T_855; end else begin _T_858 <= 10'h0; end end else begin _T_858 <= _T_860; end end end if (_T_902) begin _T_869 <= io_in_d_bits_opcode; end if (_T_902) begin _T_870 <= io_in_d_bits_param; end if (_T_902) begin _T_871 <= io_in_d_bits_size; end if (_T_902) begin _T_872 <= io_in_d_bits_source; end if (_T_902) begin _T_873 <= io_in_d_bits_sink; end if (_T_902) begin _T_874 <= io_in_d_bits_denied; end if (reset) begin _T_903 <= 2'h0; end else begin _T_903 <= _T_977; end if (reset) begin _T_913 <= 10'h0; end else begin if (_T_801) begin if (_T_916) begin if (_T_808) begin _T_913 <= _T_806; end else begin _T_913 <= 10'h0; end end else begin _T_913 <= _T_915; end end end if (reset) begin _T_932 <= 10'h0; end else begin if (_T_850) begin if (_T_935) begin if (_T_856) begin _T_932 <= _T_855; end else begin _T_932 <= 10'h0; end end else begin _T_932 <= _T_934; end end end if (reset) begin _T_978 <= 32'h0; end else begin if (_T_992) begin _T_978 <= 32'h0; end else begin _T_978 <= _T_989; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4381.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@4382.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:37:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@4388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@4389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4395.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_121) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@4396.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:37:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4403.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_125) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@4404.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_128) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@4411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:37:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4418.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_132) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@4419.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_137) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@4428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4435.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_141) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@4436.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@4489.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@4490.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:37:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@4496.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@4497.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@4503.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_121) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@4504.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:37:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@4511.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_125) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@4512.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@4518.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_128) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@4519.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:37:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@4526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_132) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@4527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_210) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:37:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4534.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_210) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@4535.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@4543.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_137) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@4544.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@4551.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@4552.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_275) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4613.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_275) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@4614.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@4620.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_121) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@4621.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@4627.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_128) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@4628.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4635.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_285) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@4636.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4643.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_289) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@4644.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@4651.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_141) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@4652.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4720.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_356) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@4721.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@4727.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_121) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@4728.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@4734.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_128) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@4735.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@4742.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_285) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@4743.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@4750.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_289) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@4751.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@4819.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_356) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@4820.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@4826.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_121) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@4827.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@4833.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_128) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@4834.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@4841.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_285) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@4842.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_449) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4851.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_449) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@4852.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4910.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_502) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@4911.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@4917.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_121) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@4918.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@4924.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_128) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@4925.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_512) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:37:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4932.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_512) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@4933.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@4940.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_289) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@4941.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@4999.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_502) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@5000.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@5006.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_121) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@5007.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@5013.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_128) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@5014.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:37:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5021.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_579) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@5022.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@5029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_289) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@5030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:37:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5088.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_636) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@5089.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@5095.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_121) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@5096.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:37:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@5102.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_128) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@5103.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:37:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@5110.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_289) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@5111.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@5118.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_141) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@5119.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:37:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5129.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_654) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@5130.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5146.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_663) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@5147.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:37:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5154.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_667) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@5155.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5162.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_671) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@5163.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5170.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_675) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@5171.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:37:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5178.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@5179.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@5188.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_663) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@5189.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@5195.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_115) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@5196.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:37:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@5203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_667) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@5204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:37:39)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5211.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_694) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@5212.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:37:39)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5219.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_698) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@5220.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@5227.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_675) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@5228.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@5246.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_663) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@5247.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@5253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_115) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@5254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:37:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@5261.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_667) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@5262.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:37:39)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@5269.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_694) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@5270.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:37:39)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@5277.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_698) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@5278.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5286.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_731) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@5287.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@5305.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_663) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@5306.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@5313.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_671) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@5314.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@5321.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_675) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@5322.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@5340.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_663) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@5341.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@5348.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_671) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@5349.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@5357.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_731) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@5358.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@5376.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_663) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@5377.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:37:39)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@5384.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_671) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@5385.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:37:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@5392.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_675) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@5393.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_831) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5466.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_831) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@5467.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_835) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5474.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_835) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@5475.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_839) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5482.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_839) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@5483.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_843) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5490.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_843) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@5491.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5498.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_847) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@5499.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_880) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5547.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_880) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@5548.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_884) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5555.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_884) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@5556.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_888) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5563.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_888) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@5564.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_892) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5571.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_892) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@5572.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5579.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_896) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@5580.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:37:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5587.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_900) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@5588.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_945 & _T_953) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:37:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5663.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_945 & _T_953) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@5664.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_960 & _T_967) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:37:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5686.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_960 & _T_967) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@5687.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:37:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5698.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@5699.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:37:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5718.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@5719.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLBuffer( // @[:freechips.rocketchip.system.TinyConfig.fir@5731.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@5732.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@5733.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@5734.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] TLMonitor_2 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@5741.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@5793.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@5792.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@5743.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@5744.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@5789.4] endmodule module TLMonitor_3( // @[:freechips.rocketchip.system.TinyConfig.fir@5823.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@5824.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@5825.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@5826.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@7286.4] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@5842.6] wire _T_8; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@5847.6] wire [26:0] _T_10; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@5849.6] wire [11:0] _T_11; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@5850.6] wire [11:0] _T_12; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@5851.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@5852.6] wire [31:0] _T_13; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@5852.6] wire _T_14; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@5853.6] wire _T_16; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@5855.6] wire [1:0] _T_17; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@5856.6] wire [1:0] _T_19; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@5858.6] wire _T_20; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@5859.6] wire _T_21; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@5860.6] wire _T_22; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@5861.6] wire _T_23; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@5862.6] wire _T_25; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5864.6] wire _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5865.6] wire _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5867.6] wire _T_29; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5868.6] wire _T_30; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@5869.6] wire _T_31; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@5870.6] wire _T_32; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@5871.6] wire _T_33; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5872.6] wire _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5873.6] wire _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5874.6] wire _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5875.6] wire _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5876.6] wire _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5877.6] wire _T_39; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5878.6] wire _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5879.6] wire _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5880.6] wire _T_42; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5881.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5882.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5883.6] wire [3:0] _T_47; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@5886.6] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5890.6] wire _T_68; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@5911.6] wire [31:0] _T_70; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5914.8] wire [32:0] _T_71; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5915.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5916.8] wire [32:0] _T_73; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5917.8] wire _T_74; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5918.8] wire [31:0] _T_75; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5919.8] wire [32:0] _T_76; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5920.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5921.8] wire [32:0] _T_78; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5922.8] wire _T_79; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5923.8] wire [31:0] _T_80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5924.8] wire [32:0] _T_81; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5925.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5926.8] wire [32:0] _T_83; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5927.8] wire _T_84; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5928.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5931.8] wire [32:0] _T_88; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5932.8] wire _T_89; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5933.8] wire [31:0] _T_90; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5934.8] wire [32:0] _T_91; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5935.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5936.8] wire [32:0] _T_93; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5937.8] wire _T_94; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5938.8] wire [31:0] _T_95; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5939.8] wire [32:0] _T_96; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5940.8] wire [32:0] _T_97; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5941.8] wire [32:0] _T_98; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5942.8] wire _T_99; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5943.8] wire [31:0] _T_100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5944.8] wire [32:0] _T_101; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5945.8] wire [32:0] _T_102; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5946.8] wire [32:0] _T_103; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5947.8] wire _T_104; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5948.8] wire _T_105; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5949.8] wire _T_106; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5950.8] wire _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5951.8] wire _T_108; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5952.8] wire _T_115; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5959.8] wire _T_120; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5972.8] wire _T_121; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5973.8] wire _T_124; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5980.8] wire _T_125; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5981.8] wire _T_127; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5987.8] wire _T_128; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5988.8] wire _T_129; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@5993.8] wire _T_131; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5995.8] wire _T_132; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5996.8] wire [3:0] _T_133; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@6001.8] wire _T_134; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@6002.8] wire _T_136; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6004.8] wire _T_137; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6005.8] wire _T_138; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@6010.8] wire _T_140; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6012.8] wire _T_141; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6013.8] wire _T_142; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@6019.6] wire _T_207; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@6109.8] wire _T_209; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6111.8] wire _T_210; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6112.8] wire _T_220; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@6135.6] wire _T_222; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6138.8] wire _T_230; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6146.8] wire _T_232; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6148.8] wire _T_265; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6181.8] wire _T_266; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6182.8] wire _T_267; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6183.8] wire _T_268; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6184.8] wire _T_269; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6185.8] wire _T_270; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6186.8] wire _T_272; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6188.8] wire _T_274; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6190.8] wire _T_275; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6191.8] wire _T_282; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@6210.8] wire _T_284; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6212.8] wire _T_285; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6213.8] wire _T_286; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@6218.8] wire _T_288; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6220.8] wire _T_289; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6221.8] wire _T_294; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@6235.6] wire _T_332; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6274.8] wire _T_341; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6283.8] wire _T_349; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6291.8] wire _T_351; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6293.8] wire _T_353; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6295.8] wire _T_355; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6297.8] wire _T_356; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6298.8] wire _T_371; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@6334.6] wire [3:0] _T_444; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@6424.8] wire [3:0] _T_445; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@6425.8] wire _T_446; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@6426.8] wire _T_448; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6428.8] wire _T_449; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6429.8] wire _T_450; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@6435.6] wire _T_452; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6438.8] wire _T_484; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6470.8] wire _T_501; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6487.8] wire _T_502; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6488.8] wire _T_509; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@6507.8] wire _T_511; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6509.8] wire _T_512; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6510.8] wire _T_517; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@6524.6] wire _T_576; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@6596.8] wire _T_578; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6598.8] wire _T_579; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6599.8] wire _T_584; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@6613.6] wire _T_635; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6665.8] wire _T_636; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6666.8] wire _T_651; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@6704.6] wire _T_653; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6706.6] wire _T_654; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6707.6] wire _T_656; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@6713.6] wire _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@6718.6] wire _T_660; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@6720.6] wire _T_662; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6723.8] wire _T_663; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6724.8] wire _T_664; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@6729.8] wire _T_666; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6731.8] wire _T_667; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6732.8] wire _T_668; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@6737.8] wire _T_670; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6739.8] wire _T_671; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6740.8] wire _T_672; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@6745.8] wire _T_674; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6747.8] wire _T_675; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6748.8] wire _T_676; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@6753.8] wire _T_678; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6755.8] wire _T_679; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6756.8] wire _T_680; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@6762.6] wire _T_691; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@6786.8] wire _T_693; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6788.8] wire _T_694; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6789.8] wire _T_695; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@6794.8] wire _T_697; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6796.8] wire _T_698; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6797.8] wire _T_708; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@6820.6] wire _T_728; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@6861.8] wire _T_730; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6863.8] wire _T_731; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6864.8] wire _T_737; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@6879.6] wire _T_754; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@6914.6] wire _T_772; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@6950.6] wire _T_801; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@7010.4] wire [9:0] _T_806; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@7015.4] wire _T_807; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@7016.4] wire _T_808; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@7017.4] reg [9:0] _T_810; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@7019.4] reg [31:0] _RAND_0; wire [9:0] _T_812; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7021.4] wire _T_813; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7022.4] reg [2:0] _T_821; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@7033.4] reg [31:0] _RAND_1; reg [2:0] _T_822; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@7034.4] reg [31:0] _RAND_2; reg [3:0] _T_823; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@7035.4] reg [31:0] _RAND_3; reg _T_824; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@7036.4] reg [31:0] _RAND_4; reg [31:0] _T_825; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@7037.4] reg [31:0] _RAND_5; wire _T_826; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@7038.4] wire _T_827; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@7039.4] wire _T_828; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@7041.6] wire _T_830; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7043.6] wire _T_831; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7044.6] wire _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@7049.6] wire _T_834; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7051.6] wire _T_835; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7052.6] wire _T_836; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@7057.6] wire _T_838; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7059.6] wire _T_839; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7060.6] wire _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@7065.6] wire _T_842; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7067.6] wire _T_843; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7068.6] wire _T_844; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@7073.6] wire _T_846; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7075.6] wire _T_847; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7076.6] wire _T_849; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@7083.4] wire _T_850; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@7091.4] wire [26:0] _T_852; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@7093.4] wire [11:0] _T_853; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@7094.4] wire [11:0] _T_854; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@7095.4] wire [9:0] _T_855; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@7096.4] wire _T_856; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@7097.4] reg [9:0] _T_858; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@7099.4] reg [31:0] _RAND_6; wire [9:0] _T_860; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7101.4] wire _T_861; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7102.4] reg [2:0] _T_869; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@7113.4] reg [31:0] _RAND_7; reg [1:0] _T_870; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@7114.4] reg [31:0] _RAND_8; reg [3:0] _T_871; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@7115.4] reg [31:0] _RAND_9; reg _T_872; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@7116.4] reg [31:0] _RAND_10; reg _T_873; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@7117.4] reg [31:0] _RAND_11; reg _T_874; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@7118.4] reg [31:0] _RAND_12; wire _T_875; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@7119.4] wire _T_876; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@7120.4] wire _T_877; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@7122.6] wire _T_879; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7124.6] wire _T_880; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7125.6] wire _T_881; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@7130.6] wire _T_883; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7132.6] wire _T_884; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7133.6] wire _T_885; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@7138.6] wire _T_887; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7140.6] wire _T_888; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7141.6] wire _T_889; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@7146.6] wire _T_891; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7148.6] wire _T_892; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7149.6] wire _T_893; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@7154.6] wire _T_895; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7156.6] wire _T_896; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7157.6] wire _T_897; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@7162.6] wire _T_899; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7164.6] wire _T_900; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7165.6] wire _T_902; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@7172.4] reg [1:0] _T_903; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@7181.4] reg [31:0] _RAND_13; reg [9:0] _T_913; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@7191.4] reg [31:0] _RAND_14; wire [9:0] _T_915; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7193.4] wire _T_916; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7194.4] reg [9:0] _T_932; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@7213.4] reg [31:0] _RAND_15; wire [9:0] _T_934; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7215.4] wire _T_935; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7216.4] wire _T_945; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@7231.4] wire [1:0] _T_947; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@7234.6] wire [1:0] _T_948; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@7236.6] wire _T_949; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@7237.6] wire _T_950; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@7238.6] wire _T_952; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7240.6] wire _T_953; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7241.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@7233.4] wire _T_957; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@7252.4] wire _T_959; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@7254.4] wire _T_960; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@7255.4] wire [1:0] _T_961; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@7257.6] wire [1:0] _T_962; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@7259.6] wire [1:0] _T_963; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@7260.6] wire _T_964; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@7261.6] wire _T_966; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7263.6] wire _T_967; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7264.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@7256.4] wire _T_968; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@7270.4] wire _T_969; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@7271.4] wire _T_970; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@7272.4] wire _T_971; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@7273.4] wire _T_973; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7275.4] wire _T_974; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7276.4] wire [1:0] _T_975; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@7281.4] wire [1:0] _T_976; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@7282.4] wire [1:0] _T_977; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@7283.4] reg [31:0] _T_978; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@7285.4] reg [31:0] _RAND_16; wire _T_979; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@7288.4] wire _T_980; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@7289.4] wire _T_981; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@7290.4] wire _T_982; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@7291.4] wire _T_983; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@7292.4] wire _T_984; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@7293.4] wire _T_986; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7295.4] wire _T_987; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7296.4] wire [31:0] _T_989; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@7302.4] wire _T_992; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@7306.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5961.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@6069.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6193.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6300.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@6399.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6490.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@6579.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6668.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6726.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@6768.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@6826.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@6885.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@6920.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@6956.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@7286.4] .out(plusarg_reader_out) ); assign _T_6 = io_in_a_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@5842.6] assign _T_8 = io_in_a_bits_source | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@5847.6] assign _T_10 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@5849.6] assign _T_11 = _T_10[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@5850.6] assign _T_12 = ~ _T_11; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@5851.6] assign _GEN_18 = {{20'd0}, _T_12}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@5852.6] assign _T_13 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@5852.6] assign _T_14 = _T_13 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@5853.6] assign _T_16 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@5855.6] assign _T_17 = 2'h1 << _T_16; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@5856.6] assign _T_19 = _T_17 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@5858.6] assign _T_20 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@5859.6] assign _T_21 = _T_19[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@5860.6] assign _T_22 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@5861.6] assign _T_23 = _T_22 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@5862.6] assign _T_25 = _T_21 & _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5864.6] assign _T_26 = _T_20 | _T_25; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5865.6] assign _T_28 = _T_21 & _T_22; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5867.6] assign _T_29 = _T_20 | _T_28; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5868.6] assign _T_30 = _T_19[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@5869.6] assign _T_31 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@5870.6] assign _T_32 = _T_31 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@5871.6] assign _T_33 = _T_23 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5872.6] assign _T_34 = _T_30 & _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5873.6] assign _T_35 = _T_26 | _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5874.6] assign _T_36 = _T_23 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5875.6] assign _T_37 = _T_30 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5876.6] assign _T_38 = _T_26 | _T_37; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5877.6] assign _T_39 = _T_22 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5878.6] assign _T_40 = _T_30 & _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5879.6] assign _T_41 = _T_29 | _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5880.6] assign _T_42 = _T_22 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@5881.6] assign _T_43 = _T_30 & _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@5882.6] assign _T_44 = _T_29 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@5883.6] assign _T_47 = {_T_44,_T_41,_T_38,_T_35}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@5886.6] assign _T_51 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5890.6] assign _T_68 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@5911.6] assign _T_70 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5914.8] assign _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5915.8] assign _T_72 = $signed(_T_71) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5916.8] assign _T_73 = $signed(_T_72); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5917.8] assign _T_74 = $signed(_T_73) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5918.8] assign _T_75 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5919.8] assign _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5920.8] assign _T_77 = $signed(_T_76) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5921.8] assign _T_78 = $signed(_T_77); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5922.8] assign _T_79 = $signed(_T_78) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5923.8] assign _T_80 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5924.8] assign _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5925.8] assign _T_82 = $signed(_T_81) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5926.8] assign _T_83 = $signed(_T_82); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5927.8] assign _T_84 = $signed(_T_83) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5928.8] assign _T_87 = $signed(_T_51) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5931.8] assign _T_88 = $signed(_T_87); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5932.8] assign _T_89 = $signed(_T_88) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5933.8] assign _T_90 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5934.8] assign _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5935.8] assign _T_92 = $signed(_T_91) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5936.8] assign _T_93 = $signed(_T_92); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5937.8] assign _T_94 = $signed(_T_93) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5938.8] assign _T_95 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5939.8] assign _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5940.8] assign _T_97 = $signed(_T_96) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5941.8] assign _T_98 = $signed(_T_97); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5942.8] assign _T_99 = $signed(_T_98) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5943.8] assign _T_100 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@5944.8] assign _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@5945.8] assign _T_102 = $signed(_T_101) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5946.8] assign _T_103 = $signed(_T_102); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@5947.8] assign _T_104 = $signed(_T_103) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@5948.8] assign _T_105 = _T_74 | _T_79; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5949.8] assign _T_106 = _T_105 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5950.8] assign _T_107 = _T_106 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5951.8] assign _T_108 = _T_107 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@5952.8] assign _T_115 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5959.8] assign _T_120 = _T_8 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5972.8] assign _T_121 = _T_120 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5973.8] assign _T_124 = _T_20 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5980.8] assign _T_125 = _T_124 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5981.8] assign _T_127 = _T_14 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5987.8] assign _T_128 = _T_127 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5988.8] assign _T_129 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@5993.8] assign _T_131 = _T_129 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5995.8] assign _T_132 = _T_131 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5996.8] assign _T_133 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@6001.8] assign _T_134 = _T_133 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@6002.8] assign _T_136 = _T_134 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6004.8] assign _T_137 = _T_136 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6005.8] assign _T_138 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@6010.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6012.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6013.8] assign _T_142 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@6019.6] assign _T_207 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@6109.8] assign _T_209 = _T_207 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6111.8] assign _T_210 = _T_209 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6112.8] assign _T_220 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@6135.6] assign _T_222 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6138.8] assign _T_230 = _T_222 & _T_74; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6146.8] assign _T_232 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6148.8] assign _T_265 = _T_79 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6181.8] assign _T_266 = _T_265 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6182.8] assign _T_267 = _T_266 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6183.8] assign _T_268 = _T_267 | _T_99; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6184.8] assign _T_269 = _T_268 | _T_104; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@6185.8] assign _T_270 = _T_232 & _T_269; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6186.8] assign _T_272 = _T_230 | _T_270; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6188.8] assign _T_274 = _T_272 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6190.8] assign _T_275 = _T_274 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6191.8] assign _T_282 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@6210.8] assign _T_284 = _T_282 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6212.8] assign _T_285 = _T_284 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6213.8] assign _T_286 = io_in_a_bits_mask == _T_47; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@6218.8] assign _T_288 = _T_286 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6220.8] assign _T_289 = _T_288 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6221.8] assign _T_294 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@6235.6] assign _T_332 = _T_232 & _T_267; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6274.8] assign _T_341 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6283.8] assign _T_349 = _T_341 & _T_104; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6291.8] assign _T_351 = _T_230 | _T_332; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6293.8] assign _T_353 = _T_351 | _T_349; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@6295.8] assign _T_355 = _T_353 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6297.8] assign _T_356 = _T_355 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6298.8] assign _T_371 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@6334.6] assign _T_444 = ~ _T_47; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@6424.8] assign _T_445 = io_in_a_bits_mask & _T_444; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@6425.8] assign _T_446 = _T_445 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@6426.8] assign _T_448 = _T_446 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6428.8] assign _T_449 = _T_448 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6429.8] assign _T_450 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@6435.6] assign _T_452 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@6438.8] assign _T_484 = _T_452 & _T_108; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@6470.8] assign _T_501 = _T_484 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6487.8] assign _T_502 = _T_501 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6488.8] assign _T_509 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@6507.8] assign _T_511 = _T_509 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6509.8] assign _T_512 = _T_511 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6510.8] assign _T_517 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@6524.6] assign _T_576 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@6596.8] assign _T_578 = _T_576 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6598.8] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6599.8] assign _T_584 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@6613.6] assign _T_635 = _T_230 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6665.8] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6666.8] assign _T_651 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@6704.6] assign _T_653 = _T_651 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6706.6] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6707.6] assign _T_656 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@6713.6] assign _T_658 = io_in_d_bits_source | _T_656; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@6718.6] assign _T_660 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@6720.6] assign _T_662 = _T_658 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6723.8] assign _T_663 = _T_662 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6724.8] assign _T_664 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@6729.8] assign _T_666 = _T_664 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6731.8] assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6732.8] assign _T_668 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@6737.8] assign _T_670 = _T_668 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6739.8] assign _T_671 = _T_670 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6740.8] assign _T_672 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@6745.8] assign _T_674 = _T_672 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6747.8] assign _T_675 = _T_674 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6748.8] assign _T_676 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@6753.8] assign _T_678 = _T_676 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6755.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6756.8] assign _T_680 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@6762.6] assign _T_691 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@6786.8] assign _T_693 = _T_691 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6788.8] assign _T_694 = _T_693 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6789.8] assign _T_695 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@6794.8] assign _T_697 = _T_695 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6796.8] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6797.8] assign _T_708 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@6820.6] assign _T_728 = _T_676 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@6861.8] assign _T_730 = _T_728 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6863.8] assign _T_731 = _T_730 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6864.8] assign _T_737 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@6879.6] assign _T_754 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@6914.6] assign _T_772 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@6950.6] assign _T_801 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@7010.4] assign _T_806 = _T_12[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@7015.4] assign _T_807 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@7016.4] assign _T_808 = _T_807 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@7017.4] assign _T_812 = _T_810 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7021.4] assign _T_813 = _T_810 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7022.4] assign _T_826 = _T_813 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@7038.4] assign _T_827 = io_in_a_valid & _T_826; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@7039.4] assign _T_828 = io_in_a_bits_opcode == _T_821; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@7041.6] assign _T_830 = _T_828 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7043.6] assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7044.6] assign _T_832 = io_in_a_bits_param == _T_822; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@7049.6] assign _T_834 = _T_832 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7051.6] assign _T_835 = _T_834 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7052.6] assign _T_836 = io_in_a_bits_size == _T_823; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@7057.6] assign _T_838 = _T_836 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7059.6] assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7060.6] assign _T_840 = io_in_a_bits_source == _T_824; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@7065.6] assign _T_842 = _T_840 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7067.6] assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7068.6] assign _T_844 = io_in_a_bits_address == _T_825; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@7073.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7075.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7076.6] assign _T_849 = _T_801 & _T_813; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@7083.4] assign _T_850 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@7091.4] assign _T_852 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@7093.4] assign _T_853 = _T_852[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@7094.4] assign _T_854 = ~ _T_853; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@7095.4] assign _T_855 = _T_854[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@7096.4] assign _T_856 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@7097.4] assign _T_860 = _T_858 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7101.4] assign _T_861 = _T_858 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7102.4] assign _T_875 = _T_861 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@7119.4] assign _T_876 = io_in_d_valid & _T_875; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@7120.4] assign _T_877 = io_in_d_bits_opcode == _T_869; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@7122.6] assign _T_879 = _T_877 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7124.6] assign _T_880 = _T_879 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7125.6] assign _T_881 = io_in_d_bits_param == _T_870; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@7130.6] assign _T_883 = _T_881 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7132.6] assign _T_884 = _T_883 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7133.6] assign _T_885 = io_in_d_bits_size == _T_871; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@7138.6] assign _T_887 = _T_885 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7140.6] assign _T_888 = _T_887 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7141.6] assign _T_889 = io_in_d_bits_source == _T_872; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@7146.6] assign _T_891 = _T_889 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7148.6] assign _T_892 = _T_891 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7149.6] assign _T_893 = io_in_d_bits_sink == _T_873; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@7154.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7156.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7157.6] assign _T_897 = io_in_d_bits_denied == _T_874; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@7162.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7164.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7165.6] assign _T_902 = _T_850 & _T_861; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@7172.4] assign _T_915 = _T_913 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7193.4] assign _T_916 = _T_913 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7194.4] assign _T_934 = _T_932 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@7215.4] assign _T_935 = _T_932 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@7216.4] assign _T_945 = _T_801 & _T_916; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@7231.4] assign _T_947 = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@7234.6] assign _T_948 = _T_903 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@7236.6] assign _T_949 = _T_948[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@7237.6] assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@7238.6] assign _T_952 = _T_950 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7240.6] assign _T_953 = _T_952 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7241.6] assign _GEN_15 = _T_945 ? _T_947 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@7233.4] assign _T_957 = _T_850 & _T_935; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@7252.4] assign _T_959 = _T_660 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@7254.4] assign _T_960 = _T_957 & _T_959; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@7255.4] assign _T_961 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@7257.6] assign _T_962 = _GEN_15 | _T_903; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@7259.6] assign _T_963 = _T_962 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@7260.6] assign _T_964 = _T_963[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@7261.6] assign _T_966 = _T_964 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7263.6] assign _T_967 = _T_966 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7264.6] assign _GEN_16 = _T_960 ? _T_961 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@7256.4] assign _T_968 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@7270.4] assign _T_969 = _GEN_15 != 2'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@7271.4] assign _T_970 = _T_969 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@7272.4] assign _T_971 = _T_968 | _T_970; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@7273.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7275.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7276.4] assign _T_975 = _T_903 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@7281.4] assign _T_976 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@7282.4] assign _T_977 = _T_975 & _T_976; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@7283.4] assign _T_979 = _T_903 != 2'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@7288.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@7289.4] assign _T_981 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@7290.4] assign _T_982 = _T_980 | _T_981; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@7291.4] assign _T_983 = _T_978 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@7292.4] assign _T_984 = _T_982 | _T_983; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@7293.4] assign _T_986 = _T_984 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7295.4] assign _T_987 = _T_986 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7296.4] assign _T_989 = _T_978 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@7302.4] assign _T_992 = _T_801 | _T_850; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@7306.4] assign _GEN_19 = io_in_a_valid & _T_68; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5961.10] assign _GEN_35 = io_in_a_valid & _T_142; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@6069.10] assign _GEN_53 = io_in_a_valid & _T_220; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6193.10] assign _GEN_65 = io_in_a_valid & _T_294; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6300.10] assign _GEN_75 = io_in_a_valid & _T_371; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@6399.10] assign _GEN_85 = io_in_a_valid & _T_450; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6490.10] assign _GEN_95 = io_in_a_valid & _T_517; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@6579.10] assign _GEN_105 = io_in_a_valid & _T_584; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6668.10] assign _GEN_115 = io_in_d_valid & _T_660; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6726.10] assign _GEN_125 = io_in_d_valid & _T_680; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@6768.10] assign _GEN_137 = io_in_d_valid & _T_708; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@6826.10] assign _GEN_149 = io_in_d_valid & _T_737; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@6885.10] assign _GEN_155 = io_in_d_valid & _T_754; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@6920.10] assign _GEN_161 = io_in_d_valid & _T_772; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@6956.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_810 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_821 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_822 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_823 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_824 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_825 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_858 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_869 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_870 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_871 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_872 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_873 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_874 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_903 = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_913 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_932 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_978 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_810 <= 10'h0; end else begin if (_T_801) begin if (_T_813) begin if (_T_808) begin _T_810 <= _T_806; end else begin _T_810 <= 10'h0; end end else begin _T_810 <= _T_812; end end end if (_T_849) begin _T_821 <= io_in_a_bits_opcode; end if (_T_849) begin _T_822 <= io_in_a_bits_param; end if (_T_849) begin _T_823 <= io_in_a_bits_size; end if (_T_849) begin _T_824 <= io_in_a_bits_source; end if (_T_849) begin _T_825 <= io_in_a_bits_address; end if (reset) begin _T_858 <= 10'h0; end else begin if (_T_850) begin if (_T_861) begin if (_T_856) begin _T_858 <= _T_855; end else begin _T_858 <= 10'h0; end end else begin _T_858 <= _T_860; end end end if (_T_902) begin _T_869 <= io_in_d_bits_opcode; end if (_T_902) begin _T_870 <= io_in_d_bits_param; end if (_T_902) begin _T_871 <= io_in_d_bits_size; end if (_T_902) begin _T_872 <= io_in_d_bits_source; end if (_T_902) begin _T_873 <= io_in_d_bits_sink; end if (_T_902) begin _T_874 <= io_in_d_bits_denied; end if (reset) begin _T_903 <= 2'h0; end else begin _T_903 <= _T_977; end if (reset) begin _T_913 <= 10'h0; end else begin if (_T_801) begin if (_T_916) begin if (_T_808) begin _T_913 <= _T_806; end else begin _T_913 <= 10'h0; end end else begin _T_913 <= _T_915; end end end if (reset) begin _T_932 <= 10'h0; end else begin if (_T_850) begin if (_T_935) begin if (_T_856) begin _T_932 <= _T_855; end else begin _T_932 <= 10'h0; end end else begin _T_932 <= _T_934; end end end if (reset) begin _T_978 <= 32'h0; end else begin if (_T_992) begin _T_978 <= 32'h0; end else begin _T_978 <= _T_989; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5961.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@5962.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:37:80)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@5968.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@5969.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5975.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_121) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@5976.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:37:80)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5983.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_125) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@5984.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5990.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_128) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@5991.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:37:80)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5998.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_132) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@5999.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6007.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_137) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@6008.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6015.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_141) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@6016.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@6069.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@6070.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:37:80)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@6076.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@6077.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@6083.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_121) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@6084.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:37:80)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@6091.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_125) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@6092.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@6098.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_128) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@6099.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:37:80)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@6106.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_132) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@6107.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_210) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:37:80)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6114.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_210) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@6115.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@6123.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_137) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@6124.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@6131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@6132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_275) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6193.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_275) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@6194.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@6200.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_121) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@6201.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@6207.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_128) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@6208.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6215.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_285) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@6216.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6223.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_289) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@6224.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@6231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_141) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@6232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6300.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_356) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@6301.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@6307.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_121) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@6308.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@6314.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_128) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@6315.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@6322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_285) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@6323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@6330.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_289) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@6331.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@6399.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_356) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@6400.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@6406.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_121) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@6407.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@6413.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_128) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@6414.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@6421.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_285) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@6422.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_449) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6431.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_449) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@6432.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6490.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_502) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@6491.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@6497.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_121) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@6498.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@6504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_128) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@6505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_512) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:37:80)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6512.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_512) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@6513.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@6520.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_289) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@6521.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@6579.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_502) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@6580.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@6586.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_121) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@6587.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@6593.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_128) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@6594.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:37:80)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6601.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_579) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@6602.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@6609.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_289) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@6610.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:37:80)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6668.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_636) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@6669.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@6675.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_121) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@6676.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:37:80)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@6682.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_128) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@6683.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:37:80)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@6690.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_289) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@6691.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@6698.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_141) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@6699.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:37:80)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6709.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_654) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@6710.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6726.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_663) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@6727.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:37:80)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6734.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_667) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@6735.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6742.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_671) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@6743.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6750.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_675) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@6751.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:37:80)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6758.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@6759.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@6768.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_663) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@6769.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@6775.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_115) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@6776.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:37:80)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@6783.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_667) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@6784.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:37:80)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6791.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_694) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@6792.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:37:80)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6799.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_698) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@6800.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@6807.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_675) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@6808.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@6826.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_663) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@6827.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@6833.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_115) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@6834.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:37:80)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@6841.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_667) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@6842.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:37:80)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@6849.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_694) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@6850.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:37:80)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@6857.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_698) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@6858.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6866.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_731) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@6867.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@6885.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_663) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@6886.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@6893.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_671) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@6894.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@6901.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_675) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@6902.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@6920.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_663) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@6921.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@6928.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_671) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@6929.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@6937.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_731) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@6938.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@6956.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_663) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@6957.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:37:80)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@6964.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_671) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@6965.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:37:80)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@6972.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_675) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@6973.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_831) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7046.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_831) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@7047.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_835) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7054.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_835) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@7055.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_839) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7062.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_839) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@7063.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_843) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7070.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_843) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@7071.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7078.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_847) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@7079.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_880) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7127.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_880) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@7128.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_884) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7135.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_884) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@7136.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_888) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7143.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_888) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@7144.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_892) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7151.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_892) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@7152.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7159.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_896) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@7160.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:37:80)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7167.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_900) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@7168.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_945 & _T_953) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:37:80)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7243.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_945 & _T_953) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@7244.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_960 & _T_967) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:37:80)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7266.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_960 & _T_967) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@7267.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:37:80)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7278.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@7279.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:37:80)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7298.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@7299.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLFIFOFixer( // @[:freechips.rocketchip.system.TinyConfig.fir@7311.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@7312.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@7313.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@7314.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] TLMonitor_3 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@7321.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7373.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7372.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@7323.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@7324.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@7369.4] endmodule module SimpleLazyModule( // @[:freechips.rocketchip.system.TinyConfig.fir@7517.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@7518.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@7519.4] input auto_buffer_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_buffer_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [2:0] auto_buffer_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [2:0] auto_buffer_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [3:0] auto_buffer_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_buffer_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [31:0] auto_buffer_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [3:0] auto_buffer_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [31:0] auto_buffer_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_buffer_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_buffer_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_buffer_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [2:0] auto_buffer_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [1:0] auto_buffer_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [3:0] auto_buffer_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_buffer_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_buffer_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_buffer_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [31:0] auto_buffer_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_buffer_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_tl_master_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [2:0] auto_tl_master_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [2:0] auto_tl_master_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [3:0] auto_tl_master_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_tl_master_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [31:0] auto_tl_master_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [3:0] auto_tl_master_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input [31:0] auto_tl_master_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_tl_master_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] input auto_tl_master_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [2:0] auto_tl_master_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [1:0] auto_tl_master_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [3:0] auto_tl_master_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output [31:0] auto_tl_master_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] output auto_tl_master_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@7520.4] ); wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] wire fixer_clock; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_reset; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [1:0] fixer_auto_in_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_in_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [1:0] fixer_auto_out_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [3:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire [31:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] wire fixer_auto_out_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] TLBuffer buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@7525.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); TLFIFOFixer fixer ( // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@7531.4] .clock(fixer_clock), .reset(fixer_reset), .auto_in_a_ready(fixer_auto_in_a_ready), .auto_in_a_valid(fixer_auto_in_a_valid), .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode), .auto_in_a_bits_param(fixer_auto_in_a_bits_param), .auto_in_a_bits_size(fixer_auto_in_a_bits_size), .auto_in_a_bits_source(fixer_auto_in_a_bits_source), .auto_in_a_bits_address(fixer_auto_in_a_bits_address), .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask), .auto_in_a_bits_data(fixer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt), .auto_in_d_ready(fixer_auto_in_d_ready), .auto_in_d_valid(fixer_auto_in_d_valid), .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode), .auto_in_d_bits_param(fixer_auto_in_d_bits_param), .auto_in_d_bits_size(fixer_auto_in_d_bits_size), .auto_in_d_bits_source(fixer_auto_in_d_bits_source), .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink), .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied), .auto_in_d_bits_data(fixer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt), .auto_out_a_ready(fixer_auto_out_a_ready), .auto_out_a_valid(fixer_auto_out_a_valid), .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode), .auto_out_a_bits_param(fixer_auto_out_a_bits_param), .auto_out_a_bits_size(fixer_auto_out_a_bits_size), .auto_out_a_bits_source(fixer_auto_out_a_bits_source), .auto_out_a_bits_address(fixer_auto_out_a_bits_address), .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask), .auto_out_a_bits_data(fixer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt), .auto_out_d_ready(fixer_auto_out_d_ready), .auto_out_d_valid(fixer_auto_out_d_valid), .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode), .auto_out_d_bits_param(fixer_auto_out_d_bits_param), .auto_out_d_bits_size(fixer_auto_out_d_bits_size), .auto_out_d_bits_source(fixer_auto_out_d_bits_source), .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink), .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied), .auto_out_d_bits_data(fixer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt) ); assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign auto_tl_master_xing_in_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign auto_tl_master_xing_in_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@7544.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@7529.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@7530.4] assign buffer_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@7545.4] assign fixer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@7535.4] assign fixer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@7536.4] assign fixer_auto_in_a_valid = auto_tl_master_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_opcode = auto_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_param = auto_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_size = auto_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_source = auto_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_address = auto_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_mask = auto_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_data = auto_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_a_bits_corrupt = auto_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_in_d_ready = auto_tl_master_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@7543.4] assign fixer_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] assign fixer_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@7542.4] endmodule module TLMonitor_4( // @[:freechips.rocketchip.system.TinyConfig.fir@7555.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@7556.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@7557.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@7558.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@9032.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@7573.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@7574.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@7577.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@7578.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@7586.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7597.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7598.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7599.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@7601.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@7602.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@7603.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@7604.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@7604.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@7605.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@7607.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@7608.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@7610.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@7611.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@7612.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@7613.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@7614.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7616.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7617.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7619.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7620.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@7621.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@7622.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@7623.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7624.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7625.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7626.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7627.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7628.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7629.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7630.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7631.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7632.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7633.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7634.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7635.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@7638.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7642.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@7695.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7698.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7699.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7700.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7701.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7702.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7703.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7704.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7705.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7706.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7707.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7708.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7709.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7710.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7711.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7712.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7715.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7716.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7717.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7718.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7719.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7720.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7721.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7722.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7723.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7724.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7725.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7726.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7727.8] wire _T_150; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7728.8] wire _T_151; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7729.8] wire _T_152; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7730.8] wire _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7731.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7737.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7750.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7751.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7758.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7759.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7765.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7766.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@7771.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7773.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7774.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@7779.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@7780.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7782.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7783.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@7788.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7790.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7791.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@7797.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@7881.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7883.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7884.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@7907.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@7910.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@7918.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@7920.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7948.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7949.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7950.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7951.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@7952.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@7954.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7956.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7957.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@7976.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7978.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7979.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@7984.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7986.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7987.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@8001.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@8040.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@8049.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8052.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8053.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@8089.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@8168.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@8169.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@8170.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8172.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8173.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@8179.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@8182.8] wire _T_494; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@8214.8] wire _T_505; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8225.8] wire _T_506; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8226.8] wire _T_513; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@8245.8] wire _T_515; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8247.8] wire _T_516; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8248.8] wire _T_521; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@8262.6] wire _T_574; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@8328.8] wire _T_576; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8330.8] wire _T_577; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8331.8] wire _T_582; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@8345.6] wire _T_627; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8391.8] wire _T_628; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8392.8] wire _T_643; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@8430.6] wire _T_645; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8432.6] wire _T_646; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8433.6] wire _T_647; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@8438.6] wire _T_648; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@8439.6] wire [1:0] _T_651; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@8442.6] wire _T_652; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@8443.6] wire _T_660; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@8451.6] wire _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8462.6] wire _T_667; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8463.6] wire _T_668; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8464.6] wire _T_670; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@8466.6] wire _T_672; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8469.8] wire _T_673; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8470.8] wire _T_674; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@8475.8] wire _T_676; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8477.8] wire _T_677; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8478.8] wire _T_678; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@8483.8] wire _T_680; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8485.8] wire _T_681; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8486.8] wire _T_682; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@8491.8] wire _T_684; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8493.8] wire _T_685; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8494.8] wire _T_686; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@8499.8] wire _T_688; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8501.8] wire _T_689; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8502.8] wire _T_690; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@8508.6] wire _T_701; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@8532.8] wire _T_703; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8534.8] wire _T_704; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8535.8] wire _T_705; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@8540.8] wire _T_707; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8542.8] wire _T_708; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8543.8] wire _T_718; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@8566.6] wire _T_738; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@8607.8] wire _T_740; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8609.8] wire _T_741; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8610.8] wire _T_747; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@8625.6] wire _T_764; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@8660.6] wire _T_782; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@8696.6] wire _T_811; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@8756.4] wire [9:0] _T_816; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@8761.4] wire _T_817; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@8762.4] wire _T_818; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@8763.4] reg [9:0] _T_820; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@8765.4] reg [31:0] _RAND_0; wire [9:0] _T_822; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8767.4] wire _T_823; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8768.4] reg [2:0] _T_831; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@8779.4] reg [31:0] _RAND_1; reg [2:0] _T_832; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@8780.4] reg [31:0] _RAND_2; reg [3:0] _T_833; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@8781.4] reg [31:0] _RAND_3; reg [4:0] _T_834; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@8782.4] reg [31:0] _RAND_4; reg [31:0] _T_835; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@8783.4] reg [31:0] _RAND_5; wire _T_836; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@8784.4] wire _T_837; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@8785.4] wire _T_838; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@8787.6] wire _T_840; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8789.6] wire _T_841; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8790.6] wire _T_842; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@8795.6] wire _T_844; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8797.6] wire _T_845; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8798.6] wire _T_846; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@8803.6] wire _T_848; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8805.6] wire _T_849; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8806.6] wire _T_850; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@8811.6] wire _T_852; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8813.6] wire _T_853; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8814.6] wire _T_854; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@8819.6] wire _T_856; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8821.6] wire _T_857; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8822.6] wire _T_859; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@8829.4] wire _T_860; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@8837.4] wire [26:0] _T_862; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@8839.4] wire [11:0] _T_863; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@8840.4] wire [11:0] _T_864; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@8841.4] wire [9:0] _T_865; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@8842.4] wire _T_866; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@8843.4] reg [9:0] _T_868; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@8845.4] reg [31:0] _RAND_6; wire [9:0] _T_870; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8847.4] wire _T_871; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8848.4] reg [2:0] _T_879; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@8859.4] reg [31:0] _RAND_7; reg [1:0] _T_880; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@8860.4] reg [31:0] _RAND_8; reg [3:0] _T_881; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@8861.4] reg [31:0] _RAND_9; reg [4:0] _T_882; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@8862.4] reg [31:0] _RAND_10; reg _T_883; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@8863.4] reg [31:0] _RAND_11; reg _T_884; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@8864.4] reg [31:0] _RAND_12; wire _T_885; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@8865.4] wire _T_886; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@8866.4] wire _T_887; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@8868.6] wire _T_889; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8870.6] wire _T_890; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8871.6] wire _T_891; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@8876.6] wire _T_893; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8878.6] wire _T_894; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8879.6] wire _T_895; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@8884.6] wire _T_897; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8886.6] wire _T_898; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8887.6] wire _T_899; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@8892.6] wire _T_901; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8894.6] wire _T_902; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8895.6] wire _T_903; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@8900.6] wire _T_905; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8902.6] wire _T_906; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8903.6] wire _T_907; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@8908.6] wire _T_909; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8910.6] wire _T_910; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8911.6] wire _T_912; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@8918.4] reg [17:0] _T_913; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@8927.4] reg [31:0] _RAND_13; reg [9:0] _T_923; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@8937.4] reg [31:0] _RAND_14; wire [9:0] _T_925; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8939.4] wire _T_926; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8940.4] reg [9:0] _T_942; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@8959.4] reg [31:0] _RAND_15; wire [9:0] _T_944; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8961.4] wire _T_945; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8962.4] wire _T_955; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@8977.4] wire [31:0] _T_957; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@8980.6] wire [17:0] _T_958; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@8982.6] wire _T_959; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@8983.6] wire _T_960; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@8984.6] wire _T_962; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8986.6] wire _T_963; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8987.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@8979.4] wire _T_967; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@8998.4] wire _T_969; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@9000.4] wire _T_970; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@9001.4] wire [31:0] _T_971; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@9003.6] wire [17:0] _T_953; // @[:freechips.rocketchip.system.TinyConfig.fir@8973.4 :freechips.rocketchip.system.TinyConfig.fir@8975.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@8981.6] wire [17:0] _T_972; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@9005.6] wire [17:0] _T_973; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@9006.6] wire _T_974; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@9007.6] wire _T_976; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9009.6] wire _T_977; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9010.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@9002.4] wire [17:0] _T_964; // @[:freechips.rocketchip.system.TinyConfig.fir@8993.4 :freechips.rocketchip.system.TinyConfig.fir@8995.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@9004.6] wire _T_978; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@9016.4] wire _T_979; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@9017.4] wire _T_980; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@9018.4] wire _T_981; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@9019.4] wire _T_983; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9021.4] wire _T_984; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9022.4] wire [17:0] _T_985; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@9027.4] wire [17:0] _T_986; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@9028.4] wire [17:0] _T_987; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@9029.4] reg [31:0] _T_988; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@9031.4] reg [31:0] _RAND_16; wire _T_989; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@9034.4] wire _T_990; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@9035.4] wire _T_991; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@9036.4] wire _T_992; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@9037.4] wire _T_993; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@9038.4] wire _T_994; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@9039.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9041.4] wire _T_997; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9042.4] wire [31:0] _T_999; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@9048.4] wire _T_1002; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@9052.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7739.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@7841.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7959.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8055.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@8143.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8228.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@8311.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8394.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8472.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@8514.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@8572.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@8631.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@8666.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@8702.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@9032.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@7573.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@7574.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@7577.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@7578.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@7586.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7597.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7598.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@7599.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@7601.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@7602.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@7603.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@7604.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@7604.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@7605.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@7607.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@7608.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@7610.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@7611.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@7612.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@7613.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@7614.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7616.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7617.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7619.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7620.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@7621.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@7622.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@7623.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7624.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7625.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7626.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7627.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7628.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7629.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7630.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7631.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7632.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@7633.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@7634.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@7635.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@7638.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7642.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@7695.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7698.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7699.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7700.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7701.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7702.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7703.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7704.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7705.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7706.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7707.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7708.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7709.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7710.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7711.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7712.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7715.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7716.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7717.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7718.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7719.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7720.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7721.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7722.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@7723.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@7724.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7725.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@7726.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@7727.8] assign _T_150 = _T_124 | _T_129; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7728.8] assign _T_151 = _T_150 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7729.8] assign _T_152 = _T_151 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7730.8] assign _T_153 = _T_152 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7731.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7737.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7750.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7751.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7758.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7759.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7765.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7766.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@7771.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7773.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7774.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@7779.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@7780.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7782.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7783.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@7788.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7790.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7791.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@7797.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@7881.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7883.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7884.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@7907.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@7910.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@7918.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@7920.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7948.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7949.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7950.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@7951.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@7952.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@7954.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7956.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7957.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@7976.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7978.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7979.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@7984.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7986.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7987.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@8001.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@8040.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@8049.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8052.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8053.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@8089.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@8168.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@8169.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@8170.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8172.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8173.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@8179.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@8182.8] assign _T_494 = _T_462 & _T_153; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@8214.8] assign _T_505 = _T_494 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8225.8] assign _T_506 = _T_505 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8226.8] assign _T_513 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@8245.8] assign _T_515 = _T_513 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8247.8] assign _T_516 = _T_515 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8248.8] assign _T_521 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@8262.6] assign _T_574 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@8328.8] assign _T_576 = _T_574 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8330.8] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8331.8] assign _T_582 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@8345.6] assign _T_627 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8391.8] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8392.8] assign _T_643 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@8430.6] assign _T_645 = _T_643 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8432.6] assign _T_646 = _T_645 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8433.6] assign _T_647 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@8438.6] assign _T_648 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@8439.6] assign _T_651 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@8442.6] assign _T_652 = _T_651 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@8443.6] assign _T_660 = _T_651 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@8451.6] assign _T_666 = _T_647 | _T_648; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8462.6] assign _T_667 = _T_666 | _T_652; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8463.6] assign _T_668 = _T_667 | _T_660; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@8464.6] assign _T_670 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@8466.6] assign _T_672 = _T_668 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8469.8] assign _T_673 = _T_672 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8470.8] assign _T_674 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@8475.8] assign _T_676 = _T_674 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8477.8] assign _T_677 = _T_676 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8478.8] assign _T_678 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@8483.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8485.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8486.8] assign _T_682 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@8491.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8493.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8494.8] assign _T_686 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@8499.8] assign _T_688 = _T_686 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8501.8] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8502.8] assign _T_690 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@8508.6] assign _T_701 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@8532.8] assign _T_703 = _T_701 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8534.8] assign _T_704 = _T_703 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8535.8] assign _T_705 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@8540.8] assign _T_707 = _T_705 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8542.8] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8543.8] assign _T_718 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@8566.6] assign _T_738 = _T_686 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@8607.8] assign _T_740 = _T_738 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8609.8] assign _T_741 = _T_740 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8610.8] assign _T_747 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@8625.6] assign _T_764 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@8660.6] assign _T_782 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@8696.6] assign _T_811 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@8756.4] assign _T_816 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@8761.4] assign _T_817 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@8762.4] assign _T_818 = _T_817 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@8763.4] assign _T_822 = _T_820 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8767.4] assign _T_823 = _T_820 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8768.4] assign _T_836 = _T_823 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@8784.4] assign _T_837 = io_in_a_valid & _T_836; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@8785.4] assign _T_838 = io_in_a_bits_opcode == _T_831; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@8787.6] assign _T_840 = _T_838 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8789.6] assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8790.6] assign _T_842 = io_in_a_bits_param == _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@8795.6] assign _T_844 = _T_842 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8797.6] assign _T_845 = _T_844 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8798.6] assign _T_846 = io_in_a_bits_size == _T_833; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@8803.6] assign _T_848 = _T_846 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8805.6] assign _T_849 = _T_848 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8806.6] assign _T_850 = io_in_a_bits_source == _T_834; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@8811.6] assign _T_852 = _T_850 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8813.6] assign _T_853 = _T_852 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8814.6] assign _T_854 = io_in_a_bits_address == _T_835; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@8819.6] assign _T_856 = _T_854 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8821.6] assign _T_857 = _T_856 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8822.6] assign _T_859 = _T_811 & _T_823; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@8829.4] assign _T_860 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@8837.4] assign _T_862 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@8839.4] assign _T_863 = _T_862[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@8840.4] assign _T_864 = ~ _T_863; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@8841.4] assign _T_865 = _T_864[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@8842.4] assign _T_866 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@8843.4] assign _T_870 = _T_868 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8847.4] assign _T_871 = _T_868 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8848.4] assign _T_885 = _T_871 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@8865.4] assign _T_886 = io_in_d_valid & _T_885; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@8866.4] assign _T_887 = io_in_d_bits_opcode == _T_879; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@8868.6] assign _T_889 = _T_887 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8870.6] assign _T_890 = _T_889 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8871.6] assign _T_891 = io_in_d_bits_param == _T_880; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@8876.6] assign _T_893 = _T_891 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8878.6] assign _T_894 = _T_893 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8879.6] assign _T_895 = io_in_d_bits_size == _T_881; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@8884.6] assign _T_897 = _T_895 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8886.6] assign _T_898 = _T_897 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8887.6] assign _T_899 = io_in_d_bits_source == _T_882; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@8892.6] assign _T_901 = _T_899 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8894.6] assign _T_902 = _T_901 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8895.6] assign _T_903 = io_in_d_bits_sink == _T_883; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@8900.6] assign _T_905 = _T_903 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8902.6] assign _T_906 = _T_905 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8903.6] assign _T_907 = io_in_d_bits_denied == _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@8908.6] assign _T_909 = _T_907 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8910.6] assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8911.6] assign _T_912 = _T_860 & _T_871; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@8918.4] assign _T_925 = _T_923 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8939.4] assign _T_926 = _T_923 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8940.4] assign _T_944 = _T_942 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@8961.4] assign _T_945 = _T_942 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@8962.4] assign _T_955 = _T_811 & _T_926; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@8977.4] assign _T_957 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@8980.6] assign _T_958 = _T_913 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@8982.6] assign _T_959 = _T_958[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@8983.6] assign _T_960 = _T_959 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@8984.6] assign _T_962 = _T_960 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8986.6] assign _T_963 = _T_962 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8987.6] assign _GEN_15 = _T_955 ? _T_957 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@8979.4] assign _T_967 = _T_860 & _T_945; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@8998.4] assign _T_969 = _T_670 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@9000.4] assign _T_970 = _T_967 & _T_969; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@9001.4] assign _T_971 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@9003.6] assign _T_953 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@8973.4 :freechips.rocketchip.system.TinyConfig.fir@8975.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@8981.6] assign _T_972 = _T_953 | _T_913; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@9005.6] assign _T_973 = _T_972 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@9006.6] assign _T_974 = _T_973[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@9007.6] assign _T_976 = _T_974 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9009.6] assign _T_977 = _T_976 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9010.6] assign _GEN_16 = _T_970 ? _T_971 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@9002.4] assign _T_964 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@8993.4 :freechips.rocketchip.system.TinyConfig.fir@8995.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@9004.6] assign _T_978 = _T_953 != _T_964; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@9016.4] assign _T_979 = _T_953 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@9017.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@9018.4] assign _T_981 = _T_978 | _T_980; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@9019.4] assign _T_983 = _T_981 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9021.4] assign _T_984 = _T_983 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9022.4] assign _T_985 = _T_913 | _T_953; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@9027.4] assign _T_986 = ~ _T_964; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@9028.4] assign _T_987 = _T_985 & _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@9029.4] assign _T_989 = _T_913 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@9034.4] assign _T_990 = _T_989 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@9035.4] assign _T_991 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@9036.4] assign _T_992 = _T_990 | _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@9037.4] assign _T_993 = _T_988 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@9038.4] assign _T_994 = _T_992 | _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@9039.4] assign _T_996 = _T_994 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9041.4] assign _T_997 = _T_996 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9042.4] assign _T_999 = _T_988 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@9048.4] assign _T_1002 = _T_811 | _T_860; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@9052.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7739.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@7841.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7959.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8055.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@8143.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8228.10] assign _GEN_95 = io_in_a_valid & _T_521; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@8311.10] assign _GEN_105 = io_in_a_valid & _T_582; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8394.10] assign _GEN_115 = io_in_d_valid & _T_670; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8472.10] assign _GEN_125 = io_in_d_valid & _T_690; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@8514.10] assign _GEN_137 = io_in_d_valid & _T_718; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@8572.10] assign _GEN_149 = io_in_d_valid & _T_747; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@8631.10] assign _GEN_155 = io_in_d_valid & _T_764; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@8666.10] assign _GEN_161 = io_in_d_valid & _T_782; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@8702.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_820 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_831 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_832 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_833 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_834 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_835 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_868 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_879 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_880 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_881 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_882 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_883 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_884 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_913 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_923 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_942 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_988 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_820 <= 10'h0; end else begin if (_T_811) begin if (_T_823) begin if (_T_818) begin _T_820 <= _T_816; end else begin _T_820 <= 10'h0; end end else begin _T_820 <= _T_822; end end end if (_T_859) begin _T_831 <= io_in_a_bits_opcode; end if (_T_859) begin _T_832 <= io_in_a_bits_param; end if (_T_859) begin _T_833 <= io_in_a_bits_size; end if (_T_859) begin _T_834 <= io_in_a_bits_source; end if (_T_859) begin _T_835 <= io_in_a_bits_address; end if (reset) begin _T_868 <= 10'h0; end else begin if (_T_860) begin if (_T_871) begin if (_T_866) begin _T_868 <= _T_865; end else begin _T_868 <= 10'h0; end end else begin _T_868 <= _T_870; end end end if (_T_912) begin _T_879 <= io_in_d_bits_opcode; end if (_T_912) begin _T_880 <= io_in_d_bits_param; end if (_T_912) begin _T_881 <= io_in_d_bits_size; end if (_T_912) begin _T_882 <= io_in_d_bits_source; end if (_T_912) begin _T_883 <= io_in_d_bits_sink; end if (_T_912) begin _T_884 <= io_in_d_bits_denied; end if (reset) begin _T_913 <= 18'h0; end else begin _T_913 <= _T_987; end if (reset) begin _T_923 <= 10'h0; end else begin if (_T_811) begin if (_T_926) begin if (_T_818) begin _T_923 <= _T_816; end else begin _T_923 <= 10'h0; end end else begin _T_923 <= _T_925; end end end if (reset) begin _T_942 <= 10'h0; end else begin if (_T_860) begin if (_T_945) begin if (_T_866) begin _T_942 <= _T_865; end else begin _T_942 <= 10'h0; end end else begin _T_942 <= _T_944; end end end if (reset) begin _T_988 <= 32'h0; end else begin if (_T_1002) begin _T_988 <= 32'h0; end else begin _T_988 <= _T_999; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7739.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@7740.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:56:61)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@7746.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@7747.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7753.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@7754.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7761.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@7762.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7768.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@7769.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@7777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7785.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@7786.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7793.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@7794.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@7841.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@7842.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:56:61)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@7848.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@7849.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@7855.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@7856.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@7863.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@7864.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@7870.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@7871.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@7878.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@7879.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:56:61)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7886.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@7887.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@7895.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@7896.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@7903.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@7904.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7959.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@7960.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@7966.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@7967.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@7973.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@7974.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7981.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@7982.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7989.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@7990.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@7997.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@7998.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8055.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@8056.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@8062.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@8063.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@8069.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@8070.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@8077.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@8078.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@8085.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@8086.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@8143.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@8144.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@8150.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@8151.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@8157.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@8158.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@8165.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@8166.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8175.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@8176.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8228.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_506) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@8229.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@8235.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@8236.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@8242.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@8243.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_516) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8250.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_516) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@8251.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@8258.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@8259.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@8311.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_506) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@8312.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@8318.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@8319.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@8325.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@8326.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8333.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_577) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@8334.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@8341.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@8342.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_628) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@8395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@8401.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@8402.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@8408.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@8409.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@8416.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@8417.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@8424.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@8425.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_646) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:56:61)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8435.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_646) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@8436.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8472.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_673) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@8473.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8480.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_677) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@8481.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8488.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_681) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@8489.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8496.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_685) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@8497.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_689) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@8505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@8514.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_673) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@8515.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@8521.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@8522.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@8529.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_677) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@8530.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8537.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_704) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@8538.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_708) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@8546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@8553.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_685) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@8554.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@8572.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_673) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@8573.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@8579.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@8580.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@8587.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_677) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@8588.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@8595.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_704) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@8596.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@8603.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_708) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@8604.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8612.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_741) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@8613.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@8631.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_673) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@8632.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@8639.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_681) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@8640.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@8647.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_685) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@8648.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@8666.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_673) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@8667.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@8674.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_681) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@8675.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@8683.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_741) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@8684.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@8702.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_673) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@8703.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@8710.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_681) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@8711.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@8718.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_685) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@8719.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_841) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8792.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_841) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@8793.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_845) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8800.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_845) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@8801.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_849) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8808.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_849) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@8809.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_853) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8816.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_853) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@8817.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_857) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8824.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_857) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@8825.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_890) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8873.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_890) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@8874.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_894) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8881.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_894) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@8882.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_898) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8889.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_898) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@8890.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_902) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8897.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_902) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@8898.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_906) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8905.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_906) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@8906.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_910) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8913.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_910) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@8914.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_955 & _T_963) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8989.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_955 & _T_963) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@8990.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_970 & _T_977) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:56:61)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9012.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_970 & _T_977) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@9013.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_984) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:56:61)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9024.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_984) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@9025.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_997) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:56:61)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9044.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_997) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@9045.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLWidthWidget( // @[:freechips.rocketchip.system.TinyConfig.fir@9057.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@9058.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@9059.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@9060.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] TLMonitor_4 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@9067.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9119.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9118.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@9069.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@9070.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@9115.4] endmodule module SimpleLazyModule_1( // @[:freechips.rocketchip.system.TinyConfig.fir@9141.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@9142.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@9143.4] output auto_widget_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_widget_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [2:0] auto_widget_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [2:0] auto_widget_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [3:0] auto_widget_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [4:0] auto_widget_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [31:0] auto_widget_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [3:0] auto_widget_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [31:0] auto_widget_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_widget_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_widget_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_widget_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [2:0] auto_widget_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [1:0] auto_widget_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [3:0] auto_widget_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [4:0] auto_widget_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_widget_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_widget_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [31:0] auto_widget_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_widget_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [2:0] auto_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [3:0] auto_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [4:0] auto_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [31:0] auto_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [3:0] auto_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output [31:0] auto_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] output auto_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [1:0] auto_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [3:0] auto_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [4:0] auto_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input [31:0] auto_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] input auto_bus_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@9144.4] ); wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [4:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [4:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [4:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [4:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] TLWidthWidget widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@9149.4] .clock(widget_clock), .reset(widget_reset), .auto_in_a_ready(widget_auto_in_a_ready), .auto_in_a_valid(widget_auto_in_a_valid), .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode), .auto_in_a_bits_param(widget_auto_in_a_bits_param), .auto_in_a_bits_size(widget_auto_in_a_bits_size), .auto_in_a_bits_source(widget_auto_in_a_bits_source), .auto_in_a_bits_address(widget_auto_in_a_bits_address), .auto_in_a_bits_mask(widget_auto_in_a_bits_mask), .auto_in_a_bits_data(widget_auto_in_a_bits_data), .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt), .auto_in_d_ready(widget_auto_in_d_ready), .auto_in_d_valid(widget_auto_in_d_valid), .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode), .auto_in_d_bits_param(widget_auto_in_d_bits_param), .auto_in_d_bits_size(widget_auto_in_d_bits_size), .auto_in_d_bits_source(widget_auto_in_d_bits_source), .auto_in_d_bits_sink(widget_auto_in_d_bits_sink), .auto_in_d_bits_denied(widget_auto_in_d_bits_denied), .auto_in_d_bits_data(widget_auto_in_d_bits_data), .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt), .auto_out_a_ready(widget_auto_out_a_ready), .auto_out_a_valid(widget_auto_out_a_valid), .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode), .auto_out_a_bits_param(widget_auto_out_a_bits_param), .auto_out_a_bits_size(widget_auto_out_a_bits_size), .auto_out_a_bits_source(widget_auto_out_a_bits_source), .auto_out_a_bits_address(widget_auto_out_a_bits_address), .auto_out_a_bits_mask(widget_auto_out_a_bits_mask), .auto_out_a_bits_data(widget_auto_out_a_bits_data), .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt), .auto_out_d_ready(widget_auto_out_d_ready), .auto_out_d_valid(widget_auto_out_d_valid), .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode), .auto_out_d_bits_param(widget_auto_out_d_bits_param), .auto_out_d_bits_size(widget_auto_out_d_bits_size), .auto_out_d_bits_source(widget_auto_out_d_bits_source), .auto_out_d_bits_sink(widget_auto_out_d_bits_sink), .auto_out_d_bits_denied(widget_auto_out_d_bits_denied), .auto_out_d_bits_data(widget_auto_out_d_bits_data), .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt) ); assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@9161.4] assign widget_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@9153.4] assign widget_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@9154.4] assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@9162.4] assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@9160.4] endmodule module TLMonitor_5( // @[:freechips.rocketchip.system.TinyConfig.fir@9172.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@9173.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@9174.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@9175.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@10677.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@9192.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@9193.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@9210.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@9212.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@9213.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@9214.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@9215.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@9215.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@9216.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@9218.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@9219.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@9221.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@9222.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@9223.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@9224.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@9225.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9227.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9228.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9230.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9231.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@9232.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@9233.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@9234.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9235.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9236.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9237.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9238.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9239.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9240.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9241.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9242.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9243.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9244.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9245.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9246.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@9249.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9260.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@9288.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9291.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9292.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9293.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9294.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9295.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9296.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9297.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9298.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9299.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9300.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9301.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9302.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9303.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9304.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9305.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9308.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9309.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9310.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9311.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9312.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9313.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9314.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9315.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9316.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9317.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9318.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9319.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9320.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9321.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9322.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9323.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9324.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9325.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9326.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9327.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9328.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9329.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9336.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9349.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9350.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9357.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9358.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9364.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9365.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@9370.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9372.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9373.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@9378.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@9379.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9381.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9382.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@9387.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9389.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9390.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@9396.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@9486.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9488.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9489.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@9512.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9515.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9523.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9525.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9558.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9559.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9560.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9561.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9562.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9563.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9565.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9567.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9568.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@9587.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9589.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9590.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@9595.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9597.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9598.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@9612.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9651.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9660.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9668.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9670.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9672.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9674.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9675.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@9711.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@9801.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@9802.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@9803.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9805.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9806.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@9812.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9815.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9847.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9864.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9865.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@9884.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9886.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9887.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@9901.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@9973.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9975.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9976.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@9990.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10042.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10043.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@10081.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10083.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10084.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@10091.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@10092.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@10109.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@10111.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10114.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10115.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@10120.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10122.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10123.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@10128.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10130.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10131.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@10136.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10138.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10139.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@10144.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10146.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10147.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@10153.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@10177.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10179.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10180.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@10185.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10187.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10188.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@10211.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@10252.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10254.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10255.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@10270.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@10305.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@10341.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@10401.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@10406.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@10407.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@10408.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@10410.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10412.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10413.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@10424.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@10425.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@10426.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@10427.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@10428.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@10429.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@10430.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@10432.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10434.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10435.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@10440.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10442.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10443.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@10448.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10450.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10451.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@10456.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10458.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10459.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@10464.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10466.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10467.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@10474.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@10482.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@10484.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@10485.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@10486.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@10487.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@10488.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@10490.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10492.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10493.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@10504.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@10505.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@10506.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@10507.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@10508.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@10509.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@10510.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@10511.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@10513.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10515.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10516.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@10521.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10523.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10524.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@10529.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10531.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10532.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@10537.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10539.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10540.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@10545.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10547.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10548.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@10553.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10555.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10556.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@10563.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@10572.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@10582.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10584.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10585.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@10604.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10606.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10607.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@10622.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@10625.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@10627.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@10628.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@10629.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10631.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10632.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@10624.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@10643.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@10645.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@10646.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@10648.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@10650.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@10651.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@10652.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10654.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10655.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@10647.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@10661.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@10662.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@10663.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@10664.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10666.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10667.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@10672.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@10673.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@10674.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@10676.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@10679.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@10680.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@10681.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@10682.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@10683.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@10684.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10686.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10687.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@10693.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@10697.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9338.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@9446.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9570.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9677.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@9776.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9867.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@9956.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10045.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10117.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@10159.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@10217.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@10276.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@10311.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@10347.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@10677.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@9192.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@9193.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@9210.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@9212.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@9213.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@9214.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@9215.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@9215.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@9216.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@9218.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@9219.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@9221.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@9222.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@9223.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@9224.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@9225.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9227.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9228.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9230.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9231.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@9232.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@9233.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@9234.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9235.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9236.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9237.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9238.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9239.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9240.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9241.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9242.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9243.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@9244.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@9245.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@9246.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@9249.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9260.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@9288.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9291.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9292.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9293.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9294.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9295.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9296.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9297.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9298.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9299.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9300.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9301.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9302.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9303.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9304.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9305.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9308.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9309.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9310.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9311.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9312.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9313.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9314.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9315.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9316.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9317.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9318.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9319.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9320.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@9321.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@9322.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9323.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@9324.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@9325.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9326.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9327.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9328.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9329.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9336.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9349.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9350.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9357.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9358.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9364.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9365.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@9370.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9372.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9373.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@9378.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@9379.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9381.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9382.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@9387.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9389.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9390.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@9396.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@9486.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9488.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9489.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@9512.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9515.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9523.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9525.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9558.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9559.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9560.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9561.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@9562.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9563.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9565.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9567.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9568.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@9587.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9589.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9590.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@9595.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9597.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9598.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@9612.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9651.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9660.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9668.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9670.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@9672.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9674.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9675.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@9711.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@9801.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@9802.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@9803.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9805.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9806.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@9812.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@9815.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@9847.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9864.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9865.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@9884.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9886.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9887.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@9901.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@9973.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9975.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9976.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@9990.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10042.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10043.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@10081.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10083.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10084.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@10091.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@10092.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@10109.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@10111.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10114.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10115.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@10120.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10122.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10123.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@10128.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10130.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10131.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@10136.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10138.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10139.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@10144.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10146.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10147.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@10153.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@10177.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10179.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10180.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@10185.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10187.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10188.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@10211.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@10252.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10254.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10255.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@10270.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@10305.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@10341.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@10401.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@10406.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@10407.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@10408.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10412.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10413.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@10429.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@10430.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@10432.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10434.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10435.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@10440.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10442.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10443.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@10448.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10450.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10451.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@10456.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10458.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10459.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@10464.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10466.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10467.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@10474.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@10482.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@10484.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@10485.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@10486.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@10487.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@10488.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10492.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10493.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@10510.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@10511.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@10513.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10515.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10516.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@10521.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10523.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10524.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@10529.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10531.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10532.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@10537.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10539.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10540.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@10545.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10547.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10548.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@10553.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10555.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10556.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@10563.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10584.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10585.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@10606.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@10607.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@10622.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@10625.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@10627.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@10628.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@10629.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10631.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10632.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@10624.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@10643.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@10645.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@10646.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@10648.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@10650.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@10651.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@10652.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10654.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10655.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@10647.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@10661.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@10662.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@10663.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@10664.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10666.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10667.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@10672.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@10673.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@10674.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@10679.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@10680.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@10681.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@10682.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@10683.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@10684.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10686.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10687.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@10693.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@10697.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9338.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@9446.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9570.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9677.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@9776.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9867.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@9956.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10045.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10117.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@10159.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@10217.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@10276.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@10311.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@10347.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9338.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@9339.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:62:42)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@9345.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@9346.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9352.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@9353.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9360.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@9361.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9367.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@9368.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9375.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@9376.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9384.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@9385.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9392.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@9393.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@9446.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@9447.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:62:42)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@9453.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@9454.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@9460.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@9461.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@9468.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@9469.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@9475.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@9476.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@9483.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@9484.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:62:42)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9491.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@9492.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@9500.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@9501.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@9508.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@9509.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9570.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@9571.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@9577.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@9578.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@9584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@9585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9592.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@9593.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9600.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@9601.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@9608.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@9609.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9677.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@9678.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@9684.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@9685.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@9691.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@9692.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@9699.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@9700.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@9707.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@9708.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@9776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@9777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@9783.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@9784.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@9790.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@9791.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@9798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@9799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9808.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@9809.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9867.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@9868.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@9874.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@9875.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@9881.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@9882.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9889.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@9890.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@9897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@9898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@9956.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@9957.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@9963.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@9964.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@9970.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@9971.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@9979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@9986.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@9987.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10045.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@10046.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@10052.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@10053.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@10059.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@10060.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@10067.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@10068.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@10075.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@10076.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:62:42)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10086.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@10087.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10117.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@10118.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@10126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@10134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10141.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@10142.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10149.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@10150.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@10159.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@10160.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@10166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@10167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@10174.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@10175.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@10183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10190.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@10191.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@10198.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@10199.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@10217.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@10218.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@10224.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@10225.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@10232.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@10233.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@10240.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@10241.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@10248.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@10249.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10257.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@10258.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@10276.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@10277.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@10284.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@10285.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@10292.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@10293.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@10311.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@10312.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@10319.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@10320.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@10328.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@10329.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@10347.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@10348.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@10355.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@10356.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@10363.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@10364.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10437.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@10438.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10445.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@10446.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10453.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@10454.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10461.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@10462.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10469.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@10470.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10518.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@10519.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10526.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@10527.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10534.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@10535.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10542.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@10543.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10550.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@10551.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10558.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@10559.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10634.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@10635.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:62:42)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10657.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@10658.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:62:42)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10669.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@10670.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:62:42)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10689.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@10690.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLWidthWidget_1( // @[:freechips.rocketchip.system.TinyConfig.fir@10702.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@10703.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@10704.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@10705.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] TLMonitor_5 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@10712.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10764.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10763.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@10714.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@10715.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@10760.4] endmodule module SimpleLazyModule_2( // @[:freechips.rocketchip.system.TinyConfig.fir@10786.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@10787.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@10788.4] input auto_widget_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_widget_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [2:0] auto_widget_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [2:0] auto_widget_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [3:0] auto_widget_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [3:0] auto_widget_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [31:0] auto_widget_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [3:0] auto_widget_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [31:0] auto_widget_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_widget_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_widget_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_widget_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [2:0] auto_widget_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [1:0] auto_widget_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [3:0] auto_widget_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [3:0] auto_widget_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_widget_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_widget_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [31:0] auto_widget_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_widget_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [2:0] auto_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [3:0] auto_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [3:0] auto_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [31:0] auto_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [3:0] auto_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input [31:0] auto_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] input auto_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [1:0] auto_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [3:0] auto_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [3:0] auto_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output [31:0] auto_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] output auto_bus_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@10789.4] ); wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] TLWidthWidget_1 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@10794.4] .clock(widget_clock), .reset(widget_reset), .auto_in_a_ready(widget_auto_in_a_ready), .auto_in_a_valid(widget_auto_in_a_valid), .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode), .auto_in_a_bits_param(widget_auto_in_a_bits_param), .auto_in_a_bits_size(widget_auto_in_a_bits_size), .auto_in_a_bits_source(widget_auto_in_a_bits_source), .auto_in_a_bits_address(widget_auto_in_a_bits_address), .auto_in_a_bits_mask(widget_auto_in_a_bits_mask), .auto_in_a_bits_data(widget_auto_in_a_bits_data), .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt), .auto_in_d_ready(widget_auto_in_d_ready), .auto_in_d_valid(widget_auto_in_d_valid), .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode), .auto_in_d_bits_param(widget_auto_in_d_bits_param), .auto_in_d_bits_size(widget_auto_in_d_bits_size), .auto_in_d_bits_source(widget_auto_in_d_bits_source), .auto_in_d_bits_sink(widget_auto_in_d_bits_sink), .auto_in_d_bits_denied(widget_auto_in_d_bits_denied), .auto_in_d_bits_data(widget_auto_in_d_bits_data), .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt), .auto_out_a_ready(widget_auto_out_a_ready), .auto_out_a_valid(widget_auto_out_a_valid), .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode), .auto_out_a_bits_param(widget_auto_out_a_bits_param), .auto_out_a_bits_size(widget_auto_out_a_bits_size), .auto_out_a_bits_source(widget_auto_out_a_bits_source), .auto_out_a_bits_address(widget_auto_out_a_bits_address), .auto_out_a_bits_mask(widget_auto_out_a_bits_mask), .auto_out_a_bits_data(widget_auto_out_a_bits_data), .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt), .auto_out_d_ready(widget_auto_out_d_ready), .auto_out_d_valid(widget_auto_out_d_valid), .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode), .auto_out_d_bits_param(widget_auto_out_d_bits_param), .auto_out_d_bits_size(widget_auto_out_d_bits_size), .auto_out_d_bits_source(widget_auto_out_d_bits_source), .auto_out_d_bits_sink(widget_auto_out_d_bits_sink), .auto_out_d_bits_denied(widget_auto_out_d_bits_denied), .auto_out_d_bits_data(widget_auto_out_d_bits_data), .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt) ); assign auto_widget_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_widget_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign auto_bus_xing_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign auto_bus_xing_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@10806.4] assign widget_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@10798.4] assign widget_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@10799.4] assign widget_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@10805.4] assign widget_auto_out_a_ready = auto_widget_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_valid = auto_widget_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_opcode = auto_widget_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_param = auto_widget_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_size = auto_widget_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_source = auto_widget_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_sink = auto_widget_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_denied = auto_widget_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_data = auto_widget_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] assign widget_auto_out_d_bits_corrupt = auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@10807.4] endmodule module Queue( // @[:freechips.rocketchip.system.TinyConfig.fir@10809.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@10810.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@10811.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [30:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [1:0] io_enq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input io_enq_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [3:0] io_enq_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [2:0] io_enq_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input [3:0] io_enq_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [30:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output io_deq_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [3:0] io_deq_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [2:0] io_deq_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] output [3:0] io_deq_bits_qos // @[:freechips.rocketchip.system.TinyConfig.fir@10812.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [30:0] _T_addr [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_1; wire [30:0] _T_addr__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_addr__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [30:0] _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_addr__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_addr__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_addr__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [7:0] _T_len [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_2; wire [7:0] _T_len__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_len__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [7:0] _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_len__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_len__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_len__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_3; wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [1:0] _T_burst [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_4; wire [1:0] _T_burst__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_burst__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [1:0] _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_burst__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_burst__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_burst__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg _T_lock [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_5; wire _T_lock__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_lock__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_lock__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_lock__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_lock__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_lock__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [3:0] _T_cache [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_6; wire [3:0] _T_cache__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_cache__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [3:0] _T_cache__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_cache__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_cache__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_cache__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [2:0] _T_prot [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_7; wire [2:0] _T_prot__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_prot__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [2:0] _T_prot__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_prot__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_prot__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_prot__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [3:0] _T_qos [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg [31:0] _RAND_8; wire [3:0] _T_qos__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_qos__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire [3:0] _T_qos__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_qos__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_qos__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] wire _T_qos__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10815.4] reg [31:0] _RAND_9; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10816.4] reg [31:0] _RAND_10; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@10817.4] reg [31:0] _RAND_11; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10818.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10819.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10820.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10821.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10822.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10825.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10841.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10847.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10850.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_addr__T_18_addr = value_1; assign _T_addr__T_18_data = _T_addr[_T_addr__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_addr__T_10_data = io_enq_bits_addr; assign _T_addr__T_10_addr = value; assign _T_addr__T_10_mask = 1'h1; assign _T_addr__T_10_en = io_enq_ready & io_enq_valid; assign _T_len__T_18_addr = value_1; assign _T_len__T_18_data = _T_len[_T_len__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_len__T_10_data = io_enq_bits_len; assign _T_len__T_10_addr = value; assign _T_len__T_10_mask = 1'h1; assign _T_len__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_burst__T_18_addr = value_1; assign _T_burst__T_18_data = _T_burst[_T_burst__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_burst__T_10_data = io_enq_bits_burst; assign _T_burst__T_10_addr = value; assign _T_burst__T_10_mask = 1'h1; assign _T_burst__T_10_en = io_enq_ready & io_enq_valid; assign _T_lock__T_18_addr = value_1; assign _T_lock__T_18_data = _T_lock[_T_lock__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_lock__T_10_data = io_enq_bits_lock; assign _T_lock__T_10_addr = value; assign _T_lock__T_10_mask = 1'h1; assign _T_lock__T_10_en = io_enq_ready & io_enq_valid; assign _T_cache__T_18_addr = value_1; assign _T_cache__T_18_data = _T_cache[_T_cache__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_cache__T_10_data = io_enq_bits_cache; assign _T_cache__T_10_addr = value; assign _T_cache__T_10_mask = 1'h1; assign _T_cache__T_10_en = io_enq_ready & io_enq_valid; assign _T_prot__T_18_addr = value_1; assign _T_prot__T_18_data = _T_prot[_T_prot__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_prot__T_10_data = io_enq_bits_prot; assign _T_prot__T_10_addr = value; assign _T_prot__T_10_mask = 1'h1; assign _T_prot__T_10_en = io_enq_ready & io_enq_valid; assign _T_qos__T_18_addr = value_1; assign _T_qos__T_18_data = _T_qos[_T_qos__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] assign _T_qos__T_10_data = io_enq_bits_qos; assign _T_qos__T_10_addr = value; assign _T_qos__T_10_mask = 1'h1; assign _T_qos__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10818.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10819.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10820.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10821.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10822.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10825.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10841.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10847.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10850.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@10857.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@10855.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10867.4] assign io_deq_bits_addr = _T_addr__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10866.4] assign io_deq_bits_len = _T_len__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10865.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10864.4] assign io_deq_bits_burst = _T_burst__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10863.4] assign io_deq_bits_lock = _T_lock__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10862.4] assign io_deq_bits_cache = _T_cache__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10861.4] assign io_deq_bits_prot = _T_prot__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10860.4] assign io_deq_bits_qos = _T_qos__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10859.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_addr[initvar] = _RAND_1[30:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_len[initvar] = _RAND_2[7:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_3[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_burst[initvar] = _RAND_4[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_lock[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_cache[initvar] = _RAND_6[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_prot[initvar] = _RAND_7[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_8 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_qos[initvar] = _RAND_8[3:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; value_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_1 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_addr__T_10_en & _T_addr__T_10_mask) begin _T_addr[_T_addr__T_10_addr] <= _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_len__T_10_en & _T_len__T_10_mask) begin _T_len[_T_len__T_10_addr] <= _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_burst__T_10_en & _T_burst__T_10_mask) begin _T_burst[_T_burst__T_10_addr] <= _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_lock__T_10_en & _T_lock__T_10_mask) begin _T_lock[_T_lock__T_10_addr] <= _T_lock__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_cache__T_10_en & _T_cache__T_10_mask) begin _T_cache[_T_cache__T_10_addr] <= _T_cache__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_prot__T_10_en & _T_prot__T_10_mask) begin _T_prot[_T_prot__T_10_addr] <= _T_prot__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if(_T_qos__T_10_en & _T_qos__T_10_mask) begin _T_qos[_T_qos__T_10_addr] <= _T_qos__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10814.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_1( // @[:freechips.rocketchip.system.TinyConfig.fir@10875.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@10876.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@10877.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] input [3:0] io_enq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] output [3:0] io_deq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@10878.4] ); reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg [31:0] _RAND_0; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg [3:0] _T_strb [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg [31:0] _RAND_1; wire [3:0] _T_strb__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_strb__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire [3:0] _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_strb__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_strb__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_strb__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg _T_last [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg [31:0] _RAND_2; wire _T_last__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_last__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10881.4] reg [31:0] _RAND_3; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10882.4] reg [31:0] _RAND_4; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@10883.4] reg [31:0] _RAND_5; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10884.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10885.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10886.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10887.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10888.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10891.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10901.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10907.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10910.4] assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_strb__T_18_addr = value_1; assign _T_strb__T_18_data = _T_strb[_T_strb__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] assign _T_strb__T_10_data = io_enq_bits_strb; assign _T_strb__T_10_addr = value; assign _T_strb__T_10_mask = 1'h1; assign _T_strb__T_10_en = io_enq_ready & io_enq_valid; assign _T_last__T_18_addr = value_1; assign _T_last__T_18_data = _T_last[_T_last__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = value; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10884.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10885.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10886.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10887.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10888.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10891.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10901.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10907.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10910.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@10917.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@10915.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10921.4] assign io_deq_bits_strb = _T_strb__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10920.4] assign io_deq_bits_last = _T_last__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10919.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_0[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_strb[initvar] = _RAND_1[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_last[initvar] = _RAND_2[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; value = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; value_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] end if(_T_strb__T_10_en & _T_strb__T_10_mask) begin _T_strb[_T_strb__T_10_addr] <= _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10880.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_2( // @[:freechips.rocketchip.system.TinyConfig.fir@10929.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@10930.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@10931.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] output [1:0] io_deq_bits_resp // @[:freechips.rocketchip.system.TinyConfig.fir@10932.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] reg [1:0] _T_resp [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] reg [31:0] _RAND_1; wire [1:0] _T_resp__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_resp__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10935.4] reg [31:0] _RAND_2; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@10936.4] reg [31:0] _RAND_3; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@10937.4] reg [31:0] _RAND_4; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10938.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10939.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10940.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10941.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10942.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10945.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10954.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10960.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10963.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_resp__T_18_addr = value_1; assign _T_resp__T_18_data = _T_resp[_T_resp__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = value; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@10938.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@10939.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@10940.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@10941.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10942.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@10945.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10954.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@10960.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@10963.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@10970.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@10968.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10973.4] assign io_deq_bits_resp = _T_resp__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@10972.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_resp[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; value = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; value_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@10934.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_4( // @[:freechips.rocketchip.system.TinyConfig.fir@11047.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@11048.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@11049.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@11050.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [31:0] _RAND_1; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [1:0] _T_resp [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [31:0] _RAND_2; wire [1:0] _T_resp__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_resp__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg _T_last [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg [31:0] _RAND_3; wire _T_last__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_last__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@11053.4] reg [31:0] _RAND_4; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@11054.4] reg [31:0] _RAND_5; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@11055.4] reg [31:0] _RAND_6; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@11056.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11057.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@11058.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@11059.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11060.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11063.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11074.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11080.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11083.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_resp__T_18_addr = value_1; assign _T_resp__T_18_data = _T_resp[_T_resp__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = value; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = io_enq_ready & io_enq_valid; assign _T_last__T_18_addr = value_1; assign _T_last__T_18_data = _T_last[_T_last__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = value; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@11056.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11057.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@11058.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@11059.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11060.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11063.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11074.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11080.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11083.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@11090.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@11088.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11095.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11094.4] assign io_deq_bits_resp = _T_resp__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11093.4] assign io_deq_bits_last = _T_last__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11092.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_1[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_resp[initvar] = _RAND_2[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_last[initvar] = _RAND_3[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; value = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; value_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_1 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11052.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module AXI4Buffer( // @[:freechips.rocketchip.system.TinyConfig.fir@11103.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@11104.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@11105.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@11106.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [30:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [7:0] Queue_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [1:0] Queue_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_enq_bits_lock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_enq_bits_cache; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [2:0] Queue_io_enq_bits_prot; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_enq_bits_qos; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [30:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [7:0] Queue_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [1:0] Queue_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_io_deq_bits_lock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_deq_bits_cache; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [2:0] Queue_io_deq_bits_prot; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire [3:0] Queue_io_deq_bits_qos; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire [3:0] Queue_1_io_enq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire [3:0] Queue_1_io_deq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_1_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] wire Queue_2_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_2_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_2_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_2_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire [3:0] Queue_2_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire [1:0] Queue_2_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_2_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_2_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire [3:0] Queue_2_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire [1:0] Queue_2_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] wire Queue_3_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [30:0] Queue_3_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [7:0] Queue_3_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [2:0] Queue_3_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [1:0] Queue_3_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_enq_bits_lock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_enq_bits_cache; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [2:0] Queue_3_io_enq_bits_prot; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_enq_bits_qos; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [30:0] Queue_3_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [7:0] Queue_3_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [2:0] Queue_3_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [1:0] Queue_3_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_3_io_deq_bits_lock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_deq_bits_cache; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [2:0] Queue_3_io_deq_bits_prot; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire [3:0] Queue_3_io_deq_bits_qos; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] wire Queue_4_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [3:0] Queue_4_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [31:0] Queue_4_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [1:0] Queue_4_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [3:0] Queue_4_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [31:0] Queue_4_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire [1:0] Queue_4_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] wire Queue_4_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] Queue Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11117.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_addr(Queue_io_enq_bits_addr), .io_enq_bits_len(Queue_io_enq_bits_len), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_burst(Queue_io_enq_bits_burst), .io_enq_bits_lock(Queue_io_enq_bits_lock), .io_enq_bits_cache(Queue_io_enq_bits_cache), .io_enq_bits_prot(Queue_io_enq_bits_prot), .io_enq_bits_qos(Queue_io_enq_bits_qos), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_addr(Queue_io_deq_bits_addr), .io_deq_bits_len(Queue_io_deq_bits_len), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_burst(Queue_io_deq_bits_burst), .io_deq_bits_lock(Queue_io_deq_bits_lock), .io_deq_bits_cache(Queue_io_deq_bits_cache), .io_deq_bits_prot(Queue_io_deq_bits_prot), .io_deq_bits_qos(Queue_io_deq_bits_qos) ); Queue_1 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11144.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_strb(Queue_1_io_enq_bits_strb), .io_enq_bits_last(Queue_1_io_enq_bits_last), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_strb(Queue_1_io_deq_bits_strb), .io_deq_bits_last(Queue_1_io_deq_bits_last) ); Queue_2 Queue_2 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11159.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits_id(Queue_2_io_enq_bits_id), .io_enq_bits_resp(Queue_2_io_enq_bits_resp), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits_id(Queue_2_io_deq_bits_id), .io_deq_bits_resp(Queue_2_io_deq_bits_resp) ); Queue Queue_3 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11172.4] .clock(Queue_3_clock), .reset(Queue_3_reset), .io_enq_ready(Queue_3_io_enq_ready), .io_enq_valid(Queue_3_io_enq_valid), .io_enq_bits_id(Queue_3_io_enq_bits_id), .io_enq_bits_addr(Queue_3_io_enq_bits_addr), .io_enq_bits_len(Queue_3_io_enq_bits_len), .io_enq_bits_size(Queue_3_io_enq_bits_size), .io_enq_bits_burst(Queue_3_io_enq_bits_burst), .io_enq_bits_lock(Queue_3_io_enq_bits_lock), .io_enq_bits_cache(Queue_3_io_enq_bits_cache), .io_enq_bits_prot(Queue_3_io_enq_bits_prot), .io_enq_bits_qos(Queue_3_io_enq_bits_qos), .io_deq_ready(Queue_3_io_deq_ready), .io_deq_valid(Queue_3_io_deq_valid), .io_deq_bits_id(Queue_3_io_deq_bits_id), .io_deq_bits_addr(Queue_3_io_deq_bits_addr), .io_deq_bits_len(Queue_3_io_deq_bits_len), .io_deq_bits_size(Queue_3_io_deq_bits_size), .io_deq_bits_burst(Queue_3_io_deq_bits_burst), .io_deq_bits_lock(Queue_3_io_deq_bits_lock), .io_deq_bits_cache(Queue_3_io_deq_bits_cache), .io_deq_bits_prot(Queue_3_io_deq_bits_prot), .io_deq_bits_qos(Queue_3_io_deq_bits_qos) ); Queue_4 Queue_4 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@11199.4] .clock(Queue_4_clock), .reset(Queue_4_reset), .io_enq_ready(Queue_4_io_enq_ready), .io_enq_valid(Queue_4_io_enq_valid), .io_enq_bits_id(Queue_4_io_enq_bits_id), .io_enq_bits_data(Queue_4_io_enq_bits_data), .io_enq_bits_resp(Queue_4_io_enq_bits_resp), .io_enq_bits_last(Queue_4_io_enq_bits_last), .io_deq_ready(Queue_4_io_deq_ready), .io_deq_valid(Queue_4_io_deq_valid), .io_deq_bits_id(Queue_4_io_deq_bits_id), .io_deq_bits_data(Queue_4_io_deq_bits_data), .io_deq_bits_resp(Queue_4_io_deq_bits_resp), .io_deq_bits_last(Queue_4_io_deq_bits_last) ); assign auto_in_aw_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_w_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_b_valid = Queue_2_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_b_bits_id = Queue_2_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_b_bits_resp = Queue_2_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_ar_ready = Queue_3_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_r_valid = Queue_4_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_r_bits_id = Queue_4_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_r_bits_data = Queue_4_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_r_bits_resp = Queue_4_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_in_r_bits_last = Queue_4_io_deq_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11116.4] assign auto_out_aw_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_addr = Queue_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_len = Queue_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_burst = Queue_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_lock = Queue_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_cache = Queue_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_prot = Queue_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_aw_bits_qos = Queue_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_w_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_w_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_w_bits_strb = Queue_1_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_w_bits_last = Queue_1_io_deq_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_b_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_valid = Queue_3_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_id = Queue_3_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_addr = Queue_3_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_len = Queue_3_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_size = Queue_3_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_burst = Queue_3_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_lock = Queue_3_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_cache = Queue_3_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_prot = Queue_3_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_ar_bits_qos = Queue_3_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign auto_out_r_ready = Queue_4_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11115.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11118.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11119.4] assign Queue_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@11120.4] assign Queue_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11129.4] assign Queue_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11128.4] assign Queue_io_enq_bits_len = auto_in_aw_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11127.4] assign Queue_io_enq_bits_size = auto_in_aw_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11126.4] assign Queue_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11125.4] assign Queue_io_enq_bits_lock = auto_in_aw_bits_lock; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11124.4] assign Queue_io_enq_bits_cache = auto_in_aw_bits_cache; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11123.4] assign Queue_io_enq_bits_prot = auto_in_aw_bits_prot; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11122.4] assign Queue_io_enq_bits_qos = auto_in_aw_bits_qos; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11121.4] assign Queue_io_deq_ready = auto_out_aw_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@11142.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11145.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11146.4] assign Queue_1_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@11147.4] assign Queue_1_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11150.4] assign Queue_1_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11149.4] assign Queue_1_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11148.4] assign Queue_1_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@11157.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11160.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11161.4] assign Queue_2_io_enq_valid = auto_out_b_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@11162.4] assign Queue_2_io_enq_bits_id = auto_out_b_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11164.4] assign Queue_2_io_enq_bits_resp = auto_out_b_bits_resp; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11163.4] assign Queue_2_io_deq_ready = auto_in_b_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@11170.4] assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11173.4] assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11174.4] assign Queue_3_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@11175.4] assign Queue_3_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11184.4] assign Queue_3_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11183.4] assign Queue_3_io_enq_bits_len = auto_in_ar_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11182.4] assign Queue_3_io_enq_bits_size = auto_in_ar_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11181.4] assign Queue_3_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11180.4] assign Queue_3_io_enq_bits_lock = auto_in_ar_bits_lock; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11179.4] assign Queue_3_io_enq_bits_cache = auto_in_ar_bits_cache; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11178.4] assign Queue_3_io_enq_bits_prot = auto_in_ar_bits_prot; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11177.4] assign Queue_3_io_enq_bits_qos = auto_in_ar_bits_qos; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11176.4] assign Queue_3_io_deq_ready = auto_out_ar_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@11197.4] assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11200.4] assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11201.4] assign Queue_4_io_enq_valid = auto_out_r_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@11202.4] assign Queue_4_io_enq_bits_id = auto_out_r_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11206.4] assign Queue_4_io_enq_bits_data = auto_out_r_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11205.4] assign Queue_4_io_enq_bits_resp = auto_out_r_bits_resp; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11204.4] assign Queue_4_io_enq_bits_last = auto_out_r_bits_last; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@11203.4] assign Queue_4_io_deq_ready = auto_in_r_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@11214.4] endmodule module Queue_5( // @[:freechips.rocketchip.system.TinyConfig.fir@11217.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@11218.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@11219.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] input [8:0] io_enq_bits, // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] output [8:0] io_deq_bits // @[:freechips.rocketchip.system.TinyConfig.fir@11220.4] ); reg [8:0] _T [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] reg [31:0] _RAND_0; wire [8:0] _T__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] wire _T__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] wire [8:0] _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] wire _T__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] wire _T__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] wire _T__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@11226.4] reg [31:0] _RAND_1; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11228.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11231.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11235.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11245.4] assign _T__T_14_addr = 1'h0; assign _T__T_14_data = _T[_T__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] assign _T__T_10_data = io_enq_bits; assign _T__T_10_addr = 1'h0; assign _T__T_10_mask = 1'h1; assign _T__T_10_en = io_enq_ready & io_enq_valid; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11228.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11231.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11235.4] assign _T_11 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11245.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@11252.4] assign io_deq_valid = _T_3 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@11250.4] assign io_deq_bits = _T__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11254.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T[initvar] = _RAND_0[8:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_1 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T__T_10_en & _T__T_10_mask) begin _T[_T__T_10_addr] <= _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11225.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin _T_1 <= _T_6; end end end endmodule module Queue_7( // @[:freechips.rocketchip.system.TinyConfig.fir@11307.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@11308.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@11309.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] input [8:0] io_enq_bits, // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] output [8:0] io_deq_bits // @[:freechips.rocketchip.system.TinyConfig.fir@11310.4] ); reg [8:0] _T [0:7]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] reg [31:0] _RAND_0; wire [8:0] _T__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] wire [2:0] _T__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] wire [8:0] _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] wire [2:0] _T__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] wire _T__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] wire _T__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] reg [2:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@11316.4] reg [31:0] _RAND_1; reg [2:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@11317.4] reg [31:0] _RAND_2; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@11318.4] reg [31:0] _RAND_3; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@11319.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11320.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@11321.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@11322.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11323.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11327.4] wire [2:0] _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11336.6] wire [2:0] _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11342.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11345.4] assign _T__T_18_addr = value_1; assign _T__T_18_data = _T[_T__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] assign _T__T_10_data = io_enq_bits; assign _T__T_10_addr = value; assign _T__T_10_mask = 1'h1; assign _T__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@11319.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@11320.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@11321.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@11322.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11323.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@11327.4] assign _T_12 = value + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11336.6] assign _T_14 = value_1 + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@11342.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@11345.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@11352.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@11350.4] assign io_deq_bits = _T__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@11354.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 8; initvar = initvar+1) _T[initvar] = _RAND_0[8:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; value = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; value_1 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T__T_10_en & _T__T_10_mask) begin _T[_T__T_10_addr] <= _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@11315.4] end if (reset) begin value <= 3'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 3'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module AXI4UserYanker( // @[:freechips.rocketchip.system.TinyConfig.fir@11617.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@11618.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@11619.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@11620.4] ); wire Queue_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire [8:0] Queue_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire [8:0] Queue_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] wire Queue_1_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_1_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_1_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_1_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire [8:0] Queue_1_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_1_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_1_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire [8:0] Queue_1_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] wire Queue_2_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_2_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_2_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_2_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire [8:0] Queue_2_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_2_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_2_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire [8:0] Queue_2_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] wire Queue_3_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_3_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_3_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_3_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire [8:0] Queue_3_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_3_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_3_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire [8:0] Queue_3_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] wire Queue_4_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_4_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_4_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_4_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire [8:0] Queue_4_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_4_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_4_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire [8:0] Queue_4_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] wire Queue_5_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_5_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_5_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_5_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire [8:0] Queue_5_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_5_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_5_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire [8:0] Queue_5_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] wire Queue_6_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_6_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_6_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_6_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire [8:0] Queue_6_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_6_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_6_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire [8:0] Queue_6_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] wire Queue_7_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire Queue_7_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire Queue_7_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire Queue_7_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire [8:0] Queue_7_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire Queue_7_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire Queue_7_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire [8:0] Queue_7_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] wire _T_26_0; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11713.4] wire _T_26_1; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11714.4] wire _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _T_26_2; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11715.4] wire _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _T_26_3; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11716.4] wire _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _GEN_15; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] wire _T_31; // @[UserYanker.scala 54:15:freechips.rocketchip.system.TinyConfig.fir@11770.4] wire _T_29_0; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11736.4] wire _T_29_1; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11737.4] wire _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _T_29_2; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11738.4] wire _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _T_29_3; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11739.4] wire _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _T_32; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] wire _T_34; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11773.4] wire _T_35; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11774.4] wire [8:0] _T_30_0; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11754.4] wire [8:0] _T_30_1; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11755.4] wire [8:0] _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _T_30_2; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11756.4] wire [8:0] _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _T_30_3; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11757.4] wire [8:0] _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [8:0] _GEN_46; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] wire [15:0] _T_37; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@11782.4] wire _T_39; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11784.4] wire _T_40; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11785.4] wire _T_41; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11786.4] wire _T_42; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11787.4] wire [15:0] _T_56; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@11801.4] wire _T_58; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11803.4] wire _T_59; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11804.4] wire _T_60; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11805.4] wire _T_61; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11806.4] wire _T_74; // @[UserYanker.scala 61:37:freechips.rocketchip.system.TinyConfig.fir@11819.4] wire _T_75; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11820.4] wire _T_77; // @[UserYanker.scala 62:37:freechips.rocketchip.system.TinyConfig.fir@11823.4] wire _T_80; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11828.4] wire _T_85; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11836.4] wire _T_90; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11844.4] wire _T_154_0; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11949.4] wire _T_154_1; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11950.4] wire _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _T_154_2; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11951.4] wire _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _T_154_3; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11952.4] wire _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _GEN_63; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] wire _T_159; // @[UserYanker.scala 75:15:freechips.rocketchip.system.TinyConfig.fir@12006.4] wire _T_157_0; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11972.4] wire _T_157_1; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11973.4] wire _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _T_157_2; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11974.4] wire _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _T_157_3; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11975.4] wire _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _T_160; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] wire _T_162; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12009.4] wire _T_163; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12010.4] wire [8:0] _T_158_0; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11990.4] wire [8:0] _T_158_1; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11991.4] wire [8:0] _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _T_158_2; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11992.4] wire [8:0] _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _T_158_3; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11993.4] wire [8:0] _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [8:0] _GEN_94; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] wire [15:0] _T_165; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12018.4] wire _T_167; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12020.4] wire _T_168; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12021.4] wire _T_169; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12022.4] wire _T_170; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12023.4] wire [15:0] _T_184; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12037.4] wire _T_186; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12039.4] wire _T_187; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12040.4] wire _T_188; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12041.4] wire _T_189; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12042.4] wire _T_202; // @[UserYanker.scala 82:37:freechips.rocketchip.system.TinyConfig.fir@12055.4] wire _T_204; // @[UserYanker.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@12058.4] Queue_5 Queue ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11631.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits(Queue_io_enq_bits), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits(Queue_io_deq_bits) ); Queue_5 Queue_1 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11635.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits(Queue_1_io_enq_bits), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits(Queue_1_io_deq_bits) ); Queue_7 Queue_2 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11639.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits(Queue_2_io_enq_bits), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits(Queue_2_io_deq_bits) ); Queue_7 Queue_3 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11643.4] .clock(Queue_3_clock), .reset(Queue_3_reset), .io_enq_ready(Queue_3_io_enq_ready), .io_enq_valid(Queue_3_io_enq_valid), .io_enq_bits(Queue_3_io_enq_bits), .io_deq_ready(Queue_3_io_deq_ready), .io_deq_valid(Queue_3_io_deq_valid), .io_deq_bits(Queue_3_io_deq_bits) ); Queue_5 Queue_4 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11671.4] .clock(Queue_4_clock), .reset(Queue_4_reset), .io_enq_ready(Queue_4_io_enq_ready), .io_enq_valid(Queue_4_io_enq_valid), .io_enq_bits(Queue_4_io_enq_bits), .io_deq_ready(Queue_4_io_deq_ready), .io_deq_valid(Queue_4_io_deq_valid), .io_deq_bits(Queue_4_io_deq_bits) ); Queue_5 Queue_5 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11675.4] .clock(Queue_5_clock), .reset(Queue_5_reset), .io_enq_ready(Queue_5_io_enq_ready), .io_enq_valid(Queue_5_io_enq_valid), .io_enq_bits(Queue_5_io_enq_bits), .io_deq_ready(Queue_5_io_deq_ready), .io_deq_valid(Queue_5_io_deq_valid), .io_deq_bits(Queue_5_io_deq_bits) ); Queue_7 Queue_6 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11679.4] .clock(Queue_6_clock), .reset(Queue_6_reset), .io_enq_ready(Queue_6_io_enq_ready), .io_enq_valid(Queue_6_io_enq_valid), .io_enq_bits(Queue_6_io_enq_bits), .io_deq_ready(Queue_6_io_deq_ready), .io_deq_valid(Queue_6_io_deq_valid), .io_deq_bits(Queue_6_io_deq_bits) ); Queue_7 Queue_7 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@11683.4] .clock(Queue_7_clock), .reset(Queue_7_reset), .io_enq_ready(Queue_7_io_enq_ready), .io_enq_valid(Queue_7_io_enq_valid), .io_enq_bits(Queue_7_io_enq_bits), .io_deq_ready(Queue_7_io_deq_ready), .io_deq_valid(Queue_7_io_deq_valid), .io_deq_bits(Queue_7_io_deq_bits) ); assign _T_26_0 = Queue_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11713.4] assign _T_26_1 = Queue_1_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11714.4] assign _GEN_1 = 4'h1 == auto_in_ar_bits_id ? _T_26_1 : _T_26_0; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _T_26_2 = Queue_2_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11715.4] assign _GEN_2 = 4'h2 == auto_in_ar_bits_id ? _T_26_2 : _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _T_26_3 = Queue_3_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11711.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@11716.4] assign _GEN_3 = 4'h3 == auto_in_ar_bits_id ? _T_26_3 : _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_4 = 4'h4 == auto_in_ar_bits_id ? 1'h0 : _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_5 = 4'h5 == auto_in_ar_bits_id ? 1'h0 : _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_6 = 4'h6 == auto_in_ar_bits_id ? 1'h0 : _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_7 = 4'h7 == auto_in_ar_bits_id ? 1'h0 : _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_8 = 4'h8 == auto_in_ar_bits_id ? 1'h0 : _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_9 = 4'h9 == auto_in_ar_bits_id ? 1'h0 : _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_10 = 4'ha == auto_in_ar_bits_id ? 1'h0 : _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_11 = 4'hb == auto_in_ar_bits_id ? 1'h0 : _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_12 = 4'hc == auto_in_ar_bits_id ? 1'h0 : _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_13 = 4'hd == auto_in_ar_bits_id ? 1'h0 : _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_14 = 4'he == auto_in_ar_bits_id ? 1'h0 : _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _GEN_15 = 4'hf == auto_in_ar_bits_id ? 1'h0 : _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@11729.4] assign _T_31 = auto_out_r_valid == 1'h0; // @[UserYanker.scala 54:15:freechips.rocketchip.system.TinyConfig.fir@11770.4] assign _T_29_0 = Queue_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11736.4] assign _T_29_1 = Queue_1_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11737.4] assign _GEN_17 = 4'h1 == auto_out_r_bits_id ? _T_29_1 : _T_29_0; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _T_29_2 = Queue_2_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11738.4] assign _GEN_18 = 4'h2 == auto_out_r_bits_id ? _T_29_2 : _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _T_29_3 = Queue_3_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11734.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@11739.4] assign _GEN_19 = 4'h3 == auto_out_r_bits_id ? _T_29_3 : _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_20 = 4'h4 == auto_out_r_bits_id ? 1'h0 : _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_21 = 4'h5 == auto_out_r_bits_id ? 1'h0 : _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_22 = 4'h6 == auto_out_r_bits_id ? 1'h0 : _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_23 = 4'h7 == auto_out_r_bits_id ? 1'h0 : _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_24 = 4'h8 == auto_out_r_bits_id ? 1'h0 : _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_25 = 4'h9 == auto_out_r_bits_id ? 1'h0 : _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_26 = 4'ha == auto_out_r_bits_id ? 1'h0 : _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_27 = 4'hb == auto_out_r_bits_id ? 1'h0 : _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_28 = 4'hc == auto_out_r_bits_id ? 1'h0 : _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_29 = 4'hd == auto_out_r_bits_id ? 1'h0 : _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_30 = 4'he == auto_out_r_bits_id ? 1'h0 : _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _GEN_31 = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _T_32 = _T_31 | _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@11771.4] assign _T_34 = _T_32 | reset; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11773.4] assign _T_35 = _T_34 == 1'h0; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11774.4] assign _T_30_0 = Queue_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11754.4] assign _T_30_1 = Queue_1_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11755.4] assign _GEN_33 = 4'h1 == auto_out_r_bits_id ? _T_30_1 : _T_30_0; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _T_30_2 = Queue_2_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11756.4] assign _GEN_34 = 4'h2 == auto_out_r_bits_id ? _T_30_2 : _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _T_30_3 = Queue_3_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11752.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@11757.4] assign _GEN_35 = 4'h3 == auto_out_r_bits_id ? _T_30_3 : _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_36 = 4'h4 == auto_out_r_bits_id ? 9'h0 : _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_37 = 4'h5 == auto_out_r_bits_id ? 9'h0 : _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_38 = 4'h6 == auto_out_r_bits_id ? 9'h0 : _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_39 = 4'h7 == auto_out_r_bits_id ? 9'h0 : _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_40 = 4'h8 == auto_out_r_bits_id ? 9'h0 : _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_41 = 4'h9 == auto_out_r_bits_id ? 9'h0 : _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_42 = 4'ha == auto_out_r_bits_id ? 9'h0 : _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_43 = 4'hb == auto_out_r_bits_id ? 9'h0 : _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_44 = 4'hc == auto_out_r_bits_id ? 9'h0 : _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_45 = 4'hd == auto_out_r_bits_id ? 9'h0 : _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _GEN_46 = 4'he == auto_out_r_bits_id ? 9'h0 : _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.TinyConfig.fir@11780.4] assign _T_37 = 16'h1 << auto_in_ar_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@11782.4] assign _T_39 = _T_37[0]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11784.4] assign _T_40 = _T_37[1]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11785.4] assign _T_41 = _T_37[2]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11786.4] assign _T_42 = _T_37[3]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@11787.4] assign _T_56 = 16'h1 << auto_out_r_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@11801.4] assign _T_58 = _T_56[0]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11803.4] assign _T_59 = _T_56[1]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11804.4] assign _T_60 = _T_56[2]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11805.4] assign _T_61 = _T_56[3]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@11806.4] assign _T_74 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala 61:37:freechips.rocketchip.system.TinyConfig.fir@11819.4] assign _T_75 = _T_74 & _T_58; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11820.4] assign _T_77 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala 62:37:freechips.rocketchip.system.TinyConfig.fir@11823.4] assign _T_80 = _T_74 & _T_59; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11828.4] assign _T_85 = _T_74 & _T_60; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11836.4] assign _T_90 = _T_74 & _T_61; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@11844.4] assign _T_154_0 = Queue_4_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11949.4] assign _T_154_1 = Queue_5_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11950.4] assign _GEN_49 = 4'h1 == auto_in_aw_bits_id ? _T_154_1 : _T_154_0; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _T_154_2 = Queue_6_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11951.4] assign _GEN_50 = 4'h2 == auto_in_aw_bits_id ? _T_154_2 : _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _T_154_3 = Queue_7_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11947.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@11952.4] assign _GEN_51 = 4'h3 == auto_in_aw_bits_id ? _T_154_3 : _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_52 = 4'h4 == auto_in_aw_bits_id ? 1'h0 : _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_53 = 4'h5 == auto_in_aw_bits_id ? 1'h0 : _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_54 = 4'h6 == auto_in_aw_bits_id ? 1'h0 : _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_55 = 4'h7 == auto_in_aw_bits_id ? 1'h0 : _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_56 = 4'h8 == auto_in_aw_bits_id ? 1'h0 : _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_57 = 4'h9 == auto_in_aw_bits_id ? 1'h0 : _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_58 = 4'ha == auto_in_aw_bits_id ? 1'h0 : _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_59 = 4'hb == auto_in_aw_bits_id ? 1'h0 : _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_60 = 4'hc == auto_in_aw_bits_id ? 1'h0 : _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_61 = 4'hd == auto_in_aw_bits_id ? 1'h0 : _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_62 = 4'he == auto_in_aw_bits_id ? 1'h0 : _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _GEN_63 = 4'hf == auto_in_aw_bits_id ? 1'h0 : _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@11965.4] assign _T_159 = auto_out_b_valid == 1'h0; // @[UserYanker.scala 75:15:freechips.rocketchip.system.TinyConfig.fir@12006.4] assign _T_157_0 = Queue_4_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11972.4] assign _T_157_1 = Queue_5_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11973.4] assign _GEN_65 = 4'h1 == auto_out_b_bits_id ? _T_157_1 : _T_157_0; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _T_157_2 = Queue_6_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11974.4] assign _GEN_66 = 4'h2 == auto_out_b_bits_id ? _T_157_2 : _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _T_157_3 = Queue_7_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11970.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@11975.4] assign _GEN_67 = 4'h3 == auto_out_b_bits_id ? _T_157_3 : _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_68 = 4'h4 == auto_out_b_bits_id ? 1'h0 : _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_69 = 4'h5 == auto_out_b_bits_id ? 1'h0 : _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_70 = 4'h6 == auto_out_b_bits_id ? 1'h0 : _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_71 = 4'h7 == auto_out_b_bits_id ? 1'h0 : _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_72 = 4'h8 == auto_out_b_bits_id ? 1'h0 : _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_73 = 4'h9 == auto_out_b_bits_id ? 1'h0 : _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_74 = 4'ha == auto_out_b_bits_id ? 1'h0 : _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_75 = 4'hb == auto_out_b_bits_id ? 1'h0 : _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_76 = 4'hc == auto_out_b_bits_id ? 1'h0 : _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_77 = 4'hd == auto_out_b_bits_id ? 1'h0 : _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_78 = 4'he == auto_out_b_bits_id ? 1'h0 : _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _GEN_79 = 4'hf == auto_out_b_bits_id ? 1'h0 : _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _T_160 = _T_159 | _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@12007.4] assign _T_162 = _T_160 | reset; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12009.4] assign _T_163 = _T_162 == 1'h0; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12010.4] assign _T_158_0 = Queue_4_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11990.4] assign _T_158_1 = Queue_5_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11991.4] assign _GEN_81 = 4'h1 == auto_out_b_bits_id ? _T_158_1 : _T_158_0; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _T_158_2 = Queue_6_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11992.4] assign _GEN_82 = 4'h2 == auto_out_b_bits_id ? _T_158_2 : _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _T_158_3 = Queue_7_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11988.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@11993.4] assign _GEN_83 = 4'h3 == auto_out_b_bits_id ? _T_158_3 : _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_84 = 4'h4 == auto_out_b_bits_id ? 9'h0 : _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_85 = 4'h5 == auto_out_b_bits_id ? 9'h0 : _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_86 = 4'h6 == auto_out_b_bits_id ? 9'h0 : _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_87 = 4'h7 == auto_out_b_bits_id ? 9'h0 : _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_88 = 4'h8 == auto_out_b_bits_id ? 9'h0 : _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_89 = 4'h9 == auto_out_b_bits_id ? 9'h0 : _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_90 = 4'ha == auto_out_b_bits_id ? 9'h0 : _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_91 = 4'hb == auto_out_b_bits_id ? 9'h0 : _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_92 = 4'hc == auto_out_b_bits_id ? 9'h0 : _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_93 = 4'hd == auto_out_b_bits_id ? 9'h0 : _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _GEN_94 = 4'he == auto_out_b_bits_id ? 9'h0 : _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.TinyConfig.fir@12016.4] assign _T_165 = 16'h1 << auto_in_aw_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12018.4] assign _T_167 = _T_165[0]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12020.4] assign _T_168 = _T_165[1]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12021.4] assign _T_169 = _T_165[2]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12022.4] assign _T_170 = _T_165[3]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@12023.4] assign _T_184 = 16'h1 << auto_out_b_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12037.4] assign _T_186 = _T_184[0]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12039.4] assign _T_187 = _T_184[1]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12040.4] assign _T_188 = _T_184[2]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12041.4] assign _T_189 = _T_184[3]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@12042.4] assign _T_202 = auto_out_b_valid & auto_in_b_ready; // @[UserYanker.scala 82:37:freechips.rocketchip.system.TinyConfig.fir@12055.4] assign _T_204 = auto_in_aw_valid & auto_out_aw_ready; // @[UserYanker.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@12058.4] assign auto_in_aw_ready = auto_out_aw_ready & _GEN_63; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_b_bits_user = 4'hf == auto_out_b_bits_id ? 9'h0 : _GEN_94; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_ar_ready = auto_out_ar_ready & _GEN_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_bits_user = 4'hf == auto_out_r_bits_id ? 9'h0 : _GEN_46; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@11630.4] assign auto_out_aw_valid = auto_in_aw_valid & _GEN_63; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_valid = auto_in_ar_valid & _GEN_15; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@11629.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11633.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11634.4] assign Queue_io_enq_valid = _T_77 & _T_39; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@11825.4] assign Queue_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@11826.4] assign Queue_io_deq_ready = _T_75 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@11822.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11637.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11638.4] assign Queue_1_io_enq_valid = _T_77 & _T_40; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@11833.4] assign Queue_1_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@11834.4] assign Queue_1_io_deq_ready = _T_80 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@11830.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11641.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11642.4] assign Queue_2_io_enq_valid = _T_77 & _T_41; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@11841.4] assign Queue_2_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@11842.4] assign Queue_2_io_deq_ready = _T_85 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@11838.4] assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11645.4] assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11646.4] assign Queue_3_io_enq_valid = _T_77 & _T_42; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@11849.4] assign Queue_3_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@11850.4] assign Queue_3_io_deq_ready = _T_90 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@11846.4] assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11673.4] assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11674.4] assign Queue_4_io_enq_valid = _T_204 & _T_167; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@12060.4] assign Queue_4_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@12061.4] assign Queue_4_io_deq_ready = _T_202 & _T_186; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@12057.4] assign Queue_5_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11677.4] assign Queue_5_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11678.4] assign Queue_5_io_enq_valid = _T_204 & _T_168; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@12067.4] assign Queue_5_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@12068.4] assign Queue_5_io_deq_ready = _T_202 & _T_187; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@12064.4] assign Queue_6_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11681.4] assign Queue_6_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11682.4] assign Queue_6_io_enq_valid = _T_204 & _T_169; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@12074.4] assign Queue_6_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@12075.4] assign Queue_6_io_deq_ready = _T_202 & _T_188; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@12071.4] assign Queue_7_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@11685.4] assign Queue_7_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@11686.4] assign Queue_7_io_enq_valid = _T_204 & _T_170; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@12081.4] assign Queue_7_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@12082.4] assign Queue_7_io_deq_ready = _T_202 & _T_189; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@12078.4] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_35) begin $fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:54 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11776.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_35) begin $fatal; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@11777.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_163) begin $fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:75 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12012.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_163) begin $fatal; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@12013.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_13( // @[:freechips.rocketchip.system.TinyConfig.fir@12169.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@12170.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@12171.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input [8:0] io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output [8:0] io_deq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@12172.4] ); reg [3:0] _T_id [0:15]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _T_data [0:15]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _RAND_1; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [1:0] _T_resp [0:15]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _RAND_2; wire [1:0] _T_resp__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_resp__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [8:0] _T_user [0:15]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _RAND_3; wire [8:0] _T_user__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_user__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [8:0] _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg _T_last [0:15]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [31:0] _RAND_4; wire _T_last__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_last__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire [3:0] _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] reg [3:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@12178.4] reg [31:0] _RAND_5; reg [3:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@12179.4] reg [31:0] _RAND_6; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@12180.4] reg [31:0] _RAND_7; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@12181.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@12182.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@12183.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@12184.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12185.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12189.4] wire [3:0] _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@12198.6] wire [3:0] _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@12204.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@12207.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_resp__T_18_addr = value_1; assign _T_resp__T_18_data = _T_resp[_T_resp__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = value; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = io_enq_ready & io_enq_valid; assign _T_user__T_18_addr = value_1; assign _T_user__T_18_data = _T_user[_T_user__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = value; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = io_enq_ready & io_enq_valid; assign _T_last__T_18_addr = value_1; assign _T_last__T_18_data = _T_last[_T_last__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = value; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@12181.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@12182.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@12183.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@12184.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12185.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12189.4] assign _T_12 = value + 4'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@12198.6] assign _T_14 = value_1 + 4'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@12204.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@12207.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@12214.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@12212.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@12216.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@12216.4] assign io_deq_bits_resp = _T_resp__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@12216.4] assign io_deq_bits_user = _T_user__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@12216.4] assign io_deq_bits_last = _T_last__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@12216.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 16; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 16; initvar = initvar+1) _T_data[initvar] = _RAND_1[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 16; initvar = initvar+1) _T_resp[initvar] = _RAND_2[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 16; initvar = initvar+1) _T_user[initvar] = _RAND_3[8:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 16; initvar = initvar+1) _T_last[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; value = _RAND_5[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; value_1 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_1 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@12177.4] end if (reset) begin value <= 4'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 4'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module AXI4Deinterleaver( // @[:freechips.rocketchip.system.TinyConfig.fir@12389.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@12390.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@12391.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@12392.4] ); wire Queue_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [3:0] Queue_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [31:0] Queue_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [1:0] Queue_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [8:0] Queue_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [3:0] Queue_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [31:0] Queue_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [1:0] Queue_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire [8:0] Queue_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] wire Queue_1_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [3:0] Queue_1_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [1:0] Queue_1_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [8:0] Queue_1_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [3:0] Queue_1_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [1:0] Queue_1_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire [8:0] Queue_1_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_1_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] wire Queue_2_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [3:0] Queue_2_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [31:0] Queue_2_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [1:0] Queue_2_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [8:0] Queue_2_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [3:0] Queue_2_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [31:0] Queue_2_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [1:0] Queue_2_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire [8:0] Queue_2_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_2_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] wire Queue_3_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [3:0] Queue_3_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [31:0] Queue_3_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [1:0] Queue_3_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [8:0] Queue_3_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [3:0] Queue_3_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [31:0] Queue_3_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [1:0] Queue_3_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire [8:0] Queue_3_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] wire Queue_3_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] reg _T_14; // @[Deinterleaver.scala 50:29:freechips.rocketchip.system.TinyConfig.fir@12447.4] reg [31:0] _RAND_0; reg [3:0] _T_15; // @[Deinterleaver.scala 51:25:freechips.rocketchip.system.TinyConfig.fir@12448.4] reg [31:0] _RAND_1; wire [15:0] _T_17; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12450.4] wire [15:0] _T_20; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12453.4] reg [4:0] _T_22; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.TinyConfig.fir@12455.4] reg [31:0] _RAND_2; wire _T_24; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12458.4] wire _T_236_3; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12757.4] wire _T_236_2; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12756.4] wire _T_236_1; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12755.4] wire _T_236_0; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12754.4] wire _GEN_83; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_84; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_85; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_86; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_87; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_88; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_89; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_90; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_91; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_92; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_93; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_94; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_95; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_96; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _GEN_97; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] wire _T_25; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12459.4] wire _T_26; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12460.4] wire _T_27; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12461.4] wire _T_28; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12462.4] wire _T_29; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12463.4] wire _T_30; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12464.4] wire _T_187_3_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] wire _T_187_2_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] wire _T_187_1_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] wire _T_187_0_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] wire _GEN_11; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_16; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_21; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_26; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_31; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_36; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_41; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_46; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_51; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_56; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_61; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_66; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_71; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_76; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _GEN_81; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire _T_31; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12465.4] wire [4:0] _GEN_98; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12466.4] wire [4:0] _T_33; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12467.4] wire [4:0] _GEN_99; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12468.4] wire [4:0] _T_35; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12469.4] wire _T_36; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12472.4] wire _T_37; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12473.4] wire _T_38; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12474.4] wire _T_40; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12476.4] wire _T_41; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12477.4] wire _T_42; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12482.4] wire _T_43; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12483.4] wire _T_44; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12484.4] wire _T_46; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12486.4] wire _T_47; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12487.4] wire _T_48; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12492.4] reg [4:0] _T_49; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.TinyConfig.fir@12493.4] reg [31:0] _RAND_3; wire _T_51; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12496.4] wire _T_53; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12498.4] wire _T_54; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12499.4] wire _T_55; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12500.4] wire _T_57; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12502.4] wire _T_58; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12503.4] wire [4:0] _GEN_100; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12504.4] wire [4:0] _T_60; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12505.4] wire [4:0] _GEN_101; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12506.4] wire [4:0] _T_62; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12507.4] wire _T_63; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12510.4] wire _T_64; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12511.4] wire _T_65; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12512.4] wire _T_67; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12514.4] wire _T_68; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12515.4] wire _T_69; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12520.4] wire _T_70; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12521.4] wire _T_71; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12522.4] wire _T_73; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12524.4] wire _T_74; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12525.4] wire _T_75; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12530.4] reg [4:0] _T_76; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.TinyConfig.fir@12531.4] reg [31:0] _RAND_4; wire _T_78; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12534.4] wire _T_80; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12536.4] wire _T_81; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12537.4] wire _T_82; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12538.4] wire _T_84; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12540.4] wire _T_85; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12541.4] wire [4:0] _GEN_102; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12542.4] wire [4:0] _T_87; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12543.4] wire [4:0] _GEN_103; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12544.4] wire [4:0] _T_89; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12545.4] wire _T_90; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12548.4] wire _T_91; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12549.4] wire _T_92; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12550.4] wire _T_94; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12552.4] wire _T_95; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12553.4] wire _T_96; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12558.4] wire _T_97; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12559.4] wire _T_98; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12560.4] wire _T_100; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12562.4] wire _T_101; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12563.4] wire _T_102; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12568.4] reg [4:0] _T_103; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.TinyConfig.fir@12569.4] reg [31:0] _RAND_5; wire _T_105; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12572.4] wire _T_107; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12574.4] wire _T_108; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12575.4] wire _T_109; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12576.4] wire _T_111; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12578.4] wire _T_112; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12579.4] wire [4:0] _GEN_104; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12580.4] wire [4:0] _T_114; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12581.4] wire [4:0] _GEN_105; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12582.4] wire [4:0] _T_116; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12583.4] wire _T_117; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12586.4] wire _T_118; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12587.4] wire _T_119; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12588.4] wire _T_121; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12590.4] wire _T_122; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12591.4] wire _T_123; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12596.4] wire _T_124; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12597.4] wire _T_125; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12598.4] wire _T_127; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12600.4] wire _T_128; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12601.4] wire _T_129; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12606.4] wire [15:0] _T_144; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12621.4] wire [16:0] _T_145; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12622.4] wire [15:0] _T_146; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12623.4] wire [15:0] _T_147; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12624.4] wire [17:0] _T_148; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12625.4] wire [15:0] _T_149; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12626.4] wire [15:0] _T_150; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12627.4] wire [19:0] _T_151; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12628.4] wire [15:0] _T_152; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12629.4] wire [15:0] _T_153; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12630.4] wire [23:0] _T_154; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12631.4] wire [15:0] _T_155; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12632.4] wire [15:0] _T_156; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12633.4] wire [16:0] _T_158; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.TinyConfig.fir@12635.4] wire [16:0] _T_159; // @[Deinterleaver.scala 76:33:freechips.rocketchip.system.TinyConfig.fir@12636.4] wire [16:0] _GEN_106; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.TinyConfig.fir@12637.4] wire [16:0] _T_160; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.TinyConfig.fir@12637.4] wire _T_161; // @[Deinterleaver.scala 77:15:freechips.rocketchip.system.TinyConfig.fir@12638.4] wire _T_163; // @[Deinterleaver.scala 77:39:freechips.rocketchip.system.TinyConfig.fir@12640.4] wire _T_164; // @[Deinterleaver.scala 77:23:freechips.rocketchip.system.TinyConfig.fir@12641.4] wire _T_165; // @[Deinterleaver.scala 78:29:freechips.rocketchip.system.TinyConfig.fir@12643.6] wire _T_166; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12645.6] wire [15:0] _T_167; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12646.6] wire [15:0] _GEN_107; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12648.6] wire [15:0] _T_169; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12648.6] wire [7:0] _T_170; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12649.6] wire [7:0] _T_171; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12650.6] wire _T_172; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12651.6] wire [7:0] _T_173; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12652.6] wire [3:0] _T_174; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12653.6] wire [3:0] _T_175; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12654.6] wire _T_176; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12655.6] wire [3:0] _T_177; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12656.6] wire [1:0] _T_178; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12657.6] wire [1:0] _T_179; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12658.6] wire _T_180; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12659.6] wire [1:0] _T_181; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12660.6] wire _T_182; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@12661.6] wire [4:0] _T_186; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12665.6] wire [4:0] _GEN_1; // @[Deinterleaver.scala 77:59:freechips.rocketchip.system.TinyConfig.fir@12642.4] wire [3:0] _T_187_0_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] wire [31:0] _T_187_0_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] wire [1:0] _T_187_0_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] wire [8:0] _T_187_0_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] wire [3:0] _T_187_1_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] wire [3:0] _GEN_7; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _T_187_1_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] wire [31:0] _GEN_8; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _T_187_1_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] wire [1:0] _GEN_9; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _T_187_1_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] wire [8:0] _GEN_10; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _T_187_2_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] wire [3:0] _GEN_12; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _T_187_2_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] wire [31:0] _GEN_13; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _T_187_2_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] wire [1:0] _GEN_14; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _T_187_2_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] wire [8:0] _GEN_15; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _T_187_3_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] wire [3:0] _GEN_17; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _T_187_3_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] wire [31:0] _GEN_18; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _T_187_3_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] wire [1:0] _GEN_19; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _T_187_3_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] wire [8:0] _GEN_20; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_22; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_23; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_24; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_25; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_27; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_28; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_29; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_30; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_32; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_33; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_34; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_35; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_37; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_38; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_39; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_40; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_42; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_43; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_44; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_45; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_47; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_48; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_49; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_50; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_52; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_53; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_54; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_55; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_57; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_58; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_59; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_60; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_62; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_63; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_64; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_65; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_67; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_68; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_69; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_70; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [3:0] _GEN_72; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [31:0] _GEN_73; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [1:0] _GEN_74; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] wire [8:0] _GEN_75; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] Queue_13 Queue ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12407.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_resp(Queue_io_enq_bits_resp), .io_enq_bits_user(Queue_io_enq_bits_user), .io_enq_bits_last(Queue_io_enq_bits_last), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_resp(Queue_io_deq_bits_resp), .io_deq_bits_user(Queue_io_deq_bits_user), .io_deq_bits_last(Queue_io_deq_bits_last) ); Queue_13 Queue_1 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12411.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_id(Queue_1_io_enq_bits_id), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_resp(Queue_1_io_enq_bits_resp), .io_enq_bits_user(Queue_1_io_enq_bits_user), .io_enq_bits_last(Queue_1_io_enq_bits_last), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_id(Queue_1_io_deq_bits_id), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_resp(Queue_1_io_deq_bits_resp), .io_deq_bits_user(Queue_1_io_deq_bits_user), .io_deq_bits_last(Queue_1_io_deq_bits_last) ); Queue_13 Queue_2 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12415.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits_id(Queue_2_io_enq_bits_id), .io_enq_bits_data(Queue_2_io_enq_bits_data), .io_enq_bits_resp(Queue_2_io_enq_bits_resp), .io_enq_bits_user(Queue_2_io_enq_bits_user), .io_enq_bits_last(Queue_2_io_enq_bits_last), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits_id(Queue_2_io_deq_bits_id), .io_deq_bits_data(Queue_2_io_deq_bits_data), .io_deq_bits_resp(Queue_2_io_deq_bits_resp), .io_deq_bits_user(Queue_2_io_deq_bits_user), .io_deq_bits_last(Queue_2_io_deq_bits_last) ); Queue_13 Queue_3 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@12419.4] .clock(Queue_3_clock), .reset(Queue_3_reset), .io_enq_ready(Queue_3_io_enq_ready), .io_enq_valid(Queue_3_io_enq_valid), .io_enq_bits_id(Queue_3_io_enq_bits_id), .io_enq_bits_data(Queue_3_io_enq_bits_data), .io_enq_bits_resp(Queue_3_io_enq_bits_resp), .io_enq_bits_user(Queue_3_io_enq_bits_user), .io_enq_bits_last(Queue_3_io_enq_bits_last), .io_deq_ready(Queue_3_io_deq_ready), .io_deq_valid(Queue_3_io_deq_valid), .io_deq_bits_id(Queue_3_io_deq_bits_id), .io_deq_bits_data(Queue_3_io_deq_bits_data), .io_deq_bits_resp(Queue_3_io_deq_bits_resp), .io_deq_bits_user(Queue_3_io_deq_bits_user), .io_deq_bits_last(Queue_3_io_deq_bits_last) ); assign _T_17 = 16'h1 << _T_15; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12450.4] assign _T_20 = 16'h1 << auto_out_r_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12453.4] assign _T_24 = _T_20[0]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12458.4] assign _T_236_3 = Queue_3_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12757.4] assign _T_236_2 = Queue_2_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12756.4] assign _T_236_1 = Queue_1_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12755.4] assign _T_236_0 = Queue_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12752.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@12754.4] assign _GEN_83 = 4'h1 == auto_out_r_bits_id ? _T_236_1 : _T_236_0; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_84 = 4'h2 == auto_out_r_bits_id ? _T_236_2 : _GEN_83; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_85 = 4'h3 == auto_out_r_bits_id ? _T_236_3 : _GEN_84; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_86 = 4'h4 == auto_out_r_bits_id ? 1'h0 : _GEN_85; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_87 = 4'h5 == auto_out_r_bits_id ? 1'h0 : _GEN_86; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_88 = 4'h6 == auto_out_r_bits_id ? 1'h0 : _GEN_87; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_89 = 4'h7 == auto_out_r_bits_id ? 1'h0 : _GEN_88; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_90 = 4'h8 == auto_out_r_bits_id ? 1'h0 : _GEN_89; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_91 = 4'h9 == auto_out_r_bits_id ? 1'h0 : _GEN_90; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_92 = 4'ha == auto_out_r_bits_id ? 1'h0 : _GEN_91; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_93 = 4'hb == auto_out_r_bits_id ? 1'h0 : _GEN_92; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_94 = 4'hc == auto_out_r_bits_id ? 1'h0 : _GEN_93; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_95 = 4'hd == auto_out_r_bits_id ? 1'h0 : _GEN_94; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_96 = 4'he == auto_out_r_bits_id ? 1'h0 : _GEN_95; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _GEN_97 = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_96; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@12770.4] assign _T_25 = _GEN_97 & auto_out_r_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12459.4] assign _T_26 = _T_24 & _T_25; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12460.4] assign _T_27 = _T_26 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12461.4] assign _T_28 = _T_17[0]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12462.4] assign _T_29 = auto_in_r_ready & _T_14; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@12463.4] assign _T_30 = _T_28 & _T_29; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12464.4] assign _T_187_3_last = Queue_3_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] assign _T_187_2_last = Queue_2_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] assign _T_187_1_last = Queue_1_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] assign _T_187_0_last = Queue_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] assign _GEN_11 = 4'h1 == _T_15 ? _T_187_1_last : _T_187_0_last; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_16 = 4'h2 == _T_15 ? _T_187_2_last : _GEN_11; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_21 = 4'h3 == _T_15 ? _T_187_3_last : _GEN_16; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_26 = 4'h4 == _T_15 ? 1'h0 : _GEN_21; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_31 = 4'h5 == _T_15 ? 1'h0 : _GEN_26; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_36 = 4'h6 == _T_15 ? 1'h0 : _GEN_31; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_41 = 4'h7 == _T_15 ? 1'h0 : _GEN_36; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_46 = 4'h8 == _T_15 ? 1'h0 : _GEN_41; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_51 = 4'h9 == _T_15 ? 1'h0 : _GEN_46; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_56 = 4'ha == _T_15 ? 1'h0 : _GEN_51; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_61 = 4'hb == _T_15 ? 1'h0 : _GEN_56; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_66 = 4'hc == _T_15 ? 1'h0 : _GEN_61; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_71 = 4'hd == _T_15 ? 1'h0 : _GEN_66; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_76 = 4'he == _T_15 ? 1'h0 : _GEN_71; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_81 = 4'hf == _T_15 ? 1'h0 : _GEN_76; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_31 = _T_30 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12465.4] assign _GEN_98 = {{4'd0}, _T_27}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12466.4] assign _T_33 = _T_22 + _GEN_98; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12467.4] assign _GEN_99 = {{4'd0}, _T_31}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12468.4] assign _T_35 = _T_33 - _GEN_99; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12469.4] assign _T_36 = _T_31 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12472.4] assign _T_37 = _T_22 != 5'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12473.4] assign _T_38 = _T_36 | _T_37; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12474.4] assign _T_40 = _T_38 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12476.4] assign _T_41 = _T_40 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12477.4] assign _T_42 = _T_27 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12482.4] assign _T_43 = _T_22 != 5'h10; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12483.4] assign _T_44 = _T_42 | _T_43; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12484.4] assign _T_46 = _T_44 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12486.4] assign _T_47 = _T_46 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12487.4] assign _T_48 = _T_35 != 5'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12492.4] assign _T_51 = _T_20[1]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12496.4] assign _T_53 = _T_51 & _T_25; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12498.4] assign _T_54 = _T_53 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12499.4] assign _T_55 = _T_17[1]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12500.4] assign _T_57 = _T_55 & _T_29; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12502.4] assign _T_58 = _T_57 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12503.4] assign _GEN_100 = {{4'd0}, _T_54}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12504.4] assign _T_60 = _T_49 + _GEN_100; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12505.4] assign _GEN_101 = {{4'd0}, _T_58}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12506.4] assign _T_62 = _T_60 - _GEN_101; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12507.4] assign _T_63 = _T_58 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12510.4] assign _T_64 = _T_49 != 5'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12511.4] assign _T_65 = _T_63 | _T_64; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12512.4] assign _T_67 = _T_65 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12514.4] assign _T_68 = _T_67 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12515.4] assign _T_69 = _T_54 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12520.4] assign _T_70 = _T_49 != 5'h10; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12521.4] assign _T_71 = _T_69 | _T_70; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12522.4] assign _T_73 = _T_71 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12524.4] assign _T_74 = _T_73 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12525.4] assign _T_75 = _T_62 != 5'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12530.4] assign _T_78 = _T_20[2]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12534.4] assign _T_80 = _T_78 & _T_25; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12536.4] assign _T_81 = _T_80 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12537.4] assign _T_82 = _T_17[2]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12538.4] assign _T_84 = _T_82 & _T_29; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12540.4] assign _T_85 = _T_84 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12541.4] assign _GEN_102 = {{4'd0}, _T_81}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12542.4] assign _T_87 = _T_76 + _GEN_102; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12543.4] assign _GEN_103 = {{4'd0}, _T_85}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12544.4] assign _T_89 = _T_87 - _GEN_103; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12545.4] assign _T_90 = _T_85 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12548.4] assign _T_91 = _T_76 != 5'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12549.4] assign _T_92 = _T_90 | _T_91; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12550.4] assign _T_94 = _T_92 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12552.4] assign _T_95 = _T_94 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12553.4] assign _T_96 = _T_81 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12558.4] assign _T_97 = _T_76 != 5'h10; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12559.4] assign _T_98 = _T_96 | _T_97; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12560.4] assign _T_100 = _T_98 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12562.4] assign _T_101 = _T_100 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12563.4] assign _T_102 = _T_89 != 5'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12568.4] assign _T_105 = _T_20[3]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.TinyConfig.fir@12572.4] assign _T_107 = _T_105 & _T_25; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@12574.4] assign _T_108 = _T_107 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12575.4] assign _T_109 = _T_17[3]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.TinyConfig.fir@12576.4] assign _T_111 = _T_109 & _T_29; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@12578.4] assign _T_112 = _T_111 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.TinyConfig.fir@12579.4] assign _GEN_104 = {{4'd0}, _T_108}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12580.4] assign _T_114 = _T_103 + _GEN_104; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.TinyConfig.fir@12581.4] assign _GEN_105 = {{4'd0}, _T_112}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12582.4] assign _T_116 = _T_114 - _GEN_105; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.TinyConfig.fir@12583.4] assign _T_117 = _T_112 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.TinyConfig.fir@12586.4] assign _T_118 = _T_103 != 5'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.TinyConfig.fir@12587.4] assign _T_119 = _T_117 | _T_118; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.TinyConfig.fir@12588.4] assign _T_121 = _T_119 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12590.4] assign _T_122 = _T_121 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12591.4] assign _T_123 = _T_108 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@12596.4] assign _T_124 = _T_103 != 5'h10; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.TinyConfig.fir@12597.4] assign _T_125 = _T_123 | _T_124; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.TinyConfig.fir@12598.4] assign _T_127 = _T_125 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12600.4] assign _T_128 = _T_127 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12601.4] assign _T_129 = _T_116 != 5'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.TinyConfig.fir@12606.4] assign _T_144 = {8'h0,4'h0,_T_129,_T_102,_T_75,_T_48}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12621.4] assign _T_145 = {_T_144, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12622.4] assign _T_146 = _T_145[15:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12623.4] assign _T_147 = _T_144 | _T_146; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12624.4] assign _T_148 = {_T_147, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12625.4] assign _T_149 = _T_148[15:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12626.4] assign _T_150 = _T_147 | _T_149; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12627.4] assign _T_151 = {_T_150, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12628.4] assign _T_152 = _T_151[15:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12629.4] assign _T_153 = _T_150 | _T_152; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12630.4] assign _T_154 = {_T_153, 8'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@12631.4] assign _T_155 = _T_154[15:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@12632.4] assign _T_156 = _T_153 | _T_155; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@12633.4] assign _T_158 = {_T_156, 1'h0}; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.TinyConfig.fir@12635.4] assign _T_159 = ~ _T_158; // @[Deinterleaver.scala 76:33:freechips.rocketchip.system.TinyConfig.fir@12636.4] assign _GEN_106 = {{1'd0}, _T_144}; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.TinyConfig.fir@12637.4] assign _T_160 = _GEN_106 & _T_159; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.TinyConfig.fir@12637.4] assign _T_161 = _T_14 == 1'h0; // @[Deinterleaver.scala 77:15:freechips.rocketchip.system.TinyConfig.fir@12638.4] assign _T_163 = _T_29 & _GEN_81; // @[Deinterleaver.scala 77:39:freechips.rocketchip.system.TinyConfig.fir@12640.4] assign _T_164 = _T_161 | _T_163; // @[Deinterleaver.scala 77:23:freechips.rocketchip.system.TinyConfig.fir@12641.4] assign _T_165 = _T_144 != 16'h0; // @[Deinterleaver.scala 78:29:freechips.rocketchip.system.TinyConfig.fir@12643.6] assign _T_166 = _T_160[16]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12645.6] assign _T_167 = _T_160[15:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12646.6] assign _GEN_107 = {{15'd0}, _T_166}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12648.6] assign _T_169 = _GEN_107 | _T_167; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12648.6] assign _T_170 = _T_169[15:8]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12649.6] assign _T_171 = _T_169[7:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12650.6] assign _T_172 = _T_170 != 8'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12651.6] assign _T_173 = _T_170 | _T_171; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12652.6] assign _T_174 = _T_173[7:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12653.6] assign _T_175 = _T_173[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12654.6] assign _T_176 = _T_174 != 4'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12655.6] assign _T_177 = _T_174 | _T_175; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12656.6] assign _T_178 = _T_177[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@12657.6] assign _T_179 = _T_177[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@12658.6] assign _T_180 = _T_178 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@12659.6] assign _T_181 = _T_178 | _T_179; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@12660.6] assign _T_182 = _T_181[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@12661.6] assign _T_186 = {_T_166,_T_172,_T_176,_T_180,_T_182}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12665.6] assign _GEN_1 = _T_164 ? _T_186 : {{1'd0}, _T_15}; // @[Deinterleaver.scala 77:59:freechips.rocketchip.system.TinyConfig.fir@12642.4] assign _T_187_0_id = Queue_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] assign _T_187_0_data = Queue_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] assign _T_187_0_resp = Queue_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] assign _T_187_0_user = Queue_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12671.4] assign _T_187_1_id = Queue_1_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] assign _GEN_7 = 4'h1 == _T_15 ? _T_187_1_id : _T_187_0_id; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_1_data = Queue_1_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] assign _GEN_8 = 4'h1 == _T_15 ? _T_187_1_data : _T_187_0_data; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_1_resp = Queue_1_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] assign _GEN_9 = 4'h1 == _T_15 ? _T_187_1_resp : _T_187_0_resp; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_1_user = Queue_1_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12672.4] assign _GEN_10 = 4'h1 == _T_15 ? _T_187_1_user : _T_187_0_user; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_2_id = Queue_2_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] assign _GEN_12 = 4'h2 == _T_15 ? _T_187_2_id : _GEN_7; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_2_data = Queue_2_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] assign _GEN_13 = 4'h2 == _T_15 ? _T_187_2_data : _GEN_8; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_2_resp = Queue_2_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] assign _GEN_14 = 4'h2 == _T_15 ? _T_187_2_resp : _GEN_9; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_2_user = Queue_2_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12673.4] assign _GEN_15 = 4'h2 == _T_15 ? _T_187_2_user : _GEN_10; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_3_id = Queue_3_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] assign _GEN_17 = 4'h3 == _T_15 ? _T_187_3_id : _GEN_12; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_3_data = Queue_3_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] assign _GEN_18 = 4'h3 == _T_15 ? _T_187_3_data : _GEN_13; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_3_resp = Queue_3_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] assign _GEN_19 = 4'h3 == _T_15 ? _T_187_3_resp : _GEN_14; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _T_187_3_user = Queue_3_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12669.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.TinyConfig.fir@12674.4] assign _GEN_20 = 4'h3 == _T_15 ? _T_187_3_user : _GEN_15; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_22 = 4'h4 == _T_15 ? 4'h0 : _GEN_17; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_23 = 4'h4 == _T_15 ? 32'h0 : _GEN_18; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_24 = 4'h4 == _T_15 ? 2'h0 : _GEN_19; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_25 = 4'h4 == _T_15 ? 9'h0 : _GEN_20; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_27 = 4'h5 == _T_15 ? 4'h0 : _GEN_22; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_28 = 4'h5 == _T_15 ? 32'h0 : _GEN_23; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_29 = 4'h5 == _T_15 ? 2'h0 : _GEN_24; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_30 = 4'h5 == _T_15 ? 9'h0 : _GEN_25; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_32 = 4'h6 == _T_15 ? 4'h0 : _GEN_27; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_33 = 4'h6 == _T_15 ? 32'h0 : _GEN_28; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_34 = 4'h6 == _T_15 ? 2'h0 : _GEN_29; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_35 = 4'h6 == _T_15 ? 9'h0 : _GEN_30; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_37 = 4'h7 == _T_15 ? 4'h0 : _GEN_32; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_38 = 4'h7 == _T_15 ? 32'h0 : _GEN_33; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_39 = 4'h7 == _T_15 ? 2'h0 : _GEN_34; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_40 = 4'h7 == _T_15 ? 9'h0 : _GEN_35; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_42 = 4'h8 == _T_15 ? 4'h0 : _GEN_37; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_43 = 4'h8 == _T_15 ? 32'h0 : _GEN_38; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_44 = 4'h8 == _T_15 ? 2'h0 : _GEN_39; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_45 = 4'h8 == _T_15 ? 9'h0 : _GEN_40; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_47 = 4'h9 == _T_15 ? 4'h0 : _GEN_42; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_48 = 4'h9 == _T_15 ? 32'h0 : _GEN_43; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_49 = 4'h9 == _T_15 ? 2'h0 : _GEN_44; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_50 = 4'h9 == _T_15 ? 9'h0 : _GEN_45; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_52 = 4'ha == _T_15 ? 4'h0 : _GEN_47; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_53 = 4'ha == _T_15 ? 32'h0 : _GEN_48; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_54 = 4'ha == _T_15 ? 2'h0 : _GEN_49; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_55 = 4'ha == _T_15 ? 9'h0 : _GEN_50; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_57 = 4'hb == _T_15 ? 4'h0 : _GEN_52; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_58 = 4'hb == _T_15 ? 32'h0 : _GEN_53; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_59 = 4'hb == _T_15 ? 2'h0 : _GEN_54; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_60 = 4'hb == _T_15 ? 9'h0 : _GEN_55; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_62 = 4'hc == _T_15 ? 4'h0 : _GEN_57; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_63 = 4'hc == _T_15 ? 32'h0 : _GEN_58; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_64 = 4'hc == _T_15 ? 2'h0 : _GEN_59; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_65 = 4'hc == _T_15 ? 9'h0 : _GEN_60; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_67 = 4'hd == _T_15 ? 4'h0 : _GEN_62; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_68 = 4'hd == _T_15 ? 32'h0 : _GEN_63; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_69 = 4'hd == _T_15 ? 2'h0 : _GEN_64; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_70 = 4'hd == _T_15 ? 9'h0 : _GEN_65; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_72 = 4'he == _T_15 ? 4'h0 : _GEN_67; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_73 = 4'he == _T_15 ? 32'h0 : _GEN_68; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_74 = 4'he == _T_15 ? 2'h0 : _GEN_69; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign _GEN_75 = 4'he == _T_15 ? 9'h0 : _GEN_70; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.TinyConfig.fir@12687.4] assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_b_bits_user = auto_out_b_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_valid = _T_14; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_bits_id = 4'hf == _T_15 ? 4'h0 : _GEN_72; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_bits_data = 4'hf == _T_15 ? 32'h0 : _GEN_73; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_bits_resp = 4'hf == _T_15 ? 2'h0 : _GEN_74; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_bits_user = 4'hf == _T_15 ? 9'h0 : _GEN_75; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_in_r_bits_last = 4'hf == _T_15 ? 1'h0 : _GEN_76; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12402.4] assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_aw_bits_user = auto_in_aw_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_ar_bits_user = auto_in_ar_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign auto_out_r_ready = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_96; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12401.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@12409.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@12410.4] assign Queue_io_enq_valid = _T_24 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@12788.4] assign Queue_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12789.4] assign Queue_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12789.4] assign Queue_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12789.4] assign Queue_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12789.4] assign Queue_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12789.4] assign Queue_io_deq_ready = _T_28 & _T_29; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@12706.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@12413.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@12414.4] assign Queue_1_io_enq_valid = _T_51 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@12791.4] assign Queue_1_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12792.4] assign Queue_1_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12792.4] assign Queue_1_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12792.4] assign Queue_1_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12792.4] assign Queue_1_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12792.4] assign Queue_1_io_deq_ready = _T_55 & _T_29; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@12709.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@12417.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@12418.4] assign Queue_2_io_enq_valid = _T_78 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@12794.4] assign Queue_2_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12795.4] assign Queue_2_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12795.4] assign Queue_2_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12795.4] assign Queue_2_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12795.4] assign Queue_2_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12795.4] assign Queue_2_io_deq_ready = _T_82 & _T_29; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@12712.4] assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@12421.4] assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@12422.4] assign Queue_3_io_enq_valid = _T_105 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@12797.4] assign Queue_3_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12798.4] assign Queue_3_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12798.4] assign Queue_3_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12798.4] assign Queue_3_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12798.4] assign Queue_3_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.TinyConfig.fir@12798.4] assign Queue_3_io_deq_ready = _T_109 & _T_29; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@12715.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_14 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_15 = _RAND_1[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_22 = _RAND_2[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_49 = _RAND_3[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_76 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_103 = _RAND_5[4:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_14 <= 1'h0; end else begin if (_T_164) begin _T_14 <= _T_165; end end _T_15 <= _GEN_1[3:0]; if (reset) begin _T_22 <= 5'h0; end else begin _T_22 <= _T_35; end if (reset) begin _T_49 <= 5'h0; end else begin _T_49 <= _T_62; end if (reset) begin _T_76 <= 5'h0; end else begin _T_76 <= _T_89; end if (reset) begin _T_103 <= 5'h0; end else begin _T_103 <= _T_116; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_41) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12479.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_41) begin $fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12480.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_47) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12489.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_47) begin $fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12490.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_68) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12517.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_68) begin $fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12518.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_74) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12527.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_74) begin $fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12528.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_95) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12555.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_95) begin $fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12556.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_101) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12565.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_101) begin $fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12566.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_122) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12593.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_122) begin $fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.TinyConfig.fir@12594.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_128) begin $fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12603.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_128) begin $fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.TinyConfig.fir@12604.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module AXI4IdIndexer( // @[:freechips.rocketchip.system.TinyConfig.fir@12836.2] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@12839.4] ); assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_b_bits_id = auto_out_b_bits_id[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_b_bits_user = auto_out_b_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_bits_id = auto_out_r_bits_id[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_bits_user = auto_out_r_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@12849.4] assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_id = {{2'd0}, auto_in_aw_bits_id}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_aw_bits_user = auto_in_aw_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_id = {{2'd0}, auto_in_ar_bits_id}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_ar_bits_user = auto_in_ar_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@12848.4] endmodule module TLMonitor_6( // @[:freechips.rocketchip.system.TinyConfig.fir@12864.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@12865.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@12866.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@12867.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@14067.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@12882.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@12883.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@12886.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@12887.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@12895.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12906.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12907.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12908.6] wire [22:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@12910.6] wire [7:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@12911.6] wire [7:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@12912.6] wire [30:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@12913.6] wire [30:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@12913.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@12914.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12916.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12917.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@12919.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@12920.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@12921.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@12922.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@12923.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12925.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12926.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12928.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12929.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@12930.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@12931.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@12932.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12933.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12934.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12935.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12936.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12937.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12938.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12939.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12940.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12941.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12942.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12943.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12944.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12947.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@13004.6] wire [30:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@13007.8] wire [31:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@13008.8] wire [31:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@13009.8] wire [31:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@13010.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@13011.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13016.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13029.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13030.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13037.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13038.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13044.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13045.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@13050.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13052.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13053.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@13058.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@13059.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13061.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13062.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@13067.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13069.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13070.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@13076.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@13130.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13132.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13133.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@13156.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@13159.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@13167.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13170.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13171.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@13190.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13192.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13193.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@13198.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13200.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13201.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@13215.6] wire _T_233; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@13218.8] wire _T_241; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@13226.8] wire _T_244; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13229.8] wire _T_245; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13230.8] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@13266.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@13308.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@13309.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@13310.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13312.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13313.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@13319.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@13350.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13352.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13353.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@13367.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@13398.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13400.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13401.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@13415.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@13465.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13467.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13468.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@13473.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@13474.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@13477.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@13478.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@13486.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13497.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13498.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13499.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@13501.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13504.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13505.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@13510.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13512.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13513.8] wire _T_408; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@13526.8] wire _T_410; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13528.8] wire _T_411; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13529.8] wire _T_412; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@13534.8] wire _T_414; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13536.8] wire _T_415; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13537.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@13543.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@13601.6] wire _T_464; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@13642.8] wire _T_466; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13644.8] wire _T_467; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13645.8] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@13660.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@13695.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@13731.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@13791.4] wire [5:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@13796.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@13797.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@13798.4] reg [5:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@13800.4] reg [31:0] _RAND_0; wire [5:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13802.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13803.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@13814.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@13815.4] reg [31:0] _RAND_2; reg [3:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@13816.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@13817.4] reg [31:0] _RAND_4; reg [30:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@13818.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@13819.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@13820.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@13822.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13824.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13825.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@13830.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13832.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13833.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@13838.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13840.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13841.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@13846.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13848.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13849.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@13854.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13856.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13857.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@13864.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@13872.4] wire [22:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@13874.4] wire [7:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@13875.4] wire [7:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@13876.4] wire [5:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@13877.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@13878.4] reg [5:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@13880.4] reg [31:0] _RAND_6; wire [5:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13882.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13883.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@13894.4] reg [31:0] _RAND_7; reg [3:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@13896.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@13897.4] reg [31:0] _RAND_9; reg _T_610; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@13899.4] reg [31:0] _RAND_10; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@13900.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@13901.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@13903.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13905.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13906.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@13919.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13921.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13922.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@13927.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13929.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13930.6] wire _T_633; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@13943.6] wire _T_635; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13945.6] wire _T_636; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13946.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@13953.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@13962.4] reg [31:0] _RAND_11; reg [5:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@13972.4] reg [31:0] _RAND_12; wire [5:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13974.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13975.4] reg [5:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@13994.4] reg [31:0] _RAND_13; wire [5:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13996.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13997.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@14012.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@14015.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@14017.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@14018.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@14019.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14021.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14022.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@14014.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@14033.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@14035.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@14036.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@14038.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@14008.4 :freechips.rocketchip.system.TinyConfig.fir@14010.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@14016.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@14040.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@14041.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@14042.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14044.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14045.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@14037.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@14028.4 :freechips.rocketchip.system.TinyConfig.fir@14030.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@14039.6] wire _T_704; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@14051.4] wire _T_705; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@14052.4] wire _T_706; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@14053.4] wire _T_707; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@14054.4] wire _T_709; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14056.4] wire _T_710; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14057.4] wire [17:0] _T_711; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@14062.4] wire [17:0] _T_712; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@14063.4] wire [17:0] _T_713; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@14064.4] reg [31:0] _T_714; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@14066.4] reg [31:0] _RAND_14; wire _T_715; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@14069.4] wire _T_716; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@14070.4] wire _T_717; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@14071.4] wire _T_718; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@14072.4] wire _T_719; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@14073.4] wire _T_720; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@14074.4] wire _T_722; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14076.4] wire _T_723; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14077.4] wire [31:0] _T_725; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@14083.4] wire _T_728; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@14087.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13018.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@13090.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13173.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13232.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@13283.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@13333.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@13381.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@13429.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13507.10] wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@13549.10] wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@13607.10] wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@13666.10] wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@13701.10] wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@13737.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@14067.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@12882.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@12883.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@12886.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@12887.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@12895.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12906.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12907.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@12908.6] assign _T_28 = 23'hff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@12910.6] assign _T_29 = _T_28[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@12911.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@12912.6] assign _GEN_18 = {{23'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@12913.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@12913.6] assign _T_32 = _T_31 == 31'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@12914.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@12916.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@12917.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@12919.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@12920.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@12921.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@12922.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@12923.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12925.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12926.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12928.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12929.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@12930.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@12931.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@12932.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12933.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12934.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12935.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12936.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12937.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12938.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12939.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12940.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12941.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@12942.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@12943.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@12944.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@12947.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@13004.6] assign _T_120 = io_in_a_bits_address ^ 31'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@13007.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@13008.8] assign _T_122 = $signed(_T_121) & $signed(-32'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@13009.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@13010.8] assign _T_124 = $signed(_T_123) == $signed(32'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@13011.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13016.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13029.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13030.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13037.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13038.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13044.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13045.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@13050.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13052.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13053.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@13058.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@13059.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13061.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13062.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@13067.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13069.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13070.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@13076.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@13130.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13132.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13133.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@13156.6] assign _T_200 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@13159.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@13167.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13170.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13171.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@13190.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13192.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13193.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@13198.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13200.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13201.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@13215.6] assign _T_233 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@13218.8] assign _T_241 = _T_233 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@13226.8] assign _T_244 = _T_241 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13229.8] assign _T_245 = _T_244 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13230.8] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@13266.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@13308.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@13309.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@13310.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13312.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13313.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@13319.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@13350.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13352.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13353.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@13367.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@13398.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13400.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13401.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@13415.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@13465.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13467.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13468.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@13473.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@13474.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@13477.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@13478.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@13486.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13497.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13498.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@13499.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@13501.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13504.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13505.8] assign _T_400 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@13510.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13512.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13513.8] assign _T_408 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@13526.8] assign _T_410 = _T_408 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13528.8] assign _T_411 = _T_410 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13529.8] assign _T_412 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@13534.8] assign _T_414 = _T_412 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13536.8] assign _T_415 = _T_414 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13537.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@13543.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@13601.6] assign _T_464 = _T_412 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@13642.8] assign _T_466 = _T_464 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13644.8] assign _T_467 = _T_466 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13645.8] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@13660.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@13695.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@13731.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@13791.4] assign _T_542 = _T_30[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@13796.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@13797.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@13798.4] assign _T_548 = _T_546 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13802.4] assign _T_549 = _T_546 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13803.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@13819.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@13820.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@13822.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13824.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13825.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@13830.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13832.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13833.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@13838.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13840.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13841.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@13846.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13848.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13849.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@13854.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13856.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13857.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@13864.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@13872.4] assign _T_588 = 23'hff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@13874.4] assign _T_589 = _T_588[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@13875.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@13876.4] assign _T_591 = _T_590[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@13877.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@13878.4] assign _T_596 = _T_594 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13882.4] assign _T_597 = _T_594 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13883.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@13900.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@13901.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@13903.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13905.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13906.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@13919.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13921.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13922.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@13927.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13929.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13930.6] assign _T_633 = io_in_d_bits_denied == _T_610; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@13943.6] assign _T_635 = _T_633 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13945.6] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13946.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@13953.4] assign _T_651 = _T_649 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13974.4] assign _T_652 = _T_649 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13975.4] assign _T_670 = _T_668 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@13996.4] assign _T_671 = _T_668 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@13997.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@14012.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@14015.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@14017.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@14018.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@14019.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14021.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14022.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@14014.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@14033.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@14035.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@14036.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@14038.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@14008.4 :freechips.rocketchip.system.TinyConfig.fir@14010.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@14016.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@14040.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@14041.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@14042.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14044.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14045.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@14037.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@14028.4 :freechips.rocketchip.system.TinyConfig.fir@14030.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@14039.6] assign _T_704 = _T_679 != _T_690; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@14051.4] assign _T_705 = _T_679 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@14052.4] assign _T_706 = _T_705 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@14053.4] assign _T_707 = _T_704 | _T_706; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@14054.4] assign _T_709 = _T_707 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14056.4] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14057.4] assign _T_711 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@14062.4] assign _T_712 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@14063.4] assign _T_713 = _T_711 & _T_712; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@14064.4] assign _T_715 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@14069.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@14070.4] assign _T_717 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@14071.4] assign _T_718 = _T_716 | _T_717; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@14072.4] assign _T_719 = _T_714 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@14073.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@14074.4] assign _T_722 = _T_720 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14076.4] assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14077.4] assign _T_725 = _T_714 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@14083.4] assign _T_728 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@14087.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13018.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@13090.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13173.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13232.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@13283.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@13333.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@13381.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@13429.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13507.10] assign _GEN_123 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@13549.10] assign _GEN_131 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@13607.10] assign _GEN_139 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@13666.10] assign _GEN_143 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@13701.10] assign _GEN_147 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@13737.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[30:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_610 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_639 = _RAND_11[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_649 = _RAND_12[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_668 = _RAND_13[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_714 = _RAND_14[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 6'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 6'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 6'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 6'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (_T_638) begin _T_610 <= io_in_d_bits_denied; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_713; end if (reset) begin _T_649 <= 6'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 6'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 6'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 6'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_714 <= 32'h0; end else begin if (_T_728) begin _T_714 <= 32'h0; end else begin _T_714 <= _T_725; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13018.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@13019.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:11)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@13025.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@13026.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13032.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@13033.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13040.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@13041.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13047.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@13048.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13055.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@13056.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13064.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@13065.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@13073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@13090.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@13091.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:11)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@13097.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@13098.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@13104.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@13105.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@13112.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@13113.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@13119.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@13120.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@13127.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@13128.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:11)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13135.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@13136.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@13144.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@13145.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@13152.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@13153.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13173.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@13174.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@13180.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@13181.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@13187.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@13188.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13195.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@13196.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@13204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@13211.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@13212.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13232.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_245) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@13233.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@13239.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@13240.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@13246.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@13247.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@13254.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@13255.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@13262.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@13263.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@13283.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_245) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@13284.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@13290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@13291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@13297.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@13298.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@13305.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@13306.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@13316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@13333.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@13334.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@13340.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@13341.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@13347.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@13348.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13355.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@13356.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@13363.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@13364.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@13381.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@13382.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@13388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@13389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@13395.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@13396.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13403.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@13404.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@13411.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@13412.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@13429.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@13430.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@13436.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@13437.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@13443.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@13444.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@13451.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@13452.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@13459.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@13460.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:11)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13470.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@13471.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13507.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@13508.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13515.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@13516.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13531.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_411) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@13532.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_415) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13539.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_415) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@13540.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@13549.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@13550.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@13556.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@13557.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@13564.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@13565.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@13588.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_411) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@13589.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@13607.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@13608.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@13614.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@13615.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@13622.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@13623.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13647.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_467) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@13648.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@13666.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@13667.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@13682.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_411) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@13683.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@13701.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@13702.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@13718.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_467) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@13719.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@13737.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@13738.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@13753.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_411) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@13754.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13827.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@13828.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13835.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@13836.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13843.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@13844.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13851.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@13852.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13859.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@13860.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13908.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@13909.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13924.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@13925.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13932.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@13933.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13948.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_636) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@13949.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14024.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@14025.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:11)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14047.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@14048.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_710) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:11)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14059.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_710) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@14060.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_723) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:11)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14079.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_723) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@14080.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_17( // @[:freechips.rocketchip.system.TinyConfig.fir@14092.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@14093.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@14094.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] input [3:0] io_enq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] output [3:0] io_deq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@14095.4] ); reg [31:0] _T_data [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg [31:0] _RAND_0; wire [31:0] _T_data__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_data__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg [3:0] _T_strb [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg [31:0] _RAND_1; wire [3:0] _T_strb__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_strb__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire [3:0] _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_strb__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_strb__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_strb__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg _T_last [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg [31:0] _RAND_2; wire _T_last__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_last__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@14098.4] reg [31:0] _RAND_3; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@14100.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14103.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14106.4] wire _GEN_9; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@14137.6] wire _GEN_14; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14132.4] wire _GEN_13; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14132.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14117.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@14121.4] assign _T_data__T_14_addr = 1'h0; assign _T_data__T_14_data = _T_data[_T_data__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = 1'h0; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_strb__T_14_addr = 1'h0; assign _T_strb__T_14_data = _T_strb[_T_strb__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] assign _T_strb__T_10_data = io_enq_bits_strb; assign _T_strb__T_10_addr = 1'h0; assign _T_strb__T_10_mask = 1'h1; assign _T_strb__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_last__T_14_addr = 1'h0; assign _T_last__T_14_data = _T_last[_T_last__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = 1'h0; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@14100.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14103.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14106.4] assign _GEN_9 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@14137.6] assign _GEN_14 = _T_3 ? _GEN_9 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14132.4] assign _GEN_13 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14132.4] assign _T_11 = _GEN_14 != _GEN_13; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14117.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@14121.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@14124.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@14122.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@14130.6] assign io_deq_bits_data = _T_3 ? io_enq_bits_data : _T_data__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14128.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14135.6] assign io_deq_bits_strb = _T_3 ? io_enq_bits_strb : _T_strb__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14127.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14134.6] assign io_deq_bits_last = _T_3 ? io_enq_bits_last : _T_last__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14126.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14133.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_data[initvar] = _RAND_0[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_strb[initvar] = _RAND_1[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_last[initvar] = _RAND_2[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] end if(_T_strb__T_10_en & _T_strb__T_10_mask) begin _T_strb[_T_strb__T_10_addr] <= _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14097.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module Queue_18( // @[:freechips.rocketchip.system.TinyConfig.fir@14148.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@14149.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@14150.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input [1:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input [30:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input [8:0] io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input io_enq_bits_wen, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [1:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [30:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output io_deq_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [3:0] io_deq_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [2:0] io_deq_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [3:0] io_deq_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output [8:0] io_deq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] output io_deq_bits_wen // @[:freechips.rocketchip.system.TinyConfig.fir@14151.4] ); reg [1:0] _T_id [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_0; wire [1:0] _T_id__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_id__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [1:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [30:0] _T_addr [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_1; wire [30:0] _T_addr__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_addr__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [30:0] _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_addr__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_addr__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_addr__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [7:0] _T_len [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_2; wire [7:0] _T_len__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_len__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [7:0] _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_len__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_len__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_len__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [2:0] _T_size [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_3; wire [2:0] _T_size__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_size__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [1:0] _T_burst [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_4; wire [1:0] _T_burst__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_burst__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [1:0] _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_burst__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_burst__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_burst__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg _T_lock [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_5; wire _T_lock__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_lock__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_lock__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_lock__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_lock__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_lock__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [3:0] _T_cache [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_6; wire [3:0] _T_cache__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_cache__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [3:0] _T_cache__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_cache__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_cache__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_cache__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [2:0] _T_prot [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_7; wire [2:0] _T_prot__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_prot__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [2:0] _T_prot__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_prot__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_prot__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_prot__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [3:0] _T_qos [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_8; wire [3:0] _T_qos__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_qos__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [3:0] _T_qos__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_qos__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_qos__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_qos__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [8:0] _T_user [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_9; wire [8:0] _T_user__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_user__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire [8:0] _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg _T_wen [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg [31:0] _RAND_10; wire _T_wen__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_wen__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_wen__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_wen__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_wen__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] wire _T_wen__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@14154.4] reg [31:0] _RAND_11; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@14156.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14159.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14162.4] wire _GEN_17; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@14217.6] wire _GEN_30; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14204.4] wire _GEN_29; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14204.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14181.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@14185.4] assign _T_id__T_14_addr = 1'h0; assign _T_id__T_14_data = _T_id[_T_id__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = 1'h0; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_addr__T_14_addr = 1'h0; assign _T_addr__T_14_data = _T_addr[_T_addr__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_addr__T_10_data = io_enq_bits_addr; assign _T_addr__T_10_addr = 1'h0; assign _T_addr__T_10_mask = 1'h1; assign _T_addr__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_len__T_14_addr = 1'h0; assign _T_len__T_14_data = _T_len[_T_len__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_len__T_10_data = io_enq_bits_len; assign _T_len__T_10_addr = 1'h0; assign _T_len__T_10_mask = 1'h1; assign _T_len__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_size__T_14_addr = 1'h0; assign _T_size__T_14_data = _T_size[_T_size__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = 1'h0; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_burst__T_14_addr = 1'h0; assign _T_burst__T_14_data = _T_burst[_T_burst__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_burst__T_10_data = 2'h1; assign _T_burst__T_10_addr = 1'h0; assign _T_burst__T_10_mask = 1'h1; assign _T_burst__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_lock__T_14_addr = 1'h0; assign _T_lock__T_14_data = _T_lock[_T_lock__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_lock__T_10_data = 1'h0; assign _T_lock__T_10_addr = 1'h0; assign _T_lock__T_10_mask = 1'h1; assign _T_lock__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_cache__T_14_addr = 1'h0; assign _T_cache__T_14_data = _T_cache[_T_cache__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_cache__T_10_data = 4'h0; assign _T_cache__T_10_addr = 1'h0; assign _T_cache__T_10_mask = 1'h1; assign _T_cache__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_prot__T_14_addr = 1'h0; assign _T_prot__T_14_data = _T_prot[_T_prot__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_prot__T_10_data = 3'h1; assign _T_prot__T_10_addr = 1'h0; assign _T_prot__T_10_mask = 1'h1; assign _T_prot__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_qos__T_14_addr = 1'h0; assign _T_qos__T_14_data = _T_qos[_T_qos__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_qos__T_10_data = 4'h0; assign _T_qos__T_10_addr = 1'h0; assign _T_qos__T_10_mask = 1'h1; assign _T_qos__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_user__T_14_addr = 1'h0; assign _T_user__T_14_data = _T_user[_T_user__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = 1'h0; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_wen__T_14_addr = 1'h0; assign _T_wen__T_14_data = _T_wen[_T_wen__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] assign _T_wen__T_10_data = io_enq_bits_wen; assign _T_wen__T_10_addr = 1'h0; assign _T_wen__T_10_mask = 1'h1; assign _T_wen__T_10_en = _T_3 ? _GEN_17 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@14156.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14159.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14162.4] assign _GEN_17 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@14217.6] assign _GEN_30 = _T_3 ? _GEN_17 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14204.4] assign _GEN_29 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@14204.4] assign _T_11 = _GEN_30 != _GEN_29; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14181.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@14185.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@14188.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@14186.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@14202.6] assign io_deq_bits_id = _T_3 ? io_enq_bits_id : _T_id__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14200.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14215.6] assign io_deq_bits_addr = _T_3 ? io_enq_bits_addr : _T_addr__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14199.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14214.6] assign io_deq_bits_len = _T_3 ? io_enq_bits_len : _T_len__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14198.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14213.6] assign io_deq_bits_size = _T_3 ? io_enq_bits_size : _T_size__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14197.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14212.6] assign io_deq_bits_burst = _T_3 ? 2'h1 : _T_burst__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14196.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14211.6] assign io_deq_bits_lock = _T_3 ? 1'h0 : _T_lock__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14195.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14210.6] assign io_deq_bits_cache = _T_3 ? 4'h0 : _T_cache__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14194.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14209.6] assign io_deq_bits_prot = _T_3 ? 3'h1 : _T_prot__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14193.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14208.6] assign io_deq_bits_qos = _T_3 ? 4'h0 : _T_qos__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14192.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14207.6] assign io_deq_bits_user = _T_3 ? io_enq_bits_user : _T_user__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14191.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14206.6] assign io_deq_bits_wen = _T_3 ? io_enq_bits_wen : _T_wen__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14190.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@14205.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_id[initvar] = _RAND_0[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_addr[initvar] = _RAND_1[30:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_len[initvar] = _RAND_2[7:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_size[initvar] = _RAND_3[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_burst[initvar] = _RAND_4[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_lock[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_cache[initvar] = _RAND_6[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_prot[initvar] = _RAND_7[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_8 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_qos[initvar] = _RAND_8[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_9 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_user[initvar] = _RAND_9[8:0]; `endif // RANDOMIZE_MEM_INIT _RAND_10 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_wen[initvar] = _RAND_10[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_1 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_addr__T_10_en & _T_addr__T_10_mask) begin _T_addr[_T_addr__T_10_addr] <= _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_len__T_10_en & _T_len__T_10_mask) begin _T_len[_T_len__T_10_addr] <= _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_burst__T_10_en & _T_burst__T_10_mask) begin _T_burst[_T_burst__T_10_addr] <= _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_lock__T_10_en & _T_lock__T_10_mask) begin _T_lock[_T_lock__T_10_addr] <= _T_lock__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_cache__T_10_en & _T_cache__T_10_mask) begin _T_cache[_T_cache__T_10_addr] <= _T_cache__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_prot__T_10_en & _T_prot__T_10_mask) begin _T_prot[_T_prot__T_10_addr] <= _T_prot__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_qos__T_10_en & _T_qos__T_10_mask) begin _T_qos[_T_qos__T_10_addr] <= _T_qos__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if(_T_wen__T_10_en & _T_wen__T_10_mask) begin _T_wen[_T_wen__T_10_addr] <= _T_wen__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@14153.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module TLToAXI4( // @[:freechips.rocketchip.system.TinyConfig.fir@14228.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@14229.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@14230.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [1:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [1:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [1:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [1:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@14231.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire [3:0] Queue_io_enq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire [3:0] Queue_io_deq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [1:0] Queue_1_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [30:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [8:0] Queue_1_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_enq_bits_wen; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [1:0] Queue_1_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [30:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_deq_bits_lock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [3:0] Queue_1_io_deq_bits_cache; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [2:0] Queue_1_io_deq_bits_prot; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [3:0] Queue_1_io_deq_bits_qos; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire [8:0] Queue_1_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire Queue_1_io_deq_bits_wen; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] wire _T_18; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@14340.4] wire _T_19; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@14341.4] reg _T_152; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.TinyConfig.fir@14600.4] reg [31:0] _RAND_0; reg _T_124; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.TinyConfig.fir@14559.4] reg [31:0] _RAND_1; reg [3:0] _T_209; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.TinyConfig.fir@14683.4] reg [31:0] _RAND_2; wire _T_211; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.TinyConfig.fir@14685.4] wire _T_234; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14720.4] reg _T_210; // @[ToAXI4.scala 226:24:freechips.rocketchip.system.TinyConfig.fir@14684.4] reg [31:0] _RAND_3; wire _T_233; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.TinyConfig.fir@14719.4] wire _T_235; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.TinyConfig.fir@14721.4] wire _T_236; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.TinyConfig.fir@14722.4] wire _T_237; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.TinyConfig.fir@14723.4] reg [3:0] _T_180; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.TinyConfig.fir@14641.4] reg [31:0] _RAND_4; wire _T_182; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.TinyConfig.fir@14643.4] wire _T_205; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14678.4] reg _T_181; // @[ToAXI4.scala 226:24:freechips.rocketchip.system.TinyConfig.fir@14642.4] reg [31:0] _RAND_5; wire _T_204; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.TinyConfig.fir@14677.4] wire _T_206; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.TinyConfig.fir@14679.4] wire _T_207; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.TinyConfig.fir@14680.4] wire _T_208; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.TinyConfig.fir@14681.4] wire _GEN_28; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_29; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_30; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_31; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_32; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_33; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_34; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_35; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_36; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _GEN_37; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] reg [5:0] _T_29; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@14351.4] reg [31:0] _RAND_6; wire _T_32; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@14354.4] wire _T_73; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] wire _T_74; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.TinyConfig.fir@14471.4] reg _T_63; // @[ToAXI4.scala 160:30:freechips.rocketchip.system.TinyConfig.fir@14446.4] reg [31:0] _RAND_7; wire _T_55_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.TinyConfig.fir@14388.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@14422.4] wire _T_75; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.TinyConfig.fir@14472.4] wire _T_56_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.TinyConfig.fir@14390.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@14399.4] wire _T_76; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.TinyConfig.fir@14473.4] wire _T_77; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.TinyConfig.fir@14474.4] wire _T_78; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.TinyConfig.fir@14475.4] wire _T_20; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14342.4] wire [22:0] _T_22; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14344.4] wire [7:0] _T_23; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14345.4] wire [7:0] _T_24; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14346.4] wire [5:0] _T_25; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@14347.4] wire [5:0] _T_28; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@14350.4] wire [5:0] _T_31; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@14353.4] wire _T_33; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@14355.4] wire _T_34; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@14356.4] wire _T_35; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@14357.4] wire [8:0] _T_49; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.TinyConfig.fir@14382.4] wire [8:0] _GEN_45; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.TinyConfig.fir@14383.4] wire [4:0] _T_51; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.TinyConfig.fir@14384.4] wire [3:0] _T_52; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.TinyConfig.fir@14385.4] wire [4:0] _T_53; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.TinyConfig.fir@14386.4] wire [3:0] _T_54; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.TinyConfig.fir@14387.4] wire _T_58_bits_wen; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@14423.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@14424.4] wire _T_59; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.TinyConfig.fir@14439.4] wire _T_58_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@14423.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@14435.4] wire _T_65; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.TinyConfig.fir@14449.6] wire [1:0] _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [1:0] _GEN_19; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] wire [24:0] _T_67; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14456.4] wire [9:0] _T_68; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14457.4] wire [9:0] _T_69; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14458.4] wire _T_71; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.TinyConfig.fir@14461.4] wire [3:0] _T_72; // @[ToAXI4.scala 168:23:freechips.rocketchip.system.TinyConfig.fir@14462.4] wire _T_80; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.TinyConfig.fir@14478.4] wire _T_81; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.TinyConfig.fir@14479.4] wire _T_82; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.TinyConfig.fir@14480.4] wire _T_83; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.TinyConfig.fir@14481.4] wire _T_84; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.TinyConfig.fir@14482.4] wire _T_87; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.TinyConfig.fir@14486.4] reg _T_90; // @[ToAXI4.scala 187:30:freechips.rocketchip.system.TinyConfig.fir@14493.4] reg [31:0] _RAND_8; wire _T_91; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14494.4] wire _T_92; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.TinyConfig.fir@14496.6] wire _T_93; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.TinyConfig.fir@14499.4] wire _T_94; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.TinyConfig.fir@14501.4] wire _T_96; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.TinyConfig.fir@14504.4] reg _T_97; // @[ToAXI4.scala 199:28:freechips.rocketchip.system.TinyConfig.fir@14506.4] reg [31:0] _RAND_9; wire _T_99; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.TinyConfig.fir@14511.4] reg _T_100; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@14512.4] reg [31:0] _RAND_10; wire _GEN_40; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@14513.4] wire _T_102; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.TinyConfig.fir@14517.4] wire _T_103; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.TinyConfig.fir@14518.4] wire _T_104; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.TinyConfig.fir@14519.4] wire [3:0] _T_109; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14544.4] wire _T_111; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14546.4] wire _T_112; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14547.4] wire _T_113; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14548.4] wire _T_114; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14549.4] wire [1:0] _T_115; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.TinyConfig.fir@14550.4] wire [3:0] _T_117; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14552.4] wire _T_119; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14554.4] wire _T_120; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14555.4] wire _T_121; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14556.4] wire _T_122; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14557.4] wire _T_123; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.TinyConfig.fir@14558.4] wire _T_127; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14562.4] wire _T_128; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14563.4] wire _T_129; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14564.4] wire _T_130; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14565.4] wire _T_131; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14566.4] wire _T_133; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14568.4] wire _T_135; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14570.4] wire _T_136; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14572.4] wire _T_138; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14574.4] wire _T_140; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14576.4] wire _T_141; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14577.4] wire _T_142; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14582.4] wire _T_143; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14583.4] wire _T_144; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14584.4] wire _T_146; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14586.4] wire _T_147; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14587.4] wire _T_156; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14604.4] wire _T_157; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14605.4] wire _T_159; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14607.4] wire _T_161; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14609.4] wire _T_163; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14611.4] wire _T_164; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14613.4] wire _T_166; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14615.4] wire _T_168; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14617.4] wire _T_169; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14618.4] wire _T_170; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14623.4] wire _T_171; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14624.4] wire _T_172; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14625.4] wire _T_174; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14627.4] wire _T_175; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14628.4] wire _T_184; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14645.4] wire _T_185; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14646.4] wire _T_187; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14648.4] wire [3:0] _GEN_46; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14649.4] wire [3:0] _T_189; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14650.4] wire [3:0] _GEN_47; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14651.4] wire [3:0] _T_191; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14652.4] wire _T_192; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14654.4] wire _T_193; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.TinyConfig.fir@14655.4] wire _T_194; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14656.4] wire _T_196; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14658.4] wire _T_197; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14659.4] wire _T_198; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14664.4] wire _T_199; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14665.4] wire _T_200; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14666.4] wire _T_202; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14668.4] wire _T_203; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14669.4] wire _T_213; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14687.4] wire _T_214; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14688.4] wire _T_216; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14690.4] wire [3:0] _GEN_48; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14691.4] wire [3:0] _T_218; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14692.4] wire [3:0] _GEN_49; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14693.4] wire [3:0] _T_220; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14694.4] wire _T_221; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14696.4] wire _T_222; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.TinyConfig.fir@14697.4] wire _T_223; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14698.4] wire _T_225; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14700.4] wire _T_226; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14701.4] wire _T_227; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14706.4] wire _T_228; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14707.4] wire _T_229; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14708.4] wire _T_231; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14710.4] wire _T_232; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14711.4] TLMonitor_6 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@14238.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_17 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14392.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_strb(Queue_io_enq_bits_strb), .io_enq_bits_last(Queue_io_enq_bits_last), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_strb(Queue_io_deq_bits_strb), .io_deq_bits_last(Queue_io_deq_bits_last) ); Queue_18 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@14407.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_id(Queue_1_io_enq_bits_id), .io_enq_bits_addr(Queue_1_io_enq_bits_addr), .io_enq_bits_len(Queue_1_io_enq_bits_len), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_user(Queue_1_io_enq_bits_user), .io_enq_bits_wen(Queue_1_io_enq_bits_wen), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_id(Queue_1_io_deq_bits_id), .io_deq_bits_addr(Queue_1_io_deq_bits_addr), .io_deq_bits_len(Queue_1_io_deq_bits_len), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_burst(Queue_1_io_deq_bits_burst), .io_deq_bits_lock(Queue_1_io_deq_bits_lock), .io_deq_bits_cache(Queue_1_io_deq_bits_cache), .io_deq_bits_prot(Queue_1_io_deq_bits_prot), .io_deq_bits_qos(Queue_1_io_deq_bits_qos), .io_deq_bits_user(Queue_1_io_deq_bits_user), .io_deq_bits_wen(Queue_1_io_deq_bits_wen) ); assign _T_18 = auto_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@14340.4] assign _T_19 = _T_18 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@14341.4] assign _T_211 = _T_209 == 4'h0; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.TinyConfig.fir@14685.4] assign _T_234 = _T_211 == 1'h0; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14720.4] assign _T_233 = _T_210 != _T_19; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.TinyConfig.fir@14719.4] assign _T_235 = _T_234 & _T_233; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.TinyConfig.fir@14721.4] assign _T_236 = _T_209 == 4'h8; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.TinyConfig.fir@14722.4] assign _T_237 = _T_235 | _T_236; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.TinyConfig.fir@14723.4] assign _T_182 = _T_180 == 4'h0; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.TinyConfig.fir@14643.4] assign _T_205 = _T_182 == 1'h0; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@14678.4] assign _T_204 = _T_181 != _T_19; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.TinyConfig.fir@14677.4] assign _T_206 = _T_205 & _T_204; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.TinyConfig.fir@14679.4] assign _T_207 = _T_180 == 4'h8; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.TinyConfig.fir@14680.4] assign _T_208 = _T_206 | _T_207; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.TinyConfig.fir@14681.4] assign _GEN_28 = 5'h8 == auto_in_a_bits_source ? _T_237 : _T_208; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_29 = 5'h9 == auto_in_a_bits_source ? _T_237 : _GEN_28; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_30 = 5'ha == auto_in_a_bits_source ? _T_237 : _GEN_29; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_31 = 5'hb == auto_in_a_bits_source ? _T_237 : _GEN_30; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_32 = 5'hc == auto_in_a_bits_source ? _T_237 : _GEN_31; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_33 = 5'hd == auto_in_a_bits_source ? _T_237 : _GEN_32; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_34 = 5'he == auto_in_a_bits_source ? _T_237 : _GEN_33; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_35 = 5'hf == auto_in_a_bits_source ? _T_237 : _GEN_34; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_36 = 5'h10 == auto_in_a_bits_source ? _T_124 : _GEN_35; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _GEN_37 = 5'h11 == auto_in_a_bits_source ? _T_152 : _GEN_36; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _T_32 = _T_29 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@14354.4] assign _T_73 = _GEN_37 & _T_32; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.TinyConfig.fir@14470.4] assign _T_74 = _T_73 == 1'h0; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.TinyConfig.fir@14471.4] assign _T_55_ready = Queue_1_io_enq_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.TinyConfig.fir@14388.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@14422.4] assign _T_75 = _T_63 | _T_55_ready; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.TinyConfig.fir@14472.4] assign _T_56_ready = Queue_io_enq_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.TinyConfig.fir@14390.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@14399.4] assign _T_76 = _T_75 & _T_56_ready; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.TinyConfig.fir@14473.4] assign _T_77 = _T_19 ? _T_76 : _T_55_ready; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.TinyConfig.fir@14474.4] assign _T_78 = _T_74 & _T_77; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.TinyConfig.fir@14475.4] assign _T_20 = _T_78 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14342.4] assign _T_22 = 23'hff << auto_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14344.4] assign _T_23 = _T_22[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14345.4] assign _T_24 = ~ _T_23; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14346.4] assign _T_25 = _T_24[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@14347.4] assign _T_28 = _T_19 ? _T_25 : 6'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@14350.4] assign _T_31 = _T_29 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@14353.4] assign _T_33 = _T_29 == 6'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@14355.4] assign _T_34 = _T_28 == 6'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@14356.4] assign _T_35 = _T_33 | _T_34; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@14357.4] assign _T_49 = {auto_in_a_bits_size, 5'h0}; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.TinyConfig.fir@14382.4] assign _GEN_45 = {{4'd0}, auto_in_a_bits_source}; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.TinyConfig.fir@14383.4] assign _T_51 = auto_out_r_bits_user[4:0]; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.TinyConfig.fir@14384.4] assign _T_52 = auto_out_r_bits_user[8:5]; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.TinyConfig.fir@14385.4] assign _T_53 = auto_out_b_bits_user[4:0]; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.TinyConfig.fir@14386.4] assign _T_54 = auto_out_b_bits_user[8:5]; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.TinyConfig.fir@14387.4] assign _T_58_bits_wen = Queue_1_io_deq_bits_wen; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@14423.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@14424.4] assign _T_59 = _T_58_bits_wen == 1'h0; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.TinyConfig.fir@14439.4] assign _T_58_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@14423.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@14435.4] assign _T_65 = _T_35 == 1'h0; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.TinyConfig.fir@14449.6] assign _GEN_10 = 5'h8 == auto_in_a_bits_source ? 2'h3 : 2'h2; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_11 = 5'h9 == auto_in_a_bits_source ? 2'h3 : _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_12 = 5'ha == auto_in_a_bits_source ? 2'h3 : _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_13 = 5'hb == auto_in_a_bits_source ? 2'h3 : _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_14 = 5'hc == auto_in_a_bits_source ? 2'h3 : _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_15 = 5'hd == auto_in_a_bits_source ? 2'h3 : _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_16 = 5'he == auto_in_a_bits_source ? 2'h3 : _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_17 = 5'hf == auto_in_a_bits_source ? 2'h3 : _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_18 = 5'h10 == auto_in_a_bits_source ? 2'h0 : _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _GEN_19 = 5'h11 == auto_in_a_bits_source ? 2'h1 : _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.TinyConfig.fir@14453.4] assign _T_67 = 25'h3ff << auto_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14456.4] assign _T_68 = _T_67[9:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14457.4] assign _T_69 = ~ _T_68; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14458.4] assign _T_71 = auto_in_a_bits_size >= 4'h2; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.TinyConfig.fir@14461.4] assign _T_72 = _T_71 ? 4'h2 : auto_in_a_bits_size; // @[ToAXI4.scala 168:23:freechips.rocketchip.system.TinyConfig.fir@14462.4] assign _T_80 = _T_74 & auto_in_a_valid; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.TinyConfig.fir@14478.4] assign _T_81 = _T_63 == 1'h0; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.TinyConfig.fir@14479.4] assign _T_82 = _T_81 & _T_56_ready; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.TinyConfig.fir@14480.4] assign _T_83 = _T_19 ? _T_82 : 1'h1; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.TinyConfig.fir@14481.4] assign _T_84 = _T_80 & _T_83; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.TinyConfig.fir@14482.4] assign _T_87 = _T_80 & _T_19; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.TinyConfig.fir@14486.4] assign _T_91 = auto_in_d_ready & auto_out_r_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14494.4] assign _T_92 = auto_out_r_bits_last == 1'h0; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.TinyConfig.fir@14496.6] assign _T_93 = auto_out_r_valid | _T_90; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.TinyConfig.fir@14499.4] assign _T_94 = _T_93 == 1'h0; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.TinyConfig.fir@14501.4] assign _T_96 = _T_93 ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.TinyConfig.fir@14504.4] assign _T_99 = auto_out_r_bits_resp == 2'h3; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.TinyConfig.fir@14511.4] assign _GEN_40 = _T_97 ? _T_99 : _T_100; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@14513.4] assign _T_102 = auto_out_r_bits_resp != 2'h0; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.TinyConfig.fir@14517.4] assign _T_103 = auto_out_b_bits_resp != 2'h0; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.TinyConfig.fir@14518.4] assign _T_104 = _T_102 | _GEN_40; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.TinyConfig.fir@14519.4] assign _T_109 = 4'h1 << _GEN_19; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14544.4] assign _T_111 = _T_109[0]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14546.4] assign _T_112 = _T_109[1]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14547.4] assign _T_113 = _T_109[2]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14548.4] assign _T_114 = _T_109[3]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.TinyConfig.fir@14549.4] assign _T_115 = _T_93 ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.TinyConfig.fir@14550.4] assign _T_117 = 4'h1 << _T_115; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14552.4] assign _T_119 = _T_117[0]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14554.4] assign _T_120 = _T_117[1]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14555.4] assign _T_121 = _T_117[2]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14556.4] assign _T_122 = _T_117[3]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.TinyConfig.fir@14557.4] assign _T_123 = _T_93 ? auto_out_r_bits_last : 1'h1; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.TinyConfig.fir@14558.4] assign _T_127 = _T_55_ready & _T_84; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14562.4] assign _T_128 = _T_111 & _T_127; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14563.4] assign _T_129 = _T_119 & _T_123; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14564.4] assign _T_130 = auto_in_d_ready & _T_96; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@14565.4] assign _T_131 = _T_129 & _T_130; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14566.4] assign _T_133 = _T_124 + _T_128; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14568.4] assign _T_135 = _T_133 - _T_131; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14570.4] assign _T_136 = _T_131 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14572.4] assign _T_138 = _T_136 | _T_124; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14574.4] assign _T_140 = _T_138 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14576.4] assign _T_141 = _T_140 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14577.4] assign _T_142 = _T_128 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14582.4] assign _T_143 = _T_124 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14583.4] assign _T_144 = _T_142 | _T_143; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14584.4] assign _T_146 = _T_144 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14586.4] assign _T_147 = _T_146 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14587.4] assign _T_156 = _T_112 & _T_127; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14604.4] assign _T_157 = _T_120 & _T_123; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14605.4] assign _T_159 = _T_157 & _T_130; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14607.4] assign _T_161 = _T_152 + _T_156; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14609.4] assign _T_163 = _T_161 - _T_159; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14611.4] assign _T_164 = _T_159 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14613.4] assign _T_166 = _T_164 | _T_152; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14615.4] assign _T_168 = _T_166 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14617.4] assign _T_169 = _T_168 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14618.4] assign _T_170 = _T_156 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14623.4] assign _T_171 = _T_152 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14624.4] assign _T_172 = _T_170 | _T_171; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14625.4] assign _T_174 = _T_172 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14627.4] assign _T_175 = _T_174 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14628.4] assign _T_184 = _T_113 & _T_127; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14645.4] assign _T_185 = _T_121 & _T_123; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14646.4] assign _T_187 = _T_185 & _T_130; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14648.4] assign _GEN_46 = {{3'd0}, _T_184}; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14649.4] assign _T_189 = _T_180 + _GEN_46; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14650.4] assign _GEN_47 = {{3'd0}, _T_187}; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14651.4] assign _T_191 = _T_189 - _GEN_47; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14652.4] assign _T_192 = _T_187 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14654.4] assign _T_193 = _T_180 != 4'h0; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.TinyConfig.fir@14655.4] assign _T_194 = _T_192 | _T_193; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14656.4] assign _T_196 = _T_194 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14658.4] assign _T_197 = _T_196 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14659.4] assign _T_198 = _T_184 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14664.4] assign _T_199 = _T_180 != 4'h8; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14665.4] assign _T_200 = _T_198 | _T_199; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14666.4] assign _T_202 = _T_200 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14668.4] assign _T_203 = _T_202 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14669.4] assign _T_213 = _T_114 & _T_127; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.TinyConfig.fir@14687.4] assign _T_214 = _T_122 & _T_123; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.TinyConfig.fir@14688.4] assign _T_216 = _T_214 & _T_130; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@14690.4] assign _GEN_48 = {{3'd0}, _T_213}; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14691.4] assign _T_218 = _T_209 + _GEN_48; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.TinyConfig.fir@14692.4] assign _GEN_49 = {{3'd0}, _T_216}; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14693.4] assign _T_220 = _T_218 - _GEN_49; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.TinyConfig.fir@14694.4] assign _T_221 = _T_216 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.TinyConfig.fir@14696.4] assign _T_222 = _T_209 != 4'h0; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.TinyConfig.fir@14697.4] assign _T_223 = _T_221 | _T_222; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.TinyConfig.fir@14698.4] assign _T_225 = _T_223 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14700.4] assign _T_226 = _T_225 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14701.4] assign _T_227 = _T_213 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.TinyConfig.fir@14706.4] assign _T_228 = _T_209 != 4'h8; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.TinyConfig.fir@14707.4] assign _T_229 = _T_227 | _T_228; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@14708.4] assign _T_231 = _T_229 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14710.4] assign _T_232 = _T_231 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14711.4] assign auto_in_a_ready = _T_74 & _T_77; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_valid = _T_93 ? auto_out_r_valid : auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_opcode = _T_93 ? 3'h1 : 3'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_size = _T_93 ? _T_52 : _T_54; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_source = _T_93 ? _T_51 : _T_53; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_denied = _T_93 ? _GEN_40 : _T_103; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_in_d_bits_corrupt = _T_93 ? _T_104 : 1'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@14290.4] assign auto_out_aw_valid = _T_58_valid & _T_58_bits_wen; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_aw_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_w_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_w_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_w_bits_strb = Queue_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_w_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_b_ready = auto_in_d_ready & _T_94; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_valid = _T_58_valid & _T_59; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_ar_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign auto_out_r_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@14289.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@14240.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@14241.4] assign TLMonitor_io_in_a_ready = _T_74 & _T_77; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_valid = _T_93 ? auto_out_r_valid : auto_out_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_bits_opcode = _T_93 ? 3'h1 : 3'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_bits_size = _T_93 ? _T_52 : _T_54; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_bits_source = _T_93 ? _T_51 : _T_53; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_bits_denied = _T_93 ? _GEN_40 : _T_103; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign TLMonitor_io_in_d_bits_corrupt = _T_93 ? _T_104 : 1'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@14286.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@14393.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@14394.4] assign Queue_io_enq_valid = _T_87 & _T_75; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@14395.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14398.4] assign Queue_io_enq_bits_strb = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14397.4] assign Queue_io_enq_bits_last = _T_33 | _T_34; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14396.4] assign Queue_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@14405.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@14408.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@14409.4] assign Queue_1_io_enq_valid = _T_80 & _T_83; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@14410.4] assign Queue_1_io_enq_bits_id = 5'h11 == auto_in_a_bits_source ? 2'h1 : _GEN_18; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14421.4] assign Queue_1_io_enq_bits_addr = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14420.4] assign Queue_1_io_enq_bits_len = _T_69[9:2]; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14419.4] assign Queue_1_io_enq_bits_size = _T_72[2:0]; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14418.4] assign Queue_1_io_enq_bits_user = _GEN_45 | _T_49; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14412.4] assign Queue_1_io_enq_bits_wen = _T_18 == 1'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@14411.4] assign Queue_1_io_deq_ready = _T_58_bits_wen ? auto_out_aw_ready : auto_out_ar_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@14436.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_152 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_124 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_209 = _RAND_2[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_210 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_180 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_181 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_29 = _RAND_6[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_63 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_90 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_97 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_100 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_152 <= 1'h0; end else begin _T_152 <= _T_163; end if (reset) begin _T_124 <= 1'h0; end else begin _T_124 <= _T_135; end if (reset) begin _T_209 <= 4'h0; end else begin _T_209 <= _T_220; end if (_T_213) begin _T_210 <= _T_19; end if (reset) begin _T_180 <= 4'h0; end else begin _T_180 <= _T_191; end if (_T_184) begin _T_181 <= _T_19; end if (reset) begin _T_29 <= 6'h0; end else begin if (_T_20) begin if (_T_32) begin if (_T_19) begin _T_29 <= _T_25; end else begin _T_29 <= 6'h0; end end else begin _T_29 <= _T_31; end end end if (reset) begin _T_63 <= 1'h0; end else begin if (_T_20) begin _T_63 <= _T_65; end end if (reset) begin _T_90 <= 1'h0; end else begin if (_T_91) begin _T_90 <= _T_92; end end if (reset) begin _T_97 <= 1'h1; end else begin if (_T_91) begin _T_97 <= auto_out_r_bits_last; end end if (_T_97) begin _T_100 <= _T_99; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_141) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14579.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_141) begin $fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14580.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_147) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14589.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_147) begin $fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14590.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_169) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14620.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_169) begin $fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14621.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_175) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14630.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_175) begin $fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14631.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_197) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14661.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_197) begin $fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14662.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_203) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14671.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_203) begin $fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14672.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_226) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14703.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_226) begin $fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@14704.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_232) begin $fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14713.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_232) begin $fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.TinyConfig.fir@14714.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_7( // @[:freechips.rocketchip.system.TinyConfig.fir@14743.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@14744.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@14745.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@14746.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@15946.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@14761.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@14762.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@14765.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@14766.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@14774.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14785.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14786.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14787.6] wire [22:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14789.6] wire [7:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14790.6] wire [7:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14791.6] wire [30:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@14792.6] wire [30:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@14792.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@14793.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@14795.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14796.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@14798.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@14799.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@14800.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@14801.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@14802.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14804.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14805.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14807.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14808.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@14809.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@14810.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@14811.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14812.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14813.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14814.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14815.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14816.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14817.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14818.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14819.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14820.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14821.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14822.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14823.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@14826.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@14883.6] wire [30:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@14886.8] wire [31:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@14887.8] wire [31:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@14888.8] wire [31:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@14889.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@14890.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14895.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14908.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14909.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14916.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14917.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14923.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14924.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@14929.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14931.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14932.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@14937.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@14938.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14940.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14941.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@14946.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14948.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14949.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@14955.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@15009.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15011.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15012.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@15035.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@15038.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@15046.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15049.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15050.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@15069.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15071.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15072.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@15077.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15079.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15080.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@15094.6] wire _T_233; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@15097.8] wire _T_241; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@15105.8] wire _T_244; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15108.8] wire _T_245; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15109.8] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@15145.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@15187.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@15188.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@15189.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15191.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15192.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@15198.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@15229.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15231.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15232.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@15246.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@15277.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15279.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15280.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@15294.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@15344.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15346.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15347.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@15352.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@15353.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@15356.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@15357.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@15365.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15376.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15377.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15378.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@15380.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15383.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15384.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@15389.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15391.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15392.8] wire _T_408; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@15405.8] wire _T_410; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15407.8] wire _T_411; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15408.8] wire _T_412; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@15413.8] wire _T_414; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15415.8] wire _T_415; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15416.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@15422.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@15480.6] wire _T_464; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@15521.8] wire _T_466; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15523.8] wire _T_467; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15524.8] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@15539.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@15574.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@15610.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@15670.4] wire [5:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@15675.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@15676.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@15677.4] reg [5:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@15679.4] reg [31:0] _RAND_0; wire [5:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15681.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15682.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@15693.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@15694.4] reg [31:0] _RAND_2; reg [3:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@15695.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@15696.4] reg [31:0] _RAND_4; reg [30:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@15697.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@15698.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@15699.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@15701.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15703.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15704.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@15709.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15711.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15712.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@15717.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15719.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15720.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@15725.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15727.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15728.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@15733.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15735.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15736.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@15743.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@15751.4] wire [22:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@15753.4] wire [7:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@15754.4] wire [7:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@15755.4] wire [5:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@15756.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@15757.4] reg [5:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@15759.4] reg [31:0] _RAND_6; wire [5:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15761.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15762.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@15773.4] reg [31:0] _RAND_7; reg [3:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@15775.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@15776.4] reg [31:0] _RAND_9; reg _T_610; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@15778.4] reg [31:0] _RAND_10; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@15779.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@15780.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@15782.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15784.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15785.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@15798.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15800.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15801.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@15806.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15808.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15809.6] wire _T_633; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@15822.6] wire _T_635; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15824.6] wire _T_636; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15825.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@15832.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@15841.4] reg [31:0] _RAND_11; reg [5:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@15851.4] reg [31:0] _RAND_12; wire [5:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15853.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15854.4] reg [5:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@15873.4] reg [31:0] _RAND_13; wire [5:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15875.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15876.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@15891.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@15894.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@15896.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@15897.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@15898.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15900.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15901.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@15893.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@15912.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@15914.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@15915.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@15917.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@15887.4 :freechips.rocketchip.system.TinyConfig.fir@15889.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@15895.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@15919.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@15920.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@15921.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15923.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15924.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@15916.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@15907.4 :freechips.rocketchip.system.TinyConfig.fir@15909.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@15918.6] wire _T_704; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@15930.4] wire _T_705; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@15931.4] wire _T_706; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@15932.4] wire _T_707; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@15933.4] wire _T_709; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15935.4] wire _T_710; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15936.4] wire [17:0] _T_711; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@15941.4] wire [17:0] _T_712; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@15942.4] wire [17:0] _T_713; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@15943.4] reg [31:0] _T_714; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@15945.4] reg [31:0] _RAND_14; wire _T_715; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@15948.4] wire _T_716; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@15949.4] wire _T_717; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@15950.4] wire _T_718; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@15951.4] wire _T_719; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@15952.4] wire _T_720; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@15953.4] wire _T_722; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15955.4] wire _T_723; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15956.4] wire [31:0] _T_725; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@15962.4] wire _T_728; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@15966.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14897.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@14969.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15052.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15111.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@15162.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@15212.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@15260.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@15308.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15386.10] wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@15428.10] wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@15486.10] wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@15545.10] wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@15580.10] wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@15616.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@15946.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@14761.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@14762.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@14765.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@14766.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@14774.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14785.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14786.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@14787.6] assign _T_28 = 23'hff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@14789.6] assign _T_29 = _T_28[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@14790.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@14791.6] assign _GEN_18 = {{23'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@14792.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@14792.6] assign _T_32 = _T_31 == 31'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@14793.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@14795.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@14796.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@14798.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@14799.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@14800.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@14801.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@14802.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14804.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14805.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14807.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14808.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@14809.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@14810.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@14811.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14812.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14813.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14814.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14815.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14816.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14817.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14818.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14819.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14820.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@14821.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@14822.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@14823.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@14826.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@14883.6] assign _T_120 = io_in_a_bits_address ^ 31'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@14886.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@14887.8] assign _T_122 = $signed(_T_121) & $signed(-32'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@14888.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@14889.8] assign _T_124 = $signed(_T_123) == $signed(32'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@14890.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14895.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14908.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14909.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14916.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14917.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14923.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14924.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@14929.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14931.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14932.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@14937.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@14938.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14940.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14941.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@14946.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14948.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14949.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@14955.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@15009.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15011.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15012.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@15035.6] assign _T_200 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@15038.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@15046.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15049.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15050.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@15069.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15071.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15072.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@15077.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15079.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15080.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@15094.6] assign _T_233 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@15097.8] assign _T_241 = _T_233 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@15105.8] assign _T_244 = _T_241 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15108.8] assign _T_245 = _T_244 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15109.8] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@15145.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@15187.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@15188.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@15189.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15191.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15192.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@15198.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@15229.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15231.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15232.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@15246.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@15277.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15279.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15280.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@15294.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@15344.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15346.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15347.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@15352.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@15353.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@15356.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@15357.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@15365.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15376.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15377.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@15378.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@15380.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15383.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15384.8] assign _T_400 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@15389.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15391.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15392.8] assign _T_408 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@15405.8] assign _T_410 = _T_408 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15407.8] assign _T_411 = _T_410 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15408.8] assign _T_412 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@15413.8] assign _T_414 = _T_412 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15415.8] assign _T_415 = _T_414 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15416.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@15422.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@15480.6] assign _T_464 = _T_412 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@15521.8] assign _T_466 = _T_464 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15523.8] assign _T_467 = _T_466 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15524.8] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@15539.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@15574.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@15610.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@15670.4] assign _T_542 = _T_30[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@15675.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@15676.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@15677.4] assign _T_548 = _T_546 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15681.4] assign _T_549 = _T_546 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15682.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@15698.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@15699.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@15701.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15703.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15704.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@15709.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15711.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15712.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@15717.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15719.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15720.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@15725.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15727.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15728.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@15733.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15735.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15736.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@15743.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@15751.4] assign _T_588 = 23'hff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@15753.4] assign _T_589 = _T_588[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@15754.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@15755.4] assign _T_591 = _T_590[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@15756.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@15757.4] assign _T_596 = _T_594 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15761.4] assign _T_597 = _T_594 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15762.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@15779.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@15780.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@15782.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15784.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15785.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@15798.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15800.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15801.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@15806.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15808.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15809.6] assign _T_633 = io_in_d_bits_denied == _T_610; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@15822.6] assign _T_635 = _T_633 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15824.6] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15825.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@15832.4] assign _T_651 = _T_649 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15853.4] assign _T_652 = _T_649 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15854.4] assign _T_670 = _T_668 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@15875.4] assign _T_671 = _T_668 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@15876.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@15891.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@15894.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@15896.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@15897.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@15898.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15900.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15901.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@15893.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@15912.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@15914.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@15915.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@15917.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@15887.4 :freechips.rocketchip.system.TinyConfig.fir@15889.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@15895.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@15919.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@15920.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@15921.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15923.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15924.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@15916.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@15907.4 :freechips.rocketchip.system.TinyConfig.fir@15909.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@15918.6] assign _T_704 = _T_679 != _T_690; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@15930.4] assign _T_705 = _T_679 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@15931.4] assign _T_706 = _T_705 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@15932.4] assign _T_707 = _T_704 | _T_706; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@15933.4] assign _T_709 = _T_707 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15935.4] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15936.4] assign _T_711 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@15941.4] assign _T_712 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@15942.4] assign _T_713 = _T_711 & _T_712; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@15943.4] assign _T_715 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@15948.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@15949.4] assign _T_717 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@15950.4] assign _T_718 = _T_716 | _T_717; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@15951.4] assign _T_719 = _T_714 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@15952.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@15953.4] assign _T_722 = _T_720 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15955.4] assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15956.4] assign _T_725 = _T_714 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@15962.4] assign _T_728 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@15966.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14897.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@14969.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15052.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15111.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@15162.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@15212.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@15260.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@15308.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15386.10] assign _GEN_123 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@15428.10] assign _GEN_131 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@15486.10] assign _GEN_139 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@15545.10] assign _GEN_143 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@15580.10] assign _GEN_147 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@15616.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[30:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_610 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_639 = _RAND_11[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_649 = _RAND_12[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_668 = _RAND_13[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_714 = _RAND_14[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 6'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 6'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 6'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 6'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (_T_638) begin _T_610 <= io_in_d_bits_denied; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_713; end if (reset) begin _T_649 <= 6'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 6'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 6'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 6'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_714 <= 32'h0; end else begin if (_T_728) begin _T_714 <= 32'h0; end else begin _T_714 <= _T_725; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@14898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@14904.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@14905.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14911.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@14912.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14919.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@14920.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14926.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@14927.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14934.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@14935.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14943.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@14944.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14951.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@14952.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@14969.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@14970.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@14976.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@14977.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@14983.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@14984.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@14991.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@14992.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@14998.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@14999.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@15006.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@15007.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15014.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@15015.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@15023.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@15024.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@15031.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@15032.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15052.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@15053.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@15059.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@15060.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@15066.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@15067.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15074.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@15075.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15082.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@15083.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@15090.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@15091.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_245) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@15112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@15118.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@15119.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@15125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@15126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@15133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@15134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@15141.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@15142.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@15162.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_245) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@15163.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@15169.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@15170.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@15176.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@15177.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@15184.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@15185.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15194.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@15195.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@15212.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@15213.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@15219.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@15220.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@15226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@15227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15234.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@15235.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@15242.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@15243.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@15260.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@15261.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@15267.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@15268.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@15274.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@15275.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15282.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@15283.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@15290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@15291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@15308.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@15309.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@15315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@15316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@15322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@15323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@15330.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@15331.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@15338.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@15339.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15349.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@15350.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15386.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@15387.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@15395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_411) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@15411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_415) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15418.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_415) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@15419.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@15428.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@15429.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@15435.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@15436.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@15443.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@15444.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@15467.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_411) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@15468.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@15486.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@15487.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@15493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@15494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@15501.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@15502.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_467) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@15527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@15545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@15546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@15561.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_411) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@15562.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@15580.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@15581.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@15597.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_467) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@15598.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@15616.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@15617.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@15632.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_411) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@15633.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15706.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@15707.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15714.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@15715.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15722.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@15723.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15730.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@15731.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15738.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@15739.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15787.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@15788.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15803.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@15804.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15811.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@15812.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15827.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_636) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@15828.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15903.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@15904.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15926.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@15927.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_710) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15938.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_710) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@15939.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_723) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15958.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_723) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@15959.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLWidthWidget_2( // @[:freechips.rocketchip.system.TinyConfig.fir@15971.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@15972.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@15973.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [30:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@15974.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] TLMonitor_7 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@15981.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@16033.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@16032.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@15983.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@15984.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@16029.4] endmodule module TLMonitor_8( // @[:freechips.rocketchip.system.TinyConfig.fir@16063.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@16064.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@16065.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@16066.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@17266.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16081.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16082.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@16085.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16086.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16094.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16105.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16106.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16107.6] wire [22:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@16109.6] wire [7:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@16110.6] wire [7:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@16111.6] wire [30:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@16112.6] wire [30:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@16112.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@16113.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@16115.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@16116.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@16118.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@16119.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@16120.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@16121.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@16122.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16124.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16125.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16127.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16128.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@16129.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@16130.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@16131.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16132.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16133.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16134.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16135.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16136.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16137.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16138.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16139.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16140.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16141.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16142.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16143.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@16146.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@16203.6] wire [30:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@16206.8] wire [31:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@16207.8] wire [31:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@16208.8] wire [31:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@16209.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@16210.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16215.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16228.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16229.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16236.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16237.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16243.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16244.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@16249.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16251.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16252.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@16257.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@16258.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16260.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16261.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@16266.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16268.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16269.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@16275.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@16329.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16331.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16332.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@16355.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@16358.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@16366.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16369.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16370.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@16389.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16391.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16392.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@16397.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16399.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16400.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@16414.6] wire _T_233; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@16417.8] wire _T_241; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@16425.8] wire _T_244; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16428.8] wire _T_245; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16429.8] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@16465.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@16507.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@16508.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@16509.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16511.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16512.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@16518.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@16549.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16551.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16552.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@16566.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@16597.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16599.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16600.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@16614.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@16664.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16666.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16667.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16672.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16673.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@16676.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16677.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16685.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16696.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16697.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16698.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@16700.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16703.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16704.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@16709.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16711.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16712.8] wire _T_408; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@16725.8] wire _T_410; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16727.8] wire _T_411; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16728.8] wire _T_412; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@16733.8] wire _T_414; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16735.8] wire _T_415; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16736.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@16742.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@16800.6] wire _T_464; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@16841.8] wire _T_466; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16843.8] wire _T_467; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16844.8] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@16859.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@16894.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@16930.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@16990.4] wire [5:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@16995.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@16996.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@16997.4] reg [5:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@16999.4] reg [31:0] _RAND_0; wire [5:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17001.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17002.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@17013.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@17014.4] reg [31:0] _RAND_2; reg [3:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@17015.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@17016.4] reg [31:0] _RAND_4; reg [30:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@17017.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@17018.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@17019.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@17021.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17023.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17024.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@17029.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17031.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17032.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@17037.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17039.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17040.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@17045.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17047.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17048.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@17053.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17055.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17056.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@17063.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@17071.4] wire [22:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@17073.4] wire [7:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@17074.4] wire [7:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@17075.4] wire [5:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@17076.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@17077.4] reg [5:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@17079.4] reg [31:0] _RAND_6; wire [5:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17081.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17082.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@17093.4] reg [31:0] _RAND_7; reg [3:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@17095.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@17096.4] reg [31:0] _RAND_9; reg _T_610; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@17098.4] reg [31:0] _RAND_10; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@17099.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@17100.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@17102.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17104.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17105.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@17118.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17120.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17121.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@17126.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17128.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17129.6] wire _T_633; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@17142.6] wire _T_635; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17144.6] wire _T_636; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17145.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@17152.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@17161.4] reg [31:0] _RAND_11; reg [5:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@17171.4] reg [31:0] _RAND_12; wire [5:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17173.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17174.4] reg [5:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@17193.4] reg [31:0] _RAND_13; wire [5:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17195.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17196.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@17211.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@17214.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@17216.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@17217.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@17218.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17220.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17221.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@17213.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@17232.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@17234.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@17235.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@17237.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@17207.4 :freechips.rocketchip.system.TinyConfig.fir@17209.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@17215.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@17239.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@17240.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@17241.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17243.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17244.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@17236.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@17227.4 :freechips.rocketchip.system.TinyConfig.fir@17229.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@17238.6] wire _T_704; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@17250.4] wire _T_705; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@17251.4] wire _T_706; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@17252.4] wire _T_707; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@17253.4] wire _T_709; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17255.4] wire _T_710; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17256.4] wire [17:0] _T_711; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@17261.4] wire [17:0] _T_712; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@17262.4] wire [17:0] _T_713; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@17263.4] reg [31:0] _T_714; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@17265.4] reg [31:0] _RAND_14; wire _T_715; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@17268.4] wire _T_716; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@17269.4] wire _T_717; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@17270.4] wire _T_718; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@17271.4] wire _T_719; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@17272.4] wire _T_720; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@17273.4] wire _T_722; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17275.4] wire _T_723; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17276.4] wire [31:0] _T_725; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@17282.4] wire _T_728; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@17286.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16217.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@16289.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16372.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16431.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@16482.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@16532.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@16580.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@16628.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16706.10] wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@16748.10] wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@16806.10] wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@16865.10] wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@16900.10] wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@16936.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@17266.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16081.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16082.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@16085.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16086.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16094.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16105.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16106.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16107.6] assign _T_28 = 23'hff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@16109.6] assign _T_29 = _T_28[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@16110.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@16111.6] assign _GEN_18 = {{23'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@16112.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@16112.6] assign _T_32 = _T_31 == 31'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@16113.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@16115.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@16116.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@16118.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@16119.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@16120.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@16121.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@16122.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16124.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16125.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16127.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16128.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@16129.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@16130.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@16131.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16132.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16133.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16134.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16135.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16136.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16137.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16138.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16139.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16140.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@16141.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@16142.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@16143.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@16146.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@16203.6] assign _T_120 = io_in_a_bits_address ^ 31'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@16206.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@16207.8] assign _T_122 = $signed(_T_121) & $signed(-32'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@16208.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@16209.8] assign _T_124 = $signed(_T_123) == $signed(32'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@16210.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16215.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16228.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16229.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16236.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16237.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16243.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16244.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@16249.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16251.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16252.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@16257.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@16258.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16260.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16261.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@16266.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16268.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16269.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@16275.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@16329.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16331.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16332.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@16355.6] assign _T_200 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@16358.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@16366.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16369.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16370.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@16389.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16391.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16392.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@16397.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16399.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16400.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@16414.6] assign _T_233 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@16417.8] assign _T_241 = _T_233 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@16425.8] assign _T_244 = _T_241 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16428.8] assign _T_245 = _T_244 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16429.8] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@16465.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@16507.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@16508.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@16509.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16511.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16512.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@16518.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@16549.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16551.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16552.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@16566.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@16597.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16599.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16600.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@16614.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@16664.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16666.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16667.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16672.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@16673.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@16676.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16677.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@16685.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16696.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16697.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@16698.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@16700.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16703.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16704.8] assign _T_400 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@16709.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16711.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16712.8] assign _T_408 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@16725.8] assign _T_410 = _T_408 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16727.8] assign _T_411 = _T_410 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16728.8] assign _T_412 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@16733.8] assign _T_414 = _T_412 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16735.8] assign _T_415 = _T_414 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16736.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@16742.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@16800.6] assign _T_464 = _T_412 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@16841.8] assign _T_466 = _T_464 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16843.8] assign _T_467 = _T_466 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16844.8] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@16859.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@16894.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@16930.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@16990.4] assign _T_542 = _T_30[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@16995.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@16996.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@16997.4] assign _T_548 = _T_546 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17001.4] assign _T_549 = _T_546 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17002.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@17018.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@17019.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@17021.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17023.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17024.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@17029.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17031.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17032.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@17037.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17039.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17040.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@17045.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17047.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17048.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@17053.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17055.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17056.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@17063.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@17071.4] assign _T_588 = 23'hff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@17073.4] assign _T_589 = _T_588[7:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@17074.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@17075.4] assign _T_591 = _T_590[7:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@17076.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@17077.4] assign _T_596 = _T_594 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17081.4] assign _T_597 = _T_594 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17082.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@17099.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@17100.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@17102.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17104.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17105.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@17118.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17120.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17121.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@17126.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17128.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17129.6] assign _T_633 = io_in_d_bits_denied == _T_610; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@17142.6] assign _T_635 = _T_633 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17144.6] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17145.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@17152.4] assign _T_651 = _T_649 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17173.4] assign _T_652 = _T_649 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17174.4] assign _T_670 = _T_668 - 6'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@17195.4] assign _T_671 = _T_668 == 6'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@17196.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@17211.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@17214.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@17216.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@17217.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@17218.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17220.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17221.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@17213.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@17232.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@17234.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@17235.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@17237.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@17207.4 :freechips.rocketchip.system.TinyConfig.fir@17209.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@17215.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@17239.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@17240.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@17241.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17243.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17244.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@17236.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@17227.4 :freechips.rocketchip.system.TinyConfig.fir@17229.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@17238.6] assign _T_704 = _T_679 != _T_690; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@17250.4] assign _T_705 = _T_679 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@17251.4] assign _T_706 = _T_705 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@17252.4] assign _T_707 = _T_704 | _T_706; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@17253.4] assign _T_709 = _T_707 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17255.4] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17256.4] assign _T_711 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@17261.4] assign _T_712 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@17262.4] assign _T_713 = _T_711 & _T_712; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@17263.4] assign _T_715 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@17268.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@17269.4] assign _T_717 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@17270.4] assign _T_718 = _T_716 | _T_717; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@17271.4] assign _T_719 = _T_714 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@17272.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@17273.4] assign _T_722 = _T_720 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17275.4] assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17276.4] assign _T_725 = _T_714 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@17282.4] assign _T_728 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@17286.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16217.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@16289.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16372.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16431.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@16482.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@16532.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@16580.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@16628.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16706.10] assign _GEN_123 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@16748.10] assign _GEN_131 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@16806.10] assign _GEN_139 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@16865.10] assign _GEN_143 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@16900.10] assign _GEN_147 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@16936.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[30:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_610 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_639 = _RAND_11[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_649 = _RAND_12[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_668 = _RAND_13[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_714 = _RAND_14[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 6'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 6'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 6'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 6'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (_T_638) begin _T_610 <= io_in_d_bits_denied; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_713; end if (reset) begin _T_649 <= 6'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 6'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 6'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 6'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_714 <= 32'h0; end else begin if (_T_728) begin _T_714 <= 32'h0; end else begin _T_714 <= _T_725; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16217.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@16218.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:60)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@16224.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@16225.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@16232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16239.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@16240.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16246.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@16247.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16254.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@16255.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16263.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@16264.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16271.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@16272.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@16289.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@16290.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:60)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@16296.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@16297.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@16303.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@16304.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@16311.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@16312.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@16318.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@16319.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@16326.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@16327.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:60)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@16335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@16343.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@16344.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@16351.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@16352.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16372.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@16373.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@16379.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@16380.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@16386.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@16387.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@16395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@16403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@16410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@16411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16431.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_245) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@16432.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@16438.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@16439.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@16445.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@16446.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@16453.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@16454.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@16461.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@16462.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_245) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@16482.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_245) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@16483.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@16489.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@16490.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@16496.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@16497.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@16504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@16505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16514.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@16515.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@16532.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@16533.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@16539.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@16540.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@16546.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@16547.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16554.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@16555.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@16562.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@16563.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@16580.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@16581.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@16587.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@16588.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@16594.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@16595.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16602.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@16603.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@16610.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@16611.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@16628.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@16629.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@16635.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@16636.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@16642.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@16643.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@16650.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@16651.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@16658.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@16659.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:60)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16669.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@16670.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16706.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@16707.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16714.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@16715.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16730.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_411) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@16731.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_415) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16738.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_415) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@16739.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@16748.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@16749.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@16755.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@16756.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@16763.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@16764.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@16787.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_411) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@16788.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@16806.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@16807.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@16813.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@16814.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@16821.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@16822.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16846.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_467) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@16847.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@16865.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@16866.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@16881.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_411) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@16882.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@16900.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@16901.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_467) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@16917.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_467) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@16918.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@16936.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@16937.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_411) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@16952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_411) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@16953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17026.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@17027.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17034.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@17035.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17042.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@17043.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17050.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@17051.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17058.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@17059.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17107.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@17108.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17123.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@17124.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17131.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@17132.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17147.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_636) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@17148.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17223.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@17224.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:60)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17246.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@17247.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_710) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:60)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17258.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_710) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@17259.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_723) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:60)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17278.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_723) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@17279.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLBuffer_1( // @[:freechips.rocketchip.system.TinyConfig.fir@17291.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@17292.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@17293.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [30:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@17294.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] TLMonitor_8 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@17301.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17353.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17352.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17303.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17304.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@17349.4] endmodule module SimpleLazyModule_3( // @[:freechips.rocketchip.system.TinyConfig.fir@17375.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@17376.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@17377.4] output auto_buffer_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_buffer_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [2:0] auto_buffer_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [2:0] auto_buffer_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [3:0] auto_buffer_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [4:0] auto_buffer_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [30:0] auto_buffer_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [3:0] auto_buffer_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [31:0] auto_buffer_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_buffer_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_buffer_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_buffer_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [2:0] auto_buffer_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_buffer_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [4:0] auto_buffer_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_buffer_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [31:0] auto_buffer_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_buffer_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [30:0] auto_axi4buf_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [7:0] auto_axi4buf_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [2:0] auto_axi4buf_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [1:0] auto_axi4buf_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [2:0] auto_axi4buf_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [31:0] auto_axi4buf_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [3:0] auto_axi4buf_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [1:0] auto_axi4buf_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [30:0] auto_axi4buf_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [7:0] auto_axi4buf_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [2:0] auto_axi4buf_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [1:0] auto_axi4buf_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [2:0] auto_axi4buf_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output [3:0] auto_axi4buf_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] output auto_axi4buf_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [3:0] auto_axi4buf_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [31:0] auto_axi4buf_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input [1:0] auto_axi4buf_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] input auto_axi4buf_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@17378.4] ); wire axi4buf_clock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_reset; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [30:0] axi4buf_auto_in_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [7:0] axi4buf_auto_in_aw_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_in_aw_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_in_aw_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_aw_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_aw_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_in_aw_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_aw_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [31:0] axi4buf_auto_in_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_w_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_in_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [30:0] axi4buf_auto_in_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [7:0] axi4buf_auto_in_ar_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_in_ar_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_in_ar_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_ar_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_ar_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_in_ar_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_ar_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_in_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [31:0] axi4buf_auto_in_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_in_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_in_r_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [30:0] axi4buf_auto_out_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [7:0] axi4buf_auto_out_aw_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_out_aw_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_out_aw_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_aw_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_aw_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_out_aw_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_aw_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [31:0] axi4buf_auto_out_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_w_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_out_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [30:0] axi4buf_auto_out_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [7:0] axi4buf_auto_out_ar_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_out_ar_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_out_ar_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_ar_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_ar_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [2:0] axi4buf_auto_out_ar_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_ar_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [3:0] axi4buf_auto_out_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [31:0] axi4buf_auto_out_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire [1:0] axi4buf_auto_out_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4buf_auto_out_r_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] wire axi4yank_clock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_reset; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [30:0] axi4yank_auto_in_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [7:0] axi4yank_auto_in_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_in_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_in_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_in_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [8:0] axi4yank_auto_in_aw_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [31:0] axi4yank_auto_in_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [8:0] axi4yank_auto_in_b_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [30:0] axi4yank_auto_in_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [7:0] axi4yank_auto_in_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_in_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_in_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_in_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [8:0] axi4yank_auto_in_ar_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_in_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [31:0] axi4yank_auto_in_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [8:0] axi4yank_auto_in_r_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_in_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [30:0] axi4yank_auto_out_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [7:0] axi4yank_auto_out_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_out_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_out_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_out_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [31:0] axi4yank_auto_out_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_out_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [30:0] axi4yank_auto_out_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [7:0] axi4yank_auto_out_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_out_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_out_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [2:0] axi4yank_auto_out_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [3:0] axi4yank_auto_out_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [31:0] axi4yank_auto_out_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire [1:0] axi4yank_auto_out_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4yank_auto_out_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] wire axi4deint_clock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_reset; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_aw_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_aw_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_aw_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [30:0] axi4deint_auto_in_aw_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [7:0] axi4deint_auto_in_aw_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_in_aw_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_in_aw_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_aw_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_aw_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_in_aw_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_aw_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_in_aw_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_w_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_w_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [31:0] axi4deint_auto_in_w_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_w_bits_strb; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_w_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_b_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_b_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_b_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_in_b_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_in_b_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_ar_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_ar_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_ar_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [30:0] axi4deint_auto_in_ar_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [7:0] axi4deint_auto_in_ar_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_in_ar_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_in_ar_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_ar_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_ar_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_in_ar_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_ar_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_in_ar_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_r_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_r_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_in_r_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [31:0] axi4deint_auto_in_r_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_in_r_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_in_r_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_in_r_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_aw_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_aw_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_aw_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [30:0] axi4deint_auto_out_aw_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [7:0] axi4deint_auto_out_aw_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_out_aw_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_out_aw_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_aw_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_aw_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_out_aw_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_aw_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_out_aw_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_w_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_w_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [31:0] axi4deint_auto_out_w_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_w_bits_strb; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_w_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_b_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_b_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_b_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_out_b_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_out_b_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_ar_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_ar_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_ar_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [30:0] axi4deint_auto_out_ar_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [7:0] axi4deint_auto_out_ar_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_out_ar_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_out_ar_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_ar_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_ar_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [2:0] axi4deint_auto_out_ar_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_ar_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_out_ar_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_r_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_r_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [3:0] axi4deint_auto_out_r_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [31:0] axi4deint_auto_out_r_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [1:0] axi4deint_auto_out_r_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire [8:0] axi4deint_auto_out_r_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4deint_auto_out_r_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] wire axi4index_auto_in_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [30:0] axi4index_auto_in_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [7:0] axi4index_auto_in_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_in_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_in_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_in_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_in_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_in_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [31:0] axi4index_auto_in_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_in_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_in_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [30:0] axi4index_auto_in_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [7:0] axi4index_auto_in_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_in_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_in_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_in_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_in_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_in_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [31:0] axi4index_auto_in_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_in_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_in_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [30:0] axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [7:0] axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_out_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [31:0] axi4index_auto_out_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_out_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_out_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [30:0] axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [7:0] axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [2:0] axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_out_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [3:0] axi4index_auto_out_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [31:0] axi4index_auto_out_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [1:0] axi4index_auto_out_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire [8:0] axi4index_auto_out_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire axi4index_auto_out_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] wire tl2axi4_clock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_reset; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_a_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_a_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_in_a_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_in_a_bits_param; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_in_a_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [4:0] tl2axi4_auto_in_a_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [30:0] tl2axi4_auto_in_a_bits_address; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_in_a_bits_mask; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [31:0] tl2axi4_auto_in_a_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_a_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_d_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_d_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_in_d_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_in_d_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [4:0] tl2axi4_auto_in_d_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_d_bits_denied; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [31:0] tl2axi4_auto_in_d_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_in_d_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_aw_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [30:0] tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [7:0] tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [8:0] tl2axi4_auto_out_aw_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_w_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_w_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [31:0] tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_b_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_b_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_b_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_b_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [8:0] tl2axi4_auto_out_b_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_ar_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [30:0] tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [7:0] tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [2:0] tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [3:0] tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [8:0] tl2axi4_auto_out_ar_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_r_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_r_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_r_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [31:0] tl2axi4_auto_out_r_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [1:0] tl2axi4_auto_out_r_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire [8:0] tl2axi4_auto_out_r_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire tl2axi4_auto_out_r_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [4:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [30:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [4:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [4:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [30:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [4:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [30:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [30:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] AXI4Buffer axi4buf ( // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@17383.4] .clock(axi4buf_clock), .reset(axi4buf_reset), .auto_in_aw_ready(axi4buf_auto_in_aw_ready), .auto_in_aw_valid(axi4buf_auto_in_aw_valid), .auto_in_aw_bits_id(axi4buf_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4buf_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4buf_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4buf_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4buf_auto_in_aw_bits_burst), .auto_in_aw_bits_lock(axi4buf_auto_in_aw_bits_lock), .auto_in_aw_bits_cache(axi4buf_auto_in_aw_bits_cache), .auto_in_aw_bits_prot(axi4buf_auto_in_aw_bits_prot), .auto_in_aw_bits_qos(axi4buf_auto_in_aw_bits_qos), .auto_in_w_ready(axi4buf_auto_in_w_ready), .auto_in_w_valid(axi4buf_auto_in_w_valid), .auto_in_w_bits_data(axi4buf_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4buf_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4buf_auto_in_w_bits_last), .auto_in_b_ready(axi4buf_auto_in_b_ready), .auto_in_b_valid(axi4buf_auto_in_b_valid), .auto_in_b_bits_id(axi4buf_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4buf_auto_in_b_bits_resp), .auto_in_ar_ready(axi4buf_auto_in_ar_ready), .auto_in_ar_valid(axi4buf_auto_in_ar_valid), .auto_in_ar_bits_id(axi4buf_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4buf_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4buf_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4buf_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4buf_auto_in_ar_bits_burst), .auto_in_ar_bits_lock(axi4buf_auto_in_ar_bits_lock), .auto_in_ar_bits_cache(axi4buf_auto_in_ar_bits_cache), .auto_in_ar_bits_prot(axi4buf_auto_in_ar_bits_prot), .auto_in_ar_bits_qos(axi4buf_auto_in_ar_bits_qos), .auto_in_r_ready(axi4buf_auto_in_r_ready), .auto_in_r_valid(axi4buf_auto_in_r_valid), .auto_in_r_bits_id(axi4buf_auto_in_r_bits_id), .auto_in_r_bits_data(axi4buf_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4buf_auto_in_r_bits_resp), .auto_in_r_bits_last(axi4buf_auto_in_r_bits_last), .auto_out_aw_ready(axi4buf_auto_out_aw_ready), .auto_out_aw_valid(axi4buf_auto_out_aw_valid), .auto_out_aw_bits_id(axi4buf_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4buf_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4buf_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4buf_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4buf_auto_out_aw_bits_burst), .auto_out_aw_bits_lock(axi4buf_auto_out_aw_bits_lock), .auto_out_aw_bits_cache(axi4buf_auto_out_aw_bits_cache), .auto_out_aw_bits_prot(axi4buf_auto_out_aw_bits_prot), .auto_out_aw_bits_qos(axi4buf_auto_out_aw_bits_qos), .auto_out_w_ready(axi4buf_auto_out_w_ready), .auto_out_w_valid(axi4buf_auto_out_w_valid), .auto_out_w_bits_data(axi4buf_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4buf_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4buf_auto_out_w_bits_last), .auto_out_b_ready(axi4buf_auto_out_b_ready), .auto_out_b_valid(axi4buf_auto_out_b_valid), .auto_out_b_bits_id(axi4buf_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4buf_auto_out_b_bits_resp), .auto_out_ar_ready(axi4buf_auto_out_ar_ready), .auto_out_ar_valid(axi4buf_auto_out_ar_valid), .auto_out_ar_bits_id(axi4buf_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4buf_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4buf_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4buf_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4buf_auto_out_ar_bits_burst), .auto_out_ar_bits_lock(axi4buf_auto_out_ar_bits_lock), .auto_out_ar_bits_cache(axi4buf_auto_out_ar_bits_cache), .auto_out_ar_bits_prot(axi4buf_auto_out_ar_bits_prot), .auto_out_ar_bits_qos(axi4buf_auto_out_ar_bits_qos), .auto_out_r_ready(axi4buf_auto_out_r_ready), .auto_out_r_valid(axi4buf_auto_out_r_valid), .auto_out_r_bits_id(axi4buf_auto_out_r_bits_id), .auto_out_r_bits_data(axi4buf_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4buf_auto_out_r_bits_resp), .auto_out_r_bits_last(axi4buf_auto_out_r_bits_last) ); AXI4UserYanker axi4yank ( // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@17389.4] .clock(axi4yank_clock), .reset(axi4yank_reset), .auto_in_aw_ready(axi4yank_auto_in_aw_ready), .auto_in_aw_valid(axi4yank_auto_in_aw_valid), .auto_in_aw_bits_id(axi4yank_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4yank_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4yank_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4yank_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4yank_auto_in_aw_bits_burst), .auto_in_aw_bits_lock(axi4yank_auto_in_aw_bits_lock), .auto_in_aw_bits_cache(axi4yank_auto_in_aw_bits_cache), .auto_in_aw_bits_prot(axi4yank_auto_in_aw_bits_prot), .auto_in_aw_bits_qos(axi4yank_auto_in_aw_bits_qos), .auto_in_aw_bits_user(axi4yank_auto_in_aw_bits_user), .auto_in_w_ready(axi4yank_auto_in_w_ready), .auto_in_w_valid(axi4yank_auto_in_w_valid), .auto_in_w_bits_data(axi4yank_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4yank_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4yank_auto_in_w_bits_last), .auto_in_b_ready(axi4yank_auto_in_b_ready), .auto_in_b_valid(axi4yank_auto_in_b_valid), .auto_in_b_bits_id(axi4yank_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4yank_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4yank_auto_in_b_bits_user), .auto_in_ar_ready(axi4yank_auto_in_ar_ready), .auto_in_ar_valid(axi4yank_auto_in_ar_valid), .auto_in_ar_bits_id(axi4yank_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4yank_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4yank_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4yank_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4yank_auto_in_ar_bits_burst), .auto_in_ar_bits_lock(axi4yank_auto_in_ar_bits_lock), .auto_in_ar_bits_cache(axi4yank_auto_in_ar_bits_cache), .auto_in_ar_bits_prot(axi4yank_auto_in_ar_bits_prot), .auto_in_ar_bits_qos(axi4yank_auto_in_ar_bits_qos), .auto_in_ar_bits_user(axi4yank_auto_in_ar_bits_user), .auto_in_r_ready(axi4yank_auto_in_r_ready), .auto_in_r_valid(axi4yank_auto_in_r_valid), .auto_in_r_bits_id(axi4yank_auto_in_r_bits_id), .auto_in_r_bits_data(axi4yank_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4yank_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4yank_auto_in_r_bits_user), .auto_in_r_bits_last(axi4yank_auto_in_r_bits_last), .auto_out_aw_ready(axi4yank_auto_out_aw_ready), .auto_out_aw_valid(axi4yank_auto_out_aw_valid), .auto_out_aw_bits_id(axi4yank_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4yank_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4yank_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4yank_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4yank_auto_out_aw_bits_burst), .auto_out_aw_bits_lock(axi4yank_auto_out_aw_bits_lock), .auto_out_aw_bits_cache(axi4yank_auto_out_aw_bits_cache), .auto_out_aw_bits_prot(axi4yank_auto_out_aw_bits_prot), .auto_out_aw_bits_qos(axi4yank_auto_out_aw_bits_qos), .auto_out_w_ready(axi4yank_auto_out_w_ready), .auto_out_w_valid(axi4yank_auto_out_w_valid), .auto_out_w_bits_data(axi4yank_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4yank_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4yank_auto_out_w_bits_last), .auto_out_b_ready(axi4yank_auto_out_b_ready), .auto_out_b_valid(axi4yank_auto_out_b_valid), .auto_out_b_bits_id(axi4yank_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4yank_auto_out_b_bits_resp), .auto_out_ar_ready(axi4yank_auto_out_ar_ready), .auto_out_ar_valid(axi4yank_auto_out_ar_valid), .auto_out_ar_bits_id(axi4yank_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4yank_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4yank_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4yank_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4yank_auto_out_ar_bits_burst), .auto_out_ar_bits_lock(axi4yank_auto_out_ar_bits_lock), .auto_out_ar_bits_cache(axi4yank_auto_out_ar_bits_cache), .auto_out_ar_bits_prot(axi4yank_auto_out_ar_bits_prot), .auto_out_ar_bits_qos(axi4yank_auto_out_ar_bits_qos), .auto_out_r_ready(axi4yank_auto_out_r_ready), .auto_out_r_valid(axi4yank_auto_out_r_valid), .auto_out_r_bits_id(axi4yank_auto_out_r_bits_id), .auto_out_r_bits_data(axi4yank_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4yank_auto_out_r_bits_resp), .auto_out_r_bits_last(axi4yank_auto_out_r_bits_last) ); AXI4Deinterleaver axi4deint ( // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.TinyConfig.fir@17395.4] .clock(axi4deint_clock), .reset(axi4deint_reset), .auto_in_aw_ready(axi4deint_auto_in_aw_ready), .auto_in_aw_valid(axi4deint_auto_in_aw_valid), .auto_in_aw_bits_id(axi4deint_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4deint_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4deint_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4deint_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4deint_auto_in_aw_bits_burst), .auto_in_aw_bits_lock(axi4deint_auto_in_aw_bits_lock), .auto_in_aw_bits_cache(axi4deint_auto_in_aw_bits_cache), .auto_in_aw_bits_prot(axi4deint_auto_in_aw_bits_prot), .auto_in_aw_bits_qos(axi4deint_auto_in_aw_bits_qos), .auto_in_aw_bits_user(axi4deint_auto_in_aw_bits_user), .auto_in_w_ready(axi4deint_auto_in_w_ready), .auto_in_w_valid(axi4deint_auto_in_w_valid), .auto_in_w_bits_data(axi4deint_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4deint_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4deint_auto_in_w_bits_last), .auto_in_b_ready(axi4deint_auto_in_b_ready), .auto_in_b_valid(axi4deint_auto_in_b_valid), .auto_in_b_bits_id(axi4deint_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4deint_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4deint_auto_in_b_bits_user), .auto_in_ar_ready(axi4deint_auto_in_ar_ready), .auto_in_ar_valid(axi4deint_auto_in_ar_valid), .auto_in_ar_bits_id(axi4deint_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4deint_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4deint_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4deint_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4deint_auto_in_ar_bits_burst), .auto_in_ar_bits_lock(axi4deint_auto_in_ar_bits_lock), .auto_in_ar_bits_cache(axi4deint_auto_in_ar_bits_cache), .auto_in_ar_bits_prot(axi4deint_auto_in_ar_bits_prot), .auto_in_ar_bits_qos(axi4deint_auto_in_ar_bits_qos), .auto_in_ar_bits_user(axi4deint_auto_in_ar_bits_user), .auto_in_r_ready(axi4deint_auto_in_r_ready), .auto_in_r_valid(axi4deint_auto_in_r_valid), .auto_in_r_bits_id(axi4deint_auto_in_r_bits_id), .auto_in_r_bits_data(axi4deint_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4deint_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4deint_auto_in_r_bits_user), .auto_in_r_bits_last(axi4deint_auto_in_r_bits_last), .auto_out_aw_ready(axi4deint_auto_out_aw_ready), .auto_out_aw_valid(axi4deint_auto_out_aw_valid), .auto_out_aw_bits_id(axi4deint_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4deint_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4deint_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4deint_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4deint_auto_out_aw_bits_burst), .auto_out_aw_bits_lock(axi4deint_auto_out_aw_bits_lock), .auto_out_aw_bits_cache(axi4deint_auto_out_aw_bits_cache), .auto_out_aw_bits_prot(axi4deint_auto_out_aw_bits_prot), .auto_out_aw_bits_qos(axi4deint_auto_out_aw_bits_qos), .auto_out_aw_bits_user(axi4deint_auto_out_aw_bits_user), .auto_out_w_ready(axi4deint_auto_out_w_ready), .auto_out_w_valid(axi4deint_auto_out_w_valid), .auto_out_w_bits_data(axi4deint_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4deint_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4deint_auto_out_w_bits_last), .auto_out_b_ready(axi4deint_auto_out_b_ready), .auto_out_b_valid(axi4deint_auto_out_b_valid), .auto_out_b_bits_id(axi4deint_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4deint_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4deint_auto_out_b_bits_user), .auto_out_ar_ready(axi4deint_auto_out_ar_ready), .auto_out_ar_valid(axi4deint_auto_out_ar_valid), .auto_out_ar_bits_id(axi4deint_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4deint_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4deint_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4deint_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4deint_auto_out_ar_bits_burst), .auto_out_ar_bits_lock(axi4deint_auto_out_ar_bits_lock), .auto_out_ar_bits_cache(axi4deint_auto_out_ar_bits_cache), .auto_out_ar_bits_prot(axi4deint_auto_out_ar_bits_prot), .auto_out_ar_bits_qos(axi4deint_auto_out_ar_bits_qos), .auto_out_ar_bits_user(axi4deint_auto_out_ar_bits_user), .auto_out_r_ready(axi4deint_auto_out_r_ready), .auto_out_r_valid(axi4deint_auto_out_r_valid), .auto_out_r_bits_id(axi4deint_auto_out_r_bits_id), .auto_out_r_bits_data(axi4deint_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4deint_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4deint_auto_out_r_bits_user), .auto_out_r_bits_last(axi4deint_auto_out_r_bits_last) ); AXI4IdIndexer axi4index ( // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@17401.4] .auto_in_aw_ready(axi4index_auto_in_aw_ready), .auto_in_aw_valid(axi4index_auto_in_aw_valid), .auto_in_aw_bits_id(axi4index_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4index_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4index_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4index_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4index_auto_in_aw_bits_burst), .auto_in_aw_bits_lock(axi4index_auto_in_aw_bits_lock), .auto_in_aw_bits_cache(axi4index_auto_in_aw_bits_cache), .auto_in_aw_bits_prot(axi4index_auto_in_aw_bits_prot), .auto_in_aw_bits_qos(axi4index_auto_in_aw_bits_qos), .auto_in_aw_bits_user(axi4index_auto_in_aw_bits_user), .auto_in_w_ready(axi4index_auto_in_w_ready), .auto_in_w_valid(axi4index_auto_in_w_valid), .auto_in_w_bits_data(axi4index_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4index_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4index_auto_in_w_bits_last), .auto_in_b_ready(axi4index_auto_in_b_ready), .auto_in_b_valid(axi4index_auto_in_b_valid), .auto_in_b_bits_id(axi4index_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4index_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4index_auto_in_b_bits_user), .auto_in_ar_ready(axi4index_auto_in_ar_ready), .auto_in_ar_valid(axi4index_auto_in_ar_valid), .auto_in_ar_bits_id(axi4index_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4index_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4index_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4index_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4index_auto_in_ar_bits_burst), .auto_in_ar_bits_lock(axi4index_auto_in_ar_bits_lock), .auto_in_ar_bits_cache(axi4index_auto_in_ar_bits_cache), .auto_in_ar_bits_prot(axi4index_auto_in_ar_bits_prot), .auto_in_ar_bits_qos(axi4index_auto_in_ar_bits_qos), .auto_in_ar_bits_user(axi4index_auto_in_ar_bits_user), .auto_in_r_ready(axi4index_auto_in_r_ready), .auto_in_r_valid(axi4index_auto_in_r_valid), .auto_in_r_bits_id(axi4index_auto_in_r_bits_id), .auto_in_r_bits_data(axi4index_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4index_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4index_auto_in_r_bits_user), .auto_in_r_bits_last(axi4index_auto_in_r_bits_last), .auto_out_aw_ready(axi4index_auto_out_aw_ready), .auto_out_aw_valid(axi4index_auto_out_aw_valid), .auto_out_aw_bits_id(axi4index_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4index_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4index_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4index_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4index_auto_out_aw_bits_burst), .auto_out_aw_bits_lock(axi4index_auto_out_aw_bits_lock), .auto_out_aw_bits_cache(axi4index_auto_out_aw_bits_cache), .auto_out_aw_bits_prot(axi4index_auto_out_aw_bits_prot), .auto_out_aw_bits_qos(axi4index_auto_out_aw_bits_qos), .auto_out_aw_bits_user(axi4index_auto_out_aw_bits_user), .auto_out_w_ready(axi4index_auto_out_w_ready), .auto_out_w_valid(axi4index_auto_out_w_valid), .auto_out_w_bits_data(axi4index_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4index_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4index_auto_out_w_bits_last), .auto_out_b_ready(axi4index_auto_out_b_ready), .auto_out_b_valid(axi4index_auto_out_b_valid), .auto_out_b_bits_id(axi4index_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4index_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4index_auto_out_b_bits_user), .auto_out_ar_ready(axi4index_auto_out_ar_ready), .auto_out_ar_valid(axi4index_auto_out_ar_valid), .auto_out_ar_bits_id(axi4index_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4index_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4index_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4index_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4index_auto_out_ar_bits_burst), .auto_out_ar_bits_lock(axi4index_auto_out_ar_bits_lock), .auto_out_ar_bits_cache(axi4index_auto_out_ar_bits_cache), .auto_out_ar_bits_prot(axi4index_auto_out_ar_bits_prot), .auto_out_ar_bits_qos(axi4index_auto_out_ar_bits_qos), .auto_out_ar_bits_user(axi4index_auto_out_ar_bits_user), .auto_out_r_ready(axi4index_auto_out_r_ready), .auto_out_r_valid(axi4index_auto_out_r_valid), .auto_out_r_bits_id(axi4index_auto_out_r_bits_id), .auto_out_r_bits_data(axi4index_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4index_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4index_auto_out_r_bits_user), .auto_out_r_bits_last(axi4index_auto_out_r_bits_last) ); TLToAXI4 tl2axi4 ( // @[ToAXI4.scala 254:29:freechips.rocketchip.system.TinyConfig.fir@17407.4] .clock(tl2axi4_clock), .reset(tl2axi4_reset), .auto_in_a_ready(tl2axi4_auto_in_a_ready), .auto_in_a_valid(tl2axi4_auto_in_a_valid), .auto_in_a_bits_opcode(tl2axi4_auto_in_a_bits_opcode), .auto_in_a_bits_param(tl2axi4_auto_in_a_bits_param), .auto_in_a_bits_size(tl2axi4_auto_in_a_bits_size), .auto_in_a_bits_source(tl2axi4_auto_in_a_bits_source), .auto_in_a_bits_address(tl2axi4_auto_in_a_bits_address), .auto_in_a_bits_mask(tl2axi4_auto_in_a_bits_mask), .auto_in_a_bits_data(tl2axi4_auto_in_a_bits_data), .auto_in_a_bits_corrupt(tl2axi4_auto_in_a_bits_corrupt), .auto_in_d_ready(tl2axi4_auto_in_d_ready), .auto_in_d_valid(tl2axi4_auto_in_d_valid), .auto_in_d_bits_opcode(tl2axi4_auto_in_d_bits_opcode), .auto_in_d_bits_size(tl2axi4_auto_in_d_bits_size), .auto_in_d_bits_source(tl2axi4_auto_in_d_bits_source), .auto_in_d_bits_denied(tl2axi4_auto_in_d_bits_denied), .auto_in_d_bits_data(tl2axi4_auto_in_d_bits_data), .auto_in_d_bits_corrupt(tl2axi4_auto_in_d_bits_corrupt), .auto_out_aw_ready(tl2axi4_auto_out_aw_ready), .auto_out_aw_valid(tl2axi4_auto_out_aw_valid), .auto_out_aw_bits_id(tl2axi4_auto_out_aw_bits_id), .auto_out_aw_bits_addr(tl2axi4_auto_out_aw_bits_addr), .auto_out_aw_bits_len(tl2axi4_auto_out_aw_bits_len), .auto_out_aw_bits_size(tl2axi4_auto_out_aw_bits_size), .auto_out_aw_bits_burst(tl2axi4_auto_out_aw_bits_burst), .auto_out_aw_bits_lock(tl2axi4_auto_out_aw_bits_lock), .auto_out_aw_bits_cache(tl2axi4_auto_out_aw_bits_cache), .auto_out_aw_bits_prot(tl2axi4_auto_out_aw_bits_prot), .auto_out_aw_bits_qos(tl2axi4_auto_out_aw_bits_qos), .auto_out_aw_bits_user(tl2axi4_auto_out_aw_bits_user), .auto_out_w_ready(tl2axi4_auto_out_w_ready), .auto_out_w_valid(tl2axi4_auto_out_w_valid), .auto_out_w_bits_data(tl2axi4_auto_out_w_bits_data), .auto_out_w_bits_strb(tl2axi4_auto_out_w_bits_strb), .auto_out_w_bits_last(tl2axi4_auto_out_w_bits_last), .auto_out_b_ready(tl2axi4_auto_out_b_ready), .auto_out_b_valid(tl2axi4_auto_out_b_valid), .auto_out_b_bits_id(tl2axi4_auto_out_b_bits_id), .auto_out_b_bits_resp(tl2axi4_auto_out_b_bits_resp), .auto_out_b_bits_user(tl2axi4_auto_out_b_bits_user), .auto_out_ar_ready(tl2axi4_auto_out_ar_ready), .auto_out_ar_valid(tl2axi4_auto_out_ar_valid), .auto_out_ar_bits_id(tl2axi4_auto_out_ar_bits_id), .auto_out_ar_bits_addr(tl2axi4_auto_out_ar_bits_addr), .auto_out_ar_bits_len(tl2axi4_auto_out_ar_bits_len), .auto_out_ar_bits_size(tl2axi4_auto_out_ar_bits_size), .auto_out_ar_bits_burst(tl2axi4_auto_out_ar_bits_burst), .auto_out_ar_bits_lock(tl2axi4_auto_out_ar_bits_lock), .auto_out_ar_bits_cache(tl2axi4_auto_out_ar_bits_cache), .auto_out_ar_bits_prot(tl2axi4_auto_out_ar_bits_prot), .auto_out_ar_bits_qos(tl2axi4_auto_out_ar_bits_qos), .auto_out_ar_bits_user(tl2axi4_auto_out_ar_bits_user), .auto_out_r_ready(tl2axi4_auto_out_r_ready), .auto_out_r_valid(tl2axi4_auto_out_r_valid), .auto_out_r_bits_id(tl2axi4_auto_out_r_bits_id), .auto_out_r_bits_data(tl2axi4_auto_out_r_bits_data), .auto_out_r_bits_resp(tl2axi4_auto_out_r_bits_resp), .auto_out_r_bits_user(tl2axi4_auto_out_r_bits_user), .auto_out_r_bits_last(tl2axi4_auto_out_r_bits_last) ); TLWidthWidget_2 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@17413.4] .clock(widget_clock), .reset(widget_reset), .auto_in_a_ready(widget_auto_in_a_ready), .auto_in_a_valid(widget_auto_in_a_valid), .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode), .auto_in_a_bits_param(widget_auto_in_a_bits_param), .auto_in_a_bits_size(widget_auto_in_a_bits_size), .auto_in_a_bits_source(widget_auto_in_a_bits_source), .auto_in_a_bits_address(widget_auto_in_a_bits_address), .auto_in_a_bits_mask(widget_auto_in_a_bits_mask), .auto_in_a_bits_data(widget_auto_in_a_bits_data), .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt), .auto_in_d_ready(widget_auto_in_d_ready), .auto_in_d_valid(widget_auto_in_d_valid), .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode), .auto_in_d_bits_size(widget_auto_in_d_bits_size), .auto_in_d_bits_source(widget_auto_in_d_bits_source), .auto_in_d_bits_denied(widget_auto_in_d_bits_denied), .auto_in_d_bits_data(widget_auto_in_d_bits_data), .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt), .auto_out_a_ready(widget_auto_out_a_ready), .auto_out_a_valid(widget_auto_out_a_valid), .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode), .auto_out_a_bits_param(widget_auto_out_a_bits_param), .auto_out_a_bits_size(widget_auto_out_a_bits_size), .auto_out_a_bits_source(widget_auto_out_a_bits_source), .auto_out_a_bits_address(widget_auto_out_a_bits_address), .auto_out_a_bits_mask(widget_auto_out_a_bits_mask), .auto_out_a_bits_data(widget_auto_out_a_bits_data), .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt), .auto_out_d_ready(widget_auto_out_d_ready), .auto_out_d_valid(widget_auto_out_d_valid), .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode), .auto_out_d_bits_size(widget_auto_out_d_bits_size), .auto_out_d_bits_source(widget_auto_out_d_bits_source), .auto_out_d_bits_denied(widget_auto_out_d_bits_denied), .auto_out_d_bits_data(widget_auto_out_d_bits_data), .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt) ); TLBuffer_1 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@17419.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign auto_axi4buf_out_aw_valid = axi4buf_auto_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_id = axi4buf_auto_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_addr = axi4buf_auto_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_len = axi4buf_auto_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_size = axi4buf_auto_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_burst = axi4buf_auto_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_lock = axi4buf_auto_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_cache = axi4buf_auto_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_prot = axi4buf_auto_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_aw_bits_qos = axi4buf_auto_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_w_valid = axi4buf_auto_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_w_bits_data = axi4buf_auto_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_w_bits_strb = axi4buf_auto_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_w_bits_last = axi4buf_auto_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_b_ready = axi4buf_auto_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_valid = axi4buf_auto_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_id = axi4buf_auto_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_addr = axi4buf_auto_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_len = axi4buf_auto_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_size = axi4buf_auto_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_burst = axi4buf_auto_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_lock = axi4buf_auto_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_cache = axi4buf_auto_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_prot = axi4buf_auto_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_ar_bits_qos = axi4buf_auto_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign auto_axi4buf_out_r_ready = axi4buf_auto_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17387.4] assign axi4buf_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17388.4] assign axi4buf_auto_in_aw_valid = axi4yank_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_id = axi4yank_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_addr = axi4yank_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_len = axi4yank_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_size = axi4yank_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_burst = axi4yank_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_lock = axi4yank_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_cache = axi4yank_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_prot = axi4yank_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_aw_bits_qos = axi4yank_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_w_valid = axi4yank_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_w_bits_data = axi4yank_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_w_bits_strb = axi4yank_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_w_bits_last = axi4yank_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_b_ready = axi4yank_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_valid = axi4yank_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_id = axi4yank_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_addr = axi4yank_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_len = axi4yank_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_size = axi4yank_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_burst = axi4yank_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_lock = axi4yank_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_cache = axi4yank_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_prot = axi4yank_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_ar_bits_qos = axi4yank_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_in_r_ready = axi4yank_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4buf_auto_out_aw_ready = auto_axi4buf_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_w_ready = auto_axi4buf_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_b_valid = auto_axi4buf_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_b_bits_id = auto_axi4buf_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_b_bits_resp = auto_axi4buf_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_ar_ready = auto_axi4buf_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_r_valid = auto_axi4buf_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_r_bits_id = auto_axi4buf_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_r_bits_data = auto_axi4buf_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_r_bits_resp = auto_axi4buf_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4buf_auto_out_r_bits_last = auto_axi4buf_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17431.4] assign axi4yank_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17393.4] assign axi4yank_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17394.4] assign axi4yank_auto_in_aw_valid = axi4deint_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_id = axi4deint_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_addr = axi4deint_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_len = axi4deint_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_size = axi4deint_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_burst = axi4deint_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_lock = axi4deint_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_cache = axi4deint_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_prot = axi4deint_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_qos = axi4deint_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_aw_bits_user = axi4deint_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_w_valid = axi4deint_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_w_bits_data = axi4deint_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_w_bits_strb = axi4deint_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_w_bits_last = axi4deint_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_b_ready = axi4deint_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_valid = axi4deint_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_id = axi4deint_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_addr = axi4deint_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_len = axi4deint_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_size = axi4deint_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_burst = axi4deint_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_lock = axi4deint_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_cache = axi4deint_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_prot = axi4deint_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_qos = axi4deint_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_ar_bits_user = axi4deint_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_in_r_ready = axi4deint_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4yank_auto_out_aw_ready = axi4buf_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_w_ready = axi4buf_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_b_valid = axi4buf_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_b_bits_id = axi4buf_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_b_bits_resp = axi4buf_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_ar_ready = axi4buf_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_r_valid = axi4buf_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_r_bits_id = axi4buf_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_r_bits_data = axi4buf_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_r_bits_resp = axi4buf_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4yank_auto_out_r_bits_last = axi4buf_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17425.4] assign axi4deint_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17399.4] assign axi4deint_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17400.4] assign axi4deint_auto_in_aw_valid = axi4index_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_id = axi4index_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_addr = axi4index_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_len = axi4index_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_size = axi4index_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_burst = axi4index_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_lock = axi4index_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_cache = axi4index_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_prot = axi4index_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_qos = axi4index_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_aw_bits_user = axi4index_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_w_valid = axi4index_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_w_bits_data = axi4index_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_w_bits_strb = axi4index_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_w_bits_last = axi4index_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_b_ready = axi4index_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_valid = axi4index_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_id = axi4index_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_addr = axi4index_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_len = axi4index_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_size = axi4index_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_burst = axi4index_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_lock = axi4index_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_cache = axi4index_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_prot = axi4index_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_qos = axi4index_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_ar_bits_user = axi4index_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_in_r_ready = axi4index_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4deint_auto_out_aw_ready = axi4yank_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_w_ready = axi4yank_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_b_valid = axi4yank_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_b_bits_id = axi4yank_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_b_bits_resp = axi4yank_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_b_bits_user = axi4yank_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_ar_ready = axi4yank_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_valid = axi4yank_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_bits_id = axi4yank_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_bits_data = axi4yank_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_bits_resp = axi4yank_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_bits_user = axi4yank_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4deint_auto_out_r_bits_last = axi4yank_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17426.4] assign axi4index_auto_in_aw_valid = tl2axi4_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_id = tl2axi4_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_addr = tl2axi4_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_len = tl2axi4_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_size = tl2axi4_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_burst = tl2axi4_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_lock = tl2axi4_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_cache = tl2axi4_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_prot = tl2axi4_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_qos = tl2axi4_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_aw_bits_user = tl2axi4_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_w_valid = tl2axi4_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_w_bits_data = tl2axi4_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_w_bits_strb = tl2axi4_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_w_bits_last = tl2axi4_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_b_ready = tl2axi4_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_valid = tl2axi4_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_id = tl2axi4_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_addr = tl2axi4_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_len = tl2axi4_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_size = tl2axi4_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_burst = tl2axi4_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_lock = tl2axi4_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_cache = tl2axi4_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_prot = tl2axi4_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_qos = tl2axi4_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_ar_bits_user = tl2axi4_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_in_r_ready = tl2axi4_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign axi4index_auto_out_aw_ready = axi4deint_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_w_ready = axi4deint_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_b_valid = axi4deint_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_b_bits_id = axi4deint_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_b_bits_resp = axi4deint_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_b_bits_user = axi4deint_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_ar_ready = axi4deint_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_valid = axi4deint_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_bits_id = axi4deint_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_bits_data = axi4deint_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_bits_resp = axi4deint_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_bits_user = axi4deint_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign axi4index_auto_out_r_bits_last = axi4deint_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17427.4] assign tl2axi4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17411.4] assign tl2axi4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17412.4] assign tl2axi4_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign tl2axi4_auto_out_aw_ready = axi4index_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_w_ready = axi4index_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_b_valid = axi4index_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_b_bits_id = axi4index_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_b_bits_resp = axi4index_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_b_bits_user = axi4index_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_ar_ready = axi4index_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_valid = axi4index_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_bits_id = axi4index_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_bits_data = axi4index_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_bits_resp = axi4index_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_bits_user = axi4index_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign tl2axi4_auto_out_r_bits_last = axi4index_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17428.4] assign widget_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17417.4] assign widget_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17418.4] assign widget_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign widget_auto_out_a_ready = tl2axi4_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_valid = tl2axi4_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_opcode = tl2axi4_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_size = tl2axi4_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_source = tl2axi4_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_denied = tl2axi4_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_data = tl2axi4_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign widget_auto_out_d_bits_corrupt = tl2axi4_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17429.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17423.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17424.4] assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17432.4] assign buffer_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] assign buffer_auto_out_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17430.4] endmodule module SystemBus( // @[:freechips.rocketchip.system.TinyConfig.fir@17434.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@17435.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@17436.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [30:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [7:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [31:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [30:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [7:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [1:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [31:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [4:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [31:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [31:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [1:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [4:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] input auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [1:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@17437.4] ); wire system_bus_xbar_clock; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_reset; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_a_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_a_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_1_a_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_1_a_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_1_a_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_1_a_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_1_a_bits_address; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_1_a_bits_mask; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_1_a_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_a_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_d_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_d_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_1_d_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [1:0] system_bus_xbar_auto_in_1_d_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_1_d_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_1_d_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_d_bits_sink; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_d_bits_denied; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_1_d_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_1_d_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_a_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_a_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_0_a_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_0_a_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_0_a_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_a_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_0_a_bits_address; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_0_a_bits_mask; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_0_a_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_a_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_in_0_d_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [1:0] system_bus_xbar_auto_in_0_d_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_in_0_d_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_bits_sink; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_bits_denied; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_in_0_d_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_in_0_d_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_a_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_a_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_1_a_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_1_a_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_1_a_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [4:0] system_bus_xbar_auto_out_1_a_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [30:0] system_bus_xbar_auto_out_1_a_bits_address; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_1_a_bits_mask; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_out_1_a_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_a_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_d_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_d_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_1_d_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_1_d_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [4:0] system_bus_xbar_auto_out_1_d_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_d_bits_denied; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_out_1_d_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_1_d_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_a_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_a_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_0_a_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_0_a_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_0_a_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [4:0] system_bus_xbar_auto_out_0_a_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_out_0_a_bits_address; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_0_a_bits_mask; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_out_0_a_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_a_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_d_ready; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_d_valid; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [2:0] system_bus_xbar_auto_out_0_d_bits_opcode; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [1:0] system_bus_xbar_auto_out_0_d_bits_param; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [3:0] system_bus_xbar_auto_out_0_d_bits_size; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [4:0] system_bus_xbar_auto_out_0_d_bits_source; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_d_bits_sink; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_d_bits_denied; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire [31:0] system_bus_xbar_auto_out_0_d_bits_data; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire system_bus_xbar_auto_out_0_d_bits_corrupt; // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] wire coupler_from_tile_named_tile_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [1:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [1:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] wire coupler_to_bus_named_periphery_bus_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [4:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [1:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [4:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [4:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [1:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [3:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [4:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire [31:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] wire coupler_from_bus_named_front_bus_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [1:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [1:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire [31:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] wire coupler_to_port_named_mmio_port_axi4_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [4:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [31:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [4:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [31:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [31:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [31:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] TLXbar system_bus_xbar ( // @[SystemBus.scala 26:43:freechips.rocketchip.system.TinyConfig.fir@17442.4] .clock(system_bus_xbar_clock), .reset(system_bus_xbar_reset), .auto_in_1_a_ready(system_bus_xbar_auto_in_1_a_ready), .auto_in_1_a_valid(system_bus_xbar_auto_in_1_a_valid), .auto_in_1_a_bits_opcode(system_bus_xbar_auto_in_1_a_bits_opcode), .auto_in_1_a_bits_param(system_bus_xbar_auto_in_1_a_bits_param), .auto_in_1_a_bits_size(system_bus_xbar_auto_in_1_a_bits_size), .auto_in_1_a_bits_source(system_bus_xbar_auto_in_1_a_bits_source), .auto_in_1_a_bits_address(system_bus_xbar_auto_in_1_a_bits_address), .auto_in_1_a_bits_mask(system_bus_xbar_auto_in_1_a_bits_mask), .auto_in_1_a_bits_data(system_bus_xbar_auto_in_1_a_bits_data), .auto_in_1_a_bits_corrupt(system_bus_xbar_auto_in_1_a_bits_corrupt), .auto_in_1_d_ready(system_bus_xbar_auto_in_1_d_ready), .auto_in_1_d_valid(system_bus_xbar_auto_in_1_d_valid), .auto_in_1_d_bits_opcode(system_bus_xbar_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param(system_bus_xbar_auto_in_1_d_bits_param), .auto_in_1_d_bits_size(system_bus_xbar_auto_in_1_d_bits_size), .auto_in_1_d_bits_source(system_bus_xbar_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink(system_bus_xbar_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied(system_bus_xbar_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data(system_bus_xbar_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt(system_bus_xbar_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready(system_bus_xbar_auto_in_0_a_ready), .auto_in_0_a_valid(system_bus_xbar_auto_in_0_a_valid), .auto_in_0_a_bits_opcode(system_bus_xbar_auto_in_0_a_bits_opcode), .auto_in_0_a_bits_param(system_bus_xbar_auto_in_0_a_bits_param), .auto_in_0_a_bits_size(system_bus_xbar_auto_in_0_a_bits_size), .auto_in_0_a_bits_source(system_bus_xbar_auto_in_0_a_bits_source), .auto_in_0_a_bits_address(system_bus_xbar_auto_in_0_a_bits_address), .auto_in_0_a_bits_mask(system_bus_xbar_auto_in_0_a_bits_mask), .auto_in_0_a_bits_data(system_bus_xbar_auto_in_0_a_bits_data), .auto_in_0_a_bits_corrupt(system_bus_xbar_auto_in_0_a_bits_corrupt), .auto_in_0_d_ready(system_bus_xbar_auto_in_0_d_ready), .auto_in_0_d_valid(system_bus_xbar_auto_in_0_d_valid), .auto_in_0_d_bits_opcode(system_bus_xbar_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_param(system_bus_xbar_auto_in_0_d_bits_param), .auto_in_0_d_bits_size(system_bus_xbar_auto_in_0_d_bits_size), .auto_in_0_d_bits_source(system_bus_xbar_auto_in_0_d_bits_source), .auto_in_0_d_bits_sink(system_bus_xbar_auto_in_0_d_bits_sink), .auto_in_0_d_bits_denied(system_bus_xbar_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data(system_bus_xbar_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt(system_bus_xbar_auto_in_0_d_bits_corrupt), .auto_out_1_a_ready(system_bus_xbar_auto_out_1_a_ready), .auto_out_1_a_valid(system_bus_xbar_auto_out_1_a_valid), .auto_out_1_a_bits_opcode(system_bus_xbar_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param(system_bus_xbar_auto_out_1_a_bits_param), .auto_out_1_a_bits_size(system_bus_xbar_auto_out_1_a_bits_size), .auto_out_1_a_bits_source(system_bus_xbar_auto_out_1_a_bits_source), .auto_out_1_a_bits_address(system_bus_xbar_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask(system_bus_xbar_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data(system_bus_xbar_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt(system_bus_xbar_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready(system_bus_xbar_auto_out_1_d_ready), .auto_out_1_d_valid(system_bus_xbar_auto_out_1_d_valid), .auto_out_1_d_bits_opcode(system_bus_xbar_auto_out_1_d_bits_opcode), .auto_out_1_d_bits_size(system_bus_xbar_auto_out_1_d_bits_size), .auto_out_1_d_bits_source(system_bus_xbar_auto_out_1_d_bits_source), .auto_out_1_d_bits_denied(system_bus_xbar_auto_out_1_d_bits_denied), .auto_out_1_d_bits_data(system_bus_xbar_auto_out_1_d_bits_data), .auto_out_1_d_bits_corrupt(system_bus_xbar_auto_out_1_d_bits_corrupt), .auto_out_0_a_ready(system_bus_xbar_auto_out_0_a_ready), .auto_out_0_a_valid(system_bus_xbar_auto_out_0_a_valid), .auto_out_0_a_bits_opcode(system_bus_xbar_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param(system_bus_xbar_auto_out_0_a_bits_param), .auto_out_0_a_bits_size(system_bus_xbar_auto_out_0_a_bits_size), .auto_out_0_a_bits_source(system_bus_xbar_auto_out_0_a_bits_source), .auto_out_0_a_bits_address(system_bus_xbar_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask(system_bus_xbar_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data(system_bus_xbar_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt(system_bus_xbar_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready(system_bus_xbar_auto_out_0_d_ready), .auto_out_0_d_valid(system_bus_xbar_auto_out_0_d_valid), .auto_out_0_d_bits_opcode(system_bus_xbar_auto_out_0_d_bits_opcode), .auto_out_0_d_bits_param(system_bus_xbar_auto_out_0_d_bits_param), .auto_out_0_d_bits_size(system_bus_xbar_auto_out_0_d_bits_size), .auto_out_0_d_bits_source(system_bus_xbar_auto_out_0_d_bits_source), .auto_out_0_d_bits_sink(system_bus_xbar_auto_out_0_d_bits_sink), .auto_out_0_d_bits_denied(system_bus_xbar_auto_out_0_d_bits_denied), .auto_out_0_d_bits_data(system_bus_xbar_auto_out_0_d_bits_data), .auto_out_0_d_bits_corrupt(system_bus_xbar_auto_out_0_d_bits_corrupt) ); SimpleLazyModule coupler_from_tile_named_tile ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17448.4] .clock(coupler_from_tile_named_tile_clock), .reset(coupler_from_tile_named_tile_reset), .auto_buffer_out_a_ready(coupler_from_tile_named_tile_auto_buffer_out_a_ready), .auto_buffer_out_a_valid(coupler_from_tile_named_tile_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode(coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param(coupler_from_tile_named_tile_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size(coupler_from_tile_named_tile_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source(coupler_from_tile_named_tile_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address(coupler_from_tile_named_tile_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask(coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data(coupler_from_tile_named_tile_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt(coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready(coupler_from_tile_named_tile_auto_buffer_out_d_ready), .auto_buffer_out_d_valid(coupler_from_tile_named_tile_auto_buffer_out_d_valid), .auto_buffer_out_d_bits_opcode(coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode), .auto_buffer_out_d_bits_param(coupler_from_tile_named_tile_auto_buffer_out_d_bits_param), .auto_buffer_out_d_bits_size(coupler_from_tile_named_tile_auto_buffer_out_d_bits_size), .auto_buffer_out_d_bits_source(coupler_from_tile_named_tile_auto_buffer_out_d_bits_source), .auto_buffer_out_d_bits_sink(coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink), .auto_buffer_out_d_bits_denied(coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied), .auto_buffer_out_d_bits_data(coupler_from_tile_named_tile_auto_buffer_out_d_bits_data), .auto_buffer_out_d_bits_corrupt(coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt), .auto_tl_master_xing_in_a_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready), .auto_tl_master_xing_in_a_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid), .auto_tl_master_xing_in_a_bits_opcode(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode), .auto_tl_master_xing_in_a_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param), .auto_tl_master_xing_in_a_bits_size(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size), .auto_tl_master_xing_in_a_bits_source(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source), .auto_tl_master_xing_in_a_bits_address(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address), .auto_tl_master_xing_in_a_bits_mask(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask), .auto_tl_master_xing_in_a_bits_data(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data), .auto_tl_master_xing_in_a_bits_corrupt(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt), .auto_tl_master_xing_in_d_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready), .auto_tl_master_xing_in_d_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid), .auto_tl_master_xing_in_d_bits_opcode(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode), .auto_tl_master_xing_in_d_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param), .auto_tl_master_xing_in_d_bits_size(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size), .auto_tl_master_xing_in_d_bits_source(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source), .auto_tl_master_xing_in_d_bits_sink(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink), .auto_tl_master_xing_in_d_bits_denied(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied), .auto_tl_master_xing_in_d_bits_data(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data), .auto_tl_master_xing_in_d_bits_corrupt(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt) ); SimpleLazyModule_1 coupler_to_bus_named_periphery_bus ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17454.4] .clock(coupler_to_bus_named_periphery_bus_clock), .reset(coupler_to_bus_named_periphery_bus_reset), .auto_widget_in_a_ready(coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready), .auto_widget_in_a_valid(coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid), .auto_widget_in_a_bits_opcode(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode), .auto_widget_in_a_bits_param(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param), .auto_widget_in_a_bits_size(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size), .auto_widget_in_a_bits_source(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source), .auto_widget_in_a_bits_address(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address), .auto_widget_in_a_bits_mask(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask), .auto_widget_in_a_bits_data(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data), .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt), .auto_widget_in_d_ready(coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready), .auto_widget_in_d_valid(coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid), .auto_widget_in_d_bits_opcode(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode), .auto_widget_in_d_bits_param(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param), .auto_widget_in_d_bits_size(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size), .auto_widget_in_d_bits_source(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source), .auto_widget_in_d_bits_sink(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink), .auto_widget_in_d_bits_denied(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied), .auto_widget_in_d_bits_data(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data), .auto_widget_in_d_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt), .auto_bus_xing_out_a_ready(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready), .auto_bus_xing_out_a_valid(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid), .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode), .auto_bus_xing_out_d_bits_param(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param), .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size), .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source), .auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink), .auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied), .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data), .auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt) ); SimpleLazyModule_2 coupler_from_bus_named_front_bus ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17460.4] .clock(coupler_from_bus_named_front_bus_clock), .reset(coupler_from_bus_named_front_bus_reset), .auto_widget_out_a_ready(coupler_from_bus_named_front_bus_auto_widget_out_a_ready), .auto_widget_out_a_valid(coupler_from_bus_named_front_bus_auto_widget_out_a_valid), .auto_widget_out_a_bits_opcode(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode), .auto_widget_out_a_bits_param(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param), .auto_widget_out_a_bits_size(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size), .auto_widget_out_a_bits_source(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source), .auto_widget_out_a_bits_address(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address), .auto_widget_out_a_bits_mask(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask), .auto_widget_out_a_bits_data(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data), .auto_widget_out_a_bits_corrupt(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt), .auto_widget_out_d_ready(coupler_from_bus_named_front_bus_auto_widget_out_d_ready), .auto_widget_out_d_valid(coupler_from_bus_named_front_bus_auto_widget_out_d_valid), .auto_widget_out_d_bits_opcode(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode), .auto_widget_out_d_bits_param(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param), .auto_widget_out_d_bits_size(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size), .auto_widget_out_d_bits_source(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source), .auto_widget_out_d_bits_sink(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink), .auto_widget_out_d_bits_denied(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied), .auto_widget_out_d_bits_data(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data), .auto_widget_out_d_bits_corrupt(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt), .auto_bus_xing_in_a_ready(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid), .auto_bus_xing_in_a_bits_opcode(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode), .auto_bus_xing_in_a_bits_param(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param), .auto_bus_xing_in_a_bits_size(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size), .auto_bus_xing_in_a_bits_source(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source), .auto_bus_xing_in_a_bits_address(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address), .auto_bus_xing_in_a_bits_mask(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask), .auto_bus_xing_in_a_bits_data(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data), .auto_bus_xing_in_a_bits_corrupt(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt), .auto_bus_xing_in_d_ready(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready), .auto_bus_xing_in_d_valid(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt) ); SimpleLazyModule_3 coupler_to_port_named_mmio_port_axi4 ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@17466.4] .clock(coupler_to_port_named_mmio_port_axi4_clock), .reset(coupler_to_port_named_mmio_port_axi4_reset), .auto_buffer_in_a_ready(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready), .auto_buffer_in_a_valid(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid), .auto_buffer_in_a_bits_opcode(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode), .auto_buffer_in_a_bits_param(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param), .auto_buffer_in_a_bits_size(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size), .auto_buffer_in_a_bits_source(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source), .auto_buffer_in_a_bits_address(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address), .auto_buffer_in_a_bits_mask(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask), .auto_buffer_in_a_bits_data(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data), .auto_buffer_in_a_bits_corrupt(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt), .auto_buffer_in_d_ready(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready), .auto_buffer_in_d_valid(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_size(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_denied(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt), .auto_axi4buf_out_aw_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready), .auto_axi4buf_out_aw_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid), .auto_axi4buf_out_aw_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id), .auto_axi4buf_out_aw_bits_addr(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr), .auto_axi4buf_out_aw_bits_len(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len), .auto_axi4buf_out_aw_bits_size(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size), .auto_axi4buf_out_aw_bits_burst(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst), .auto_axi4buf_out_aw_bits_lock(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock), .auto_axi4buf_out_aw_bits_cache(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache), .auto_axi4buf_out_aw_bits_prot(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot), .auto_axi4buf_out_aw_bits_qos(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos), .auto_axi4buf_out_w_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready), .auto_axi4buf_out_w_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid), .auto_axi4buf_out_w_bits_data(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data), .auto_axi4buf_out_w_bits_strb(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb), .auto_axi4buf_out_w_bits_last(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last), .auto_axi4buf_out_b_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready), .auto_axi4buf_out_b_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid), .auto_axi4buf_out_b_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id), .auto_axi4buf_out_b_bits_resp(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp), .auto_axi4buf_out_ar_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready), .auto_axi4buf_out_ar_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid), .auto_axi4buf_out_ar_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id), .auto_axi4buf_out_ar_bits_addr(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr), .auto_axi4buf_out_ar_bits_len(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len), .auto_axi4buf_out_ar_bits_size(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size), .auto_axi4buf_out_ar_bits_burst(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst), .auto_axi4buf_out_ar_bits_lock(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock), .auto_axi4buf_out_ar_bits_cache(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache), .auto_axi4buf_out_ar_bits_prot(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot), .auto_axi4buf_out_ar_bits_qos(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos), .auto_axi4buf_out_r_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready), .auto_axi4buf_out_r_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid), .auto_axi4buf_out_r_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id), .auto_axi4buf_out_r_bits_data(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data), .auto_axi4buf_out_r_bits_resp(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp), .auto_axi4buf_out_r_bits_last(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last) ); assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready = coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready = coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign system_bus_xbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17446.4] assign system_bus_xbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17447.4] assign system_bus_xbar_auto_in_1_a_valid = coupler_from_bus_named_front_bus_auto_widget_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_opcode = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_param = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_size = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_source = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_address = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_mask = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_data = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_a_bits_corrupt = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_1_d_ready = coupler_from_bus_named_front_bus_auto_widget_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign system_bus_xbar_auto_in_0_a_valid = coupler_from_tile_named_tile_auto_buffer_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_opcode = coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_param = coupler_from_tile_named_tile_auto_buffer_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_size = coupler_from_tile_named_tile_auto_buffer_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_source = coupler_from_tile_named_tile_auto_buffer_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_address = coupler_from_tile_named_tile_auto_buffer_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_mask = coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_data = coupler_from_tile_named_tile_auto_buffer_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_a_bits_corrupt = coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_in_0_d_ready = coupler_from_tile_named_tile_auto_buffer_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign system_bus_xbar_auto_out_1_a_ready = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_valid = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_opcode = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_size = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_source = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_denied = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_data = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_1_d_bits_corrupt = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign system_bus_xbar_auto_out_0_a_ready = coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_valid = coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_opcode = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_param = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_size = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_source = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_sink = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_denied = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_data = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign system_bus_xbar_auto_out_0_d_bits_corrupt = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_from_tile_named_tile_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17452.4] assign coupler_from_tile_named_tile_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17453.4] assign coupler_from_tile_named_tile_auto_buffer_out_a_ready = system_bus_xbar_auto_in_0_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_valid = system_bus_xbar_auto_in_0_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode = system_bus_xbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_param = system_bus_xbar_auto_in_0_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_size = system_bus_xbar_auto_in_0_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_source = system_bus_xbar_auto_in_0_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink = system_bus_xbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied = system_bus_xbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_data = system_bus_xbar_auto_in_0_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt = system_bus_xbar_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17474.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready = auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17476.4] assign coupler_to_bus_named_periphery_bus_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17458.4] assign coupler_to_bus_named_periphery_bus_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17459.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid = system_bus_xbar_auto_out_0_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode = system_bus_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param = system_bus_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size = system_bus_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source = system_bus_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address = system_bus_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask = system_bus_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data = system_bus_xbar_auto_out_0_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt = system_bus_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready = system_bus_xbar_auto_out_0_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17472.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17477.4] assign coupler_from_bus_named_front_bus_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17464.4] assign coupler_from_bus_named_front_bus_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17465.4] assign coupler_from_bus_named_front_bus_auto_widget_out_a_ready = system_bus_xbar_auto_in_1_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_valid = system_bus_xbar_auto_in_1_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode = system_bus_xbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param = system_bus_xbar_auto_in_1_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size = system_bus_xbar_auto_in_1_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source = system_bus_xbar_auto_in_1_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink = system_bus_xbar_auto_in_1_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied = system_bus_xbar_auto_in_1_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data = system_bus_xbar_auto_in_1_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt = system_bus_xbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@17475.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready = auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@17478.4] assign coupler_to_port_named_mmio_port_axi4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@17470.4] assign coupler_to_port_named_mmio_port_axi4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@17471.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid = system_bus_xbar_auto_out_1_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode = system_bus_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param = system_bus_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size = system_bus_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source = system_bus_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address = system_bus_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask = system_bus_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data = system_bus_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt = system_bus_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready = system_bus_xbar_auto_out_1_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@17473.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@17479.4] endmodule module TLMonitor_9( // @[:freechips.rocketchip.system.TinyConfig.fir@17596.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@17597.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@17598.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@17599.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@19101.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@17616.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@17617.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@17634.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@17636.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@17637.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@17638.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@17639.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@17639.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@17640.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@17642.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@17643.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@17645.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@17646.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@17647.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@17648.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@17649.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17651.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17652.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17654.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17655.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@17656.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@17657.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@17658.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17659.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17660.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17661.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17662.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17663.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17664.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17665.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17666.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17667.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17668.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17669.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17670.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@17673.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17684.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@17712.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17715.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17716.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17717.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17718.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17719.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17720.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17721.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17722.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17723.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17724.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17725.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17726.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17727.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17728.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17729.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17732.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17733.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17734.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17735.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17736.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17737.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17738.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17739.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17740.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17741.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17742.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17743.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17744.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17745.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17746.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17747.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17748.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17749.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17750.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17751.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17752.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17753.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17760.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17773.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17774.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17781.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17782.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17788.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17789.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@17794.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17796.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17797.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@17802.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@17803.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17805.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17806.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@17811.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17813.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17814.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@17820.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@17910.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17912.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17913.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@17936.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@17939.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@17947.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@17949.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17982.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17983.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17984.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17985.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17986.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@17987.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@17989.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17991.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17992.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@18011.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18013.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18014.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@18019.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18021.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18022.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@18036.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18075.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@18084.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18092.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@18094.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@18096.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18098.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18099.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@18135.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@18225.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@18226.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@18227.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18229.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18230.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@18236.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@18239.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18271.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18288.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18289.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@18308.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18310.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18311.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@18325.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@18397.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18399.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18400.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@18414.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18466.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18467.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@18505.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18507.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18508.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@18515.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@18516.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@18533.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@18535.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18538.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18539.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@18544.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18546.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18547.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@18552.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18554.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18555.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@18560.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18562.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18563.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@18568.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18570.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18571.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@18577.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@18601.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18603.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18604.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@18609.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18611.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18612.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@18635.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@18676.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18678.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18679.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@18694.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@18729.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@18765.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@18825.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@18830.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@18831.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@18832.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@18834.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@18836.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@18837.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@18848.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@18849.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@18850.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@18851.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@18852.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@18853.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@18854.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@18856.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18858.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18859.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@18864.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18866.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18867.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@18872.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18874.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18875.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@18880.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18882.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18883.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@18888.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18890.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18891.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@18898.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@18906.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@18908.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@18909.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@18910.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@18911.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@18912.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@18914.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@18916.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@18917.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@18928.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@18929.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@18930.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@18931.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@18932.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@18933.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@18934.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@18935.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@18937.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18939.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18940.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@18945.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18947.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18948.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@18953.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18955.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18956.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@18961.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18963.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18964.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@18969.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18971.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18972.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@18977.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18979.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18980.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@18987.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@18996.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@19006.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@19008.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@19009.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@19028.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@19030.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@19031.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@19046.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@19049.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@19051.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@19052.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@19053.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19055.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19056.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@19048.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@19067.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@19069.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@19070.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@19072.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@19074.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@19075.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@19076.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19078.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19079.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@19071.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@19085.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@19086.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@19087.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@19088.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19090.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19091.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@19096.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@19097.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@19098.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@19100.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@19103.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@19104.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@19105.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@19106.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@19107.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@19108.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19110.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19111.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@19117.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@19121.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17762.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@17870.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17994.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18101.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@18200.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18291.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@18380.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18469.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18541.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@18583.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@18641.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@18700.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@18735.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@18771.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@19101.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@17616.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@17617.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@17634.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@17636.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@17637.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@17638.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@17639.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@17639.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@17640.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@17642.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@17643.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@17645.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@17646.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@17647.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@17648.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@17649.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17651.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17652.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17654.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17655.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@17656.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@17657.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@17658.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17659.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17660.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17661.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17662.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17663.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17664.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17665.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17666.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17667.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@17668.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@17669.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@17670.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@17673.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17684.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@17712.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17715.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17716.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17717.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17718.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17719.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17720.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17721.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17722.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17723.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17724.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17725.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17726.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17727.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17728.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17729.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17732.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17733.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17734.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17735.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17736.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17737.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17738.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17739.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17740.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17741.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17742.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17743.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17744.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@17745.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@17746.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17747.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@17748.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@17749.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17750.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17751.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17752.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17753.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17760.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17773.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17774.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17781.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17782.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17788.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17789.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@17794.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17796.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17797.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@17802.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@17803.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17805.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17806.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@17811.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17813.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17814.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@17820.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@17910.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17912.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17913.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@17936.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@17939.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@17947.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@17949.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17982.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17983.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17984.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17985.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@17986.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@17987.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@17989.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17991.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17992.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@18011.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18013.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18014.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@18019.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18021.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18022.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@18036.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18075.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@18084.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18092.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@18094.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@18096.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18098.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18099.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@18135.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@18225.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@18226.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@18227.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18229.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18230.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@18236.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@18239.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@18271.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18288.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18289.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@18308.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18310.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18311.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@18325.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@18397.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18399.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18400.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@18414.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18466.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18467.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@18505.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18507.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18508.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@18515.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@18516.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@18533.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@18535.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18538.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18539.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@18544.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18546.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18547.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@18552.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18554.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18555.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@18560.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18562.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18563.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@18568.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18570.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18571.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@18577.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@18601.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18603.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18604.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@18609.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18611.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18612.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@18635.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@18676.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18678.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18679.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@18694.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@18729.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@18765.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@18825.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@18830.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@18831.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@18832.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@18836.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@18837.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@18853.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@18854.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@18856.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18858.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18859.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@18864.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18866.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18867.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@18872.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18874.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18875.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@18880.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18882.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18883.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@18888.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18890.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18891.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@18898.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@18906.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@18908.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@18909.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@18910.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@18911.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@18912.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@18916.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@18917.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@18934.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@18935.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@18937.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18939.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18940.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@18945.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18947.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18948.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@18953.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18955.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18956.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@18961.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18963.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18964.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@18969.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18971.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18972.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@18977.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18979.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18980.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@18987.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@19008.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@19009.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@19030.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@19031.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@19046.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@19049.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@19051.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@19052.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@19053.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19055.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19056.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@19048.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@19067.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@19069.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@19070.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@19072.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@19074.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@19075.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@19076.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19078.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19079.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@19071.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@19085.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@19086.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@19087.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@19088.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19090.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19091.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@19096.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@19097.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@19098.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@19103.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@19104.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@19105.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@19106.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@19107.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@19108.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19110.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19111.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@19117.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@19121.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17762.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@17870.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17994.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18101.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@18200.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18291.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@18380.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18469.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18541.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@18583.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@18641.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@18700.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@18735.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@18771.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17762.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@17763.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@17769.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@17770.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@17777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17784.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@17785.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17791.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@17792.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17799.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@17800.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17808.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@17809.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17816.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@17817.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@17870.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@17871.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@17877.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@17878.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@17884.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@17885.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@17892.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@17893.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@17899.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@17900.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@17907.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@17908.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17915.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@17916.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@17924.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@17925.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@17932.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@17933.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17994.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@17995.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@18001.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@18002.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@18008.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@18009.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18016.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@18017.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18024.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@18025.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@18032.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@18033.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18101.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@18102.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@18108.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@18109.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@18115.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@18116.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@18123.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@18124.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@18131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@18132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@18200.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@18201.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@18207.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@18208.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@18214.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@18215.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@18222.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@18223.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18232.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@18233.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18291.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@18292.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@18298.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@18299.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@18305.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@18306.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18313.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@18314.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@18321.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@18322.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@18380.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@18381.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@18387.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@18388.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@18394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@18395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@18403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@18410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@18411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@18470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@18476.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@18477.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@18483.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@18484.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@18491.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@18492.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@18499.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@18500.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18510.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@18511.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18541.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@18542.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18549.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@18550.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18557.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@18558.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18565.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@18566.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@18574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@18583.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@18584.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@18590.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@18591.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@18598.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@18599.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18606.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@18607.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18614.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@18615.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@18622.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@18623.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@18641.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@18642.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@18648.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@18649.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@18656.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@18657.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@18664.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@18665.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@18672.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@18673.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18681.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@18682.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@18700.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@18701.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@18708.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@18709.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@18716.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@18717.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@18735.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@18736.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@18743.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@18744.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@18752.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@18753.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@18771.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@18772.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@18779.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@18780.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@18787.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@18788.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18861.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@18862.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18869.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@18870.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18877.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@18878.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18885.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@18886.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18893.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@18894.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18942.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@18943.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18950.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@18951.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18958.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@18959.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18966.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@18967.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18974.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@18975.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18982.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@18983.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19058.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@19059.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19081.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@19082.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at BusWrapper.scala:164:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19093.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@19094.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19113.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@19114.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_3( // @[:freechips.rocketchip.system.TinyConfig.fir@19126.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@19127.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@19128.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@19129.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] TLMonitor_9 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@19136.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@19188.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@19187.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@19138.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@19139.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@19184.4] endmodule module TLMonitor_10( // @[:freechips.rocketchip.system.TinyConfig.fir@19370.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@19371.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@19372.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@19373.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@20875.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@19390.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@19391.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@19408.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@19410.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@19411.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@19412.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@19413.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@19413.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@19414.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@19416.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@19417.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@19419.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@19420.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@19421.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@19422.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@19423.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19425.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19426.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19428.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19429.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@19430.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@19431.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@19432.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19433.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19434.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19435.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19436.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19437.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19438.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19439.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19440.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19441.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19442.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19443.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19444.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@19447.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19458.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@19486.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19489.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19490.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19491.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19492.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19493.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19494.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19495.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19496.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19497.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19498.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19499.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19500.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19501.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19502.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19503.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19506.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19507.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19508.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19509.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19510.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19511.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19512.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19513.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19514.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19515.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19516.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19517.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19518.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19519.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19520.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19521.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19522.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19523.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19524.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19525.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19526.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19527.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19534.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19547.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19548.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19555.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19556.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19562.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19563.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@19568.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19570.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19571.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@19576.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@19577.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19579.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19580.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@19585.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19587.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19588.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@19594.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@19684.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19686.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19687.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@19710.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19713.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19721.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19723.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19756.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19757.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19758.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19759.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19760.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19761.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19763.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19765.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19766.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@19785.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19787.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19788.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@19793.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19795.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19796.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@19810.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19849.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19858.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19866.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19868.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19870.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19872.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19873.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@19909.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@19999.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@20000.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@20001.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20003.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20004.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@20010.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@20013.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@20045.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20062.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20063.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@20082.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20084.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20085.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@20099.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@20171.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20173.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20174.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@20188.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20240.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20241.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@20279.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20281.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20282.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@20289.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@20290.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@20307.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@20309.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20312.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20313.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@20318.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20320.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20321.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@20326.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20328.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20329.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@20334.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20336.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20337.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@20342.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20344.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20345.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@20351.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@20375.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20377.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20378.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@20383.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20385.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20386.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@20409.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@20450.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20452.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20453.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@20468.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@20503.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@20539.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@20599.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@20604.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@20605.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@20606.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@20608.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20610.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20611.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@20622.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@20623.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@20624.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@20625.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@20626.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@20627.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@20628.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@20630.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20632.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20633.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@20638.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20640.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20641.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@20646.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20648.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20649.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@20654.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20656.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20657.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@20662.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20664.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20665.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@20672.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@20680.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@20682.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@20683.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@20684.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@20685.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@20686.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@20688.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20690.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20691.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@20702.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@20703.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@20704.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@20705.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@20706.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@20707.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@20708.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@20709.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@20711.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20713.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20714.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@20719.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20721.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20722.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@20727.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20729.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20730.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@20735.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20737.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20738.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@20743.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20745.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20746.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@20751.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20753.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20754.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@20761.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@20770.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@20780.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20782.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20783.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@20802.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20804.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20805.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@20820.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@20823.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@20825.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@20826.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@20827.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20829.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20830.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@20822.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@20841.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@20843.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@20844.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@20846.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@20848.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@20849.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@20850.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20852.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20853.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@20845.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@20859.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@20860.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@20861.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@20862.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20864.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20865.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@20870.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@20871.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@20872.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@20874.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@20877.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@20878.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@20879.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@20880.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@20881.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@20882.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20884.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20885.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@20891.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@20895.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19536.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@19644.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19768.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19875.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@19974.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20065.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@20154.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20243.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20315.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@20357.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@20415.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@20474.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@20509.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@20545.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@20875.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@19390.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@19391.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@19408.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@19410.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@19411.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@19412.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@19413.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@19413.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@19414.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@19416.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@19417.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@19419.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@19420.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@19421.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@19422.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@19423.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19425.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19426.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19428.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19429.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@19430.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@19431.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@19432.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19433.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19434.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19435.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19436.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19437.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19438.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19439.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19440.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19441.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@19442.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@19443.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@19444.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@19447.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19458.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@19486.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19489.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19490.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19491.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19492.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19493.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19494.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19495.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19496.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19497.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19498.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19499.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19500.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19501.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19502.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19503.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19506.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19507.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19508.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19509.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19510.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19511.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19512.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19513.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19514.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19515.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19516.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19517.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19518.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@19519.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@19520.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19521.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@19522.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@19523.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19524.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19525.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19526.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19527.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19534.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19547.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19548.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19555.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19556.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19562.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19563.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@19568.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19570.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19571.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@19576.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@19577.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19579.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19580.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@19585.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19587.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19588.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@19594.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@19684.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19686.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19687.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@19710.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19713.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19721.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19723.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19756.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19757.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19758.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19759.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@19760.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19761.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19763.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19765.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19766.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@19785.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19787.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19788.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@19793.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19795.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19796.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@19810.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19849.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@19858.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@19866.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19868.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@19870.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19872.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19873.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@19909.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@19999.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@20000.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@20001.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20003.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20004.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@20010.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@20013.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@20045.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20062.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20063.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@20082.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20084.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20085.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@20099.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@20171.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20173.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20174.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@20188.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20240.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20241.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@20279.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20281.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20282.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@20289.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@20290.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@20307.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@20309.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20312.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20313.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@20318.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20320.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20321.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@20326.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20328.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20329.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@20334.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20336.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20337.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@20342.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20344.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20345.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@20351.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@20375.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20377.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20378.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@20383.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20385.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20386.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@20409.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@20450.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20452.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20453.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@20468.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@20503.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@20539.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@20599.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@20604.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@20605.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@20606.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20610.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20611.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@20627.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@20628.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@20630.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20632.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20633.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@20638.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20640.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20641.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@20646.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20648.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20649.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@20654.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20656.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20657.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@20662.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20664.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20665.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@20672.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@20680.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@20682.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@20683.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@20684.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@20685.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@20686.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20690.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20691.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@20708.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@20709.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@20711.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20713.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20714.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@20719.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20721.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20722.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@20727.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20729.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20730.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@20735.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20737.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20738.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@20743.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20745.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20746.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@20751.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20753.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20754.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@20761.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20782.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20783.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@20804.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@20805.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@20820.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@20823.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@20825.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@20826.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@20827.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20829.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20830.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@20822.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@20841.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@20843.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@20844.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@20846.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@20848.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@20849.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@20850.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20852.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20853.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@20845.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@20859.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@20860.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@20861.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@20862.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20864.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20865.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@20870.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@20871.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@20872.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@20877.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@20878.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@20879.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@20880.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@20881.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@20882.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20884.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20885.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@20891.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@20895.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19536.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@19644.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19768.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19875.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@19974.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20065.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@20154.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20243.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20315.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@20357.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@20415.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@20474.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@20509.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@20545.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19536.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@19537.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@19543.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@19544.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19550.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@19551.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@19559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19565.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@19566.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@19574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19582.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@19583.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19590.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@19591.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@19644.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@19645.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@19651.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@19652.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@19658.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@19659.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@19666.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@19667.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@19673.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@19674.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@19681.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@19682.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19689.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@19690.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@19698.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@19699.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@19706.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@19707.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19768.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@19769.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@19775.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@19776.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@19782.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@19783.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19790.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@19791.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@19799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@19806.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@19807.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19875.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@19876.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@19882.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@19883.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@19889.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@19890.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@19897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@19898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@19905.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@19906.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@19974.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@19975.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@19981.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@19982.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@19988.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@19989.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@19996.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@19997.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20006.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@20007.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20065.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@20066.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@20072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@20073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@20079.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@20080.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20087.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@20088.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@20095.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@20096.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@20154.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@20155.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@20161.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@20162.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@20168.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@20169.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20176.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@20177.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@20184.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@20185.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20243.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@20244.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@20250.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@20251.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@20257.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@20258.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@20265.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@20266.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@20273.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@20274.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20284.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@20285.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@20316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20323.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@20324.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20331.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@20332.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20339.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@20340.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20347.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@20348.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@20357.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@20358.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@20364.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@20365.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@20372.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@20373.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20380.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@20381.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@20389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@20396.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@20397.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@20415.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@20416.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@20422.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@20423.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@20430.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@20431.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@20438.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@20439.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@20446.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@20447.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20455.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@20456.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@20474.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@20475.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@20482.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@20483.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@20490.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@20491.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@20509.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@20510.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@20517.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@20518.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@20526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@20527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@20545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@20546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@20553.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@20554.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@20561.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@20562.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20635.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@20636.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20643.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@20644.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20651.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@20652.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20659.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@20660.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20667.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@20668.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20716.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@20717.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20724.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@20725.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20732.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@20733.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20740.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@20741.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20748.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@20749.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20756.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@20757.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20832.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@20833.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20855.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@20856.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20867.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@20868.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20887.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@20888.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_19( // @[:freechips.rocketchip.system.TinyConfig.fir@20900.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@20901.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@20902.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [3:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [3:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@20903.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_1; wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [3:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_3; wire [3:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [3:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_4; wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_address__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_5; wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@20906.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@20907.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@20908.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@20909.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@20910.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@20911.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@20912.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20913.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20916.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20931.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20937.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@20940.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_address__T_18_addr = value_1; assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_address__T_10_data = io_enq_bits_address; assign _T_address__T_10_addr = value; assign _T_address__T_10_mask = 1'h1; assign _T_address__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_18_addr = value_1; assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = value; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@20909.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@20910.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@20911.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@20912.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20913.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20916.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20931.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20937.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@20940.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@20947.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@20945.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20956.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20955.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20954.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20953.4] assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20952.4] assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20951.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20950.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@20949.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_address[initvar] = _RAND_4[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_mask[initvar] = _RAND_5[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_address__T_10_en & _T_address__T_10_mask) begin _T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20905.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_20( // @[:freechips.rocketchip.system.TinyConfig.fir@20964.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@20965.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@20966.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input [1:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input [3:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input io_enq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input io_enq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output [3:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output io_deq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output io_deq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@20967.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_1; wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [3:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_3; wire [3:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire [3:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg _T_sink [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_4; wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg _T_denied [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_5; wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@20970.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@20971.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@20972.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@20973.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@20974.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@20975.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@20976.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20977.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20980.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20995.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@21001.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@21004.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_sink__T_18_addr = value_1; assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_sink__T_10_data = io_enq_bits_sink; assign _T_sink__T_10_addr = value; assign _T_sink__T_10_mask = 1'h1; assign _T_sink__T_10_en = io_enq_ready & io_enq_valid; assign _T_denied__T_18_addr = value_1; assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_denied__T_10_data = io_enq_bits_denied; assign _T_denied__T_10_addr = value; assign _T_denied__T_10_mask = 1'h1; assign _T_denied__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@20973.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@20974.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@20975.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@20976.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20977.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@20980.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@20995.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@21001.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@21004.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@21011.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@21009.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21020.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21019.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21018.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21017.4] assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21016.4] assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21015.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21014.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@21013.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_sink[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_denied[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_sink__T_10_en & _T_sink__T_10_mask) begin _T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_denied__T_10_en & _T_denied__T_10_mask) begin _T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@20969.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module TLBuffer_4( // @[:freechips.rocketchip.system.TinyConfig.fir@21028.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@21029.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@21030.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@21031.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [3:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [3:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] TLMonitor_10 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@21038.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_19 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21091.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_corrupt(Queue_io_enq_bits_corrupt), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_corrupt(Queue_io_deq_bits_corrupt) ); Queue_20 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@21105.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_param(Queue_1_io_enq_bits_param), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_sink(Queue_1_io_enq_bits_sink), .io_enq_bits_denied(Queue_1_io_enq_bits_denied), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@21090.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@21089.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@21040.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@21041.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@21086.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@21092.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@21093.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@21094.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21102.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21101.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21100.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21099.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21098.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21097.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21096.4] assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21095.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@21104.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@21106.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@21107.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@21108.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21116.4] assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21115.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21114.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21113.4] assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21112.4] assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21111.4] assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21110.4] assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@21109.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@21118.4] endmodule module TLMonitor_11( // @[:freechips.rocketchip.system.TinyConfig.fir@21146.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@21147.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@21148.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@21149.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@22651.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@21166.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@21167.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@21184.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@21186.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@21187.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@21188.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@21189.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@21189.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@21190.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@21192.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@21193.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@21195.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@21196.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@21197.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@21198.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@21199.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21201.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21202.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21204.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21205.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@21206.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@21207.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@21208.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21209.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21210.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21211.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21212.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21213.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21214.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21215.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21216.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21217.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21218.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21219.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21220.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@21223.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21234.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@21262.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21265.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21266.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21267.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21268.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21269.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21270.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21271.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21272.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21273.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21274.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21275.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21276.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21277.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21278.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21279.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21282.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21283.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21284.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21285.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21286.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21287.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21288.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21289.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21290.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21291.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21292.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21293.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21294.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21295.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21296.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21297.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21298.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21299.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21300.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21301.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21302.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21303.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21310.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21323.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21324.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21331.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21332.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21338.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21339.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@21344.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21346.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21347.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@21352.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@21353.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21355.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21356.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@21361.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21363.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21364.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@21370.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@21460.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21462.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21463.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@21486.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21489.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21497.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21499.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21532.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21533.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21534.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21535.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21536.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21537.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21539.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21541.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21542.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@21561.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21563.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21564.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@21569.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21571.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21572.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@21586.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21625.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21634.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21642.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21644.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21646.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21648.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21649.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@21685.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@21775.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@21776.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@21777.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21779.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21780.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@21786.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21789.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21821.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21838.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21839.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@21858.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21860.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21861.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@21875.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@21947.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21949.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21950.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@21964.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22016.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22017.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@22055.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22057.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22058.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@22065.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@22066.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@22083.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@22085.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22088.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22089.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@22094.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22096.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22097.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@22102.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22104.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22105.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@22110.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22112.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22113.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@22118.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22120.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22121.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@22127.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@22151.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22153.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22154.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@22159.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22161.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22162.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@22185.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@22226.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22228.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22229.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@22244.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@22279.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@22315.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@22375.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@22380.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@22381.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@22382.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@22384.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22386.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22387.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@22398.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@22399.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@22400.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@22401.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@22402.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@22403.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@22404.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@22406.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22408.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22409.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@22414.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22416.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22417.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@22422.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22424.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22425.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@22430.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22432.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22433.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@22438.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22440.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22441.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@22448.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@22456.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@22458.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@22459.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@22460.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@22461.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@22462.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@22464.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22466.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22467.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@22478.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@22479.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@22480.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@22481.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@22482.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@22483.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@22484.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@22485.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@22487.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22489.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22490.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@22495.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22497.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22498.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@22503.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22505.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22506.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@22511.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22513.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22514.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@22519.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22521.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22522.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@22527.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22529.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22530.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@22537.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@22546.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@22556.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22558.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22559.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@22578.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22580.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22581.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@22596.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@22599.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@22601.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@22602.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@22603.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22605.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22606.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@22598.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@22617.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@22619.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@22620.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@22622.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@22624.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@22625.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@22626.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22628.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22629.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@22621.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@22635.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@22636.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@22637.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@22638.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22640.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22641.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@22646.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@22647.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@22648.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@22650.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@22653.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@22654.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@22655.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@22656.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@22657.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@22658.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22660.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22661.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@22667.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@22671.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21312.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@21420.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21544.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21651.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@21750.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21841.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@21930.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22019.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22091.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@22133.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@22191.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@22250.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@22285.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@22321.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@22651.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@21166.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@21167.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@21184.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@21186.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@21187.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@21188.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@21189.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@21189.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@21190.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@21192.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@21193.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@21195.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@21196.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@21197.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@21198.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@21199.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21201.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21202.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21204.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21205.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@21206.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@21207.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@21208.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21209.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21210.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21211.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21212.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21213.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21214.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21215.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21216.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21217.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@21218.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@21219.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@21220.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@21223.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21234.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@21262.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21265.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21266.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21267.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21268.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21269.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21270.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21271.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21272.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21273.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21274.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21275.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21276.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21277.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21278.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21279.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21282.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21283.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21284.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21285.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21286.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21287.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21288.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21289.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21290.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21291.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21292.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21293.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21294.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@21295.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@21296.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21297.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@21298.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@21299.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21300.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21301.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21302.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21303.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21310.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21323.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21324.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21331.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21332.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21338.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21339.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@21344.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21346.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21347.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@21352.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@21353.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21355.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21356.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@21361.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21363.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21364.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@21370.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@21460.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21462.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21463.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@21486.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21489.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21497.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21499.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21532.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21533.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21534.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21535.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@21536.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21537.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21539.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21541.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21542.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@21561.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21563.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21564.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@21569.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21571.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21572.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@21586.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21625.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21634.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21642.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21644.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@21646.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21648.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21649.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@21685.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@21775.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@21776.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@21777.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21779.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21780.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@21786.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@21789.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@21821.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21838.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21839.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@21858.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21860.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21861.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@21875.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@21947.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21949.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21950.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@21964.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22016.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22017.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@22055.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22057.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22058.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@22065.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@22066.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@22083.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@22085.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22088.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22089.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@22094.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22096.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22097.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@22102.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22104.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22105.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@22110.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22112.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22113.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@22118.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22120.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22121.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@22127.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@22151.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22153.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22154.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@22159.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22161.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22162.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@22185.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@22226.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22228.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22229.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@22244.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@22279.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@22315.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@22375.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@22380.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@22381.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@22382.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22386.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22387.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@22403.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@22404.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@22406.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22408.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22409.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@22414.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22416.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22417.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@22422.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22424.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22425.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@22430.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22432.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22433.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@22438.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22440.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22441.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@22448.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@22456.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@22458.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@22459.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@22460.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@22461.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@22462.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22466.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22467.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@22484.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@22485.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@22487.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22489.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22490.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@22495.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22497.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22498.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@22503.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22505.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22506.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@22511.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22513.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22514.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@22519.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22521.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22522.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@22527.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22529.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22530.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@22537.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22558.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22559.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@22580.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@22581.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@22596.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@22599.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@22601.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@22602.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@22603.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22605.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22606.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@22598.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@22617.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@22619.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@22620.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@22622.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@22624.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@22625.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@22626.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22628.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22629.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@22621.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@22635.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@22636.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@22637.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@22638.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22640.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22641.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@22646.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@22647.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@22648.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@22653.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@22654.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@22655.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@22656.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@22657.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@22658.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22660.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22661.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@22667.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@22671.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21312.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@21420.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21544.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21651.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@21750.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21841.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@21930.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22019.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22091.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@22133.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@22191.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@22250.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@22285.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@22321.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21312.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@21313.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@21319.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@21320.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21326.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@21327.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@21335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21341.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@21342.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21349.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@21350.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21358.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@21359.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21366.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@21367.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@21420.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@21421.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@21427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@21428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@21434.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@21435.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@21442.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@21443.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@21449.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@21450.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@21457.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@21458.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21465.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@21466.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@21474.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@21475.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@21482.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@21483.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21544.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@21545.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@21551.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@21552.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@21558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@21559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21566.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@21567.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21574.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@21575.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@21582.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@21583.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21651.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@21652.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@21658.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@21659.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@21665.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@21666.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@21673.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@21674.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@21681.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@21682.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@21750.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@21751.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@21757.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@21758.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@21764.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@21765.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@21772.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@21773.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21782.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@21783.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21841.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@21842.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@21848.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@21849.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@21855.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@21856.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21863.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@21864.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@21871.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@21872.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@21930.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@21931.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@21937.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@21938.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@21944.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@21945.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@21953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@21960.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@21961.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22019.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@22020.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@22026.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@22027.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@22033.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@22034.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@22041.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@22042.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@22049.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@22050.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22060.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@22061.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22091.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@22092.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22099.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@22100.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22107.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@22108.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22115.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@22116.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22123.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@22124.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@22133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@22134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@22140.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@22141.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@22148.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@22149.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22156.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@22157.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22164.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@22165.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@22172.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@22173.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@22191.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@22192.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@22198.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@22199.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@22206.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@22207.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@22214.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@22215.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@22222.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@22223.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@22232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@22250.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@22251.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@22258.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@22259.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@22266.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@22267.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@22285.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@22286.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@22293.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@22294.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@22302.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@22303.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@22321.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@22322.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@22329.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@22330.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@22337.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@22338.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22411.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@22412.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22419.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@22420.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22427.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@22428.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22435.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@22436.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22443.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@22444.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22492.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@22493.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22500.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@22501.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22508.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@22509.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22516.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@22517.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22524.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@22525.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22532.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@22533.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22608.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@22609.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22631.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@22632.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 6 (connected at BusWrapper.scala:164:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22643.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@22644.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22663.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@22664.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLBuffer_5( // @[:freechips.rocketchip.system.TinyConfig.fir@22804.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@22805.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@22806.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@22807.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [3:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [3:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] TLMonitor_11 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@22814.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_19 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22867.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_corrupt(Queue_io_enq_bits_corrupt), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_corrupt(Queue_io_deq_bits_corrupt) ); Queue_20 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@22881.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_param(Queue_1_io_enq_bits_param), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_sink(Queue_1_io_enq_bits_sink), .io_enq_bits_denied(Queue_1_io_enq_bits_denied), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@22866.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@22865.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@22816.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@22817.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@22862.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@22868.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@22869.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@22870.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22878.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22877.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22876.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22875.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22874.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22873.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22872.4] assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22871.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@22880.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@22882.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@22883.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@22884.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22892.4] assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22891.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22890.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22889.4] assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22888.4] assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22887.4] assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22886.4] assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@22885.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@22894.4] endmodule module TLMonitor_12( // @[:freechips.rocketchip.system.TinyConfig.fir@22922.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@22923.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@22924.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@22925.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@24427.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@22942.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@22943.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@22960.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@22962.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@22963.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@22964.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@22965.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@22965.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@22966.6] wire _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@22968.6] wire [1:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@22969.6] wire [1:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@22971.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@22972.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@22973.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@22974.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@22975.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22977.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22978.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22980.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22981.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@22982.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@22983.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@22984.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22985.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22986.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22987.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22988.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22989.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22990.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22991.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22992.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22993.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22994.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22995.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22996.6] wire [3:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@22999.6] wire [32:0] _T_72; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23010.6] wire _T_96; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@23038.6] wire [31:0] _T_98; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23041.8] wire [32:0] _T_99; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23042.8] wire [32:0] _T_100; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23043.8] wire [32:0] _T_101; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23044.8] wire _T_102; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23045.8] wire [31:0] _T_103; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23046.8] wire [32:0] _T_104; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23047.8] wire [32:0] _T_105; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23048.8] wire [32:0] _T_106; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23049.8] wire _T_107; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23050.8] wire [31:0] _T_108; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23051.8] wire [32:0] _T_109; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23052.8] wire [32:0] _T_110; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23053.8] wire [32:0] _T_111; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23054.8] wire _T_112; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23055.8] wire [32:0] _T_115; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23058.8] wire [32:0] _T_116; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23059.8] wire _T_117; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23060.8] wire [31:0] _T_118; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23061.8] wire [32:0] _T_119; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23062.8] wire [32:0] _T_120; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23063.8] wire [32:0] _T_121; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23064.8] wire _T_122; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23065.8] wire [31:0] _T_123; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23066.8] wire [32:0] _T_124; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23067.8] wire [32:0] _T_125; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23068.8] wire [32:0] _T_126; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23069.8] wire _T_127; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23070.8] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23071.8] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23072.8] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23073.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23074.8] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23075.8] wire _T_133; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23076.8] wire _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23077.8] wire _T_135; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23078.8] wire _T_136; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23079.8] wire _T_143; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23086.8] wire _T_148; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23099.8] wire _T_149; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23100.8] wire _T_152; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23107.8] wire _T_153; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23108.8] wire _T_155; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23114.8] wire _T_156; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23115.8] wire _T_157; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@23120.8] wire _T_159; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23122.8] wire _T_160; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23123.8] wire [3:0] _T_161; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@23128.8] wire _T_162; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@23129.8] wire _T_164; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23131.8] wire _T_165; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23132.8] wire _T_166; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@23137.8] wire _T_168; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23139.8] wire _T_169; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23140.8] wire _T_170; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@23146.6] wire _T_235; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@23236.8] wire _T_237; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23238.8] wire _T_238; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23239.8] wire _T_248; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@23262.6] wire _T_250; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23265.8] wire _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23273.8] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23275.8] wire _T_293; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23308.8] wire _T_294; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23309.8] wire _T_295; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23310.8] wire _T_296; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23311.8] wire _T_297; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23312.8] wire _T_298; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23313.8] wire _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23315.8] wire _T_302; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23317.8] wire _T_303; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23318.8] wire _T_310; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@23337.8] wire _T_312; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23339.8] wire _T_313; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23340.8] wire _T_314; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@23345.8] wire _T_316; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23347.8] wire _T_317; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23348.8] wire _T_322; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@23362.6] wire _T_360; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23401.8] wire _T_369; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23410.8] wire _T_377; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23418.8] wire _T_379; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23420.8] wire _T_381; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23422.8] wire _T_383; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23424.8] wire _T_384; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23425.8] wire _T_399; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@23461.6] wire [3:0] _T_472; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@23551.8] wire [3:0] _T_473; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@23552.8] wire _T_474; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@23553.8] wire _T_476; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23555.8] wire _T_477; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23556.8] wire _T_478; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@23562.6] wire _T_480; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23565.8] wire _T_512; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23597.8] wire _T_529; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23614.8] wire _T_530; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23615.8] wire _T_537; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@23634.8] wire _T_539; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23636.8] wire _T_540; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23637.8] wire _T_545; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@23651.6] wire _T_604; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@23723.8] wire _T_606; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23725.8] wire _T_607; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23726.8] wire _T_612; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@23740.6] wire _T_663; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23792.8] wire _T_664; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23793.8] wire _T_679; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@23831.6] wire _T_681; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23833.6] wire _T_682; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23834.6] wire _T_685; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@23841.6] wire _T_686; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@23842.6] wire _T_700; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@23859.6] wire _T_702; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@23861.6] wire _T_704; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23864.8] wire _T_705; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23865.8] wire _T_706; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@23870.8] wire _T_708; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23872.8] wire _T_709; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23873.8] wire _T_710; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@23878.8] wire _T_712; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23880.8] wire _T_713; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23881.8] wire _T_714; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@23886.8] wire _T_716; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23888.8] wire _T_717; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23889.8] wire _T_718; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@23894.8] wire _T_720; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23896.8] wire _T_721; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23897.8] wire _T_722; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@23903.6] wire _T_733; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@23927.8] wire _T_735; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23929.8] wire _T_736; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23930.8] wire _T_737; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@23935.8] wire _T_739; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23937.8] wire _T_740; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23938.8] wire _T_750; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@23961.6] wire _T_770; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@24002.8] wire _T_772; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24004.8] wire _T_773; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24005.8] wire _T_779; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@24020.6] wire _T_796; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@24055.6] wire _T_814; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@24091.6] wire _T_843; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@24151.4] wire [9:0] _T_848; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24156.4] wire _T_849; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@24157.4] wire _T_850; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@24158.4] reg [9:0] _T_852; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24160.4] reg [31:0] _RAND_0; wire [9:0] _T_854; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24162.4] wire _T_855; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24163.4] reg [2:0] _T_863; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@24174.4] reg [31:0] _RAND_1; reg [2:0] _T_864; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@24175.4] reg [31:0] _RAND_2; reg [3:0] _T_865; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@24176.4] reg [31:0] _RAND_3; reg [3:0] _T_866; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@24177.4] reg [31:0] _RAND_4; reg [31:0] _T_867; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@24178.4] reg [31:0] _RAND_5; wire _T_868; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@24179.4] wire _T_869; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@24180.4] wire _T_870; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@24182.6] wire _T_872; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24184.6] wire _T_873; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24185.6] wire _T_874; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@24190.6] wire _T_876; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24192.6] wire _T_877; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24193.6] wire _T_878; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@24198.6] wire _T_880; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24200.6] wire _T_881; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24201.6] wire _T_882; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@24206.6] wire _T_884; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24208.6] wire _T_885; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24209.6] wire _T_886; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@24214.6] wire _T_888; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24216.6] wire _T_889; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24217.6] wire _T_891; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@24224.4] wire _T_892; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@24232.4] wire [26:0] _T_894; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24234.4] wire [11:0] _T_895; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24235.4] wire [11:0] _T_896; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24236.4] wire [9:0] _T_897; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24237.4] wire _T_898; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@24238.4] reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24240.4] reg [31:0] _RAND_6; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24242.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24243.4] reg [2:0] _T_911; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@24254.4] reg [31:0] _RAND_7; reg [1:0] _T_912; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@24255.4] reg [31:0] _RAND_8; reg [3:0] _T_913; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@24256.4] reg [31:0] _RAND_9; reg [3:0] _T_914; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@24257.4] reg [31:0] _RAND_10; reg _T_915; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@24258.4] reg [31:0] _RAND_11; reg _T_916; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@24259.4] reg [31:0] _RAND_12; wire _T_917; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@24260.4] wire _T_918; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@24261.4] wire _T_919; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@24263.6] wire _T_921; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24265.6] wire _T_922; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24266.6] wire _T_923; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@24271.6] wire _T_925; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24273.6] wire _T_926; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24274.6] wire _T_927; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@24279.6] wire _T_929; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24281.6] wire _T_930; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24282.6] wire _T_931; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@24287.6] wire _T_933; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24289.6] wire _T_934; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24290.6] wire _T_935; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@24295.6] wire _T_937; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24297.6] wire _T_938; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24298.6] wire _T_939; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@24303.6] wire _T_941; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24305.6] wire _T_942; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24306.6] wire _T_944; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@24313.4] reg [15:0] _T_945; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@24322.4] reg [31:0] _RAND_13; reg [9:0] _T_955; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24332.4] reg [31:0] _RAND_14; wire [9:0] _T_957; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24334.4] wire _T_958; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24335.4] reg [9:0] _T_974; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24354.4] reg [31:0] _RAND_15; wire [9:0] _T_976; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24356.4] wire _T_977; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24357.4] wire _T_987; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@24372.4] wire [15:0] _T_989; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@24375.6] wire [15:0] _T_990; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@24377.6] wire _T_991; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@24378.6] wire _T_992; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@24379.6] wire _T_994; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24381.6] wire _T_995; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24382.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@24374.4] wire _T_999; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@24393.4] wire _T_1001; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@24395.4] wire _T_1002; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@24396.4] wire [15:0] _T_1003; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@24398.6] wire [15:0] _T_1004; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@24400.6] wire [15:0] _T_1005; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@24401.6] wire _T_1006; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@24402.6] wire _T_1008; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24404.6] wire _T_1009; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24405.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@24397.4] wire _T_1010; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@24411.4] wire _T_1011; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@24412.4] wire _T_1012; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@24413.4] wire _T_1013; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@24414.4] wire _T_1015; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24416.4] wire _T_1016; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24417.4] wire [15:0] _T_1017; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@24422.4] wire [15:0] _T_1018; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@24423.4] wire [15:0] _T_1019; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@24424.4] reg [31:0] _T_1020; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@24426.4] reg [31:0] _RAND_16; wire _T_1021; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@24429.4] wire _T_1022; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@24430.4] wire _T_1023; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@24431.4] wire _T_1024; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@24432.4] wire _T_1025; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@24433.4] wire _T_1026; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@24434.4] wire _T_1028; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24436.4] wire _T_1029; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24437.4] wire [31:0] _T_1031; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@24443.4] wire _T_1034; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@24447.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23088.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@23196.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23320.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23427.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@23526.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23617.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@23706.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23795.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23867.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@23909.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@23967.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@24026.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@24061.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@24097.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@24427.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@22942.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@22943.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@22960.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@22962.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@22963.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@22964.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@22965.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@22965.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@22966.6] assign _T_30 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@22968.6] assign _T_31 = 2'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@22969.6] assign _T_33 = _T_31 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@22971.6] assign _T_34 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@22972.6] assign _T_35 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@22973.6] assign _T_36 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@22974.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@22975.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22977.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22978.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22980.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22981.6] assign _T_44 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@22982.6] assign _T_45 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@22983.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@22984.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22985.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22986.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22987.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22988.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22989.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22990.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22991.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22992.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22993.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@22994.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@22995.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@22996.6] assign _T_61 = {_T_58,_T_55,_T_52,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@22999.6] assign _T_72 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23010.6] assign _T_96 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@23038.6] assign _T_98 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23041.8] assign _T_99 = {1'b0,$signed(_T_98)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23042.8] assign _T_100 = $signed(_T_99) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23043.8] assign _T_101 = $signed(_T_100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23044.8] assign _T_102 = $signed(_T_101) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23045.8] assign _T_103 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23046.8] assign _T_104 = {1'b0,$signed(_T_103)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23047.8] assign _T_105 = $signed(_T_104) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23048.8] assign _T_106 = $signed(_T_105); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23049.8] assign _T_107 = $signed(_T_106) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23050.8] assign _T_108 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23051.8] assign _T_109 = {1'b0,$signed(_T_108)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23052.8] assign _T_110 = $signed(_T_109) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23053.8] assign _T_111 = $signed(_T_110); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23054.8] assign _T_112 = $signed(_T_111) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23055.8] assign _T_115 = $signed(_T_72) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23058.8] assign _T_116 = $signed(_T_115); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23059.8] assign _T_117 = $signed(_T_116) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23060.8] assign _T_118 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23061.8] assign _T_119 = {1'b0,$signed(_T_118)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23062.8] assign _T_120 = $signed(_T_119) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23063.8] assign _T_121 = $signed(_T_120); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23064.8] assign _T_122 = $signed(_T_121) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23065.8] assign _T_123 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23066.8] assign _T_124 = {1'b0,$signed(_T_123)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23067.8] assign _T_125 = $signed(_T_124) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23068.8] assign _T_126 = $signed(_T_125); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23069.8] assign _T_127 = $signed(_T_126) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23070.8] assign _T_128 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@23071.8] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@23072.8] assign _T_130 = $signed(_T_129) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23073.8] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@23074.8] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@23075.8] assign _T_133 = _T_102 | _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23076.8] assign _T_134 = _T_133 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23077.8] assign _T_135 = _T_134 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23078.8] assign _T_136 = _T_135 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23079.8] assign _T_143 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23086.8] assign _T_148 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23099.8] assign _T_149 = _T_148 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23100.8] assign _T_152 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23107.8] assign _T_153 = _T_152 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23108.8] assign _T_155 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23114.8] assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23115.8] assign _T_157 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@23120.8] assign _T_159 = _T_157 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23122.8] assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23123.8] assign _T_161 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@23128.8] assign _T_162 = _T_161 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@23129.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23131.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23132.8] assign _T_166 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@23137.8] assign _T_168 = _T_166 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23139.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23140.8] assign _T_170 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@23146.6] assign _T_235 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@23236.8] assign _T_237 = _T_235 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23238.8] assign _T_238 = _T_237 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23239.8] assign _T_248 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@23262.6] assign _T_250 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23265.8] assign _T_258 = _T_250 & _T_102; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23273.8] assign _T_260 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23275.8] assign _T_293 = _T_107 | _T_112; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23308.8] assign _T_294 = _T_293 | _T_117; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23309.8] assign _T_295 = _T_294 | _T_122; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23310.8] assign _T_296 = _T_295 | _T_127; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23311.8] assign _T_297 = _T_296 | _T_132; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@23312.8] assign _T_298 = _T_260 & _T_297; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23313.8] assign _T_300 = _T_258 | _T_298; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23315.8] assign _T_302 = _T_300 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23317.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23318.8] assign _T_310 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@23337.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23339.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23340.8] assign _T_314 = io_in_a_bits_mask == _T_61; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@23345.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23347.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23348.8] assign _T_322 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@23362.6] assign _T_360 = _T_260 & _T_295; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23401.8] assign _T_369 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23410.8] assign _T_377 = _T_369 & _T_132; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23418.8] assign _T_379 = _T_258 | _T_360; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23420.8] assign _T_381 = _T_379 | _T_377; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@23422.8] assign _T_383 = _T_381 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23424.8] assign _T_384 = _T_383 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23425.8] assign _T_399 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@23461.6] assign _T_472 = ~ _T_61; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@23551.8] assign _T_473 = io_in_a_bits_mask & _T_472; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@23552.8] assign _T_474 = _T_473 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@23553.8] assign _T_476 = _T_474 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23555.8] assign _T_477 = _T_476 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23556.8] assign _T_478 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@23562.6] assign _T_480 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@23565.8] assign _T_512 = _T_480 & _T_136; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@23597.8] assign _T_529 = _T_512 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23614.8] assign _T_530 = _T_529 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23615.8] assign _T_537 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@23634.8] assign _T_539 = _T_537 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23636.8] assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23637.8] assign _T_545 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@23651.6] assign _T_604 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@23723.8] assign _T_606 = _T_604 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23725.8] assign _T_607 = _T_606 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23726.8] assign _T_612 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@23740.6] assign _T_663 = _T_258 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23792.8] assign _T_664 = _T_663 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23793.8] assign _T_679 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@23831.6] assign _T_681 = _T_679 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23833.6] assign _T_682 = _T_681 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23834.6] assign _T_685 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@23841.6] assign _T_686 = _T_685 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@23842.6] assign _T_700 = _T_686 | _T_685; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@23859.6] assign _T_702 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@23861.6] assign _T_704 = _T_700 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23864.8] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23865.8] assign _T_706 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@23870.8] assign _T_708 = _T_706 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23872.8] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23873.8] assign _T_710 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@23878.8] assign _T_712 = _T_710 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23880.8] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23881.8] assign _T_714 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@23886.8] assign _T_716 = _T_714 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23888.8] assign _T_717 = _T_716 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23889.8] assign _T_718 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@23894.8] assign _T_720 = _T_718 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23896.8] assign _T_721 = _T_720 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23897.8] assign _T_722 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@23903.6] assign _T_733 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@23927.8] assign _T_735 = _T_733 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23929.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23930.8] assign _T_737 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@23935.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23937.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23938.8] assign _T_750 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@23961.6] assign _T_770 = _T_718 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@24002.8] assign _T_772 = _T_770 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24004.8] assign _T_773 = _T_772 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24005.8] assign _T_779 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@24020.6] assign _T_796 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@24055.6] assign _T_814 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@24091.6] assign _T_843 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@24151.4] assign _T_848 = _T_26[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24156.4] assign _T_849 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@24157.4] assign _T_850 = _T_849 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@24158.4] assign _T_854 = _T_852 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24162.4] assign _T_855 = _T_852 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24163.4] assign _T_868 = _T_855 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@24179.4] assign _T_869 = io_in_a_valid & _T_868; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@24180.4] assign _T_870 = io_in_a_bits_opcode == _T_863; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@24182.6] assign _T_872 = _T_870 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24184.6] assign _T_873 = _T_872 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24185.6] assign _T_874 = io_in_a_bits_param == _T_864; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@24190.6] assign _T_876 = _T_874 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24192.6] assign _T_877 = _T_876 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24193.6] assign _T_878 = io_in_a_bits_size == _T_865; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@24198.6] assign _T_880 = _T_878 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24200.6] assign _T_881 = _T_880 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24201.6] assign _T_882 = io_in_a_bits_source == _T_866; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@24206.6] assign _T_884 = _T_882 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24208.6] assign _T_885 = _T_884 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24209.6] assign _T_886 = io_in_a_bits_address == _T_867; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@24214.6] assign _T_888 = _T_886 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24216.6] assign _T_889 = _T_888 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24217.6] assign _T_891 = _T_843 & _T_855; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@24224.4] assign _T_892 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@24232.4] assign _T_894 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24234.4] assign _T_895 = _T_894[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24235.4] assign _T_896 = ~ _T_895; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24236.4] assign _T_897 = _T_896[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24237.4] assign _T_898 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@24238.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24242.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24243.4] assign _T_917 = _T_903 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@24260.4] assign _T_918 = io_in_d_valid & _T_917; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@24261.4] assign _T_919 = io_in_d_bits_opcode == _T_911; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@24263.6] assign _T_921 = _T_919 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24265.6] assign _T_922 = _T_921 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24266.6] assign _T_923 = io_in_d_bits_param == _T_912; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@24271.6] assign _T_925 = _T_923 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24273.6] assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24274.6] assign _T_927 = io_in_d_bits_size == _T_913; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@24279.6] assign _T_929 = _T_927 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24281.6] assign _T_930 = _T_929 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24282.6] assign _T_931 = io_in_d_bits_source == _T_914; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@24287.6] assign _T_933 = _T_931 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24289.6] assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24290.6] assign _T_935 = io_in_d_bits_sink == _T_915; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@24295.6] assign _T_937 = _T_935 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24297.6] assign _T_938 = _T_937 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24298.6] assign _T_939 = io_in_d_bits_denied == _T_916; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@24303.6] assign _T_941 = _T_939 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24305.6] assign _T_942 = _T_941 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24306.6] assign _T_944 = _T_892 & _T_903; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@24313.4] assign _T_957 = _T_955 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24334.4] assign _T_958 = _T_955 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24335.4] assign _T_976 = _T_974 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24356.4] assign _T_977 = _T_974 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24357.4] assign _T_987 = _T_843 & _T_958; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@24372.4] assign _T_989 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@24375.6] assign _T_990 = _T_945 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@24377.6] assign _T_991 = _T_990[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@24378.6] assign _T_992 = _T_991 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@24379.6] assign _T_994 = _T_992 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24381.6] assign _T_995 = _T_994 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24382.6] assign _GEN_15 = _T_987 ? _T_989 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@24374.4] assign _T_999 = _T_892 & _T_977; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@24393.4] assign _T_1001 = _T_702 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@24395.4] assign _T_1002 = _T_999 & _T_1001; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@24396.4] assign _T_1003 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@24398.6] assign _T_1004 = _GEN_15 | _T_945; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@24400.6] assign _T_1005 = _T_1004 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@24401.6] assign _T_1006 = _T_1005[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@24402.6] assign _T_1008 = _T_1006 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24404.6] assign _T_1009 = _T_1008 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24405.6] assign _GEN_16 = _T_1002 ? _T_1003 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@24397.4] assign _T_1010 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@24411.4] assign _T_1011 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@24412.4] assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@24413.4] assign _T_1013 = _T_1010 | _T_1012; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@24414.4] assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24416.4] assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24417.4] assign _T_1017 = _T_945 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@24422.4] assign _T_1018 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@24423.4] assign _T_1019 = _T_1017 & _T_1018; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@24424.4] assign _T_1021 = _T_945 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@24429.4] assign _T_1022 = _T_1021 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@24430.4] assign _T_1023 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@24431.4] assign _T_1024 = _T_1022 | _T_1023; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@24432.4] assign _T_1025 = _T_1020 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@24433.4] assign _T_1026 = _T_1024 | _T_1025; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@24434.4] assign _T_1028 = _T_1026 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24436.4] assign _T_1029 = _T_1028 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24437.4] assign _T_1031 = _T_1020 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@24443.4] assign _T_1034 = _T_843 | _T_892; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@24447.4] assign _GEN_19 = io_in_a_valid & _T_96; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23088.10] assign _GEN_35 = io_in_a_valid & _T_170; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@23196.10] assign _GEN_53 = io_in_a_valid & _T_248; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23320.10] assign _GEN_65 = io_in_a_valid & _T_322; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23427.10] assign _GEN_75 = io_in_a_valid & _T_399; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@23526.10] assign _GEN_85 = io_in_a_valid & _T_478; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23617.10] assign _GEN_95 = io_in_a_valid & _T_545; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@23706.10] assign _GEN_105 = io_in_a_valid & _T_612; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23795.10] assign _GEN_115 = io_in_d_valid & _T_702; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23867.10] assign _GEN_125 = io_in_d_valid & _T_722; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@23909.10] assign _GEN_137 = io_in_d_valid & _T_750; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@23967.10] assign _GEN_149 = io_in_d_valid & _T_779; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@24026.10] assign _GEN_155 = io_in_d_valid & _T_796; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@24061.10] assign _GEN_161 = io_in_d_valid & _T_814; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@24097.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_852 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_863 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_864 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_865 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_866 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_867 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_900 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_911 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_912 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_913 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_914 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_915 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_916 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_945 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_955 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_974 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1020 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_852 <= 10'h0; end else begin if (_T_843) begin if (_T_855) begin if (_T_850) begin _T_852 <= _T_848; end else begin _T_852 <= 10'h0; end end else begin _T_852 <= _T_854; end end end if (_T_891) begin _T_863 <= io_in_a_bits_opcode; end if (_T_891) begin _T_864 <= io_in_a_bits_param; end if (_T_891) begin _T_865 <= io_in_a_bits_size; end if (_T_891) begin _T_866 <= io_in_a_bits_source; end if (_T_891) begin _T_867 <= io_in_a_bits_address; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_892) begin if (_T_903) begin if (_T_898) begin _T_900 <= _T_897; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (_T_944) begin _T_911 <= io_in_d_bits_opcode; end if (_T_944) begin _T_912 <= io_in_d_bits_param; end if (_T_944) begin _T_913 <= io_in_d_bits_size; end if (_T_944) begin _T_914 <= io_in_d_bits_source; end if (_T_944) begin _T_915 <= io_in_d_bits_sink; end if (_T_944) begin _T_916 <= io_in_d_bits_denied; end if (reset) begin _T_945 <= 16'h0; end else begin _T_945 <= _T_1019; end if (reset) begin _T_955 <= 10'h0; end else begin if (_T_843) begin if (_T_958) begin if (_T_850) begin _T_955 <= _T_848; end else begin _T_955 <= 10'h0; end end else begin _T_955 <= _T_957; end end end if (reset) begin _T_974 <= 10'h0; end else begin if (_T_892) begin if (_T_977) begin if (_T_898) begin _T_974 <= _T_897; end else begin _T_974 <= 10'h0; end end else begin _T_974 <= _T_976; end end end if (reset) begin _T_1020 <= 32'h0; end else begin if (_T_1034) begin _T_1020 <= 32'h0; end else begin _T_1020 <= _T_1031; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23088.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@23089.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:72)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@23095.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_143) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@23096.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23102.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_149) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@23103.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23110.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_153) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@23111.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23117.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_156) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@23118.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_160) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@23126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23134.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@23135.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23142.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@23143.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@23196.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@23197.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:72)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@23203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_143) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@23204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@23210.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_149) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@23211.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_153) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@23218.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_153) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@23219.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@23225.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_156) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@23226.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_160) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@23233.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_160) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@23234.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_238) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:72)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23241.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_238) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@23242.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@23250.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@23251.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@23258.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@23259.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23320.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_303) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@23321.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@23327.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_149) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@23328.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@23334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_156) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@23335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23342.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_313) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@23343.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23350.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@23351.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@23358.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_169) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@23359.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_384) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@23428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@23434.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_149) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@23435.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@23441.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_156) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@23442.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@23449.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_313) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@23450.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@23457.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@23458.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_384) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@23526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_384) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@23527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@23533.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_149) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@23534.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@23540.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_156) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@23541.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@23548.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_313) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@23549.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_477) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_477) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@23559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23617.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_530) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@23618.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@23624.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_149) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@23625.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@23631.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_156) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@23632.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_540) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23639.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_540) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@23640.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@23647.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_317) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@23648.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_530) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@23706.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_530) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@23707.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@23713.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_149) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@23714.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@23720.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_156) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@23721.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_607) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23728.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_607) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@23729.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@23736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_317) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@23737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_664) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23795.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_664) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@23796.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_149) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@23802.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_149) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@23803.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_156) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@23809.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_156) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@23810.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@23817.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_317) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@23818.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@23825.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_169) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@23826.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_682) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:72)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23836.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_682) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@23837.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23867.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_705) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@23868.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23875.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_709) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@23876.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23883.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_713) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@23884.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23891.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_717) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@23892.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_721) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23899.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_721) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@23900.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@23909.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_705) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@23910.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@23916.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_143) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@23917.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@23924.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_709) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@23925.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23932.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@23933.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23940.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@23941.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@23948.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_717) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@23949.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@23967.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_705) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@23968.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_143) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@23974.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_143) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@23975.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_709) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@23982.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_709) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@23983.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@23990.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@23991.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@23998.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@23999.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24007.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_773) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@24008.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@24026.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_705) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@24027.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@24034.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_713) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@24035.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@24042.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_717) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@24043.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@24061.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_705) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@24062.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@24069.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_713) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@24070.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_773) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@24078.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_773) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@24079.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@24097.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_705) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@24098.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@24105.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_713) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@24106.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_717) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@24113.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_717) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@24114.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_873) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24187.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_873) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@24188.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_877) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24195.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_877) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@24196.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_881) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24203.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_881) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@24204.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_885) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24211.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_885) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@24212.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869 & _T_889) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24219.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869 & _T_889) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@24220.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_922) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24268.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_922) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@24269.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_926) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24276.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_926) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@24277.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_930) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24284.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_930) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@24285.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_934) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24292.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_934) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@24293.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_938) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24300.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_938) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@24301.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_918 & _T_942) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24308.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_918 & _T_942) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@24309.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987 & _T_995) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24384.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987 & _T_995) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@24385.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1002 & _T_1009) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:72)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24407.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1002 & _T_1009) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@24408.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1016) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 6 (connected at BusWrapper.scala:164:72)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24419.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1016) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@24420.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1029) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:72)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24439.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1029) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@24440.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLFIFOFixer_2( // @[:freechips.rocketchip.system.TinyConfig.fir@24452.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@24453.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@24454.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@24455.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] wire [32:0] _T_15; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24516.4] wire [32:0] _T_21; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24522.4] wire [32:0] _T_22; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24523.4] wire _T_23; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24524.4] wire [31:0] _T_24; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24525.4] wire [32:0] _T_25; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24526.4] wire [32:0] _T_26; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24527.4] wire [32:0] _T_27; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24528.4] wire _T_28; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24529.4] wire [1:0] _T_30; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24531.4] wire [1:0] _GEN_70; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24532.4] wire [1:0] _T_31; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24532.4] wire _T_33; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.TinyConfig.fir@24535.4] wire _T_84; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@24615.4] wire _T_85; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@24616.4] reg [9:0] _T_43; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24545.4] reg [31:0] _RAND_0; wire _T_46; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24548.4] wire _T_95; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@24629.4] reg _T_76_0; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_1; reg _T_76_1; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_2; wire _T_96; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24630.4] reg _T_76_2; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_3; wire _T_97; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24631.4] reg _T_76_3; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_4; wire _T_98; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24632.4] reg _T_76_4; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_5; wire _T_99; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24633.4] reg _T_76_5; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_6; wire _T_100; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24634.4] reg _T_76_6; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_7; wire _T_101; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24635.4] reg _T_76_7; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_8; wire _T_102; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24636.4] wire _T_103; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@24637.4] reg [1:0] _T_94; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@24625.4] reg [31:0] _RAND_9; wire _T_104; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@24638.4] wire _T_105; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@24639.4] wire _T_106; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@24640.4] wire _T_120; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@24657.4] reg _T_76_8; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_10; reg _T_76_9; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_11; wire _T_121; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24658.4] reg _T_76_10; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_12; wire _T_122; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24659.4] reg _T_76_11; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_13; wire _T_123; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24660.4] reg _T_76_12; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_14; wire _T_124; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24661.4] reg _T_76_13; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_15; wire _T_125; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24662.4] reg _T_76_14; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_16; wire _T_126; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24663.4] reg _T_76_15; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@24601.4] reg [31:0] _RAND_17; wire _T_127; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24664.4] wire _T_128; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@24665.4] reg [1:0] _T_119; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@24653.4] reg [31:0] _RAND_18; wire _T_129; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@24666.4] wire _T_130; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@24667.4] wire _T_131; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@24668.4] wire _T_133; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.TinyConfig.fir@24670.4] wire _T_137; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.TinyConfig.fir@24677.4] wire _T_139; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.TinyConfig.fir@24679.4] wire _T_34; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@24536.4] wire [26:0] _T_36; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24538.4] wire [11:0] _T_37; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24539.4] wire [11:0] _T_38; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24540.4] wire [9:0] _T_39; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24541.4] wire _T_40; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@24542.4] wire _T_41; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@24543.4] wire [9:0] _T_45; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24547.4] wire _T_54; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@24559.4] wire [26:0] _T_56; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24561.4] wire [11:0] _T_57; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24562.4] wire [11:0] _T_58; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24563.4] wire [9:0] _T_59; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24564.4] wire _T_60; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@24565.4] reg [9:0] _T_62; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@24567.4] reg [31:0] _RAND_19; wire [9:0] _T_64; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24569.4] wire _T_65; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24570.4] wire _T_73; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.TinyConfig.fir@24581.4] wire _T_74; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.TinyConfig.fir@24582.4] wire _T_78; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.TinyConfig.fir@24603.4] wire _T_81; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.TinyConfig.fir@24609.4] wire _T_91; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@24622.4] wire _T_116; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@24650.4] TLMonitor_12 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@24462.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign _T_15 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24516.4] assign _T_21 = $signed(_T_15) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24522.4] assign _T_22 = $signed(_T_21); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24523.4] assign _T_23 = $signed(_T_22) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24524.4] assign _T_24 = auto_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24525.4] assign _T_25 = {1'b0,$signed(_T_24)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24526.4] assign _T_26 = $signed(_T_25) & $signed(33'sh40000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24527.4] assign _T_27 = $signed(_T_26); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24528.4] assign _T_28 = $signed(_T_27) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24529.4] assign _T_30 = _T_28 ? 2'h2 : 2'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24531.4] assign _GEN_70 = {{1'd0}, _T_23}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24532.4] assign _T_31 = _GEN_70 | _T_30; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@24532.4] assign _T_33 = _T_31 == 2'h0; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.TinyConfig.fir@24535.4] assign _T_84 = auto_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@24615.4] assign _T_85 = _T_84 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@24616.4] assign _T_46 = _T_43 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24548.4] assign _T_95 = _T_85 & _T_46; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@24629.4] assign _T_96 = _T_76_0 | _T_76_1; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24630.4] assign _T_97 = _T_96 | _T_76_2; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24631.4] assign _T_98 = _T_97 | _T_76_3; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24632.4] assign _T_99 = _T_98 | _T_76_4; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24633.4] assign _T_100 = _T_99 | _T_76_5; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24634.4] assign _T_101 = _T_100 | _T_76_6; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24635.4] assign _T_102 = _T_101 | _T_76_7; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24636.4] assign _T_103 = _T_95 & _T_102; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@24637.4] assign _T_104 = _T_94 != _T_31; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@24638.4] assign _T_105 = _T_33 | _T_104; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@24639.4] assign _T_106 = _T_103 & _T_105; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@24640.4] assign _T_120 = _T_84 & _T_46; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@24657.4] assign _T_121 = _T_76_8 | _T_76_9; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24658.4] assign _T_122 = _T_121 | _T_76_10; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24659.4] assign _T_123 = _T_122 | _T_76_11; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24660.4] assign _T_124 = _T_123 | _T_76_12; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24661.4] assign _T_125 = _T_124 | _T_76_13; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24662.4] assign _T_126 = _T_125 | _T_76_14; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24663.4] assign _T_127 = _T_126 | _T_76_15; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@24664.4] assign _T_128 = _T_120 & _T_127; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@24665.4] assign _T_129 = _T_119 != _T_31; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@24666.4] assign _T_130 = _T_33 | _T_129; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@24667.4] assign _T_131 = _T_128 & _T_130; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@24668.4] assign _T_133 = _T_106 | _T_131; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.TinyConfig.fir@24670.4] assign _T_137 = _T_133 == 1'h0; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.TinyConfig.fir@24677.4] assign _T_139 = auto_out_a_ready & _T_137; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.TinyConfig.fir@24679.4] assign _T_34 = _T_139 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@24536.4] assign _T_36 = 27'hfff << auto_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24538.4] assign _T_37 = _T_36[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24539.4] assign _T_38 = ~ _T_37; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24540.4] assign _T_39 = _T_38[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24541.4] assign _T_40 = auto_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@24542.4] assign _T_41 = _T_40 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@24543.4] assign _T_45 = _T_43 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24547.4] assign _T_54 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@24559.4] assign _T_56 = 27'hfff << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24561.4] assign _T_57 = _T_56[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24562.4] assign _T_58 = ~ _T_57; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24563.4] assign _T_59 = _T_58[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@24564.4] assign _T_60 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@24565.4] assign _T_64 = _T_62 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@24569.4] assign _T_65 = _T_62 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@24570.4] assign _T_73 = auto_out_d_bits_opcode != 3'h6; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.TinyConfig.fir@24581.4] assign _T_74 = _T_65 & _T_73; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.TinyConfig.fir@24582.4] assign _T_78 = _T_46 & _T_34; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.TinyConfig.fir@24603.4] assign _T_81 = _T_74 & _T_54; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.TinyConfig.fir@24609.4] assign _T_91 = _T_34 & _T_85; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@24622.4] assign _T_116 = _T_34 & _T_84; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@24650.4] assign auto_in_a_ready = auto_out_a_ready & _T_137; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@24514.4] assign auto_out_a_valid = auto_in_a_valid & _T_137; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@24513.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@24464.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@24465.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready & _T_137; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@24510.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_43 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_76_0 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_76_1 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_76_2 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_76_3 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_76_4 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_76_5 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_76_6 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_76_7 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_94 = _RAND_9[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_76_8 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_76_9 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_76_10 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_76_11 = _RAND_13[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_76_12 = _RAND_14[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_76_13 = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_76_14 = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; _T_76_15 = _RAND_17[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; _T_119 = _RAND_18[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; _T_62 = _RAND_19[9:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_43 <= 10'h0; end else begin if (_T_34) begin if (_T_46) begin if (_T_41) begin _T_43 <= _T_39; end else begin _T_43 <= 10'h0; end end else begin _T_43 <= _T_45; end end end if (reset) begin _T_76_0 <= 1'h0; end else begin if (_T_81) begin if (4'h0 == auto_out_d_bits_source) begin _T_76_0 <= 1'h0; end else begin if (_T_78) begin if (4'h0 == auto_in_a_bits_source) begin _T_76_0 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h0 == auto_in_a_bits_source) begin _T_76_0 <= 1'h1; end end end end if (reset) begin _T_76_1 <= 1'h0; end else begin if (_T_81) begin if (4'h1 == auto_out_d_bits_source) begin _T_76_1 <= 1'h0; end else begin if (_T_78) begin if (4'h1 == auto_in_a_bits_source) begin _T_76_1 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h1 == auto_in_a_bits_source) begin _T_76_1 <= 1'h1; end end end end if (reset) begin _T_76_2 <= 1'h0; end else begin if (_T_81) begin if (4'h2 == auto_out_d_bits_source) begin _T_76_2 <= 1'h0; end else begin if (_T_78) begin if (4'h2 == auto_in_a_bits_source) begin _T_76_2 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h2 == auto_in_a_bits_source) begin _T_76_2 <= 1'h1; end end end end if (reset) begin _T_76_3 <= 1'h0; end else begin if (_T_81) begin if (4'h3 == auto_out_d_bits_source) begin _T_76_3 <= 1'h0; end else begin if (_T_78) begin if (4'h3 == auto_in_a_bits_source) begin _T_76_3 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h3 == auto_in_a_bits_source) begin _T_76_3 <= 1'h1; end end end end if (reset) begin _T_76_4 <= 1'h0; end else begin if (_T_81) begin if (4'h4 == auto_out_d_bits_source) begin _T_76_4 <= 1'h0; end else begin if (_T_78) begin if (4'h4 == auto_in_a_bits_source) begin _T_76_4 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h4 == auto_in_a_bits_source) begin _T_76_4 <= 1'h1; end end end end if (reset) begin _T_76_5 <= 1'h0; end else begin if (_T_81) begin if (4'h5 == auto_out_d_bits_source) begin _T_76_5 <= 1'h0; end else begin if (_T_78) begin if (4'h5 == auto_in_a_bits_source) begin _T_76_5 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h5 == auto_in_a_bits_source) begin _T_76_5 <= 1'h1; end end end end if (reset) begin _T_76_6 <= 1'h0; end else begin if (_T_81) begin if (4'h6 == auto_out_d_bits_source) begin _T_76_6 <= 1'h0; end else begin if (_T_78) begin if (4'h6 == auto_in_a_bits_source) begin _T_76_6 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h6 == auto_in_a_bits_source) begin _T_76_6 <= 1'h1; end end end end if (reset) begin _T_76_7 <= 1'h0; end else begin if (_T_81) begin if (4'h7 == auto_out_d_bits_source) begin _T_76_7 <= 1'h0; end else begin if (_T_78) begin if (4'h7 == auto_in_a_bits_source) begin _T_76_7 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h7 == auto_in_a_bits_source) begin _T_76_7 <= 1'h1; end end end end if (_T_91) begin _T_94 <= _T_31; end if (reset) begin _T_76_8 <= 1'h0; end else begin if (_T_81) begin if (4'h8 == auto_out_d_bits_source) begin _T_76_8 <= 1'h0; end else begin if (_T_78) begin if (4'h8 == auto_in_a_bits_source) begin _T_76_8 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h8 == auto_in_a_bits_source) begin _T_76_8 <= 1'h1; end end end end if (reset) begin _T_76_9 <= 1'h0; end else begin if (_T_81) begin if (4'h9 == auto_out_d_bits_source) begin _T_76_9 <= 1'h0; end else begin if (_T_78) begin if (4'h9 == auto_in_a_bits_source) begin _T_76_9 <= 1'h1; end end end end else begin if (_T_78) begin if (4'h9 == auto_in_a_bits_source) begin _T_76_9 <= 1'h1; end end end end if (reset) begin _T_76_10 <= 1'h0; end else begin if (_T_81) begin if (4'ha == auto_out_d_bits_source) begin _T_76_10 <= 1'h0; end else begin if (_T_78) begin if (4'ha == auto_in_a_bits_source) begin _T_76_10 <= 1'h1; end end end end else begin if (_T_78) begin if (4'ha == auto_in_a_bits_source) begin _T_76_10 <= 1'h1; end end end end if (reset) begin _T_76_11 <= 1'h0; end else begin if (_T_81) begin if (4'hb == auto_out_d_bits_source) begin _T_76_11 <= 1'h0; end else begin if (_T_78) begin if (4'hb == auto_in_a_bits_source) begin _T_76_11 <= 1'h1; end end end end else begin if (_T_78) begin if (4'hb == auto_in_a_bits_source) begin _T_76_11 <= 1'h1; end end end end if (reset) begin _T_76_12 <= 1'h0; end else begin if (_T_81) begin if (4'hc == auto_out_d_bits_source) begin _T_76_12 <= 1'h0; end else begin if (_T_78) begin if (4'hc == auto_in_a_bits_source) begin _T_76_12 <= 1'h1; end end end end else begin if (_T_78) begin if (4'hc == auto_in_a_bits_source) begin _T_76_12 <= 1'h1; end end end end if (reset) begin _T_76_13 <= 1'h0; end else begin if (_T_81) begin if (4'hd == auto_out_d_bits_source) begin _T_76_13 <= 1'h0; end else begin if (_T_78) begin if (4'hd == auto_in_a_bits_source) begin _T_76_13 <= 1'h1; end end end end else begin if (_T_78) begin if (4'hd == auto_in_a_bits_source) begin _T_76_13 <= 1'h1; end end end end if (reset) begin _T_76_14 <= 1'h0; end else begin if (_T_81) begin if (4'he == auto_out_d_bits_source) begin _T_76_14 <= 1'h0; end else begin if (_T_78) begin if (4'he == auto_in_a_bits_source) begin _T_76_14 <= 1'h1; end end end end else begin if (_T_78) begin if (4'he == auto_in_a_bits_source) begin _T_76_14 <= 1'h1; end end end end if (reset) begin _T_76_15 <= 1'h0; end else begin if (_T_81) begin if (4'hf == auto_out_d_bits_source) begin _T_76_15 <= 1'h0; end else begin if (_T_78) begin if (4'hf == auto_in_a_bits_source) begin _T_76_15 <= 1'h1; end end end end else begin if (_T_78) begin if (4'hf == auto_in_a_bits_source) begin _T_76_15 <= 1'h1; end end end end if (_T_116) begin _T_119 <= _T_31; end if (reset) begin _T_62 <= 10'h0; end else begin if (_T_54) begin if (_T_65) begin if (_T_60) begin _T_62 <= _T_59; end else begin _T_62 <= 10'h0; end end else begin _T_62 <= _T_64; end end end end endmodule module TLMonitor_13( // @[:freechips.rocketchip.system.TinyConfig.fir@24752.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@24753.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@24754.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@24755.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@26288.4] wire _T_7; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@24772.6] wire _T_8; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@24773.6] wire _T_22; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@24790.6] wire [26:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24792.6] wire [11:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24793.6] wire [11:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24794.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@24795.6] wire [31:0] _T_27; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@24795.6] wire _T_28; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@24796.6] wire [1:0] _T_30; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@24798.6] wire [3:0] _T_31; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@24799.6] wire [2:0] _T_32; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@24800.6] wire [2:0] _T_33; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@24801.6] wire _T_34; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@24802.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24803.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24804.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24805.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24807.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24808.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24810.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24811.6] wire _T_44; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24812.6] wire _T_45; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24813.6] wire _T_46; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24814.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24815.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24816.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24817.6] wire _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24818.6] wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24819.6] wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24820.6] wire _T_53; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24821.6] wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24822.6] wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24823.6] wire _T_56; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24824.6] wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24825.6] wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24826.6] wire _T_59; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24827.6] wire _T_60; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24828.6] wire _T_61; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24829.6] wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24830.6] wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24831.6] wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24832.6] wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24833.6] wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24834.6] wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24835.6] wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24836.6] wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24837.6] wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24838.6] wire _T_71; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24839.6] wire _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24840.6] wire _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24841.6] wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24842.6] wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24843.6] wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24844.6] wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24845.6] wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24846.6] wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24847.6] wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24848.6] wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24849.6] wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24850.6] wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24851.6] wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24852.6] wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24853.6] wire [7:0] _T_92; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@24860.6] wire [32:0] _T_103; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24871.6] wire _T_127; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@24899.6] wire [31:0] _T_129; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24902.8] wire [32:0] _T_130; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24903.8] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24904.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24905.8] wire _T_133; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24906.8] wire [31:0] _T_134; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24907.8] wire [32:0] _T_135; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24908.8] wire [32:0] _T_136; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24909.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24910.8] wire _T_138; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24911.8] wire [31:0] _T_139; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24912.8] wire [32:0] _T_140; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24913.8] wire [32:0] _T_141; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24914.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24915.8] wire _T_143; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24916.8] wire [32:0] _T_146; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24919.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24920.8] wire _T_148; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24921.8] wire [31:0] _T_149; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24922.8] wire [32:0] _T_150; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24923.8] wire [32:0] _T_151; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24924.8] wire [32:0] _T_152; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24925.8] wire _T_153; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24926.8] wire [31:0] _T_154; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24927.8] wire [32:0] _T_155; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24928.8] wire [32:0] _T_156; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24929.8] wire [32:0] _T_157; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24930.8] wire _T_158; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24931.8] wire [31:0] _T_159; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24932.8] wire [32:0] _T_160; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24933.8] wire [32:0] _T_161; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24934.8] wire [32:0] _T_162; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24935.8] wire _T_163; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24936.8] wire _T_164; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24937.8] wire _T_165; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24938.8] wire _T_166; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24939.8] wire _T_167; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24940.8] wire _T_174; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24947.8] wire _T_179; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24960.8] wire _T_180; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24961.8] wire _T_183; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24968.8] wire _T_184; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24969.8] wire _T_186; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24975.8] wire _T_187; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24976.8] wire _T_188; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@24981.8] wire _T_190; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24983.8] wire _T_191; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24984.8] wire [7:0] _T_192; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@24989.8] wire _T_193; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@24990.8] wire _T_195; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24992.8] wire _T_196; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24993.8] wire _T_197; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@24998.8] wire _T_199; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25000.8] wire _T_200; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25001.8] wire _T_201; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@25007.6] wire _T_266; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@25097.8] wire _T_268; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25099.8] wire _T_269; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25100.8] wire _T_279; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@25123.6] wire _T_281; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25126.8] wire _T_289; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25134.8] wire _T_291; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25136.8] wire _T_324; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25169.8] wire _T_325; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25170.8] wire _T_326; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25171.8] wire _T_327; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25172.8] wire _T_328; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25173.8] wire _T_329; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25174.8] wire _T_331; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25176.8] wire _T_333; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25178.8] wire _T_334; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25179.8] wire _T_341; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@25198.8] wire _T_343; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25200.8] wire _T_344; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25201.8] wire _T_345; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@25206.8] wire _T_347; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25208.8] wire _T_348; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25209.8] wire _T_353; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@25223.6] wire _T_391; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25262.8] wire _T_400; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25271.8] wire _T_408; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25279.8] wire _T_410; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25281.8] wire _T_412; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25283.8] wire _T_414; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25285.8] wire _T_415; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25286.8] wire _T_430; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@25322.6] wire [7:0] _T_503; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@25412.8] wire [7:0] _T_504; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@25413.8] wire _T_505; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@25414.8] wire _T_507; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25416.8] wire _T_508; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25417.8] wire _T_509; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@25423.6] wire _T_511; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25426.8] wire _T_543; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25458.8] wire _T_560; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25475.8] wire _T_561; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25476.8] wire _T_568; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@25495.8] wire _T_570; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25497.8] wire _T_571; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25498.8] wire _T_576; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@25512.6] wire _T_635; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@25584.8] wire _T_637; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25586.8] wire _T_638; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25587.8] wire _T_643; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@25601.6] wire _T_694; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25653.8] wire _T_695; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25654.8] wire _T_710; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@25692.6] wire _T_712; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25694.6] wire _T_713; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25695.6] wire _T_716; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@25702.6] wire _T_717; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@25703.6] wire _T_731; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@25720.6] wire _T_733; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@25722.6] wire _T_735; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25725.8] wire _T_736; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25726.8] wire _T_737; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@25731.8] wire _T_739; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25733.8] wire _T_740; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25734.8] wire _T_741; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@25739.8] wire _T_743; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25741.8] wire _T_744; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25742.8] wire _T_745; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@25747.8] wire _T_747; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25749.8] wire _T_748; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25750.8] wire _T_749; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@25755.8] wire _T_751; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25757.8] wire _T_752; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25758.8] wire _T_753; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@25764.6] wire _T_764; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@25788.8] wire _T_766; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25790.8] wire _T_767; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25791.8] wire _T_768; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@25796.8] wire _T_770; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25798.8] wire _T_771; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25799.8] wire _T_781; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@25822.6] wire _T_801; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@25863.8] wire _T_803; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25865.8] wire _T_804; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25866.8] wire _T_810; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@25881.6] wire _T_827; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@25916.6] wire _T_845; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@25952.6] wire _T_874; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@26012.4] wire [8:0] _T_879; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@26017.4] wire _T_880; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@26018.4] wire _T_881; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26019.4] reg [8:0] _T_883; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@26021.4] reg [31:0] _RAND_0; wire [8:0] _T_885; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26023.4] wire _T_886; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26024.4] reg [2:0] _T_894; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@26035.4] reg [31:0] _RAND_1; reg [2:0] _T_895; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@26036.4] reg [31:0] _RAND_2; reg [3:0] _T_896; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@26037.4] reg [31:0] _RAND_3; reg [3:0] _T_897; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@26038.4] reg [31:0] _RAND_4; reg [31:0] _T_898; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@26039.4] reg [31:0] _RAND_5; wire _T_899; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@26040.4] wire _T_900; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@26041.4] wire _T_901; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@26043.6] wire _T_903; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26045.6] wire _T_904; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26046.6] wire _T_905; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@26051.6] wire _T_907; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26053.6] wire _T_908; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26054.6] wire _T_909; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@26059.6] wire _T_911; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26061.6] wire _T_912; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26062.6] wire _T_913; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@26067.6] wire _T_915; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26069.6] wire _T_916; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26070.6] wire _T_917; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@26075.6] wire _T_919; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26077.6] wire _T_920; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26078.6] wire _T_922; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@26085.4] wire _T_923; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@26093.4] wire [26:0] _T_925; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26095.4] wire [11:0] _T_926; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26096.4] wire [11:0] _T_927; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26097.4] wire [8:0] _T_928; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@26098.4] wire _T_929; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@26099.4] reg [8:0] _T_931; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@26101.4] reg [31:0] _RAND_6; wire [8:0] _T_933; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26103.4] wire _T_934; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26104.4] reg [2:0] _T_942; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@26115.4] reg [31:0] _RAND_7; reg [1:0] _T_943; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@26116.4] reg [31:0] _RAND_8; reg [3:0] _T_944; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@26117.4] reg [31:0] _RAND_9; reg [3:0] _T_945; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@26118.4] reg [31:0] _RAND_10; reg _T_946; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@26119.4] reg [31:0] _RAND_11; reg _T_947; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@26120.4] reg [31:0] _RAND_12; wire _T_948; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@26121.4] wire _T_949; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@26122.4] wire _T_950; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@26124.6] wire _T_952; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26126.6] wire _T_953; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26127.6] wire _T_954; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@26132.6] wire _T_956; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26134.6] wire _T_957; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26135.6] wire _T_958; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@26140.6] wire _T_960; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26142.6] wire _T_961; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26143.6] wire _T_962; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@26148.6] wire _T_964; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26150.6] wire _T_965; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26151.6] wire _T_966; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@26156.6] wire _T_968; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26158.6] wire _T_969; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26159.6] wire _T_970; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@26164.6] wire _T_972; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26166.6] wire _T_973; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26167.6] wire _T_975; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@26174.4] reg [15:0] _T_976; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@26183.4] reg [31:0] _RAND_13; reg [8:0] _T_986; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@26193.4] reg [31:0] _RAND_14; wire [8:0] _T_988; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26195.4] wire _T_989; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26196.4] reg [8:0] _T_1005; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@26215.4] reg [31:0] _RAND_15; wire [8:0] _T_1007; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26217.4] wire _T_1008; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26218.4] wire _T_1018; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@26233.4] wire [15:0] _T_1020; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@26236.6] wire [15:0] _T_1021; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@26238.6] wire _T_1022; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@26239.6] wire _T_1023; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@26240.6] wire _T_1025; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26242.6] wire _T_1026; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26243.6] wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@26235.4] wire _T_1030; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@26254.4] wire _T_1032; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@26256.4] wire _T_1033; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@26257.4] wire [15:0] _T_1034; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@26259.6] wire [15:0] _T_1035; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@26261.6] wire [15:0] _T_1036; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@26262.6] wire _T_1037; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@26263.6] wire _T_1039; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26265.6] wire _T_1040; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26266.6] wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@26258.4] wire _T_1041; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@26272.4] wire _T_1042; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@26273.4] wire _T_1043; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@26274.4] wire _T_1044; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@26275.4] wire _T_1046; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26277.4] wire _T_1047; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26278.4] wire [15:0] _T_1048; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@26283.4] wire [15:0] _T_1049; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@26284.4] wire [15:0] _T_1050; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@26285.4] reg [31:0] _T_1051; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@26287.4] reg [31:0] _RAND_16; wire _T_1052; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@26290.4] wire _T_1053; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@26291.4] wire _T_1054; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@26292.4] wire _T_1055; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@26293.4] wire _T_1056; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@26294.4] wire _T_1057; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@26295.4] wire _T_1059; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26297.4] wire _T_1060; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26298.4] wire [31:0] _T_1062; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@26304.4] wire _T_1065; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@26308.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24949.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@25057.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25181.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25288.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@25387.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25478.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@25567.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25656.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25728.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@25770.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@25828.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@25887.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@25922.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@25958.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@26288.4] .out(plusarg_reader_out) ); assign _T_7 = io_in_a_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@24772.6] assign _T_8 = _T_7 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@24773.6] assign _T_22 = _T_8 | _T_7; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@24790.6] assign _T_24 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@24792.6] assign _T_25 = _T_24[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@24793.6] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@24794.6] assign _GEN_18 = {{20'd0}, _T_26}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@24795.6] assign _T_27 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@24795.6] assign _T_28 = _T_27 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@24796.6] assign _T_30 = io_in_a_bits_size[1:0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@24798.6] assign _T_31 = 4'h1 << _T_30; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@24799.6] assign _T_32 = _T_31[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@24800.6] assign _T_33 = _T_32 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@24801.6] assign _T_34 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@24802.6] assign _T_35 = _T_33[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24803.6] assign _T_36 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24804.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24805.6] assign _T_39 = _T_35 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24807.6] assign _T_40 = _T_34 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24808.6] assign _T_42 = _T_35 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24810.6] assign _T_43 = _T_34 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24811.6] assign _T_44 = _T_33[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24812.6] assign _T_45 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24813.6] assign _T_46 = _T_45 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24814.6] assign _T_47 = _T_37 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24815.6] assign _T_48 = _T_44 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24816.6] assign _T_49 = _T_40 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24817.6] assign _T_50 = _T_37 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24818.6] assign _T_51 = _T_44 & _T_50; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24819.6] assign _T_52 = _T_40 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24820.6] assign _T_53 = _T_36 & _T_46; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24821.6] assign _T_54 = _T_44 & _T_53; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24822.6] assign _T_55 = _T_43 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24823.6] assign _T_56 = _T_36 & _T_45; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24824.6] assign _T_57 = _T_44 & _T_56; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24825.6] assign _T_58 = _T_43 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24826.6] assign _T_59 = _T_33[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@24827.6] assign _T_60 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@24828.6] assign _T_61 = _T_60 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@24829.6] assign _T_62 = _T_47 & _T_61; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24830.6] assign _T_63 = _T_59 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24831.6] assign _T_64 = _T_49 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24832.6] assign _T_65 = _T_47 & _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24833.6] assign _T_66 = _T_59 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24834.6] assign _T_67 = _T_49 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24835.6] assign _T_68 = _T_50 & _T_61; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24836.6] assign _T_69 = _T_59 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24837.6] assign _T_70 = _T_52 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24838.6] assign _T_71 = _T_50 & _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24839.6] assign _T_72 = _T_59 & _T_71; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24840.6] assign _T_73 = _T_52 | _T_72; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24841.6] assign _T_74 = _T_53 & _T_61; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24842.6] assign _T_75 = _T_59 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24843.6] assign _T_76 = _T_55 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24844.6] assign _T_77 = _T_53 & _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24845.6] assign _T_78 = _T_59 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24846.6] assign _T_79 = _T_55 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24847.6] assign _T_80 = _T_56 & _T_61; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24848.6] assign _T_81 = _T_59 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24849.6] assign _T_82 = _T_58 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24850.6] assign _T_83 = _T_56 & _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@24851.6] assign _T_84 = _T_59 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@24852.6] assign _T_85 = _T_58 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@24853.6] assign _T_92 = {_T_85,_T_82,_T_79,_T_76,_T_73,_T_70,_T_67,_T_64}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@24860.6] assign _T_103 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24871.6] assign _T_127 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@24899.6] assign _T_129 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24902.8] assign _T_130 = {1'b0,$signed(_T_129)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24903.8] assign _T_131 = $signed(_T_130) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24904.8] assign _T_132 = $signed(_T_131); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24905.8] assign _T_133 = $signed(_T_132) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24906.8] assign _T_134 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24907.8] assign _T_135 = {1'b0,$signed(_T_134)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24908.8] assign _T_136 = $signed(_T_135) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24909.8] assign _T_137 = $signed(_T_136); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24910.8] assign _T_138 = $signed(_T_137) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24911.8] assign _T_139 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24912.8] assign _T_140 = {1'b0,$signed(_T_139)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24913.8] assign _T_141 = $signed(_T_140) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24914.8] assign _T_142 = $signed(_T_141); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24915.8] assign _T_143 = $signed(_T_142) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24916.8] assign _T_146 = $signed(_T_103) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24919.8] assign _T_147 = $signed(_T_146); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24920.8] assign _T_148 = $signed(_T_147) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24921.8] assign _T_149 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24922.8] assign _T_150 = {1'b0,$signed(_T_149)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24923.8] assign _T_151 = $signed(_T_150) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24924.8] assign _T_152 = $signed(_T_151); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24925.8] assign _T_153 = $signed(_T_152) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24926.8] assign _T_154 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24927.8] assign _T_155 = {1'b0,$signed(_T_154)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24928.8] assign _T_156 = $signed(_T_155) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24929.8] assign _T_157 = $signed(_T_156); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24930.8] assign _T_158 = $signed(_T_157) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24931.8] assign _T_159 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@24932.8] assign _T_160 = {1'b0,$signed(_T_159)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@24933.8] assign _T_161 = $signed(_T_160) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24934.8] assign _T_162 = $signed(_T_161); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@24935.8] assign _T_163 = $signed(_T_162) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@24936.8] assign _T_164 = _T_133 | _T_138; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24937.8] assign _T_165 = _T_164 | _T_143; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24938.8] assign _T_166 = _T_165 | _T_148; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24939.8] assign _T_167 = _T_166 | _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@24940.8] assign _T_174 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24947.8] assign _T_179 = _T_22 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24960.8] assign _T_180 = _T_179 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24961.8] assign _T_183 = _T_34 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24968.8] assign _T_184 = _T_183 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24969.8] assign _T_186 = _T_28 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24975.8] assign _T_187 = _T_186 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24976.8] assign _T_188 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@24981.8] assign _T_190 = _T_188 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24983.8] assign _T_191 = _T_190 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24984.8] assign _T_192 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@24989.8] assign _T_193 = _T_192 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@24990.8] assign _T_195 = _T_193 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24992.8] assign _T_196 = _T_195 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24993.8] assign _T_197 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@24998.8] assign _T_199 = _T_197 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25000.8] assign _T_200 = _T_199 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25001.8] assign _T_201 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@25007.6] assign _T_266 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@25097.8] assign _T_268 = _T_266 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25099.8] assign _T_269 = _T_268 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25100.8] assign _T_279 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@25123.6] assign _T_281 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25126.8] assign _T_289 = _T_281 & _T_133; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25134.8] assign _T_291 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25136.8] assign _T_324 = _T_138 | _T_143; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25169.8] assign _T_325 = _T_324 | _T_148; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25170.8] assign _T_326 = _T_325 | _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25171.8] assign _T_327 = _T_326 | _T_158; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25172.8] assign _T_328 = _T_327 | _T_163; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@25173.8] assign _T_329 = _T_291 & _T_328; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25174.8] assign _T_331 = _T_289 | _T_329; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25176.8] assign _T_333 = _T_331 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25178.8] assign _T_334 = _T_333 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25179.8] assign _T_341 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@25198.8] assign _T_343 = _T_341 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25200.8] assign _T_344 = _T_343 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25201.8] assign _T_345 = io_in_a_bits_mask == _T_92; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@25206.8] assign _T_347 = _T_345 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25208.8] assign _T_348 = _T_347 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25209.8] assign _T_353 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@25223.6] assign _T_391 = _T_291 & _T_326; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25262.8] assign _T_400 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25271.8] assign _T_408 = _T_400 & _T_163; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25279.8] assign _T_410 = _T_289 | _T_391; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25281.8] assign _T_412 = _T_410 | _T_408; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@25283.8] assign _T_414 = _T_412 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25285.8] assign _T_415 = _T_414 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25286.8] assign _T_430 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@25322.6] assign _T_503 = ~ _T_92; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@25412.8] assign _T_504 = io_in_a_bits_mask & _T_503; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@25413.8] assign _T_505 = _T_504 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@25414.8] assign _T_507 = _T_505 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25416.8] assign _T_508 = _T_507 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25417.8] assign _T_509 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@25423.6] assign _T_511 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@25426.8] assign _T_543 = _T_511 & _T_167; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@25458.8] assign _T_560 = _T_543 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25475.8] assign _T_561 = _T_560 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25476.8] assign _T_568 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@25495.8] assign _T_570 = _T_568 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25497.8] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25498.8] assign _T_576 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@25512.6] assign _T_635 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@25584.8] assign _T_637 = _T_635 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25586.8] assign _T_638 = _T_637 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25587.8] assign _T_643 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@25601.6] assign _T_694 = _T_289 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25653.8] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25654.8] assign _T_710 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@25692.6] assign _T_712 = _T_710 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25694.6] assign _T_713 = _T_712 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25695.6] assign _T_716 = io_in_d_bits_source[3:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@25702.6] assign _T_717 = _T_716 == 1'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@25703.6] assign _T_731 = _T_717 | _T_716; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@25720.6] assign _T_733 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@25722.6] assign _T_735 = _T_731 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25725.8] assign _T_736 = _T_735 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25726.8] assign _T_737 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@25731.8] assign _T_739 = _T_737 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25733.8] assign _T_740 = _T_739 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25734.8] assign _T_741 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@25739.8] assign _T_743 = _T_741 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25741.8] assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25742.8] assign _T_745 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@25747.8] assign _T_747 = _T_745 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25749.8] assign _T_748 = _T_747 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25750.8] assign _T_749 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@25755.8] assign _T_751 = _T_749 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25757.8] assign _T_752 = _T_751 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25758.8] assign _T_753 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@25764.6] assign _T_764 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@25788.8] assign _T_766 = _T_764 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25790.8] assign _T_767 = _T_766 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25791.8] assign _T_768 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@25796.8] assign _T_770 = _T_768 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25798.8] assign _T_771 = _T_770 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25799.8] assign _T_781 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@25822.6] assign _T_801 = _T_749 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@25863.8] assign _T_803 = _T_801 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25865.8] assign _T_804 = _T_803 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25866.8] assign _T_810 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@25881.6] assign _T_827 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@25916.6] assign _T_845 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@25952.6] assign _T_874 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@26012.4] assign _T_879 = _T_26[11:3]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@26017.4] assign _T_880 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@26018.4] assign _T_881 = _T_880 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26019.4] assign _T_885 = _T_883 - 9'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26023.4] assign _T_886 = _T_883 == 9'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26024.4] assign _T_899 = _T_886 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@26040.4] assign _T_900 = io_in_a_valid & _T_899; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@26041.4] assign _T_901 = io_in_a_bits_opcode == _T_894; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@26043.6] assign _T_903 = _T_901 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26045.6] assign _T_904 = _T_903 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26046.6] assign _T_905 = io_in_a_bits_param == _T_895; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@26051.6] assign _T_907 = _T_905 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26053.6] assign _T_908 = _T_907 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26054.6] assign _T_909 = io_in_a_bits_size == _T_896; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@26059.6] assign _T_911 = _T_909 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26061.6] assign _T_912 = _T_911 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26062.6] assign _T_913 = io_in_a_bits_source == _T_897; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@26067.6] assign _T_915 = _T_913 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26069.6] assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26070.6] assign _T_917 = io_in_a_bits_address == _T_898; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@26075.6] assign _T_919 = _T_917 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26077.6] assign _T_920 = _T_919 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26078.6] assign _T_922 = _T_874 & _T_886; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@26085.4] assign _T_923 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@26093.4] assign _T_925 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26095.4] assign _T_926 = _T_925[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26096.4] assign _T_927 = ~ _T_926; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26097.4] assign _T_928 = _T_927[11:3]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@26098.4] assign _T_929 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@26099.4] assign _T_933 = _T_931 - 9'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26103.4] assign _T_934 = _T_931 == 9'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26104.4] assign _T_948 = _T_934 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@26121.4] assign _T_949 = io_in_d_valid & _T_948; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@26122.4] assign _T_950 = io_in_d_bits_opcode == _T_942; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@26124.6] assign _T_952 = _T_950 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26126.6] assign _T_953 = _T_952 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26127.6] assign _T_954 = io_in_d_bits_param == _T_943; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@26132.6] assign _T_956 = _T_954 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26134.6] assign _T_957 = _T_956 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26135.6] assign _T_958 = io_in_d_bits_size == _T_944; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@26140.6] assign _T_960 = _T_958 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26142.6] assign _T_961 = _T_960 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26143.6] assign _T_962 = io_in_d_bits_source == _T_945; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@26148.6] assign _T_964 = _T_962 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26150.6] assign _T_965 = _T_964 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26151.6] assign _T_966 = io_in_d_bits_sink == _T_946; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@26156.6] assign _T_968 = _T_966 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26158.6] assign _T_969 = _T_968 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26159.6] assign _T_970 = io_in_d_bits_denied == _T_947; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@26164.6] assign _T_972 = _T_970 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26166.6] assign _T_973 = _T_972 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26167.6] assign _T_975 = _T_923 & _T_934; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@26174.4] assign _T_988 = _T_986 - 9'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26195.4] assign _T_989 = _T_986 == 9'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26196.4] assign _T_1007 = _T_1005 - 9'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@26217.4] assign _T_1008 = _T_1005 == 9'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@26218.4] assign _T_1018 = _T_874 & _T_989; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@26233.4] assign _T_1020 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@26236.6] assign _T_1021 = _T_976 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@26238.6] assign _T_1022 = _T_1021[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@26239.6] assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@26240.6] assign _T_1025 = _T_1023 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26242.6] assign _T_1026 = _T_1025 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26243.6] assign _GEN_15 = _T_1018 ? _T_1020 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@26235.4] assign _T_1030 = _T_923 & _T_1008; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@26254.4] assign _T_1032 = _T_733 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@26256.4] assign _T_1033 = _T_1030 & _T_1032; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@26257.4] assign _T_1034 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@26259.6] assign _T_1035 = _GEN_15 | _T_976; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@26261.6] assign _T_1036 = _T_1035 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@26262.6] assign _T_1037 = _T_1036[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@26263.6] assign _T_1039 = _T_1037 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26265.6] assign _T_1040 = _T_1039 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26266.6] assign _GEN_16 = _T_1033 ? _T_1034 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@26258.4] assign _T_1041 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@26272.4] assign _T_1042 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@26273.4] assign _T_1043 = _T_1042 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@26274.4] assign _T_1044 = _T_1041 | _T_1043; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@26275.4] assign _T_1046 = _T_1044 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26277.4] assign _T_1047 = _T_1046 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26278.4] assign _T_1048 = _T_976 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@26283.4] assign _T_1049 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@26284.4] assign _T_1050 = _T_1048 & _T_1049; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@26285.4] assign _T_1052 = _T_976 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@26290.4] assign _T_1053 = _T_1052 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@26291.4] assign _T_1054 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@26292.4] assign _T_1055 = _T_1053 | _T_1054; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@26293.4] assign _T_1056 = _T_1051 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@26294.4] assign _T_1057 = _T_1055 | _T_1056; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@26295.4] assign _T_1059 = _T_1057 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26297.4] assign _T_1060 = _T_1059 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26298.4] assign _T_1062 = _T_1051 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@26304.4] assign _T_1065 = _T_874 | _T_923; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@26308.4] assign _GEN_19 = io_in_a_valid & _T_127; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24949.10] assign _GEN_35 = io_in_a_valid & _T_201; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@25057.10] assign _GEN_53 = io_in_a_valid & _T_279; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25181.10] assign _GEN_65 = io_in_a_valid & _T_353; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25288.10] assign _GEN_75 = io_in_a_valid & _T_430; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@25387.10] assign _GEN_85 = io_in_a_valid & _T_509; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25478.10] assign _GEN_95 = io_in_a_valid & _T_576; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@25567.10] assign _GEN_105 = io_in_a_valid & _T_643; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25656.10] assign _GEN_115 = io_in_d_valid & _T_733; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25728.10] assign _GEN_125 = io_in_d_valid & _T_753; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@25770.10] assign _GEN_137 = io_in_d_valid & _T_781; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@25828.10] assign _GEN_149 = io_in_d_valid & _T_810; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@25887.10] assign _GEN_155 = io_in_d_valid & _T_827; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@25922.10] assign _GEN_161 = io_in_d_valid & _T_845; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@25958.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_883 = _RAND_0[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_894 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_895 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_896 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_897 = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_898 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_931 = _RAND_6[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_942 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_943 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_944 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_945 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_946 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_947 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_976 = _RAND_13[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_986 = _RAND_14[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_1005 = _RAND_15[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_1051 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_883 <= 9'h0; end else begin if (_T_874) begin if (_T_886) begin if (_T_881) begin _T_883 <= _T_879; end else begin _T_883 <= 9'h0; end end else begin _T_883 <= _T_885; end end end if (_T_922) begin _T_894 <= io_in_a_bits_opcode; end if (_T_922) begin _T_895 <= io_in_a_bits_param; end if (_T_922) begin _T_896 <= io_in_a_bits_size; end if (_T_922) begin _T_897 <= io_in_a_bits_source; end if (_T_922) begin _T_898 <= io_in_a_bits_address; end if (reset) begin _T_931 <= 9'h0; end else begin if (_T_923) begin if (_T_934) begin if (_T_929) begin _T_931 <= _T_928; end else begin _T_931 <= 9'h0; end end else begin _T_931 <= _T_933; end end end if (_T_975) begin _T_942 <= io_in_d_bits_opcode; end if (_T_975) begin _T_943 <= io_in_d_bits_param; end if (_T_975) begin _T_944 <= io_in_d_bits_size; end if (_T_975) begin _T_945 <= io_in_d_bits_source; end if (_T_975) begin _T_946 <= io_in_d_bits_sink; end if (_T_975) begin _T_947 <= io_in_d_bits_denied; end if (reset) begin _T_976 <= 16'h0; end else begin _T_976 <= _T_1050; end if (reset) begin _T_986 <= 9'h0; end else begin if (_T_874) begin if (_T_989) begin if (_T_881) begin _T_986 <= _T_879; end else begin _T_986 <= 9'h0; end end else begin _T_986 <= _T_988; end end end if (reset) begin _T_1005 <= 9'h0; end else begin if (_T_923) begin if (_T_1008) begin if (_T_929) begin _T_1005 <= _T_928; end else begin _T_1005 <= 9'h0; end end else begin _T_1005 <= _T_1007; end end end if (reset) begin _T_1051 <= 32'h0; end else begin if (_T_1065) begin _T_1051 <= 32'h0; end else begin _T_1051 <= _T_1062; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24949.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_174) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@24950.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Ports.scala:142:9)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@24956.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_174) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@24957.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24963.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_180) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@24964.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_184) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Ports.scala:142:9)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24971.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_184) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@24972.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_187) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@24979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_191) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Ports.scala:142:9)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24986.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_191) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@24987.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_196) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24995.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_196) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@24996.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_200) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25003.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_200) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@25004.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@25057.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_174) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@25058.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Ports.scala:142:9)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@25064.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_174) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@25065.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@25071.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_180) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@25072.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_184) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Ports.scala:142:9)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@25079.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_184) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@25080.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@25086.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_187) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@25087.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_191) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Ports.scala:142:9)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@25094.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_191) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@25095.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_269) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Ports.scala:142:9)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25102.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_269) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@25103.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_196) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@25111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_196) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@25112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_200) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@25119.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_200) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@25120.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25181.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_334) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@25182.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@25188.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_180) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@25189.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@25195.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_187) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@25196.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_344) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_344) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@25204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_348) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25211.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_348) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@25212.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_200) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@25219.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_200) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@25220.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_415) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25288.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_415) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@25289.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@25295.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_180) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@25296.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@25302.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_187) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@25303.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_344) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@25310.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_344) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@25311.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_348) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@25318.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_348) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@25319.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_415) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@25387.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_415) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@25388.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@25394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_180) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@25395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@25401.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_187) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@25402.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_344) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@25409.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_344) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@25410.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_508) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25419.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_508) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@25420.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_561) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25478.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_561) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@25479.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@25485.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_180) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@25486.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@25492.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_187) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@25493.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Ports.scala:142:9)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25500.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_571) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@25501.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_348) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@25508.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_348) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@25509.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_561) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@25567.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_561) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@25568.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@25574.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_180) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@25575.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@25581.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_187) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@25582.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_638) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Ports.scala:142:9)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25589.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_638) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@25590.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_348) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@25597.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_348) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@25598.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_695) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Ports.scala:142:9)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25656.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_695) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@25657.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_180) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@25663.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_180) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@25664.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Ports.scala:142:9)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@25670.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_187) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@25671.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_348) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Ports.scala:142:9)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@25678.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_348) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@25679.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_200) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@25686.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_200) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@25687.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_713) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Ports.scala:142:9)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25697.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_713) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@25698.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25728.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_736) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@25729.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Ports.scala:142:9)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_740) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@25737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_744) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_744) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@25745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_748) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25752.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_748) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@25753.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_752) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Ports.scala:142:9)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25760.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_752) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@25761.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@25770.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_736) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@25771.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Ports.scala:142:9)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@25777.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_174) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@25778.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Ports.scala:142:9)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@25785.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_740) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@25786.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_767) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Ports.scala:142:9)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25793.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_767) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@25794.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_771) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Ports.scala:142:9)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25801.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_771) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@25802.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_748) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@25809.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_748) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@25810.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@25828.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_736) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@25829.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_174) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Ports.scala:142:9)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@25835.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_174) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@25836.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_740) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Ports.scala:142:9)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@25843.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_740) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@25844.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_767) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Ports.scala:142:9)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@25851.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_767) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@25852.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_771) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Ports.scala:142:9)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@25859.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_771) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@25860.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_804) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25868.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_804) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@25869.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@25887.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_736) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@25888.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_744) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@25895.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_744) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@25896.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_748) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@25903.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_748) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@25904.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@25922.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_736) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@25923.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_744) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@25930.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_744) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@25931.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_804) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@25939.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_804) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@25940.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_736) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Ports.scala:142:9)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@25958.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_736) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@25959.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_744) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Ports.scala:142:9)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@25966.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_744) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@25967.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_748) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Ports.scala:142:9)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@25974.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_748) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@25975.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_900 & _T_904) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26048.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_900 & _T_904) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@26049.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_900 & _T_908) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26056.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_900 & _T_908) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@26057.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_900 & _T_912) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26064.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_900 & _T_912) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@26065.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_900 & _T_916) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26072.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_900 & _T_916) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@26073.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_900 & _T_920) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26080.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_900 & _T_920) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@26081.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_953) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26129.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_953) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@26130.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_957) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26137.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_957) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@26138.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_961) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26145.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_961) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@26146.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_965) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26153.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_965) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@26154.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_969) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26161.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_969) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@26162.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_949 & _T_973) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Ports.scala:142:9)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26169.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_949 & _T_973) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@26170.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1018 & _T_1026) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Ports.scala:142:9)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26245.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1018 & _T_1026) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@26246.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1033 & _T_1040) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Ports.scala:142:9)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26268.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1033 & _T_1040) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@26269.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1047) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 6 (connected at Ports.scala:142:9)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26280.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1047) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@26281.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1060) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Ports.scala:142:9)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26300.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1060) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@26301.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Repeater( // @[:freechips.rocketchip.system.TinyConfig.fir@26313.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@26314.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@26315.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [3:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [3:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@26316.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@26321.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_2; reg [3:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_3; reg [3:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_4; reg [31:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_5; reg [7:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_6; reg [63:0] saved_data; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [63:0] _RAND_7; reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@26322.4] reg [31:0] _RAND_8; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@26325.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26331.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@26332.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26337.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@26338.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@26339.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@26325.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26331.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@26332.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26337.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@26338.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@26339.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@26327.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@26324.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_data = full ? saved_data : io_enq_bits_data; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@26329.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {2{`RANDOM}}; saved_data = _RAND_7[63:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; saved_corrupt = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end if (_T_5) begin saved_data <= io_enq_bits_data; end if (_T_5) begin saved_corrupt <= io_enq_bits_corrupt; end end endmodule module TLWidthWidget_3( // @[:freechips.rocketchip.system.TinyConfig.fir@26344.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@26345.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@26346.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@26347.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] wire Repeater_clock; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_reset; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_repeat; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_enq_ready; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_enq_valid; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [2:0] Repeater_io_enq_bits_param; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [3:0] Repeater_io_enq_bits_size; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [3:0] Repeater_io_enq_bits_source; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [31:0] Repeater_io_enq_bits_address; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [7:0] Repeater_io_enq_bits_mask; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [63:0] Repeater_io_enq_bits_data; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_enq_bits_corrupt; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_deq_ready; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_deq_valid; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [2:0] Repeater_io_deq_bits_param; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [3:0] Repeater_io_deq_bits_size; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [3:0] Repeater_io_deq_bits_source; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [31:0] Repeater_io_deq_bits_address; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [7:0] Repeater_io_deq_bits_mask; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [63:0] Repeater_io_deq_bits_data; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire Repeater_io_deq_bits_corrupt; // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] wire [31:0] _T_16; // @[WidthWidget.scala 144:37:freechips.rocketchip.system.TinyConfig.fir@26418.4] wire [31:0] _T_17; // @[WidthWidget.scala 145:31:freechips.rocketchip.system.TinyConfig.fir@26419.4] wire [63:0] _T_18; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26420.4] wire [2:0] _T_15_bits_opcode; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] wire _T_19; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@26422.4] wire _T_20; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26423.4] wire [3:0] _T_15_bits_size; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] wire [17:0] _T_22; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26425.4] wire [2:0] _T_23; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26426.4] wire [2:0] _T_24; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26427.4] wire _T_25; // @[WidthWidget.scala 87:47:freechips.rocketchip.system.TinyConfig.fir@26428.4] reg _T_26; // @[WidthWidget.scala 89:26:freechips.rocketchip.system.TinyConfig.fir@26429.4] reg [31:0] _RAND_0; wire _T_28; // @[WidthWidget.scala 91:25:freechips.rocketchip.system.TinyConfig.fir@26431.4] wire _T_29; // @[WidthWidget.scala 91:38:freechips.rocketchip.system.TinyConfig.fir@26432.4] wire _T_30; // @[WidthWidget.scala 91:35:freechips.rocketchip.system.TinyConfig.fir@26433.4] wire _T_15_valid; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] wire _T_31; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26434.4] wire _T_33; // @[WidthWidget.scala 94:24:freechips.rocketchip.system.TinyConfig.fir@26437.6] wire [31:0] _T_15_bits_address; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] wire _T_34; // @[WidthWidget.scala 100:39:freechips.rocketchip.system.TinyConfig.fir@26443.4] wire _T_35; // @[WidthWidget.scala 110:24:freechips.rocketchip.system.TinyConfig.fir@26444.4] wire [31:0] _T_36; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26446.4] wire [31:0] _T_37; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26447.4] wire [7:0] _T_15_bits_mask; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] wire [3:0] _T_39; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26453.4] wire [3:0] _T_40; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26454.4] wire _T_43; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@26462.4] wire [17:0] _T_45; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26464.4] wire [2:0] _T_46; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26465.4] wire [2:0] _T_47; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26466.4] wire _T_48; // @[WidthWidget.scala 29:47:freechips.rocketchip.system.TinyConfig.fir@26467.4] reg _T_49; // @[WidthWidget.scala 31:27:freechips.rocketchip.system.TinyConfig.fir@26468.4] reg [31:0] _RAND_1; wire _T_51; // @[WidthWidget.scala 33:26:freechips.rocketchip.system.TinyConfig.fir@26470.4] wire _T_52; // @[WidthWidget.scala 33:39:freechips.rocketchip.system.TinyConfig.fir@26471.4] wire _T_53; // @[WidthWidget.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@26472.4] wire _T_55; // @[WidthWidget.scala 34:67:freechips.rocketchip.system.TinyConfig.fir@26474.4] wire _T_57; // @[WidthWidget.scala 34:47:freechips.rocketchip.system.TinyConfig.fir@26476.4] reg _T_62; // @[WidthWidget.scala 36:32:freechips.rocketchip.system.TinyConfig.fir@26481.4] reg [31:0] _RAND_2; wire _T_63; // @[WidthWidget.scala 38:36:freechips.rocketchip.system.TinyConfig.fir@26482.4] wire _T_67; // @[WidthWidget.scala 60:32:freechips.rocketchip.system.TinyConfig.fir@26494.4] wire _T_68; // @[WidthWidget.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@26495.4] wire _T_64; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26483.4] wire _T_66; // @[WidthWidget.scala 41:24:freechips.rocketchip.system.TinyConfig.fir@26486.6] reg [31:0] _T_70_0; // @[WidthWidget.scala 51:24:freechips.rocketchip.system.TinyConfig.fir@26500.4] reg [31:0] _RAND_3; wire [31:0] _T_71; // @[WidthWidget.scala 53:81:freechips.rocketchip.system.TinyConfig.fir@26501.4] wire _T_75; // @[WidthWidget.scala 54:25:freechips.rocketchip.system.TinyConfig.fir@26505.4] TLMonitor_13 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@26354.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Repeater Repeater ( // @[Repeater.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@26409.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_enq_bits_data(Repeater_io_enq_bits_data), .io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask), .io_deq_bits_data(Repeater_io_deq_bits_data), .io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt) ); assign _T_16 = Repeater_io_deq_bits_data[63:32]; // @[WidthWidget.scala 144:37:freechips.rocketchip.system.TinyConfig.fir@26418.4] assign _T_17 = auto_in_a_bits_data[31:0]; // @[WidthWidget.scala 145:31:freechips.rocketchip.system.TinyConfig.fir@26419.4] assign _T_18 = {_T_16,_T_17}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26420.4] assign _T_15_bits_opcode = Repeater_io_deq_bits_opcode; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] assign _T_19 = _T_15_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@26422.4] assign _T_20 = _T_19 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26423.4] assign _T_15_bits_size = Repeater_io_deq_bits_size; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] assign _T_22 = 18'h7 << _T_15_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26425.4] assign _T_23 = _T_22[2:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26426.4] assign _T_24 = ~ _T_23; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26427.4] assign _T_25 = _T_24[2:2]; // @[WidthWidget.scala 87:47:freechips.rocketchip.system.TinyConfig.fir@26428.4] assign _T_28 = _T_26 == _T_25; // @[WidthWidget.scala 91:25:freechips.rocketchip.system.TinyConfig.fir@26431.4] assign _T_29 = _T_20 == 1'h0; // @[WidthWidget.scala 91:38:freechips.rocketchip.system.TinyConfig.fir@26432.4] assign _T_30 = _T_28 | _T_29; // @[WidthWidget.scala 91:35:freechips.rocketchip.system.TinyConfig.fir@26433.4] assign _T_15_valid = Repeater_io_deq_valid; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] assign _T_31 = auto_out_a_ready & _T_15_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26434.4] assign _T_33 = _T_26 + 1'h1; // @[WidthWidget.scala 94:24:freechips.rocketchip.system.TinyConfig.fir@26437.6] assign _T_15_bits_address = Repeater_io_deq_bits_address; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] assign _T_34 = _T_15_bits_address[2]; // @[WidthWidget.scala 100:39:freechips.rocketchip.system.TinyConfig.fir@26443.4] assign _T_35 = _T_34 | _T_26; // @[WidthWidget.scala 110:24:freechips.rocketchip.system.TinyConfig.fir@26444.4] assign _T_36 = _T_18[31:0]; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26446.4] assign _T_37 = _T_18[63:32]; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26447.4] assign _T_15_bits_mask = Repeater_io_deq_bits_mask; // @[WidthWidget.scala 141:25:freechips.rocketchip.system.TinyConfig.fir@26415.4 WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] assign _T_39 = _T_15_bits_mask[3:0]; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26453.4] assign _T_40 = _T_15_bits_mask[7:4]; // @[WidthWidget.scala 112:51:freechips.rocketchip.system.TinyConfig.fir@26454.4] assign _T_43 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@26462.4] assign _T_45 = 18'h7 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26464.4] assign _T_46 = _T_45[2:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26465.4] assign _T_47 = ~ _T_46; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26466.4] assign _T_48 = _T_47[2:2]; // @[WidthWidget.scala 29:47:freechips.rocketchip.system.TinyConfig.fir@26467.4] assign _T_51 = _T_49 == _T_48; // @[WidthWidget.scala 33:26:freechips.rocketchip.system.TinyConfig.fir@26470.4] assign _T_52 = _T_43 == 1'h0; // @[WidthWidget.scala 33:39:freechips.rocketchip.system.TinyConfig.fir@26471.4] assign _T_53 = _T_51 | _T_52; // @[WidthWidget.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@26472.4] assign _T_55 = _T_49 & _T_48; // @[WidthWidget.scala 34:67:freechips.rocketchip.system.TinyConfig.fir@26474.4] assign _T_57 = _T_55 == 1'h0; // @[WidthWidget.scala 34:47:freechips.rocketchip.system.TinyConfig.fir@26476.4] assign _T_63 = auto_out_d_bits_corrupt | _T_62; // @[WidthWidget.scala 38:36:freechips.rocketchip.system.TinyConfig.fir@26482.4] assign _T_67 = _T_53 == 1'h0; // @[WidthWidget.scala 60:32:freechips.rocketchip.system.TinyConfig.fir@26494.4] assign _T_68 = auto_in_d_ready | _T_67; // @[WidthWidget.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@26495.4] assign _T_64 = _T_68 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26483.4] assign _T_66 = _T_49 + 1'h1; // @[WidthWidget.scala 41:24:freechips.rocketchip.system.TinyConfig.fir@26486.6] assign _T_71 = _T_57 ? auto_out_d_bits_data : _T_70_0; // @[WidthWidget.scala 53:81:freechips.rocketchip.system.TinyConfig.fir@26501.4] assign _T_75 = _T_64 & _T_67; // @[WidthWidget.scala 54:25:freechips.rocketchip.system.TinyConfig.fir@26505.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_valid = auto_out_d_valid & _T_53; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_data = {auto_out_d_bits_data,_T_71}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt | _T_62; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26406.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_size = Repeater_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_source = Repeater_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_mask = _T_35 ? _T_40 : _T_39; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_data = _T_35 ? _T_37 : _T_36; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign auto_out_d_ready = auto_in_d_ready | _T_67; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26405.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@26356.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@26357.4] assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_53; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt | _T_62; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@26402.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@26411.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@26412.4] assign Repeater_io_repeat = _T_30 == 1'h0; // @[Repeater.scala 35:24:freechips.rocketchip.system.TinyConfig.fir@26413.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_data = auto_in_a_bits_data; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Repeater.scala 36:21:freechips.rocketchip.system.TinyConfig.fir@26414.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[WidthWidget.scala 142:15:freechips.rocketchip.system.TinyConfig.fir@26417.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_26 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_49 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_62 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_70_0 = _RAND_3[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_26 <= 1'h0; end else begin if (_T_31) begin if (_T_30) begin _T_26 <= 1'h0; end else begin _T_26 <= _T_33; end end end if (reset) begin _T_49 <= 1'h0; end else begin if (_T_64) begin if (_T_53) begin _T_49 <= 1'h0; end else begin _T_49 <= _T_66; end end end if (reset) begin _T_62 <= 1'h0; end else begin if (_T_64) begin if (_T_53) begin _T_62 <= 1'h0; end else begin _T_62 <= _T_63; end end end if (_T_75) begin if (_T_57) begin _T_70_0 <= auto_out_d_bits_data; end end end endmodule module Queue_23( // @[:freechips.rocketchip.system.TinyConfig.fir@26531.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@26532.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@26533.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] output io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@26534.4] ); reg _T_id [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [31:0] _RAND_0; wire _T_id__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_id__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [63:0] _T_data [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [63:0] _RAND_1; wire [63:0] _T_data__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_data__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire [63:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [1:0] _T_resp [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [31:0] _RAND_2; wire [1:0] _T_resp__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_resp__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg _T_last [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg [31:0] _RAND_3; wire _T_last__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_last__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@26537.4] reg [31:0] _RAND_4; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@26539.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26542.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26545.4] wire _GEN_10; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@26579.6] wire _GEN_16; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26573.4] wire _GEN_15; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26573.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@26557.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@26561.4] assign _T_id__T_14_addr = 1'h0; assign _T_id__T_14_data = _T_id[_T_id__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = 1'h0; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = _T_3 ? _GEN_10 : _T_6; assign _T_data__T_14_addr = 1'h0; assign _T_data__T_14_data = _T_data[_T_data__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = 1'h0; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = _T_3 ? _GEN_10 : _T_6; assign _T_resp__T_14_addr = 1'h0; assign _T_resp__T_14_data = _T_resp[_T_resp__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = 1'h0; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = _T_3 ? _GEN_10 : _T_6; assign _T_last__T_14_addr = 1'h0; assign _T_last__T_14_data = _T_last[_T_last__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = 1'h0; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = _T_3 ? _GEN_10 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@26539.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26542.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26545.4] assign _GEN_10 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@26579.6] assign _GEN_16 = _T_3 ? _GEN_10 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26573.4] assign _GEN_15 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26573.4] assign _T_11 = _GEN_16 != _GEN_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@26557.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@26561.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@26564.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@26562.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@26571.6] assign io_deq_bits_id = _T_3 ? io_enq_bits_id : _T_id__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26569.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26577.6] assign io_deq_bits_data = _T_3 ? io_enq_bits_data : _T_data__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26568.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26576.6] assign io_deq_bits_resp = _T_3 ? io_enq_bits_resp : _T_resp__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26567.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26575.6] assign io_deq_bits_last = _T_3 ? io_enq_bits_last : _T_last__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26566.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26574.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_id[initvar] = _RAND_0[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {2{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_data[initvar] = _RAND_1[63:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_resp[initvar] = _RAND_2[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_last[initvar] = _RAND_3[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26536.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module Queue_24( // @[:freechips.rocketchip.system.TinyConfig.fir@26590.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@26591.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@26592.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] input io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] output io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] output [1:0] io_deq_bits_resp // @[:freechips.rocketchip.system.TinyConfig.fir@26593.4] ); reg _T_id [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] reg [31:0] _RAND_0; wire _T_id__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_id__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] reg [1:0] _T_resp [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] reg [31:0] _RAND_1; wire [1:0] _T_resp__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_resp__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@26596.4] reg [31:0] _RAND_2; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@26598.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26601.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26604.4] wire _GEN_8; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@26632.6] wire _GEN_12; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26628.4] wire _GEN_11; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26628.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@26614.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@26618.4] assign _T_id__T_14_addr = 1'h0; assign _T_id__T_14_data = _T_id[_T_id__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = 1'h0; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = _T_3 ? _GEN_8 : _T_6; assign _T_resp__T_14_addr = 1'h0; assign _T_resp__T_14_data = _T_resp[_T_resp__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = 1'h0; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = _T_3 ? _GEN_8 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@26598.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26601.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26604.4] assign _GEN_8 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@26632.6] assign _GEN_12 = _T_3 ? _GEN_8 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26628.4] assign _GEN_11 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@26628.4] assign _T_11 = _GEN_12 != _GEN_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@26614.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@26618.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@26621.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@26619.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@26626.6] assign io_deq_bits_id = _T_3 ? io_enq_bits_id : _T_id__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26624.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26630.6] assign io_deq_bits_resp = _T_3 ? io_enq_bits_resp : _T_resp__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@26623.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@26629.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_id[initvar] = _RAND_0[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_resp[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_1 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@26595.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module AXI4ToTL( // @[:freechips.rocketchip.system.TinyConfig.fir@26643.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@26644.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@26645.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@26646.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire [1:0] Queue_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire [1:0] Queue_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire [1:0] Queue_1_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire Queue_1_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire [1:0] Queue_1_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] wire [15:0] _T_3; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26659.4] wire [22:0] _GEN_16; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26660.4] wire [22:0] _T_4; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26660.4] wire [14:0] _T_5; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@26661.4] wire [15:0] _T_6; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@26662.4] wire [15:0] _T_7; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@26663.4] wire [15:0] _T_8; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26664.4] wire [15:0] _T_9; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@26665.4] wire [15:0] _T_10; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@26666.4] wire [7:0] _T_11; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26667.4] wire [7:0] _T_12; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26668.4] wire _T_13; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26669.4] wire [7:0] _T_14; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26670.4] wire [3:0] _T_15; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26671.4] wire [3:0] _T_16; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26672.4] wire _T_17; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26673.4] wire [3:0] _T_18; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26674.4] wire [1:0] _T_19; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26675.4] wire [1:0] _T_20; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26676.4] wire _T_21; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26677.4] wire [1:0] _T_22; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26678.4] wire _T_23; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@26679.4] wire [3:0] _T_26; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26682.4] wire _T_28; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26684.4] wire [31:0] _T_31; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26687.4] wire [32:0] _T_32; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26688.4] wire [32:0] _T_33; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26689.4] wire [32:0] _T_34; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26690.4] wire _T_35; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26691.4] wire _T_36; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26692.4] wire _T_38; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26694.4] wire [31:0] _T_41; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26697.4] wire [32:0] _T_42; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26698.4] wire [32:0] _T_43; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26699.4] wire [32:0] _T_44; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26700.4] wire _T_45; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26701.4] wire [31:0] _T_46; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26702.4] wire [32:0] _T_47; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26703.4] wire [32:0] _T_48; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26704.4] wire [32:0] _T_49; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26705.4] wire _T_50; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26706.4] wire [32:0] _T_52; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26708.4] wire [32:0] _T_53; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26709.4] wire [32:0] _T_54; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26710.4] wire _T_55; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26711.4] wire [31:0] _T_56; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26712.4] wire [32:0] _T_57; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26713.4] wire [32:0] _T_58; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26714.4] wire [32:0] _T_59; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26715.4] wire _T_60; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26716.4] wire [31:0] _T_61; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26717.4] wire [32:0] _T_62; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26718.4] wire [32:0] _T_63; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26719.4] wire [32:0] _T_64; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26720.4] wire _T_65; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26721.4] wire [31:0] _T_66; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26722.4] wire [32:0] _T_67; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26723.4] wire [32:0] _T_68; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26724.4] wire [32:0] _T_69; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26725.4] wire _T_70; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26726.4] wire _T_71; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26727.4] wire _T_72; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26728.4] wire _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26729.4] wire _T_74; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26730.4] wire _T_75; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26731.4] wire _T_76; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26732.4] wire _T_78; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26734.4] wire [2:0] _T_79; // @[ToTL.scala 74:76:freechips.rocketchip.system.TinyConfig.fir@26735.4] wire [13:0] _GEN_17; // @[ToTL.scala 74:59:freechips.rocketchip.system.TinyConfig.fir@26736.4] wire [13:0] _T_80; // @[ToTL.scala 74:59:freechips.rocketchip.system.TinyConfig.fir@26736.4] wire [31:0] _T_81; // @[ToTL.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@26737.4] reg [2:0] _T_83_0; // @[ToTL.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@26742.4] reg [31:0] _RAND_0; reg [2:0] _T_83_1; // @[ToTL.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@26742.4] reg [31:0] _RAND_1; wire [2:0] _GEN_1; // @[ToTL.scala 76:59:freechips.rocketchip.system.TinyConfig.fir@26743.4] wire [1:0] _T_84; // @[ToTL.scala 76:59:freechips.rocketchip.system.TinyConfig.fir@26743.4] wire _T_87; // @[ToTL.scala 78:15:freechips.rocketchip.system.TinyConfig.fir@26746.4] wire [29:0] _T_89; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26748.4] wire [14:0] _T_90; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26749.4] wire [14:0] _T_91; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26750.4] wire _T_92; // @[ToTL.scala 78:39:freechips.rocketchip.system.TinyConfig.fir@26751.4] wire _T_93; // @[ToTL.scala 78:28:freechips.rocketchip.system.TinyConfig.fir@26752.4] wire _T_95; // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26754.4] wire _T_96; // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26755.4] wire [1:0] _T_145; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@26816.4] wire [3:0] _T_146; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@26817.4] wire [2:0] _T_147; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@26818.4] wire [2:0] _T_148; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@26819.4] wire _T_149; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@26820.4] wire _T_150; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26821.4] wire _T_151; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26822.4] wire _T_152; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26823.4] wire _T_154; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26825.4] wire _T_155; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26826.4] wire _T_157; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26828.4] wire _T_158; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26829.4] wire _T_159; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26830.4] wire _T_160; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26831.4] wire _T_161; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26832.4] wire _T_162; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26833.4] wire _T_163; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26834.4] wire _T_164; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26835.4] wire _T_165; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26836.4] wire _T_166; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26837.4] wire _T_167; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26838.4] wire _T_168; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26839.4] wire _T_169; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26840.4] wire _T_170; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26841.4] wire _T_171; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26842.4] wire _T_172; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26843.4] wire _T_173; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26844.4] wire _T_174; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26845.4] wire _T_175; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26846.4] wire _T_176; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26847.4] wire _T_177; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26848.4] wire _T_178; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26849.4] wire _T_179; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26850.4] wire _T_180; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26851.4] wire _T_181; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26852.4] wire _T_182; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26853.4] wire _T_183; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26854.4] wire _T_184; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26855.4] wire _T_185; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26856.4] wire _T_186; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26857.4] wire _T_187; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26858.4] wire _T_188; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26859.4] wire _T_189; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26860.4] wire _T_190; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26861.4] wire _T_191; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26862.4] wire _T_192; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26863.4] wire _T_193; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26864.4] wire _T_194; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26865.4] wire _T_195; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26866.4] wire _T_196; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26867.4] wire _T_197; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26868.4] wire _T_198; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26869.4] wire _T_199; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26870.4] wire _T_200; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26871.4] wire [1:0] _T_209; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@26884.4] wire _T_211; // @[ToTL.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@26886.4] wire _T_212; // @[ToTL.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@26887.4] reg [7:0] _T_402; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@27114.4] reg [31:0] _RAND_2; wire _T_403; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27115.4] wire _T_334; // @[ToTL.scala 100:34:freechips.rocketchip.system.TinyConfig.fir@27029.4] wire [1:0] _T_405; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@27117.4] reg [1:0] _T_412; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@27128.4] reg [31:0] _RAND_3; wire [1:0] _T_413; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@27129.4] wire [1:0] _T_414; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@27130.4] wire [3:0] _T_415; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@27131.4] wire [2:0] _T_416; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@27132.4] wire [3:0] _GEN_18; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@27133.4] wire [3:0] _T_417; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@27133.4] wire [2:0] _T_419; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@27135.4] wire [3:0] _T_420; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@27136.4] wire [3:0] _GEN_19; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@27137.4] wire [3:0] _T_421; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@27137.4] wire [1:0] _T_422; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@27138.4] wire [1:0] _T_423; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@27139.4] wire [1:0] _T_424; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@27140.4] wire [1:0] _T_425; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@27141.4] wire _T_434; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@27153.4] reg _T_467_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@27204.4] reg [31:0] _RAND_4; wire _T_469_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@27207.4] wire _T_470; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@27208.4] wire _T_213; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26888.4] wire _T_214; // @[ToTL.scala 85:28:freechips.rocketchip.system.TinyConfig.fir@26889.4] wire [2:0] _T_216; // @[ToTL.scala 85:43:freechips.rocketchip.system.TinyConfig.fir@26892.6] wire _T_218; // @[ToTL.scala 85:28:freechips.rocketchip.system.TinyConfig.fir@26896.4] wire [2:0] _T_220; // @[ToTL.scala 85:43:freechips.rocketchip.system.TinyConfig.fir@26899.6] wire [15:0] _T_222; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26904.4] wire [22:0] _GEN_20; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26905.4] wire [22:0] _T_223; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26905.4] wire [14:0] _T_224; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@26906.4] wire [15:0] _T_225; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@26907.4] wire [15:0] _T_226; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@26908.4] wire [15:0] _T_227; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26909.4] wire [15:0] _T_228; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@26910.4] wire [15:0] _T_229; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@26911.4] wire [7:0] _T_230; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26912.4] wire [7:0] _T_231; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26913.4] wire _T_232; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26914.4] wire [7:0] _T_233; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26915.4] wire [3:0] _T_234; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26916.4] wire [3:0] _T_235; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26917.4] wire _T_236; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26918.4] wire [3:0] _T_237; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26919.4] wire [1:0] _T_238; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26920.4] wire [1:0] _T_239; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26921.4] wire _T_240; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26922.4] wire [1:0] _T_241; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26923.4] wire _T_242; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@26924.4] wire [3:0] _T_245; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26927.4] wire _T_247; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26929.4] wire [31:0] _T_250; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26932.4] wire [32:0] _T_251; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26933.4] wire [32:0] _T_252; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26934.4] wire [32:0] _T_253; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26935.4] wire _T_254; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26936.4] wire _T_255; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26937.4] wire _T_257; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26939.4] wire [31:0] _T_260; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26942.4] wire [32:0] _T_261; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26943.4] wire [32:0] _T_262; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26944.4] wire [32:0] _T_263; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26945.4] wire _T_264; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26946.4] wire [31:0] _T_265; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26947.4] wire [32:0] _T_266; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26948.4] wire [32:0] _T_267; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26949.4] wire [32:0] _T_268; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26950.4] wire _T_269; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26951.4] wire [32:0] _T_271; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26953.4] wire [32:0] _T_272; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26954.4] wire [32:0] _T_273; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26955.4] wire _T_274; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26956.4] wire [31:0] _T_275; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26957.4] wire [32:0] _T_276; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26958.4] wire [32:0] _T_277; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26959.4] wire [32:0] _T_278; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26960.4] wire _T_279; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26961.4] wire _T_280; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26962.4] wire _T_281; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26963.4] wire _T_282; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26964.4] wire _T_283; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26965.4] wire _T_292; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26974.4] wire [31:0] _T_295; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26977.4] wire [32:0] _T_296; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26978.4] wire [32:0] _T_297; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26979.4] wire [32:0] _T_298; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26980.4] wire _T_299; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26981.4] wire _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26982.4] wire _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26984.4] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26986.4] wire [2:0] _T_305; // @[ToTL.scala 92:76:freechips.rocketchip.system.TinyConfig.fir@26987.4] wire [13:0] _GEN_21; // @[ToTL.scala 92:59:freechips.rocketchip.system.TinyConfig.fir@26988.4] wire [13:0] _T_306; // @[ToTL.scala 92:59:freechips.rocketchip.system.TinyConfig.fir@26988.4] wire [31:0] _T_307; // @[ToTL.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@26989.4] reg [2:0] _T_309_0; // @[ToTL.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26994.4] reg [31:0] _RAND_5; reg [2:0] _T_309_1; // @[ToTL.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@26994.4] reg [31:0] _RAND_6; wire [2:0] _GEN_5; // @[ToTL.scala 94:59:freechips.rocketchip.system.TinyConfig.fir@26995.4] wire [1:0] _T_310; // @[ToTL.scala 94:59:freechips.rocketchip.system.TinyConfig.fir@26995.4] wire _T_313; // @[ToTL.scala 96:15:freechips.rocketchip.system.TinyConfig.fir@26998.4] wire [29:0] _T_315; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@27000.4] wire [14:0] _T_316; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@27001.4] wire [14:0] _T_317; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@27002.4] wire _T_318; // @[ToTL.scala 96:39:freechips.rocketchip.system.TinyConfig.fir@27003.4] wire _T_319; // @[ToTL.scala 96:28:freechips.rocketchip.system.TinyConfig.fir@27004.4] wire _T_321; // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27006.4] wire _T_322; // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27007.4] wire _T_324; // @[ToTL.scala 97:46:freechips.rocketchip.system.TinyConfig.fir@27013.4] wire _T_325; // @[ToTL.scala 97:28:freechips.rocketchip.system.TinyConfig.fir@27014.4] wire _T_326; // @[ToTL.scala 97:77:freechips.rocketchip.system.TinyConfig.fir@27015.4] wire _T_327; // @[ToTL.scala 97:58:freechips.rocketchip.system.TinyConfig.fir@27016.4] wire _T_329; // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27018.4] wire _T_330; // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27019.4] wire _T_435; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@27154.4] reg _T_467_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@27204.4] reg [31:0] _RAND_7; wire _T_469_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@27207.4] wire _T_471; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@27210.4] wire _T_331; // @[ToTL.scala 98:34:freechips.rocketchip.system.TinyConfig.fir@27024.4] wire _T_332; // @[ToTL.scala 98:48:freechips.rocketchip.system.TinyConfig.fir@27025.4] wire [1:0] _T_390; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27096.4] wire _T_392; // @[ToTL.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@27098.4] wire _T_393; // @[ToTL.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@27099.4] wire _T_394; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27100.4] wire _T_395; // @[ToTL.scala 106:28:freechips.rocketchip.system.TinyConfig.fir@27101.4] wire [2:0] _T_397; // @[ToTL.scala 106:43:freechips.rocketchip.system.TinyConfig.fir@27104.6] wire _T_399; // @[ToTL.scala 106:28:freechips.rocketchip.system.TinyConfig.fir@27108.4] wire [2:0] _T_401; // @[ToTL.scala 106:43:freechips.rocketchip.system.TinyConfig.fir@27111.6] wire _T_404; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@27116.4] wire _T_407; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@27119.4] wire _T_409; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27121.4] wire _T_410; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27122.4] wire _T_426; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@27142.4] wire _T_427; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@27143.4] wire [1:0] _T_428; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@27145.6] wire [2:0] _T_429; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@27146.6] wire [1:0] _T_430; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@27147.6] wire [1:0] _T_431; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@27148.6] wire _T_437; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@27159.4] wire _T_438; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@27160.4] wire _T_441; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@27166.4] wire _T_443; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@27168.4] wire _T_446; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@27171.4] wire _T_447; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@27172.4] wire _T_450; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27175.4] wire _T_451; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27176.4] wire _T_452; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@27181.4] wire _T_453; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@27182.4] wire _T_455; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@27184.4] wire _T_457; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27186.4] wire _T_458; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27187.4] wire _T_473; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27213.4] wire _T_474; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27214.4] wire _T_475; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27215.4] wire _T_477; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@27218.4] wire _T_462; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27195.4] wire [7:0] _GEN_22; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@27196.4] wire [7:0] _T_464; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@27197.4] wire _T_468_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@27205.4] wire _T_468_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@27205.4] wire [104:0] _T_480; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27222.4] wire [118:0] _T_484; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27226.4] wire [118:0] _T_485; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27227.4] wire [104:0] _T_488; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27230.4] wire [118:0] _T_492; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27234.4] wire [118:0] _T_493; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27235.4] wire [118:0] _T_494; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27236.4] wire _T_507; // @[ToTL.scala 114:42:freechips.rocketchip.system.TinyConfig.fir@27261.4] wire _T_509; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@27263.4] wire _T_506_ready; // @[ToTL.scala 112:23:freechips.rocketchip.system.TinyConfig.fir@27259.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@27306.4] wire _T_505_ready; // @[ToTL.scala 111:23:freechips.rocketchip.system.TinyConfig.fir@27257.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@27324.4] wire _T_529; // @[ToTL.scala 118:25:freechips.rocketchip.system.TinyConfig.fir@27286.4] wire _T_510; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27264.4] wire [26:0] _T_512; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@27266.4] wire [11:0] _T_513; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@27267.4] wire [11:0] _T_514; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@27268.4] wire [8:0] _T_515; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@27269.4] wire [8:0] _T_517; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@27271.4] reg [8:0] _T_518; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@27272.4] reg [31:0] _RAND_8; wire [8:0] _T_520; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@27274.4] wire _T_521; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@27275.4] wire _T_522; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@27276.4] wire _T_523; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@27277.4] wire _T_531; // @[ToTL.scala 120:36:freechips.rocketchip.system.TinyConfig.fir@27290.4] reg [2:0] _T_538_0; // @[ToTL.scala 138:28:freechips.rocketchip.system.TinyConfig.fir@27334.4] reg [31:0] _RAND_9; reg [2:0] _T_538_1; // @[ToTL.scala 138:28:freechips.rocketchip.system.TinyConfig.fir@27334.4] reg [31:0] _RAND_10; wire _T_536_bits_id; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27325.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27327.4] wire [2:0] _GEN_11; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] wire [2:0] _GEN_13; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] wire _T_539; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] wire [1:0] _T_541; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27337.4] wire _T_543; // @[ToTL.scala 142:14:freechips.rocketchip.system.TinyConfig.fir@27339.4] wire _T_544; // @[ToTL.scala 142:14:freechips.rocketchip.system.TinyConfig.fir@27340.4] wire _T_536_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27325.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@27328.4] wire _T_553; // @[ToTL.scala 147:31:freechips.rocketchip.system.TinyConfig.fir@27356.4] wire _T_545; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27341.4] wire _T_546; // @[ToTL.scala 143:27:freechips.rocketchip.system.TinyConfig.fir@27342.4] wire [2:0] _T_548; // @[ToTL.scala 143:42:freechips.rocketchip.system.TinyConfig.fir@27345.6] wire _T_550; // @[ToTL.scala 143:27:freechips.rocketchip.system.TinyConfig.fir@27349.4] wire [2:0] _T_552; // @[ToTL.scala 143:42:freechips.rocketchip.system.TinyConfig.fir@27352.6] Queue_23 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27298.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_resp(Queue_io_enq_bits_resp), .io_enq_bits_last(Queue_io_enq_bits_last), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_resp(Queue_io_deq_bits_resp), .io_deq_bits_last(Queue_io_deq_bits_last) ); Queue_24 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27318.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_id(Queue_1_io_enq_bits_id), .io_enq_bits_resp(Queue_1_io_enq_bits_resp), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_id(Queue_1_io_deq_bits_id), .io_deq_bits_resp(Queue_1_io_deq_bits_resp) ); assign _T_3 = {auto_in_ar_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26659.4] assign _GEN_16 = {{7'd0}, _T_3}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26660.4] assign _T_4 = _GEN_16 << auto_in_ar_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26660.4] assign _T_5 = _T_4[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@26661.4] assign _T_6 = {_T_5, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@26662.4] assign _T_7 = _T_6 | 16'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@26663.4] assign _T_8 = {1'h0,_T_5}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26664.4] assign _T_9 = ~ _T_8; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@26665.4] assign _T_10 = _T_7 & _T_9; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@26666.4] assign _T_11 = _T_10[15:8]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26667.4] assign _T_12 = _T_10[7:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26668.4] assign _T_13 = _T_11 != 8'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26669.4] assign _T_14 = _T_11 | _T_12; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26670.4] assign _T_15 = _T_14[7:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26671.4] assign _T_16 = _T_14[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26672.4] assign _T_17 = _T_15 != 4'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26673.4] assign _T_18 = _T_15 | _T_16; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26674.4] assign _T_19 = _T_18[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26675.4] assign _T_20 = _T_18[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26676.4] assign _T_21 = _T_19 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26677.4] assign _T_22 = _T_19 | _T_20; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26678.4] assign _T_23 = _T_22[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@26679.4] assign _T_26 = {_T_13,_T_17,_T_21,_T_23}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26682.4] assign _T_28 = _T_26 <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26684.4] assign _T_31 = auto_in_ar_bits_addr ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26687.4] assign _T_32 = {1'b0,$signed(_T_31)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26688.4] assign _T_33 = $signed(_T_32) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26689.4] assign _T_34 = $signed(_T_33); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26690.4] assign _T_35 = $signed(_T_34) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26691.4] assign _T_36 = _T_28 & _T_35; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26692.4] assign _T_38 = _T_26 <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26694.4] assign _T_41 = auto_in_ar_bits_addr ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26697.4] assign _T_42 = {1'b0,$signed(_T_41)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26698.4] assign _T_43 = $signed(_T_42) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26699.4] assign _T_44 = $signed(_T_43); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26700.4] assign _T_45 = $signed(_T_44) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26701.4] assign _T_46 = auto_in_ar_bits_addr ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26702.4] assign _T_47 = {1'b0,$signed(_T_46)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26703.4] assign _T_48 = $signed(_T_47) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26704.4] assign _T_49 = $signed(_T_48); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26705.4] assign _T_50 = $signed(_T_49) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26706.4] assign _T_52 = {1'b0,$signed(auto_in_ar_bits_addr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26708.4] assign _T_53 = $signed(_T_52) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26709.4] assign _T_54 = $signed(_T_53); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26710.4] assign _T_55 = $signed(_T_54) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26711.4] assign _T_56 = auto_in_ar_bits_addr ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26712.4] assign _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26713.4] assign _T_58 = $signed(_T_57) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26714.4] assign _T_59 = $signed(_T_58); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26715.4] assign _T_60 = $signed(_T_59) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26716.4] assign _T_61 = auto_in_ar_bits_addr ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26717.4] assign _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26718.4] assign _T_63 = $signed(_T_62) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26719.4] assign _T_64 = $signed(_T_63); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26720.4] assign _T_65 = $signed(_T_64) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26721.4] assign _T_66 = auto_in_ar_bits_addr ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26722.4] assign _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26723.4] assign _T_68 = $signed(_T_67) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26724.4] assign _T_69 = $signed(_T_68); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26725.4] assign _T_70 = $signed(_T_69) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26726.4] assign _T_71 = _T_45 | _T_50; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26727.4] assign _T_72 = _T_71 | _T_55; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26728.4] assign _T_73 = _T_72 | _T_60; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26729.4] assign _T_74 = _T_73 | _T_65; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26730.4] assign _T_75 = _T_74 | _T_70; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26731.4] assign _T_76 = _T_38 & _T_75; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26732.4] assign _T_78 = _T_36 | _T_76; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26734.4] assign _T_79 = auto_in_ar_bits_addr[2:0]; // @[ToTL.scala 74:76:freechips.rocketchip.system.TinyConfig.fir@26735.4] assign _GEN_17 = {{11'd0}, _T_79}; // @[ToTL.scala 74:59:freechips.rocketchip.system.TinyConfig.fir@26736.4] assign _T_80 = 14'h3000 | _GEN_17; // @[ToTL.scala 74:59:freechips.rocketchip.system.TinyConfig.fir@26736.4] assign _T_81 = _T_78 ? auto_in_ar_bits_addr : {{18'd0}, _T_80}; // @[ToTL.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@26737.4] assign _GEN_1 = auto_in_ar_bits_id ? _T_83_1 : _T_83_0; // @[ToTL.scala 76:59:freechips.rocketchip.system.TinyConfig.fir@26743.4] assign _T_84 = _GEN_1[1:0]; // @[ToTL.scala 76:59:freechips.rocketchip.system.TinyConfig.fir@26743.4] assign _T_87 = auto_in_ar_valid == 1'h0; // @[ToTL.scala 78:15:freechips.rocketchip.system.TinyConfig.fir@26746.4] assign _T_89 = 30'h7fff << _T_26; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@26748.4] assign _T_90 = _T_89[14:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@26749.4] assign _T_91 = ~ _T_90; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@26750.4] assign _T_92 = _T_5 == _T_91; // @[ToTL.scala 78:39:freechips.rocketchip.system.TinyConfig.fir@26751.4] assign _T_93 = _T_87 | _T_92; // @[ToTL.scala 78:28:freechips.rocketchip.system.TinyConfig.fir@26752.4] assign _T_95 = _T_93 | reset; // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26754.4] assign _T_96 = _T_95 == 1'h0; // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26755.4] assign _T_145 = _T_26[1:0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@26816.4] assign _T_146 = 4'h1 << _T_145; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@26817.4] assign _T_147 = _T_146[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@26818.4] assign _T_148 = _T_147 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@26819.4] assign _T_149 = _T_26 >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@26820.4] assign _T_150 = _T_148[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26821.4] assign _T_151 = _T_81[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26822.4] assign _T_152 = _T_151 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26823.4] assign _T_154 = _T_150 & _T_152; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26825.4] assign _T_155 = _T_149 | _T_154; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26826.4] assign _T_157 = _T_150 & _T_151; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26828.4] assign _T_158 = _T_149 | _T_157; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26829.4] assign _T_159 = _T_148[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26830.4] assign _T_160 = _T_81[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26831.4] assign _T_161 = _T_160 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26832.4] assign _T_162 = _T_152 & _T_161; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26833.4] assign _T_163 = _T_159 & _T_162; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26834.4] assign _T_164 = _T_155 | _T_163; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26835.4] assign _T_165 = _T_152 & _T_160; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26836.4] assign _T_166 = _T_159 & _T_165; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26837.4] assign _T_167 = _T_155 | _T_166; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26838.4] assign _T_168 = _T_151 & _T_161; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26839.4] assign _T_169 = _T_159 & _T_168; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26840.4] assign _T_170 = _T_158 | _T_169; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26841.4] assign _T_171 = _T_151 & _T_160; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26842.4] assign _T_172 = _T_159 & _T_171; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26843.4] assign _T_173 = _T_158 | _T_172; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26844.4] assign _T_174 = _T_148[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@26845.4] assign _T_175 = _T_81[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@26846.4] assign _T_176 = _T_175 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@26847.4] assign _T_177 = _T_162 & _T_176; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26848.4] assign _T_178 = _T_174 & _T_177; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26849.4] assign _T_179 = _T_164 | _T_178; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26850.4] assign _T_180 = _T_162 & _T_175; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26851.4] assign _T_181 = _T_174 & _T_180; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26852.4] assign _T_182 = _T_164 | _T_181; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26853.4] assign _T_183 = _T_165 & _T_176; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26854.4] assign _T_184 = _T_174 & _T_183; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26855.4] assign _T_185 = _T_167 | _T_184; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26856.4] assign _T_186 = _T_165 & _T_175; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26857.4] assign _T_187 = _T_174 & _T_186; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26858.4] assign _T_188 = _T_167 | _T_187; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26859.4] assign _T_189 = _T_168 & _T_176; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26860.4] assign _T_190 = _T_174 & _T_189; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26861.4] assign _T_191 = _T_170 | _T_190; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26862.4] assign _T_192 = _T_168 & _T_175; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26863.4] assign _T_193 = _T_174 & _T_192; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26864.4] assign _T_194 = _T_170 | _T_193; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26865.4] assign _T_195 = _T_171 & _T_176; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26866.4] assign _T_196 = _T_174 & _T_195; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26867.4] assign _T_197 = _T_173 | _T_196; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26868.4] assign _T_198 = _T_171 & _T_175; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@26869.4] assign _T_199 = _T_174 & _T_198; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@26870.4] assign _T_200 = _T_173 | _T_199; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@26871.4] assign _T_209 = 2'h1 << auto_in_ar_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@26884.4] assign _T_211 = _T_209[0]; // @[ToTL.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@26886.4] assign _T_212 = _T_209[1]; // @[ToTL.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@26887.4] assign _T_403 = _T_402 == 8'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27115.4] assign _T_334 = auto_in_aw_valid & auto_in_w_valid; // @[ToTL.scala 100:34:freechips.rocketchip.system.TinyConfig.fir@27029.4] assign _T_405 = {_T_334,auto_in_ar_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@27117.4] assign _T_413 = ~ _T_412; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@27129.4] assign _T_414 = _T_405 & _T_413; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@27130.4] assign _T_415 = {_T_414,_T_334,auto_in_ar_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@27131.4] assign _T_416 = _T_415[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@27132.4] assign _GEN_18 = {{1'd0}, _T_416}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@27133.4] assign _T_417 = _T_415 | _GEN_18; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@27133.4] assign _T_419 = _T_417[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@27135.4] assign _T_420 = {_T_412, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@27136.4] assign _GEN_19 = {{1'd0}, _T_419}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@27137.4] assign _T_421 = _GEN_19 | _T_420; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@27137.4] assign _T_422 = _T_421[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@27138.4] assign _T_423 = _T_421[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@27139.4] assign _T_424 = _T_422 & _T_423; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@27140.4] assign _T_425 = ~ _T_424; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@27141.4] assign _T_434 = _T_425[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@27153.4] assign _T_469_0 = _T_403 ? _T_434 : _T_467_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@27207.4] assign _T_470 = auto_out_a_ready & _T_469_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@27208.4] assign _T_213 = _T_470 & auto_in_ar_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@26888.4] assign _T_214 = _T_213 & _T_211; // @[ToTL.scala 85:28:freechips.rocketchip.system.TinyConfig.fir@26889.4] assign _T_216 = _T_83_0 + 3'h1; // @[ToTL.scala 85:43:freechips.rocketchip.system.TinyConfig.fir@26892.6] assign _T_218 = _T_213 & _T_212; // @[ToTL.scala 85:28:freechips.rocketchip.system.TinyConfig.fir@26896.4] assign _T_220 = _T_83_1 + 3'h1; // @[ToTL.scala 85:43:freechips.rocketchip.system.TinyConfig.fir@26899.6] assign _T_222 = {auto_in_aw_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26904.4] assign _GEN_20 = {{7'd0}, _T_222}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26905.4] assign _T_223 = _GEN_20 << auto_in_aw_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@26905.4] assign _T_224 = _T_223[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@26906.4] assign _T_225 = {_T_224, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@26907.4] assign _T_226 = _T_225 | 16'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@26908.4] assign _T_227 = {1'h0,_T_224}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26909.4] assign _T_228 = ~ _T_227; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@26910.4] assign _T_229 = _T_226 & _T_228; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@26911.4] assign _T_230 = _T_229[15:8]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26912.4] assign _T_231 = _T_229[7:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26913.4] assign _T_232 = _T_230 != 8'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26914.4] assign _T_233 = _T_230 | _T_231; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26915.4] assign _T_234 = _T_233[7:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26916.4] assign _T_235 = _T_233[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26917.4] assign _T_236 = _T_234 != 4'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26918.4] assign _T_237 = _T_234 | _T_235; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26919.4] assign _T_238 = _T_237[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@26920.4] assign _T_239 = _T_237[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@26921.4] assign _T_240 = _T_238 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@26922.4] assign _T_241 = _T_238 | _T_239; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@26923.4] assign _T_242 = _T_241[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@26924.4] assign _T_245 = {_T_232,_T_236,_T_240,_T_242}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@26927.4] assign _T_247 = _T_245 <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26929.4] assign _T_250 = auto_in_aw_bits_addr ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26932.4] assign _T_251 = {1'b0,$signed(_T_250)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26933.4] assign _T_252 = $signed(_T_251) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26934.4] assign _T_253 = $signed(_T_252); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26935.4] assign _T_254 = $signed(_T_253) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26936.4] assign _T_255 = _T_247 & _T_254; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26937.4] assign _T_257 = _T_245 <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26939.4] assign _T_260 = auto_in_aw_bits_addr ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26942.4] assign _T_261 = {1'b0,$signed(_T_260)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26943.4] assign _T_262 = $signed(_T_261) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26944.4] assign _T_263 = $signed(_T_262); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26945.4] assign _T_264 = $signed(_T_263) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26946.4] assign _T_265 = auto_in_aw_bits_addr ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26947.4] assign _T_266 = {1'b0,$signed(_T_265)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26948.4] assign _T_267 = $signed(_T_266) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26949.4] assign _T_268 = $signed(_T_267); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26950.4] assign _T_269 = $signed(_T_268) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26951.4] assign _T_271 = {1'b0,$signed(auto_in_aw_bits_addr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26953.4] assign _T_272 = $signed(_T_271) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26954.4] assign _T_273 = $signed(_T_272); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26955.4] assign _T_274 = $signed(_T_273) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26956.4] assign _T_275 = auto_in_aw_bits_addr ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26957.4] assign _T_276 = {1'b0,$signed(_T_275)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26958.4] assign _T_277 = $signed(_T_276) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26959.4] assign _T_278 = $signed(_T_277); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26960.4] assign _T_279 = $signed(_T_278) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26961.4] assign _T_280 = _T_264 | _T_269; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26962.4] assign _T_281 = _T_280 | _T_274; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26963.4] assign _T_282 = _T_281 | _T_279; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@26964.4] assign _T_283 = _T_257 & _T_282; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26965.4] assign _T_292 = _T_245 <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@26974.4] assign _T_295 = auto_in_aw_bits_addr ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@26977.4] assign _T_296 = {1'b0,$signed(_T_295)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@26978.4] assign _T_297 = $signed(_T_296) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26979.4] assign _T_298 = $signed(_T_297); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@26980.4] assign _T_299 = $signed(_T_298) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@26981.4] assign _T_300 = _T_292 & _T_299; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@26982.4] assign _T_302 = _T_255 | _T_283; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26984.4] assign _T_304 = _T_302 | _T_300; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@26986.4] assign _T_305 = auto_in_aw_bits_addr[2:0]; // @[ToTL.scala 92:76:freechips.rocketchip.system.TinyConfig.fir@26987.4] assign _GEN_21 = {{11'd0}, _T_305}; // @[ToTL.scala 92:59:freechips.rocketchip.system.TinyConfig.fir@26988.4] assign _T_306 = 14'h3000 | _GEN_21; // @[ToTL.scala 92:59:freechips.rocketchip.system.TinyConfig.fir@26988.4] assign _T_307 = _T_304 ? auto_in_aw_bits_addr : {{18'd0}, _T_306}; // @[ToTL.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@26989.4] assign _GEN_5 = auto_in_aw_bits_id ? _T_309_1 : _T_309_0; // @[ToTL.scala 94:59:freechips.rocketchip.system.TinyConfig.fir@26995.4] assign _T_310 = _GEN_5[1:0]; // @[ToTL.scala 94:59:freechips.rocketchip.system.TinyConfig.fir@26995.4] assign _T_313 = auto_in_aw_valid == 1'h0; // @[ToTL.scala 96:15:freechips.rocketchip.system.TinyConfig.fir@26998.4] assign _T_315 = 30'h7fff << _T_245; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@27000.4] assign _T_316 = _T_315[14:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@27001.4] assign _T_317 = ~ _T_316; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@27002.4] assign _T_318 = _T_224 == _T_317; // @[ToTL.scala 96:39:freechips.rocketchip.system.TinyConfig.fir@27003.4] assign _T_319 = _T_313 | _T_318; // @[ToTL.scala 96:28:freechips.rocketchip.system.TinyConfig.fir@27004.4] assign _T_321 = _T_319 | reset; // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27006.4] assign _T_322 = _T_321 == 1'h0; // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27007.4] assign _T_324 = auto_in_aw_bits_len == 8'h0; // @[ToTL.scala 97:46:freechips.rocketchip.system.TinyConfig.fir@27013.4] assign _T_325 = _T_313 | _T_324; // @[ToTL.scala 97:28:freechips.rocketchip.system.TinyConfig.fir@27014.4] assign _T_326 = auto_in_aw_bits_size == 3'h3; // @[ToTL.scala 97:77:freechips.rocketchip.system.TinyConfig.fir@27015.4] assign _T_327 = _T_325 | _T_326; // @[ToTL.scala 97:58:freechips.rocketchip.system.TinyConfig.fir@27016.4] assign _T_329 = _T_327 | reset; // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27018.4] assign _T_330 = _T_329 == 1'h0; // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27019.4] assign _T_435 = _T_425[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@27154.4] assign _T_469_1 = _T_403 ? _T_435 : _T_467_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@27207.4] assign _T_471 = auto_out_a_ready & _T_469_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@27210.4] assign _T_331 = _T_471 & auto_in_w_valid; // @[ToTL.scala 98:34:freechips.rocketchip.system.TinyConfig.fir@27024.4] assign _T_332 = _T_331 & auto_in_w_bits_last; // @[ToTL.scala 98:48:freechips.rocketchip.system.TinyConfig.fir@27025.4] assign _T_390 = 2'h1 << auto_in_aw_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27096.4] assign _T_392 = _T_390[0]; // @[ToTL.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@27098.4] assign _T_393 = _T_390[1]; // @[ToTL.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@27099.4] assign _T_394 = _T_332 & auto_in_aw_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27100.4] assign _T_395 = _T_394 & _T_392; // @[ToTL.scala 106:28:freechips.rocketchip.system.TinyConfig.fir@27101.4] assign _T_397 = _T_309_0 + 3'h1; // @[ToTL.scala 106:43:freechips.rocketchip.system.TinyConfig.fir@27104.6] assign _T_399 = _T_394 & _T_393; // @[ToTL.scala 106:28:freechips.rocketchip.system.TinyConfig.fir@27108.4] assign _T_401 = _T_309_1 + 3'h1; // @[ToTL.scala 106:43:freechips.rocketchip.system.TinyConfig.fir@27111.6] assign _T_404 = _T_403 & auto_out_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@27116.4] assign _T_407 = _T_405 == _T_405; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@27119.4] assign _T_409 = _T_407 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27121.4] assign _T_410 = _T_409 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27122.4] assign _T_426 = _T_405 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@27142.4] assign _T_427 = _T_404 & _T_426; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@27143.4] assign _T_428 = _T_425 & _T_405; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@27145.6] assign _T_429 = {_T_428, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@27146.6] assign _T_430 = _T_429[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@27147.6] assign _T_431 = _T_428 | _T_430; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@27148.6] assign _T_437 = _T_434 & auto_in_ar_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@27159.4] assign _T_438 = _T_435 & _T_334; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@27160.4] assign _T_441 = _T_437 | _T_438; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@27166.4] assign _T_443 = _T_437 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@27168.4] assign _T_446 = _T_438 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@27171.4] assign _T_447 = _T_443 | _T_446; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@27172.4] assign _T_450 = _T_447 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27175.4] assign _T_451 = _T_450 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27176.4] assign _T_452 = auto_in_ar_valid | _T_334; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@27181.4] assign _T_453 = _T_452 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@27182.4] assign _T_455 = _T_453 | _T_441; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@27184.4] assign _T_457 = _T_455 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27186.4] assign _T_458 = _T_457 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27187.4] assign _T_473 = _T_467_0 ? auto_in_ar_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27213.4] assign _T_474 = _T_467_1 ? _T_334 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27214.4] assign _T_475 = _T_473 | _T_474; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27215.4] assign _T_477 = _T_403 ? _T_452 : _T_475; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@27218.4] assign _T_462 = auto_out_a_ready & _T_477; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27195.4] assign _GEN_22 = {{7'd0}, _T_462}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@27196.4] assign _T_464 = _T_402 - _GEN_22; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@27197.4] assign _T_468_0 = _T_403 ? _T_437 : _T_467_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@27205.4] assign _T_468_1 = _T_403 ? _T_438 : _T_467_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@27205.4] assign _T_480 = {_T_81,_T_200,_T_197,_T_194,_T_191,_T_188,_T_185,_T_182,_T_179,65'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27222.4] assign _T_484 = {6'h20,_T_13,_T_17,_T_21,_T_23,auto_in_ar_bits_id,_T_84,1'h0,_T_480}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27226.4] assign _T_485 = _T_468_0 ? _T_484 : 119'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27227.4] assign _T_488 = {_T_307,auto_in_w_bits_strb,auto_in_w_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27230.4] assign _T_492 = {6'h8,_T_232,_T_236,_T_240,_T_242,auto_in_aw_bits_id,_T_310,1'h1,_T_488}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27234.4] assign _T_493 = _T_468_1 ? _T_492 : 119'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27235.4] assign _T_494 = _T_485 | _T_493; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@27236.4] assign _T_507 = auto_out_d_bits_denied | auto_out_d_bits_corrupt; // @[ToTL.scala 114:42:freechips.rocketchip.system.TinyConfig.fir@27261.4] assign _T_509 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@27263.4] assign _T_506_ready = Queue_io_enq_ready; // @[ToTL.scala 112:23:freechips.rocketchip.system.TinyConfig.fir@27259.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@27306.4] assign _T_505_ready = Queue_1_io_enq_ready; // @[ToTL.scala 111:23:freechips.rocketchip.system.TinyConfig.fir@27257.4 Decoupled.scala 297:17:freechips.rocketchip.system.TinyConfig.fir@27324.4] assign _T_529 = _T_509 ? _T_506_ready : _T_505_ready; // @[ToTL.scala 118:25:freechips.rocketchip.system.TinyConfig.fir@27286.4] assign _T_510 = _T_529 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27264.4] assign _T_512 = 27'hfff << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@27266.4] assign _T_513 = _T_512[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@27267.4] assign _T_514 = ~ _T_513; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@27268.4] assign _T_515 = _T_514[11:3]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@27269.4] assign _T_517 = _T_509 ? _T_515 : 9'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@27271.4] assign _T_520 = _T_518 - 9'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@27274.4] assign _T_521 = _T_518 == 9'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@27275.4] assign _T_522 = _T_518 == 9'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@27276.4] assign _T_523 = _T_517 == 9'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@27277.4] assign _T_531 = _T_509 == 1'h0; // @[ToTL.scala 120:36:freechips.rocketchip.system.TinyConfig.fir@27290.4] assign _T_536_bits_id = Queue_1_io_deq_bits_id; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27325.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27327.4] assign _GEN_11 = _T_536_bits_id ? _T_538_1 : _T_538_0; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] assign _GEN_13 = _T_536_bits_id ? _T_309_1 : _T_309_0; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] assign _T_539 = _GEN_11 != _GEN_13; // @[ToTL.scala 139:43:freechips.rocketchip.system.TinyConfig.fir@27335.4] assign _T_541 = 2'h1 << _T_536_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27337.4] assign _T_543 = _T_541[0]; // @[ToTL.scala 142:14:freechips.rocketchip.system.TinyConfig.fir@27339.4] assign _T_544 = _T_541[1]; // @[ToTL.scala 142:14:freechips.rocketchip.system.TinyConfig.fir@27340.4] assign _T_536_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27325.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@27328.4] assign _T_553 = _T_536_valid & _T_539; // @[ToTL.scala 147:31:freechips.rocketchip.system.TinyConfig.fir@27356.4] assign _T_545 = auto_in_b_ready & _T_553; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27341.4] assign _T_546 = _T_545 & _T_543; // @[ToTL.scala 143:27:freechips.rocketchip.system.TinyConfig.fir@27342.4] assign _T_548 = _T_538_0 + 3'h1; // @[ToTL.scala 143:42:freechips.rocketchip.system.TinyConfig.fir@27345.6] assign _T_550 = _T_545 & _T_544; // @[ToTL.scala 143:27:freechips.rocketchip.system.TinyConfig.fir@27349.4] assign _T_552 = _T_538_1 + 3'h1; // @[ToTL.scala 143:42:freechips.rocketchip.system.TinyConfig.fir@27352.6] assign auto_in_aw_ready = _T_331 & auto_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_w_ready = _T_471 & auto_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_b_valid = _T_536_valid & _T_539; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_b_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_b_bits_resp = Queue_1_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_ar_ready = auto_out_a_ready & _T_469_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_r_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_r_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_r_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_r_bits_resp = Queue_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_in_r_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@26656.4] assign auto_out_a_valid = _T_403 ? _T_452 : _T_475; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_opcode = _T_494[118:116]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_param = _T_494[115:113]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_size = _T_494[112:109]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_source = _T_494[108:105]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_address = _T_494[104:73]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_mask = _T_494[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_data = _T_494[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_a_bits_corrupt = _T_494[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign auto_out_d_ready = _T_509 ? _T_506_ready : _T_505_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@26655.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27299.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27300.4] assign Queue_io_enq_valid = auto_out_d_valid & _T_509; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@27301.4] assign Queue_io_enq_bits_id = auto_out_d_bits_source[3:3]; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27305.4] assign Queue_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27304.4] assign Queue_io_enq_bits_resp = _T_507 ? 2'h2 : 2'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27303.4] assign Queue_io_enq_bits_last = _T_522 | _T_523; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27302.4] assign Queue_io_deq_ready = auto_in_r_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@27313.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27319.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27320.4] assign Queue_1_io_enq_valid = auto_out_d_valid & _T_531; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@27321.4] assign Queue_1_io_enq_bits_id = auto_out_d_bits_source[3:3]; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27323.4] assign Queue_1_io_enq_bits_resp = _T_507 ? 2'h2 : 2'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27322.4] assign Queue_1_io_deq_ready = auto_in_b_ready & _T_539; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@27329.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_83_0 = _RAND_0[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_83_1 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_402 = _RAND_2[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_412 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_467_0 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_309_0 = _RAND_5[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_309_1 = _RAND_6[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_467_1 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_518 = _RAND_8[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_538_0 = _RAND_9[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_538_1 = _RAND_10[2:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_83_0 <= 3'h0; end else begin if (_T_214) begin _T_83_0 <= _T_216; end end if (reset) begin _T_83_1 <= 3'h0; end else begin if (_T_218) begin _T_83_1 <= _T_220; end end if (reset) begin _T_402 <= 8'h0; end else begin if (_T_404) begin if (_T_438) begin _T_402 <= auto_in_aw_bits_len; end else begin _T_402 <= 8'h0; end end else begin _T_402 <= _T_464; end end if (reset) begin _T_412 <= 2'h3; end else begin if (_T_427) begin _T_412 <= _T_431; end end if (reset) begin _T_467_0 <= 1'h0; end else begin if (_T_403) begin _T_467_0 <= _T_437; end end if (reset) begin _T_309_0 <= 3'h0; end else begin if (_T_395) begin _T_309_0 <= _T_397; end end if (reset) begin _T_309_1 <= 3'h0; end else begin if (_T_399) begin _T_309_1 <= _T_401; end end if (reset) begin _T_467_1 <= 1'h0; end else begin if (_T_403) begin _T_467_1 <= _T_438; end end if (reset) begin _T_518 <= 9'h0; end else begin if (_T_510) begin if (_T_521) begin if (_T_509) begin _T_518 <= _T_515; end else begin _T_518 <= 9'h0; end end else begin _T_518 <= _T_520; end end end if (reset) begin _T_538_0 <= 3'h0; end else begin if (_T_546) begin _T_538_0 <= _T_548; end end if (reset) begin _T_538_1 <= 3'h0; end else begin if (_T_550) begin _T_538_1 <= _T_552; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_96) begin $fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:78 assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned\n"); // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26757.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_96) begin $fatal; // @[ToTL.scala 78:14:freechips.rocketchip.system.TinyConfig.fir@26758.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_322) begin $fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:96 assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned\n"); // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27009.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_322) begin $fatal; // @[ToTL.scala 96:14:freechips.rocketchip.system.TinyConfig.fir@27010.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_330) begin $fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:97 assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned\n"); // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27021.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_330) begin $fatal; // @[ToTL.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@27022.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_410) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27124.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_410) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@27125.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_451) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27178.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_451) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@27179.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_458) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27189.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_458) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@27190.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_25( // @[:freechips.rocketchip.system.TinyConfig.fir@27370.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@27371.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@27372.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] input [7:0] io_enq_bits, // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] output [7:0] io_deq_bits // @[:freechips.rocketchip.system.TinyConfig.fir@27373.4] ); reg [7:0] _T [0:3]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] reg [31:0] _RAND_0; wire [7:0] _T__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] wire [1:0] _T__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] wire [7:0] _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] wire [1:0] _T__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] wire _T__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] wire _T__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] reg [1:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@27379.4] reg [31:0] _RAND_1; reg [1:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@27380.4] reg [31:0] _RAND_2; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@27381.4] reg [31:0] _RAND_3; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@27382.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27383.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@27384.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@27385.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27386.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27390.4] wire [1:0] _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@27399.6] wire [1:0] _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@27405.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27408.4] assign _T__T_18_addr = value_1; assign _T__T_18_data = _T[_T__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] assign _T__T_10_data = io_enq_bits; assign _T__T_10_addr = value; assign _T__T_10_mask = 1'h1; assign _T__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@27382.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27383.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@27384.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@27385.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27386.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27390.4] assign _T_12 = value + 2'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@27399.6] assign _T_14 = value_1 + 2'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@27405.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27408.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@27415.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@27413.4] assign io_deq_bits = _T__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27417.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 4; initvar = initvar+1) _T[initvar] = _RAND_0[7:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; value = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; value_1 = _RAND_2[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T__T_10_en & _T__T_10_mask) begin _T[_T__T_10_addr] <= _T__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27378.4] end if (reset) begin value <= 2'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 2'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module AXI4UserYanker_1( // @[:freechips.rocketchip.system.TinyConfig.fir@27590.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@27591.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@27592.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [7:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [7:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [7:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [7:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@27593.4] ); wire Queue_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire [7:0] Queue_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire [7:0] Queue_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] wire Queue_1_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_1_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_1_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_1_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire [7:0] Queue_1_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_1_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_1_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire [7:0] Queue_1_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] wire Queue_2_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_2_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_2_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_2_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire [7:0] Queue_2_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_2_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_2_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire [7:0] Queue_2_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] wire Queue_3_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire Queue_3_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire Queue_3_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire Queue_3_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire [7:0] Queue_3_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire Queue_3_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire Queue_3_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire [7:0] Queue_3_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] wire _T_2_0; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27620.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27622.4] wire _T_2_1; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27620.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27623.4] wire _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@27624.4] wire _T_7; // @[UserYanker.scala 54:15:freechips.rocketchip.system.TinyConfig.fir@27637.4] wire _T_5_0; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27629.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27631.4] wire _T_5_1; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27629.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27632.4] wire _GEN_3; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27638.4] wire _T_8; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27638.4] wire _T_10; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27640.4] wire _T_11; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27641.4] wire [7:0] _T_6_0; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27633.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27635.4] wire [7:0] _T_6_1; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27633.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27636.4] wire [1:0] _T_13; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27649.4] wire _T_15; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@27651.4] wire _T_16; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@27652.4] wire [1:0] _T_18; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27654.4] wire _T_20; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@27656.4] wire _T_21; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@27657.4] wire _T_22; // @[UserYanker.scala 61:37:freechips.rocketchip.system.TinyConfig.fir@27658.4] wire _T_23; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@27659.4] wire _T_25; // @[UserYanker.scala 62:37:freechips.rocketchip.system.TinyConfig.fir@27662.4] wire _T_28; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@27667.4] wire _T_32_0; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27674.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27676.4] wire _T_32_1; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27674.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27677.4] wire _GEN_7; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@27678.4] wire _T_37; // @[UserYanker.scala 75:15:freechips.rocketchip.system.TinyConfig.fir@27691.4] wire _T_35_0; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27683.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27685.4] wire _T_35_1; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27683.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27686.4] wire _GEN_9; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@27692.4] wire _T_38; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@27692.4] wire _T_40; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27694.4] wire _T_41; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27695.4] wire [7:0] _T_36_0; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27687.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27689.4] wire [7:0] _T_36_1; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27687.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27690.4] wire [1:0] _T_43; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27703.4] wire _T_45; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@27705.4] wire _T_46; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@27706.4] wire [1:0] _T_48; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27708.4] wire _T_50; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@27710.4] wire _T_51; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@27711.4] wire _T_52; // @[UserYanker.scala 82:37:freechips.rocketchip.system.TinyConfig.fir@27712.4] wire _T_54; // @[UserYanker.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@27715.4] Queue_25 Queue ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27604.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits(Queue_io_enq_bits), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits(Queue_io_deq_bits) ); Queue_25 Queue_1 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27608.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits(Queue_1_io_enq_bits), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits(Queue_1_io_deq_bits) ); Queue_25 Queue_2 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27612.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits(Queue_2_io_enq_bits), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits(Queue_2_io_deq_bits) ); Queue_25 Queue_3 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.TinyConfig.fir@27616.4] .clock(Queue_3_clock), .reset(Queue_3_reset), .io_enq_ready(Queue_3_io_enq_ready), .io_enq_valid(Queue_3_io_enq_valid), .io_enq_bits(Queue_3_io_enq_bits), .io_deq_ready(Queue_3_io_deq_ready), .io_deq_valid(Queue_3_io_deq_valid), .io_deq_bits(Queue_3_io_deq_bits) ); assign _T_2_0 = Queue_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27620.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27622.4] assign _T_2_1 = Queue_1_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27620.4 UserYanker.scala 46:25:freechips.rocketchip.system.TinyConfig.fir@27623.4] assign _GEN_1 = auto_in_ar_bits_id ? _T_2_1 : _T_2_0; // @[UserYanker.scala 47:36:freechips.rocketchip.system.TinyConfig.fir@27624.4] assign _T_7 = auto_out_r_valid == 1'h0; // @[UserYanker.scala 54:15:freechips.rocketchip.system.TinyConfig.fir@27637.4] assign _T_5_0 = Queue_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27629.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27631.4] assign _T_5_1 = Queue_1_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27629.4 UserYanker.scala 52:24:freechips.rocketchip.system.TinyConfig.fir@27632.4] assign _GEN_3 = auto_out_r_bits_id ? _T_5_1 : _T_5_0; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27638.4] assign _T_8 = _T_7 | _GEN_3; // @[UserYanker.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@27638.4] assign _T_10 = _T_8 | reset; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27640.4] assign _T_11 = _T_10 == 1'h0; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27641.4] assign _T_6_0 = Queue_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27633.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27635.4] assign _T_6_1 = Queue_1_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27633.4 UserYanker.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@27636.4] assign _T_13 = 2'h1 << auto_in_ar_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27649.4] assign _T_15 = _T_13[0]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@27651.4] assign _T_16 = _T_13[1]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.TinyConfig.fir@27652.4] assign _T_18 = 2'h1 << auto_out_r_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27654.4] assign _T_20 = _T_18[0]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@27656.4] assign _T_21 = _T_18[1]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.TinyConfig.fir@27657.4] assign _T_22 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala 61:37:freechips.rocketchip.system.TinyConfig.fir@27658.4] assign _T_23 = _T_22 & _T_20; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@27659.4] assign _T_25 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala 62:37:freechips.rocketchip.system.TinyConfig.fir@27662.4] assign _T_28 = _T_22 & _T_21; // @[UserYanker.scala 61:53:freechips.rocketchip.system.TinyConfig.fir@27667.4] assign _T_32_0 = Queue_2_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27674.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27676.4] assign _T_32_1 = Queue_3_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27674.4 UserYanker.scala 67:25:freechips.rocketchip.system.TinyConfig.fir@27677.4] assign _GEN_7 = auto_in_aw_bits_id ? _T_32_1 : _T_32_0; // @[UserYanker.scala 68:36:freechips.rocketchip.system.TinyConfig.fir@27678.4] assign _T_37 = auto_out_b_valid == 1'h0; // @[UserYanker.scala 75:15:freechips.rocketchip.system.TinyConfig.fir@27691.4] assign _T_35_0 = Queue_2_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27683.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27685.4] assign _T_35_1 = Queue_3_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27683.4 UserYanker.scala 73:24:freechips.rocketchip.system.TinyConfig.fir@27686.4] assign _GEN_9 = auto_out_b_bits_id ? _T_35_1 : _T_35_0; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@27692.4] assign _T_38 = _T_37 | _GEN_9; // @[UserYanker.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@27692.4] assign _T_40 = _T_38 | reset; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27694.4] assign _T_41 = _T_40 == 1'h0; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27695.4] assign _T_36_0 = Queue_2_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27687.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27689.4] assign _T_36_1 = Queue_3_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27687.4 UserYanker.scala 74:23:freechips.rocketchip.system.TinyConfig.fir@27690.4] assign _T_43 = 2'h1 << auto_in_aw_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27703.4] assign _T_45 = _T_43[0]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@27705.4] assign _T_46 = _T_43[1]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.TinyConfig.fir@27706.4] assign _T_48 = 2'h1 << auto_out_b_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@27708.4] assign _T_50 = _T_48[0]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@27710.4] assign _T_51 = _T_48[1]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.TinyConfig.fir@27711.4] assign _T_52 = auto_out_b_valid & auto_in_b_ready; // @[UserYanker.scala 82:37:freechips.rocketchip.system.TinyConfig.fir@27712.4] assign _T_54 = auto_in_aw_valid & auto_out_aw_ready; // @[UserYanker.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@27715.4] assign auto_in_aw_ready = auto_out_aw_ready & _GEN_7; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_b_bits_user = auto_out_b_bits_id ? _T_36_1 : _T_36_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_ar_ready = auto_out_ar_ready & _GEN_1; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_bits_user = auto_out_r_bits_id ? _T_6_1 : _T_6_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27603.4] assign auto_out_aw_valid = auto_in_aw_valid & _GEN_7; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_ar_valid = auto_in_ar_valid & _GEN_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27602.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27606.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27607.4] assign Queue_io_enq_valid = _T_25 & _T_15; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@27664.4] assign Queue_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@27665.4] assign Queue_io_deq_ready = _T_23 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@27661.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27610.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27611.4] assign Queue_1_io_enq_valid = _T_25 & _T_16; // @[UserYanker.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@27672.4] assign Queue_1_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@27673.4] assign Queue_1_io_deq_ready = _T_28 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@27669.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27614.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27615.4] assign Queue_2_io_enq_valid = _T_54 & _T_45; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@27717.4] assign Queue_2_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@27718.4] assign Queue_2_io_deq_ready = _T_52 & _T_50; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@27714.4] assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27618.4] assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27619.4] assign Queue_3_io_enq_valid = _T_54 & _T_46; // @[UserYanker.scala 83:21:freechips.rocketchip.system.TinyConfig.fir@27724.4] assign Queue_3_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.TinyConfig.fir@27725.4] assign Queue_3_io_deq_ready = _T_52 & _T_51; // @[UserYanker.scala 82:21:freechips.rocketchip.system.TinyConfig.fir@27721.4] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_11) begin $fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:54 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27643.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_11) begin $fatal; // @[UserYanker.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@27644.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_41) begin $fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:75 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27697.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_41) begin $fatal; // @[UserYanker.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@27698.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_29( // @[:freechips.rocketchip.system.TinyConfig.fir@27728.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@27729.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@27730.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input [31:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input [1:0] io_enq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input [6:0] io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output [31:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] output [6:0] io_deq_bits_user // @[:freechips.rocketchip.system.TinyConfig.fir@27731.4] ); reg _T_id [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_0; wire _T_id__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_id__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _T_addr [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_1; wire [31:0] _T_addr__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_addr__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire [31:0] _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_addr__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_addr__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_addr__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [7:0] _T_len [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_2; wire [7:0] _T_len__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_len__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire [7:0] _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_len__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_len__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_len__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [2:0] _T_size [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_3; wire [2:0] _T_size__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_size__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [1:0] _T_burst [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_4; wire [1:0] _T_burst__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_burst__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire [1:0] _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_burst__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_burst__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_burst__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [6:0] _T_user [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg [31:0] _RAND_5; wire [6:0] _T_user__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_user__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire [6:0] _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@27734.4] reg [31:0] _RAND_6; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27736.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27739.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27742.4] wire _GEN_16; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@27794.6] wire _GEN_28; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27782.4] wire _GEN_27; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27782.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27760.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@27764.4] assign _T_id__T_14_addr = 1'h0; assign _T_id__T_14_data = _T_id[_T_id__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = 1'h0; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_addr__T_14_addr = 1'h0; assign _T_addr__T_14_data = _T_addr[_T_addr__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_addr__T_10_data = io_enq_bits_addr; assign _T_addr__T_10_addr = 1'h0; assign _T_addr__T_10_mask = 1'h1; assign _T_addr__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_len__T_14_addr = 1'h0; assign _T_len__T_14_data = _T_len[_T_len__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_len__T_10_data = io_enq_bits_len; assign _T_len__T_10_addr = 1'h0; assign _T_len__T_10_mask = 1'h1; assign _T_len__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_size__T_14_addr = 1'h0; assign _T_size__T_14_data = _T_size[_T_size__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = 1'h0; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_burst__T_14_addr = 1'h0; assign _T_burst__T_14_data = _T_burst[_T_burst__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_burst__T_10_data = io_enq_bits_burst; assign _T_burst__T_10_addr = 1'h0; assign _T_burst__T_10_mask = 1'h1; assign _T_burst__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_user__T_14_addr = 1'h0; assign _T_user__T_14_data = _T_user[_T_user__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = 1'h0; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = _T_3 ? _GEN_16 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27736.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27739.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27742.4] assign _GEN_16 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@27794.6] assign _GEN_28 = _T_3 ? _GEN_16 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27782.4] assign _GEN_27 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27782.4] assign _T_11 = _GEN_28 != _GEN_27; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27760.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@27764.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@27767.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@27765.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@27780.6] assign io_deq_bits_id = _T_3 ? io_enq_bits_id : _T_id__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27778.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27792.6] assign io_deq_bits_addr = _T_3 ? io_enq_bits_addr : _T_addr__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27777.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27791.6] assign io_deq_bits_len = _T_3 ? io_enq_bits_len : _T_len__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27776.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27790.6] assign io_deq_bits_size = _T_3 ? io_enq_bits_size : _T_size__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27775.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27789.6] assign io_deq_bits_burst = _T_3 ? io_enq_bits_burst : _T_burst__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27774.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27788.6] assign io_deq_bits_user = _T_3 ? io_enq_bits_user : _T_user__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27769.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27783.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_id[initvar] = _RAND_0[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_addr[initvar] = _RAND_1[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_len[initvar] = _RAND_2[7:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_size[initvar] = _RAND_3[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_burst[initvar] = _RAND_4[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_user[initvar] = _RAND_5[6:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_1 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if(_T_addr__T_10_en & _T_addr__T_10_mask) begin _T_addr[_T_addr__T_10_addr] <= _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if(_T_len__T_10_en & _T_len__T_10_mask) begin _T_len[_T_len__T_10_addr] <= _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if(_T_burst__T_10_en & _T_burst__T_10_mask) begin _T_burst[_T_burst__T_10_addr] <= _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27733.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module Queue_31( // @[:freechips.rocketchip.system.TinyConfig.fir@27882.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@27883.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@27884.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] input [7:0] io_enq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] input io_enq_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] output [7:0] io_deq_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@27885.4] ); reg [63:0] _T_data [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg [63:0] _RAND_0; wire [63:0] _T_data__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_data__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire [63:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg [7:0] _T_strb [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg [31:0] _RAND_1; wire [7:0] _T_strb__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_strb__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire [7:0] _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_strb__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_strb__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_strb__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg _T_last [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg [31:0] _RAND_2; wire _T_last__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_last__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@27888.4] reg [31:0] _RAND_3; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27890.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27893.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27896.4] wire _GEN_9; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@27927.6] wire _GEN_14; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27922.4] wire _GEN_13; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27922.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27907.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@27911.4] assign _T_data__T_14_addr = 1'h0; assign _T_data__T_14_data = _T_data[_T_data__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = 1'h0; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_strb__T_14_addr = 1'h0; assign _T_strb__T_14_data = _T_strb[_T_strb__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] assign _T_strb__T_10_data = io_enq_bits_strb; assign _T_strb__T_10_addr = 1'h0; assign _T_strb__T_10_mask = 1'h1; assign _T_strb__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_last__T_14_addr = 1'h0; assign _T_last__T_14_data = _T_last[_T_last__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] assign _T_last__T_10_data = io_enq_bits_last; assign _T_last__T_10_addr = 1'h0; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = _T_3 ? _GEN_9 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@27890.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27893.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@27896.4] assign _GEN_9 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@27927.6] assign _GEN_14 = _T_3 ? _GEN_9 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27922.4] assign _GEN_13 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@27922.4] assign _T_11 = _GEN_14 != _GEN_13; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@27907.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@27911.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@27914.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@27912.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@27920.6] assign io_deq_bits_data = _T_3 ? io_enq_bits_data : _T_data__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27918.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27925.6] assign io_deq_bits_strb = _T_3 ? io_enq_bits_strb : _T_strb__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27917.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27924.6] assign io_deq_bits_last = _T_3 ? io_enq_bits_last : _T_last__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@27916.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@27923.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {2{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_data[initvar] = _RAND_0[63:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_strb[initvar] = _RAND_1[7:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_last[initvar] = _RAND_2[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] end if(_T_strb__T_10_en & _T_strb__T_10_mask) begin _T_strb[_T_strb__T_10_addr] <= _T_strb__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@27887.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module AXI4Fragmenter( // @[:freechips.rocketchip.system.TinyConfig.fir@27938.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@27939.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@27940.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [6:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [6:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [6:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [6:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [7:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [7:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output [7:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input [7:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@27941.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [31:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [7:0] Queue_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [1:0] Queue_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [6:0] Queue_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [31:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [7:0] Queue_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [1:0] Queue_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire [6:0] Queue_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [31:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [1:0] Queue_1_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [6:0] Queue_1_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_1_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [31:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire [6:0] Queue_1_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] wire Queue_2_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire [63:0] Queue_2_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire [7:0] Queue_2_io_enq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire [63:0] Queue_2_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire [7:0] Queue_2_io_deq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] wire Queue_2_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] reg _T_4; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@27982.4] reg [31:0] _RAND_0; reg [31:0] _T_5; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@27983.4] reg [31:0] _RAND_1; reg [7:0] _T_6; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.TinyConfig.fir@27984.4] reg [31:0] _RAND_2; wire [7:0] _T_2_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27975.4] wire [7:0] _T_7; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@27985.4] wire [31:0] _T_2_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27976.4] wire [31:0] _T_8; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@27986.4] wire [7:0] _T_10; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.TinyConfig.fir@27988.4] wire [31:0] _T_11; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@27989.4] wire [32:0] _T_12; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@27990.4] wire [32:0] _T_13; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27991.4] wire [32:0] _T_14; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27992.4] wire _T_15; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@27993.4] wire [31:0] _T_16; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@27994.4] wire [32:0] _T_17; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@27995.4] wire [32:0] _T_18; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27996.4] wire [32:0] _T_19; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27997.4] wire _T_20; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@27998.4] wire [32:0] _T_22; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28000.4] wire [32:0] _T_23; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28001.4] wire [32:0] _T_24; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28002.4] wire _T_25; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28003.4] wire [31:0] _T_26; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28004.4] wire [32:0] _T_27; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28005.4] wire [32:0] _T_28; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28006.4] wire [32:0] _T_29; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28007.4] wire _T_30; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28008.4] wire [31:0] _T_31; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28009.4] wire [32:0] _T_32; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28010.4] wire [32:0] _T_33; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28011.4] wire [32:0] _T_34; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28012.4] wire _T_35; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28013.4] wire _T_36; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28014.4] wire _T_37; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28015.4] wire _T_38; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28016.4] wire _T_39; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28017.4] wire [31:0] _T_40; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28018.4] wire [32:0] _T_41; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28019.4] wire [32:0] _T_42; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28020.4] wire [32:0] _T_43; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28021.4] wire _T_44; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28022.4] wire [2:0] _T_45; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28023.4] wire [7:0] _T_46; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28024.4] wire [7:0] _GEN_16; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28025.4] wire [7:0] _T_47; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28025.4] wire [6:0] _T_49; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28028.4] wire [7:0] _GEN_17; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28029.4] wire [7:0] _T_50; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28029.4] wire [5:0] _T_51; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28030.4] wire [7:0] _GEN_18; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28031.4] wire [7:0] _T_52; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28031.4] wire [3:0] _T_53; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28032.4] wire [7:0] _GEN_19; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28033.4] wire [7:0] _T_54; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28033.4] wire [6:0] _T_56; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@28035.4] wire [7:0] _T_57; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.TinyConfig.fir@28036.4] wire [8:0] _T_58; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28037.4] wire [7:0] _T_59; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28038.4] wire [7:0] _T_60; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28039.4] wire [9:0] _T_61; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28040.4] wire [7:0] _T_62; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28041.4] wire [7:0] _T_63; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28042.4] wire [11:0] _T_64; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28043.4] wire [7:0] _T_65; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28044.4] wire [7:0] _T_66; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28045.4] wire [7:0] _T_68; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.TinyConfig.fir@28047.4] wire [7:0] _GEN_20; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28048.4] wire [7:0] _T_69; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28048.4] wire [8:0] _T_70; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28049.4] wire [7:0] _T_71; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28050.4] wire [7:0] _T_72; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28051.4] wire [9:0] _T_73; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28052.4] wire [7:0] _T_74; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28053.4] wire [7:0] _T_75; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28054.4] wire [11:0] _T_76; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28055.4] wire [7:0] _T_77; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28056.4] wire [7:0] _T_78; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28057.4] wire [7:0] _T_80; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@28059.4] wire [7:0] _T_81; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.TinyConfig.fir@28060.4] wire [7:0] _T_82; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.TinyConfig.fir@28061.4] wire [1:0] _T_2_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27973.4] wire _T_83; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@28062.4] wire [2:0] _T_2_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27974.4] wire _T_84; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.TinyConfig.fir@28063.4] wire _T_85; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.TinyConfig.fir@28064.4] wire [7:0] _T_86; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.TinyConfig.fir@28065.4] wire [8:0] _T_87; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@28066.4] wire [8:0] _T_88; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@28067.4] wire [8:0] _T_89; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28068.4] wire [8:0] _T_90; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@28069.4] wire [8:0] _T_91; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@28070.4] wire [15:0] _GEN_21; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28071.4] wire [15:0] _T_92; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28071.4] wire [31:0] _GEN_22; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28072.4] wire [31:0] _T_94; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28073.4] wire [15:0] _T_95; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28074.4] wire [22:0] _GEN_23; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28075.4] wire [22:0] _T_96; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28075.4] wire [14:0] _T_97; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@28076.4] wire _T_99; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@28080.4] wire [31:0] _GEN_24; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28082.6] wire [31:0] _T_100; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28082.6] wire [31:0] _T_101; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@28083.6] wire [31:0] _T_102; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@28084.6] wire [31:0] _T_103; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@28085.6] wire [31:0] _T_104; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@28086.6] wire _T_106; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@28093.4] wire [31:0] _T_108; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@28099.4] wire [9:0] _T_110; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28101.4] wire [2:0] _T_111; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28102.4] wire [2:0] _T_112; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28103.4] wire [31:0] _GEN_26; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28104.4] wire [31:0] _T_113; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28104.4] wire _T_2_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@27978.4] wire _T_115; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28107.4] wire _T_116; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@28109.6] wire [8:0] _GEN_27; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28112.6] wire [8:0] _T_118; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28113.6] wire [8:0] _GEN_4; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@28108.4] reg _T_121; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@28146.4] reg [31:0] _RAND_3; reg [31:0] _T_122; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@28147.4] reg [31:0] _RAND_4; reg [7:0] _T_123; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.TinyConfig.fir@28148.4] reg [31:0] _RAND_5; wire [7:0] _T_119_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28139.4] wire [7:0] _T_124; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@28149.4] wire [31:0] _T_119_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28140.4] wire [31:0] _T_125; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@28150.4] wire [7:0] _T_127; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.TinyConfig.fir@28152.4] wire [31:0] _T_128; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28153.4] wire [32:0] _T_129; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28154.4] wire [32:0] _T_130; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28155.4] wire [32:0] _T_131; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28156.4] wire _T_132; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28157.4] wire [31:0] _T_133; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28158.4] wire [32:0] _T_134; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28159.4] wire [32:0] _T_135; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28160.4] wire [32:0] _T_136; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28161.4] wire _T_137; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28162.4] wire [31:0] _T_138; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28163.4] wire [32:0] _T_139; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28164.4] wire [32:0] _T_140; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28165.4] wire [32:0] _T_141; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28166.4] wire _T_142; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28167.4] wire [32:0] _T_144; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28169.4] wire [32:0] _T_145; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28170.4] wire [32:0] _T_146; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28171.4] wire _T_147; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28172.4] wire _T_148; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28173.4] wire _T_149; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28174.4] wire [31:0] _T_150; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28175.4] wire [32:0] _T_151; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28176.4] wire [32:0] _T_152; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28177.4] wire [32:0] _T_153; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28178.4] wire _T_154; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28179.4] wire [4:0] _T_155; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28180.4] wire [2:0] _T_156; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28181.4] wire [7:0] _T_157; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28182.4] wire [4:0] _GEN_28; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28183.4] wire [4:0] _T_158; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28183.4] wire [7:0] _GEN_29; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28184.4] wire [7:0] _T_159; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28184.4] wire [6:0] _T_161; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28187.4] wire [7:0] _GEN_30; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28188.4] wire [7:0] _T_162; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28188.4] wire [5:0] _T_163; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28189.4] wire [7:0] _GEN_31; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28190.4] wire [7:0] _T_164; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28190.4] wire [3:0] _T_165; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28191.4] wire [7:0] _GEN_32; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28192.4] wire [7:0] _T_166; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28192.4] wire [6:0] _T_168; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@28194.4] wire [7:0] _T_169; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.TinyConfig.fir@28195.4] wire [8:0] _T_170; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28196.4] wire [7:0] _T_171; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28197.4] wire [7:0] _T_172; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28198.4] wire [9:0] _T_173; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28199.4] wire [7:0] _T_174; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28200.4] wire [7:0] _T_175; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28201.4] wire [11:0] _T_176; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28202.4] wire [7:0] _T_177; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28203.4] wire [7:0] _T_178; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28204.4] wire [7:0] _T_180; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.TinyConfig.fir@28206.4] wire [7:0] _GEN_33; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28207.4] wire [7:0] _T_181; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28207.4] wire [8:0] _T_182; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28208.4] wire [7:0] _T_183; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28209.4] wire [7:0] _T_184; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28210.4] wire [9:0] _T_185; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28211.4] wire [7:0] _T_186; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28212.4] wire [7:0] _T_187; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28213.4] wire [11:0] _T_188; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28214.4] wire [7:0] _T_189; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28215.4] wire [7:0] _T_190; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28216.4] wire [7:0] _T_192; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@28218.4] wire [7:0] _T_193; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.TinyConfig.fir@28219.4] wire [7:0] _T_194; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.TinyConfig.fir@28220.4] wire [1:0] _T_119_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28137.4] wire _T_195; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@28221.4] wire [2:0] _T_119_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28138.4] wire _T_196; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.TinyConfig.fir@28222.4] wire _T_197; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.TinyConfig.fir@28223.4] wire [7:0] _T_198; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.TinyConfig.fir@28224.4] wire [8:0] _T_199; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@28225.4] wire [8:0] _T_200; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@28226.4] wire [8:0] _T_201; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28227.4] wire [8:0] _T_202; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@28228.4] wire [8:0] _T_203; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@28229.4] wire [15:0] _GEN_34; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28230.4] wire [15:0] _T_204; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28230.4] wire [31:0] _GEN_35; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28231.4] wire [31:0] _T_206; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28232.4] wire [15:0] _T_207; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28233.4] wire [22:0] _GEN_36; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28234.4] wire [22:0] _T_208; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28234.4] wire [14:0] _T_209; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@28235.4] wire _T_211; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@28239.4] wire [31:0] _GEN_37; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28241.6] wire [31:0] _T_212; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28241.6] wire [31:0] _T_213; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@28242.6] wire [31:0] _T_214; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@28243.6] wire [31:0] _T_215; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@28244.6] wire [31:0] _T_216; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@28245.6] wire _T_218; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@28252.4] reg [8:0] _T_245; // @[Fragmenter.scala 162:30:freechips.rocketchip.system.TinyConfig.fir@28317.4] reg [31:0] _RAND_6; wire _T_246; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.TinyConfig.fir@28318.4] reg _T_233; // @[Fragmenter.scala 148:35:freechips.rocketchip.system.TinyConfig.fir@28292.4] reg [31:0] _RAND_7; wire _T_240; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.TinyConfig.fir@28308.4] wire _T_241; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.TinyConfig.fir@28309.4] wire [31:0] _T_220; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@28258.4] wire [9:0] _T_222; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28260.4] wire [2:0] _T_223; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28261.4] wire [2:0] _T_224; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28262.4] wire [31:0] _GEN_39; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28263.4] wire [31:0] _T_225; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28263.4] wire _T_119_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@28142.4] wire _T_227; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28266.4] wire _T_228; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@28268.6] wire [8:0] _GEN_40; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28271.6] wire [8:0] _T_230; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28272.6] wire [8:0] _GEN_9; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@28267.4] wire [6:0] _T_2_bits_user; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27968.4] wire _T_242; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.TinyConfig.fir@28311.4] wire _T_243; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.TinyConfig.fir@28312.4] wire _T_236; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@28297.4] wire _T_239; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.TinyConfig.fir@28306.4] wire _T_237; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28301.4] wire [6:0] _T_119_bits_user; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28132.4] wire [8:0] _T_247; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.TinyConfig.fir@28319.4] wire [8:0] _T_248; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.TinyConfig.fir@28320.4] wire _T_249; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.TinyConfig.fir@28321.4] wire _T_231_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28283.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@28287.4] wire _T_260; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@28338.4] wire _T_261; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.TinyConfig.fir@28339.4] wire _T_262; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.TinyConfig.fir@28340.4] wire _T_250; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28322.4] wire [8:0] _GEN_41; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@28323.4] wire [8:0] _T_252; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@28324.4] wire _T_254; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.TinyConfig.fir@28327.4] wire _T_255; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.TinyConfig.fir@28328.4] wire _T_256; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.TinyConfig.fir@28329.4] wire _T_258; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28331.4] wire _T_259; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28332.4] wire _T_266; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.TinyConfig.fir@28348.4] wire _T_231_bits_last; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28283.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28284.4] wire _T_267; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.TinyConfig.fir@28349.4] wire _T_268; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.TinyConfig.fir@28350.4] wire _T_269; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.TinyConfig.fir@28351.4] wire _T_271; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28353.4] wire _T_272; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28354.4] wire _T_273; // @[Fragmenter.scala 179:39:freechips.rocketchip.system.TinyConfig.fir@28359.4] wire _T_276; // @[Fragmenter.scala 185:39:freechips.rocketchip.system.TinyConfig.fir@28365.4] wire _T_278; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.TinyConfig.fir@28369.4] wire _T_279; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.TinyConfig.fir@28370.4] reg [1:0] _T_282_0; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@28378.4] reg [31:0] _RAND_8; reg [1:0] _T_282_1; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@28378.4] reg [31:0] _RAND_9; wire [1:0] _GEN_13; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@28379.4] wire [1:0] _T_285; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@28382.4] wire _T_287; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@28384.4] wire _T_288; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@28385.4] wire _T_289; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28386.4] wire _T_290; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@28387.4] wire [1:0] _T_291; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@28389.6] wire _T_294; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@28394.4] wire [1:0] _T_295; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@28396.6] Queue_29 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@27952.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_addr(Queue_io_enq_bits_addr), .io_enq_bits_len(Queue_io_enq_bits_len), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_burst(Queue_io_enq_bits_burst), .io_enq_bits_user(Queue_io_enq_bits_user), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_addr(Queue_io_deq_bits_addr), .io_deq_bits_len(Queue_io_deq_bits_len), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_burst(Queue_io_deq_bits_burst), .io_deq_bits_user(Queue_io_deq_bits_user) ); Queue_29 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28116.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_id(Queue_1_io_enq_bits_id), .io_enq_bits_addr(Queue_1_io_enq_bits_addr), .io_enq_bits_len(Queue_1_io_enq_bits_len), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_burst(Queue_1_io_enq_bits_burst), .io_enq_bits_user(Queue_1_io_enq_bits_user), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_id(Queue_1_io_deq_bits_id), .io_deq_bits_addr(Queue_1_io_deq_bits_addr), .io_deq_bits_len(Queue_1_io_deq_bits_len), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_burst(Queue_1_io_deq_bits_burst), .io_deq_bits_user(Queue_1_io_deq_bits_user) ); Queue_31 Queue_2 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@28275.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits_data(Queue_2_io_enq_bits_data), .io_enq_bits_strb(Queue_2_io_enq_bits_strb), .io_enq_bits_last(Queue_2_io_enq_bits_last), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits_data(Queue_2_io_deq_bits_data), .io_deq_bits_strb(Queue_2_io_deq_bits_strb), .io_deq_bits_last(Queue_2_io_deq_bits_last) ); assign _T_2_bits_len = Queue_io_deq_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27975.4] assign _T_7 = _T_4 ? _T_6 : _T_2_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@27985.4] assign _T_2_bits_addr = Queue_io_deq_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27976.4] assign _T_8 = _T_4 ? _T_5 : _T_2_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@27986.4] assign _T_10 = _T_8[10:3]; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.TinyConfig.fir@27988.4] assign _T_11 = _T_8 ^ 32'h8000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@27989.4] assign _T_12 = {1'b0,$signed(_T_11)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@27990.4] assign _T_13 = $signed(_T_12) & $signed(33'shc8000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27991.4] assign _T_14 = $signed(_T_13); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27992.4] assign _T_15 = $signed(_T_14) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@27993.4] assign _T_16 = _T_8 ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@27994.4] assign _T_17 = {1'b0,$signed(_T_16)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@27995.4] assign _T_18 = $signed(_T_17) & $signed(33'shca010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27996.4] assign _T_19 = $signed(_T_18); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@27997.4] assign _T_20 = $signed(_T_19) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@27998.4] assign _T_22 = {1'b0,$signed(_T_8)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28000.4] assign _T_23 = $signed(_T_22) & $signed(33'sh4a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28001.4] assign _T_24 = $signed(_T_23); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28002.4] assign _T_25 = $signed(_T_24) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28003.4] assign _T_26 = _T_8 ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28004.4] assign _T_27 = {1'b0,$signed(_T_26)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28005.4] assign _T_28 = $signed(_T_27) & $signed(33'shca010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28006.4] assign _T_29 = $signed(_T_28); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28007.4] assign _T_30 = $signed(_T_29) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28008.4] assign _T_31 = _T_8 ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28009.4] assign _T_32 = {1'b0,$signed(_T_31)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28010.4] assign _T_33 = $signed(_T_32) & $signed(33'shc0000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28011.4] assign _T_34 = $signed(_T_33); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28012.4] assign _T_35 = $signed(_T_34) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28013.4] assign _T_36 = _T_15 | _T_20; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28014.4] assign _T_37 = _T_36 | _T_25; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28015.4] assign _T_38 = _T_37 | _T_30; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28016.4] assign _T_39 = _T_38 | _T_35; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28017.4] assign _T_40 = _T_8 ^ 32'h2000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28018.4] assign _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28019.4] assign _T_42 = $signed(_T_41) & $signed(33'shca012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28020.4] assign _T_43 = $signed(_T_42); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28021.4] assign _T_44 = $signed(_T_43) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28022.4] assign _T_45 = _T_39 ? 3'h7 : 3'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28023.4] assign _T_46 = _T_44 ? 8'hff : 8'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28024.4] assign _GEN_16 = {{5'd0}, _T_45}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28025.4] assign _T_47 = _GEN_16 | _T_46; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28025.4] assign _T_49 = _T_7[7:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28028.4] assign _GEN_17 = {{1'd0}, _T_49}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28029.4] assign _T_50 = _T_7 | _GEN_17; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28029.4] assign _T_51 = _T_50[7:2]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28030.4] assign _GEN_18 = {{2'd0}, _T_51}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28031.4] assign _T_52 = _T_50 | _GEN_18; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28031.4] assign _T_53 = _T_52[7:4]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28032.4] assign _GEN_19 = {{4'd0}, _T_53}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28033.4] assign _T_54 = _T_52 | _GEN_19; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28033.4] assign _T_56 = _T_54[7:1]; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@28035.4] assign _T_57 = ~ _T_7; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.TinyConfig.fir@28036.4] assign _T_58 = {_T_57, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28037.4] assign _T_59 = _T_58[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28038.4] assign _T_60 = _T_57 | _T_59; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28039.4] assign _T_61 = {_T_60, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28040.4] assign _T_62 = _T_61[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28041.4] assign _T_63 = _T_60 | _T_62; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28042.4] assign _T_64 = {_T_63, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28043.4] assign _T_65 = _T_64[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28044.4] assign _T_66 = _T_63 | _T_65; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28045.4] assign _T_68 = ~ _T_66; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.TinyConfig.fir@28047.4] assign _GEN_20 = {{1'd0}, _T_56}; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28048.4] assign _T_69 = _GEN_20 | _T_68; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28048.4] assign _T_70 = {_T_10, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28049.4] assign _T_71 = _T_70[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28050.4] assign _T_72 = _T_10 | _T_71; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28051.4] assign _T_73 = {_T_72, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28052.4] assign _T_74 = _T_73[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28053.4] assign _T_75 = _T_72 | _T_74; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28054.4] assign _T_76 = {_T_75, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28055.4] assign _T_77 = _T_76[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28056.4] assign _T_78 = _T_75 | _T_77; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28057.4] assign _T_80 = ~ _T_78; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@28059.4] assign _T_81 = _T_69 & _T_80; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.TinyConfig.fir@28060.4] assign _T_82 = _T_81 & _T_47; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.TinyConfig.fir@28061.4] assign _T_2_bits_burst = Queue_io_deq_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27973.4] assign _T_83 = _T_2_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@28062.4] assign _T_2_bits_size = Queue_io_deq_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27974.4] assign _T_84 = _T_2_bits_size != 3'h3; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.TinyConfig.fir@28063.4] assign _T_85 = _T_83 | _T_84; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.TinyConfig.fir@28064.4] assign _T_86 = _T_85 ? 8'h0 : _T_82; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.TinyConfig.fir@28065.4] assign _T_87 = {_T_86, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@28066.4] assign _T_88 = _T_87 | 9'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@28067.4] assign _T_89 = {1'h0,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28068.4] assign _T_90 = ~ _T_89; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@28069.4] assign _T_91 = _T_88 & _T_90; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@28070.4] assign _GEN_21 = {{7'd0}, _T_91}; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28071.4] assign _T_92 = _GEN_21 << _T_2_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28071.4] assign _GEN_22 = {{16'd0}, _T_92}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28072.4] assign _T_94 = _T_8 + _GEN_22; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28073.4] assign _T_95 = {_T_2_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28074.4] assign _GEN_23 = {{7'd0}, _T_95}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28075.4] assign _T_96 = _GEN_23 << _T_2_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28075.4] assign _T_97 = _T_96[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@28076.4] assign _T_99 = _T_2_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@28080.4] assign _GEN_24 = {{17'd0}, _T_97}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28082.6] assign _T_100 = _T_94 & _GEN_24; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28082.6] assign _T_101 = ~ _T_2_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@28083.6] assign _T_102 = _T_101 | _GEN_24; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@28084.6] assign _T_103 = ~ _T_102; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@28085.6] assign _T_104 = _T_100 | _T_103; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@28086.6] assign _T_106 = _T_86 == _T_7; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@28093.4] assign _T_108 = ~ _T_8; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@28099.4] assign _T_110 = 10'h7 << _T_2_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28101.4] assign _T_111 = _T_110[2:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28102.4] assign _T_112 = ~ _T_111; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28103.4] assign _GEN_26 = {{29'd0}, _T_112}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28104.4] assign _T_113 = _T_108 | _GEN_26; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28104.4] assign _T_2_valid = Queue_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@27978.4] assign _T_115 = auto_out_ar_ready & _T_2_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28107.4] assign _T_116 = _T_106 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@28109.6] assign _GEN_27 = {{1'd0}, _T_7}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28112.6] assign _T_118 = _GEN_27 - _T_91; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28113.6] assign _GEN_4 = _T_115 ? _T_118 : {{1'd0}, _T_6}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@28108.4] assign _T_119_bits_len = Queue_1_io_deq_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28139.4] assign _T_124 = _T_121 ? _T_123 : _T_119_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@28149.4] assign _T_119_bits_addr = Queue_1_io_deq_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28140.4] assign _T_125 = _T_121 ? _T_122 : _T_119_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@28150.4] assign _T_127 = _T_125[10:3]; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.TinyConfig.fir@28152.4] assign _T_128 = _T_125 ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28153.4] assign _T_129 = {1'b0,$signed(_T_128)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28154.4] assign _T_130 = $signed(_T_129) & $signed(33'shc0000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28155.4] assign _T_131 = $signed(_T_130); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28156.4] assign _T_132 = $signed(_T_131) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28157.4] assign _T_133 = _T_125 ^ 32'h8000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28158.4] assign _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28159.4] assign _T_135 = $signed(_T_134) & $signed(33'shc8000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28160.4] assign _T_136 = $signed(_T_135); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28161.4] assign _T_137 = $signed(_T_136) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28162.4] assign _T_138 = _T_125 ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28163.4] assign _T_139 = {1'b0,$signed(_T_138)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28164.4] assign _T_140 = $signed(_T_139) & $signed(33'shca000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28165.4] assign _T_141 = $signed(_T_140); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28166.4] assign _T_142 = $signed(_T_141) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28167.4] assign _T_144 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28169.4] assign _T_145 = $signed(_T_144) & $signed(33'sh4a002000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28170.4] assign _T_146 = $signed(_T_145); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28171.4] assign _T_147 = $signed(_T_146) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28172.4] assign _T_148 = _T_137 | _T_142; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28173.4] assign _T_149 = _T_148 | _T_147; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.TinyConfig.fir@28174.4] assign _T_150 = _T_125 ^ 32'h2000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28175.4] assign _T_151 = {1'b0,$signed(_T_150)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28176.4] assign _T_152 = $signed(_T_151) & $signed(33'shca002000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28177.4] assign _T_153 = $signed(_T_152); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28178.4] assign _T_154 = $signed(_T_153) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28179.4] assign _T_155 = _T_132 ? 5'h1f : 5'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28180.4] assign _T_156 = _T_149 ? 3'h7 : 3'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28181.4] assign _T_157 = _T_154 ? 8'hff : 8'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28182.4] assign _GEN_28 = {{2'd0}, _T_156}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28183.4] assign _T_158 = _T_155 | _GEN_28; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28183.4] assign _GEN_29 = {{3'd0}, _T_158}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28184.4] assign _T_159 = _GEN_29 | _T_157; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@28184.4] assign _T_161 = _T_124[7:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28187.4] assign _GEN_30 = {{1'd0}, _T_161}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28188.4] assign _T_162 = _T_124 | _GEN_30; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28188.4] assign _T_163 = _T_162[7:2]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28189.4] assign _GEN_31 = {{2'd0}, _T_163}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28190.4] assign _T_164 = _T_162 | _GEN_31; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28190.4] assign _T_165 = _T_164[7:4]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@28191.4] assign _GEN_32 = {{4'd0}, _T_165}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28192.4] assign _T_166 = _T_164 | _GEN_32; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@28192.4] assign _T_168 = _T_166[7:1]; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.TinyConfig.fir@28194.4] assign _T_169 = ~ _T_124; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.TinyConfig.fir@28195.4] assign _T_170 = {_T_169, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28196.4] assign _T_171 = _T_170[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28197.4] assign _T_172 = _T_169 | _T_171; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28198.4] assign _T_173 = {_T_172, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28199.4] assign _T_174 = _T_173[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28200.4] assign _T_175 = _T_172 | _T_174; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28201.4] assign _T_176 = {_T_175, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28202.4] assign _T_177 = _T_176[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28203.4] assign _T_178 = _T_175 | _T_177; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28204.4] assign _T_180 = ~ _T_178; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.TinyConfig.fir@28206.4] assign _GEN_33 = {{1'd0}, _T_168}; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28207.4] assign _T_181 = _GEN_33 | _T_180; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.TinyConfig.fir@28207.4] assign _T_182 = {_T_127, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28208.4] assign _T_183 = _T_182[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28209.4] assign _T_184 = _T_127 | _T_183; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28210.4] assign _T_185 = {_T_184, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28211.4] assign _T_186 = _T_185[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28212.4] assign _T_187 = _T_184 | _T_186; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28213.4] assign _T_188 = {_T_187, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@28214.4] assign _T_189 = _T_188[7:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@28215.4] assign _T_190 = _T_187 | _T_189; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@28216.4] assign _T_192 = ~ _T_190; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@28218.4] assign _T_193 = _T_181 & _T_192; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.TinyConfig.fir@28219.4] assign _T_194 = _T_193 & _T_159; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.TinyConfig.fir@28220.4] assign _T_119_bits_burst = Queue_1_io_deq_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28137.4] assign _T_195 = _T_119_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@28221.4] assign _T_119_bits_size = Queue_1_io_deq_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28138.4] assign _T_196 = _T_119_bits_size != 3'h3; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.TinyConfig.fir@28222.4] assign _T_197 = _T_195 | _T_196; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.TinyConfig.fir@28223.4] assign _T_198 = _T_197 ? 8'h0 : _T_194; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.TinyConfig.fir@28224.4] assign _T_199 = {_T_198, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@28225.4] assign _T_200 = _T_199 | 9'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@28226.4] assign _T_201 = {1'h0,_T_198}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28227.4] assign _T_202 = ~ _T_201; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@28228.4] assign _T_203 = _T_200 & _T_202; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@28229.4] assign _GEN_34 = {{7'd0}, _T_203}; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28230.4] assign _T_204 = _GEN_34 << _T_119_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@28230.4] assign _GEN_35 = {{16'd0}, _T_204}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28231.4] assign _T_206 = _T_125 + _GEN_35; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@28232.4] assign _T_207 = {_T_119_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28233.4] assign _GEN_36 = {{7'd0}, _T_207}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28234.4] assign _T_208 = _GEN_36 << _T_119_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@28234.4] assign _T_209 = _T_208[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@28235.4] assign _T_211 = _T_119_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@28239.4] assign _GEN_37 = {{17'd0}, _T_209}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28241.6] assign _T_212 = _T_206 & _GEN_37; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@28241.6] assign _T_213 = ~ _T_119_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@28242.6] assign _T_214 = _T_213 | _GEN_37; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@28243.6] assign _T_215 = ~ _T_214; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@28244.6] assign _T_216 = _T_212 | _T_215; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@28245.6] assign _T_218 = _T_198 == _T_124; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@28252.4] assign _T_246 = _T_245 == 9'h0; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.TinyConfig.fir@28318.4] assign _T_240 = _T_246 | _T_233; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.TinyConfig.fir@28308.4] assign _T_241 = auto_out_aw_ready & _T_240; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.TinyConfig.fir@28309.4] assign _T_220 = ~ _T_125; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@28258.4] assign _T_222 = 10'h7 << _T_119_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28260.4] assign _T_223 = _T_222[2:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28261.4] assign _T_224 = ~ _T_223; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28262.4] assign _GEN_39 = {{29'd0}, _T_224}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28263.4] assign _T_225 = _T_220 | _GEN_39; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@28263.4] assign _T_119_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@28142.4] assign _T_227 = _T_241 & _T_119_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28266.4] assign _T_228 = _T_218 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@28268.6] assign _GEN_40 = {{1'd0}, _T_124}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28271.6] assign _T_230 = _GEN_40 - _T_203; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@28272.6] assign _GEN_9 = _T_227 ? _T_230 : {{1'd0}, _T_123}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@28267.4] assign _T_2_bits_user = Queue_io_deq_bits_user; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@27967.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@27968.4] assign _T_242 = _T_233 == 1'h0; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.TinyConfig.fir@28311.4] assign _T_243 = _T_119_valid & _T_242; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.TinyConfig.fir@28312.4] assign _T_236 = _T_243 & _T_246; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@28297.4] assign _T_239 = _T_119_valid & _T_240; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.TinyConfig.fir@28306.4] assign _T_237 = auto_out_aw_ready & _T_239; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28301.4] assign _T_119_bits_user = Queue_1_io_deq_bits_user; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28131.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28132.4] assign _T_247 = _T_243 ? _T_203 : 9'h0; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.TinyConfig.fir@28319.4] assign _T_248 = _T_246 ? _T_247 : _T_245; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.TinyConfig.fir@28320.4] assign _T_249 = _T_248 == 9'h1; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.TinyConfig.fir@28321.4] assign _T_231_valid = Queue_2_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28283.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@28287.4] assign _T_260 = _T_246 == 1'h0; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@28338.4] assign _T_261 = _T_260 | _T_243; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.TinyConfig.fir@28339.4] assign _T_262 = _T_231_valid & _T_261; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.TinyConfig.fir@28340.4] assign _T_250 = auto_out_w_ready & _T_262; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28322.4] assign _GEN_41 = {{8'd0}, _T_250}; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@28323.4] assign _T_252 = _T_248 - _GEN_41; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@28324.4] assign _T_254 = _T_250 == 1'h0; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.TinyConfig.fir@28327.4] assign _T_255 = _T_248 != 9'h0; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.TinyConfig.fir@28328.4] assign _T_256 = _T_254 | _T_255; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.TinyConfig.fir@28329.4] assign _T_258 = _T_256 | reset; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28331.4] assign _T_259 = _T_258 == 1'h0; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28332.4] assign _T_266 = _T_262 == 1'h0; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.TinyConfig.fir@28348.4] assign _T_231_bits_last = Queue_2_io_deq_bits_last; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@28283.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@28284.4] assign _T_267 = _T_231_bits_last == 1'h0; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.TinyConfig.fir@28349.4] assign _T_268 = _T_266 | _T_267; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.TinyConfig.fir@28350.4] assign _T_269 = _T_268 | _T_249; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.TinyConfig.fir@28351.4] assign _T_271 = _T_269 | reset; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28353.4] assign _T_272 = _T_271 == 1'h0; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28354.4] assign _T_273 = auto_out_r_bits_user[0]; // @[Fragmenter.scala 179:39:freechips.rocketchip.system.TinyConfig.fir@28359.4] assign _T_276 = auto_out_b_bits_user[0]; // @[Fragmenter.scala 185:39:freechips.rocketchip.system.TinyConfig.fir@28365.4] assign _T_278 = _T_276 == 1'h0; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.TinyConfig.fir@28369.4] assign _T_279 = auto_in_b_ready | _T_278; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.TinyConfig.fir@28370.4] assign _GEN_13 = auto_out_b_bits_id ? _T_282_1 : _T_282_0; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@28379.4] assign _T_285 = 2'h1 << auto_out_b_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@28382.4] assign _T_287 = _T_285[0]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@28384.4] assign _T_288 = _T_285[1]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@28385.4] assign _T_289 = _T_279 & auto_out_b_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@28386.4] assign _T_290 = _T_287 & _T_289; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@28387.4] assign _T_291 = _T_282_0 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@28389.6] assign _T_294 = _T_288 & _T_289; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@28394.4] assign _T_295 = _T_282_1 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@28396.6] assign auto_in_aw_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_w_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_b_valid = auto_out_b_valid & _T_276; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp | _GEN_13; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_b_bits_user = auto_out_b_bits_user[7:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_ar_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_bits_user = auto_out_r_bits_user[7:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_in_r_bits_last = auto_out_r_bits_last & _T_273; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@27951.4] assign auto_out_aw_valid = _T_119_valid & _T_240; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_aw_bits_addr = ~ _T_225; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_aw_bits_len = _T_197 ? 8'h0 : _T_194; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_aw_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_aw_bits_user = {_T_119_bits_user,_T_218}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_w_valid = _T_231_valid & _T_261; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_w_bits_data = Queue_2_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_w_bits_strb = Queue_2_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_w_bits_last = _T_248 == 9'h1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_b_ready = auto_in_b_ready | _T_278; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_bits_addr = ~ _T_113; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_bits_len = _T_85 ? 8'h0 : _T_82; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_ar_bits_user = {_T_2_bits_user,_T_106}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@27950.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@27953.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@27954.4] assign Queue_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@27955.4] assign Queue_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27965.4] assign Queue_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27964.4] assign Queue_io_enq_bits_len = auto_in_ar_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27963.4] assign Queue_io_enq_bits_size = auto_in_ar_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27962.4] assign Queue_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27961.4] assign Queue_io_enq_bits_user = auto_in_ar_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@27956.4] assign Queue_io_deq_ready = auto_out_ar_ready & _T_106; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@27979.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28117.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28118.4] assign Queue_1_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@28119.4] assign Queue_1_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28129.4] assign Queue_1_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28128.4] assign Queue_1_io_enq_bits_len = auto_in_aw_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28127.4] assign Queue_1_io_enq_bits_size = auto_in_aw_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28126.4] assign Queue_1_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28125.4] assign Queue_1_io_enq_bits_user = auto_in_aw_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28120.4] assign Queue_1_io_deq_ready = _T_241 & _T_218; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@28143.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28276.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28277.4] assign Queue_2_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@28278.4] assign Queue_2_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28281.4] assign Queue_2_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28280.4] assign Queue_2_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@28279.4] assign Queue_2_io_deq_ready = auto_out_w_ready & _T_261; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@28288.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_4 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_5 = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_6 = _RAND_2[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_121 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_122 = _RAND_4[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_123 = _RAND_5[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_245 = _RAND_6[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_233 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_282_0 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_282_1 = _RAND_9[1:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_4 <= 1'h0; end else begin if (_T_115) begin _T_4 <= _T_116; end end if (_T_115) begin if (_T_83) begin _T_5 <= _T_2_bits_addr; end else begin if (_T_99) begin _T_5 <= _T_104; end else begin _T_5 <= _T_94; end end end _T_6 <= _GEN_4[7:0]; if (reset) begin _T_121 <= 1'h0; end else begin if (_T_227) begin _T_121 <= _T_228; end end if (_T_227) begin if (_T_195) begin _T_122 <= _T_119_bits_addr; end else begin if (_T_211) begin _T_122 <= _T_216; end else begin _T_122 <= _T_206; end end end _T_123 <= _GEN_9[7:0]; if (reset) begin _T_245 <= 9'h0; end else begin _T_245 <= _T_252; end if (reset) begin _T_233 <= 1'h0; end else begin if (_T_237) begin _T_233 <= 1'h0; end else begin if (_T_236) begin _T_233 <= 1'h1; end end end if (reset) begin _T_282_0 <= 2'h0; end else begin if (_T_290) begin if (_T_276) begin _T_282_0 <= 2'h0; end else begin _T_282_0 <= _T_291; end end end if (reset) begin _T_282_1 <= 2'h0; end else begin if (_T_294) begin if (_T_276) begin _T_282_1 <= 2'h0; end else begin _T_282_1 <= _T_295; end end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_259) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:167 assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible\n"); // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28334.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_259) begin $fatal; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@28335.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_272) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:176 assert (!out.w.valid || !in_w.bits.last || w_last)\n"); // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28356.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_272) begin $fatal; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@28357.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module AXI4IdIndexer_1( // @[:freechips.rocketchip.system.TinyConfig.fir@28401.2] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [7:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [7:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [7:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [7:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [6:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [6:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output [6:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input [6:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@28404.4] ); assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_b_bits_id = {auto_out_b_bits_user,auto_out_b_bits_id}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_r_bits_id = {auto_out_r_bits_user,auto_out_r_bits_id}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28414.4] assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_id = auto_in_aw_bits_id[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_aw_bits_user = auto_in_aw_bits_id[7:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_id = auto_in_ar_bits_id[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_ar_bits_user = auto_in_ar_bits_id[7:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28413.4] endmodule module SimpleLazyModule_4( // @[:freechips.rocketchip.system.TinyConfig.fir@28429.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@28430.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@28431.4] output auto_axi4index_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [7:0] auto_axi4index_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [31:0] auto_axi4index_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [7:0] auto_axi4index_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [2:0] auto_axi4index_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [1:0] auto_axi4index_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_axi4index_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [63:0] auto_axi4index_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [7:0] auto_axi4index_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_axi4index_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [7:0] auto_axi4index_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [1:0] auto_axi4index_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_axi4index_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [7:0] auto_axi4index_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [31:0] auto_axi4index_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [7:0] auto_axi4index_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [2:0] auto_axi4index_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [1:0] auto_axi4index_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_axi4index_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_axi4index_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [7:0] auto_axi4index_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [63:0] auto_axi4index_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [1:0] auto_axi4index_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_axi4index_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_buffer_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_buffer_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [2:0] auto_buffer_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [2:0] auto_buffer_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [3:0] auto_buffer_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [3:0] auto_buffer_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [31:0] auto_buffer_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [3:0] auto_buffer_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output [31:0] auto_buffer_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_buffer_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] output auto_buffer_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_buffer_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [2:0] auto_buffer_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [1:0] auto_buffer_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [3:0] auto_buffer_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [3:0] auto_buffer_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_buffer_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_buffer_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input [31:0] auto_buffer_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] input auto_buffer_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@28432.4] ); wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] wire fixer_clock; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_reset; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [1:0] fixer_auto_in_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_in_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [1:0] fixer_auto_out_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [3:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire [31:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire fixer_auto_out_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] wire axi42tl_clock; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_reset; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_aw_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_aw_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_aw_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [31:0] axi42tl_auto_in_aw_bits_addr; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [7:0] axi42tl_auto_in_aw_bits_len; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [2:0] axi42tl_auto_in_aw_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_w_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_w_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [63:0] axi42tl_auto_in_w_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [7:0] axi42tl_auto_in_w_bits_strb; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_w_bits_last; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_b_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_b_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_b_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [1:0] axi42tl_auto_in_b_bits_resp; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_ar_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_ar_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_ar_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [31:0] axi42tl_auto_in_ar_bits_addr; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [7:0] axi42tl_auto_in_ar_bits_len; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [2:0] axi42tl_auto_in_ar_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_r_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_r_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_r_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [63:0] axi42tl_auto_in_r_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [1:0] axi42tl_auto_in_r_bits_resp; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_in_r_bits_last; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_a_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_a_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [2:0] axi42tl_auto_out_a_bits_opcode; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [2:0] axi42tl_auto_out_a_bits_param; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [3:0] axi42tl_auto_out_a_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [3:0] axi42tl_auto_out_a_bits_source; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [31:0] axi42tl_auto_out_a_bits_address; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [7:0] axi42tl_auto_out_a_bits_mask; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [63:0] axi42tl_auto_out_a_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_a_bits_corrupt; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_d_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_d_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [2:0] axi42tl_auto_out_d_bits_opcode; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [3:0] axi42tl_auto_out_d_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [3:0] axi42tl_auto_out_d_bits_source; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_d_bits_denied; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire [63:0] axi42tl_auto_out_d_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi42tl_auto_out_d_bits_corrupt; // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] wire axi4yank_clock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_reset; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [31:0] axi4yank_auto_in_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [2:0] axi4yank_auto_in_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_aw_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [63:0] axi4yank_auto_in_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [1:0] axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_b_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [31:0] axi4yank_auto_in_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [2:0] axi4yank_auto_in_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_ar_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [63:0] axi4yank_auto_in_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [1:0] axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_in_r_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_in_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [31:0] axi4yank_auto_out_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_out_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [2:0] axi4yank_auto_out_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [63:0] axi4yank_auto_out_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_out_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [1:0] axi4yank_auto_out_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [31:0] axi4yank_auto_out_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [7:0] axi4yank_auto_out_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [2:0] axi4yank_auto_out_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [63:0] axi4yank_auto_out_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire [1:0] axi4yank_auto_out_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4yank_auto_out_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] wire axi4frag_clock; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_reset; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [31:0] axi4frag_auto_in_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_in_aw_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [2:0] axi4frag_auto_in_aw_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_in_aw_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [6:0] axi4frag_auto_in_aw_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [63:0] axi4frag_auto_in_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_in_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_in_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [6:0] axi4frag_auto_in_b_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [31:0] axi4frag_auto_in_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_in_ar_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [2:0] axi4frag_auto_in_ar_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_in_ar_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [6:0] axi4frag_auto_in_ar_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [63:0] axi4frag_auto_in_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_in_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [6:0] axi4frag_auto_in_r_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_in_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [31:0] axi4frag_auto_out_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_aw_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [2:0] axi4frag_auto_out_aw_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_aw_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [63:0] axi4frag_auto_out_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_out_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_b_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [31:0] axi4frag_auto_out_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_ar_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [2:0] axi4frag_auto_out_ar_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_ar_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [63:0] axi4frag_auto_out_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [1:0] axi4frag_auto_out_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire [7:0] axi4frag_auto_out_r_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4frag_auto_out_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] wire axi4index_auto_in_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [31:0] axi4index_auto_in_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [2:0] axi4index_auto_in_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_in_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [63:0] axi4index_auto_in_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [31:0] axi4index_auto_in_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [2:0] axi4index_auto_in_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_in_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_in_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [63:0] axi4index_auto_in_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_in_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [31:0] axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [2:0] axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [6:0] axi4index_auto_out_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [63:0] axi4index_auto_out_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_out_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [6:0] axi4index_auto_out_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [31:0] axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [7:0] axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [2:0] axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [6:0] axi4index_auto_out_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [63:0] axi4index_auto_out_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [1:0] axi4index_auto_out_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire [6:0] axi4index_auto_out_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] wire axi4index_auto_out_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] TLBuffer_5 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28437.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); TLFIFOFixer_2 fixer ( // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.TinyConfig.fir@28443.4] .clock(fixer_clock), .reset(fixer_reset), .auto_in_a_ready(fixer_auto_in_a_ready), .auto_in_a_valid(fixer_auto_in_a_valid), .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode), .auto_in_a_bits_param(fixer_auto_in_a_bits_param), .auto_in_a_bits_size(fixer_auto_in_a_bits_size), .auto_in_a_bits_source(fixer_auto_in_a_bits_source), .auto_in_a_bits_address(fixer_auto_in_a_bits_address), .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask), .auto_in_a_bits_data(fixer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt), .auto_in_d_ready(fixer_auto_in_d_ready), .auto_in_d_valid(fixer_auto_in_d_valid), .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode), .auto_in_d_bits_param(fixer_auto_in_d_bits_param), .auto_in_d_bits_size(fixer_auto_in_d_bits_size), .auto_in_d_bits_source(fixer_auto_in_d_bits_source), .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink), .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied), .auto_in_d_bits_data(fixer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt), .auto_out_a_ready(fixer_auto_out_a_ready), .auto_out_a_valid(fixer_auto_out_a_valid), .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode), .auto_out_a_bits_param(fixer_auto_out_a_bits_param), .auto_out_a_bits_size(fixer_auto_out_a_bits_size), .auto_out_a_bits_source(fixer_auto_out_a_bits_source), .auto_out_a_bits_address(fixer_auto_out_a_bits_address), .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask), .auto_out_a_bits_data(fixer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt), .auto_out_d_ready(fixer_auto_out_d_ready), .auto_out_d_valid(fixer_auto_out_d_valid), .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode), .auto_out_d_bits_param(fixer_auto_out_d_bits_param), .auto_out_d_bits_size(fixer_auto_out_d_bits_size), .auto_out_d_bits_source(fixer_auto_out_d_bits_source), .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink), .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied), .auto_out_d_bits_data(fixer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt) ); TLWidthWidget_3 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@28449.4] .clock(widget_clock), .reset(widget_reset), .auto_in_a_ready(widget_auto_in_a_ready), .auto_in_a_valid(widget_auto_in_a_valid), .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode), .auto_in_a_bits_param(widget_auto_in_a_bits_param), .auto_in_a_bits_size(widget_auto_in_a_bits_size), .auto_in_a_bits_source(widget_auto_in_a_bits_source), .auto_in_a_bits_address(widget_auto_in_a_bits_address), .auto_in_a_bits_mask(widget_auto_in_a_bits_mask), .auto_in_a_bits_data(widget_auto_in_a_bits_data), .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt), .auto_in_d_ready(widget_auto_in_d_ready), .auto_in_d_valid(widget_auto_in_d_valid), .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode), .auto_in_d_bits_size(widget_auto_in_d_bits_size), .auto_in_d_bits_source(widget_auto_in_d_bits_source), .auto_in_d_bits_denied(widget_auto_in_d_bits_denied), .auto_in_d_bits_data(widget_auto_in_d_bits_data), .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt), .auto_out_a_ready(widget_auto_out_a_ready), .auto_out_a_valid(widget_auto_out_a_valid), .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode), .auto_out_a_bits_param(widget_auto_out_a_bits_param), .auto_out_a_bits_size(widget_auto_out_a_bits_size), .auto_out_a_bits_source(widget_auto_out_a_bits_source), .auto_out_a_bits_address(widget_auto_out_a_bits_address), .auto_out_a_bits_mask(widget_auto_out_a_bits_mask), .auto_out_a_bits_data(widget_auto_out_a_bits_data), .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt), .auto_out_d_ready(widget_auto_out_d_ready), .auto_out_d_valid(widget_auto_out_d_valid), .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode), .auto_out_d_bits_param(widget_auto_out_d_bits_param), .auto_out_d_bits_size(widget_auto_out_d_bits_size), .auto_out_d_bits_source(widget_auto_out_d_bits_source), .auto_out_d_bits_sink(widget_auto_out_d_bits_sink), .auto_out_d_bits_denied(widget_auto_out_d_bits_denied), .auto_out_d_bits_data(widget_auto_out_d_bits_data), .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt) ); AXI4ToTL axi42tl ( // @[ToTL.scala 168:29:freechips.rocketchip.system.TinyConfig.fir@28455.4] .clock(axi42tl_clock), .reset(axi42tl_reset), .auto_in_aw_ready(axi42tl_auto_in_aw_ready), .auto_in_aw_valid(axi42tl_auto_in_aw_valid), .auto_in_aw_bits_id(axi42tl_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi42tl_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi42tl_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi42tl_auto_in_aw_bits_size), .auto_in_w_ready(axi42tl_auto_in_w_ready), .auto_in_w_valid(axi42tl_auto_in_w_valid), .auto_in_w_bits_data(axi42tl_auto_in_w_bits_data), .auto_in_w_bits_strb(axi42tl_auto_in_w_bits_strb), .auto_in_w_bits_last(axi42tl_auto_in_w_bits_last), .auto_in_b_ready(axi42tl_auto_in_b_ready), .auto_in_b_valid(axi42tl_auto_in_b_valid), .auto_in_b_bits_id(axi42tl_auto_in_b_bits_id), .auto_in_b_bits_resp(axi42tl_auto_in_b_bits_resp), .auto_in_ar_ready(axi42tl_auto_in_ar_ready), .auto_in_ar_valid(axi42tl_auto_in_ar_valid), .auto_in_ar_bits_id(axi42tl_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi42tl_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi42tl_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi42tl_auto_in_ar_bits_size), .auto_in_r_ready(axi42tl_auto_in_r_ready), .auto_in_r_valid(axi42tl_auto_in_r_valid), .auto_in_r_bits_id(axi42tl_auto_in_r_bits_id), .auto_in_r_bits_data(axi42tl_auto_in_r_bits_data), .auto_in_r_bits_resp(axi42tl_auto_in_r_bits_resp), .auto_in_r_bits_last(axi42tl_auto_in_r_bits_last), .auto_out_a_ready(axi42tl_auto_out_a_ready), .auto_out_a_valid(axi42tl_auto_out_a_valid), .auto_out_a_bits_opcode(axi42tl_auto_out_a_bits_opcode), .auto_out_a_bits_param(axi42tl_auto_out_a_bits_param), .auto_out_a_bits_size(axi42tl_auto_out_a_bits_size), .auto_out_a_bits_source(axi42tl_auto_out_a_bits_source), .auto_out_a_bits_address(axi42tl_auto_out_a_bits_address), .auto_out_a_bits_mask(axi42tl_auto_out_a_bits_mask), .auto_out_a_bits_data(axi42tl_auto_out_a_bits_data), .auto_out_a_bits_corrupt(axi42tl_auto_out_a_bits_corrupt), .auto_out_d_ready(axi42tl_auto_out_d_ready), .auto_out_d_valid(axi42tl_auto_out_d_valid), .auto_out_d_bits_opcode(axi42tl_auto_out_d_bits_opcode), .auto_out_d_bits_size(axi42tl_auto_out_d_bits_size), .auto_out_d_bits_source(axi42tl_auto_out_d_bits_source), .auto_out_d_bits_denied(axi42tl_auto_out_d_bits_denied), .auto_out_d_bits_data(axi42tl_auto_out_d_bits_data), .auto_out_d_bits_corrupt(axi42tl_auto_out_d_bits_corrupt) ); AXI4UserYanker_1 axi4yank ( // @[UserYanker.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@28461.4] .clock(axi4yank_clock), .reset(axi4yank_reset), .auto_in_aw_ready(axi4yank_auto_in_aw_ready), .auto_in_aw_valid(axi4yank_auto_in_aw_valid), .auto_in_aw_bits_id(axi4yank_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4yank_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4yank_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4yank_auto_in_aw_bits_size), .auto_in_aw_bits_user(axi4yank_auto_in_aw_bits_user), .auto_in_w_ready(axi4yank_auto_in_w_ready), .auto_in_w_valid(axi4yank_auto_in_w_valid), .auto_in_w_bits_data(axi4yank_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4yank_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4yank_auto_in_w_bits_last), .auto_in_b_ready(axi4yank_auto_in_b_ready), .auto_in_b_valid(axi4yank_auto_in_b_valid), .auto_in_b_bits_id(axi4yank_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4yank_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4yank_auto_in_b_bits_user), .auto_in_ar_ready(axi4yank_auto_in_ar_ready), .auto_in_ar_valid(axi4yank_auto_in_ar_valid), .auto_in_ar_bits_id(axi4yank_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4yank_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4yank_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4yank_auto_in_ar_bits_size), .auto_in_ar_bits_user(axi4yank_auto_in_ar_bits_user), .auto_in_r_ready(axi4yank_auto_in_r_ready), .auto_in_r_valid(axi4yank_auto_in_r_valid), .auto_in_r_bits_id(axi4yank_auto_in_r_bits_id), .auto_in_r_bits_data(axi4yank_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4yank_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4yank_auto_in_r_bits_user), .auto_in_r_bits_last(axi4yank_auto_in_r_bits_last), .auto_out_aw_ready(axi4yank_auto_out_aw_ready), .auto_out_aw_valid(axi4yank_auto_out_aw_valid), .auto_out_aw_bits_id(axi4yank_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4yank_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4yank_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4yank_auto_out_aw_bits_size), .auto_out_w_ready(axi4yank_auto_out_w_ready), .auto_out_w_valid(axi4yank_auto_out_w_valid), .auto_out_w_bits_data(axi4yank_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4yank_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4yank_auto_out_w_bits_last), .auto_out_b_ready(axi4yank_auto_out_b_ready), .auto_out_b_valid(axi4yank_auto_out_b_valid), .auto_out_b_bits_id(axi4yank_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4yank_auto_out_b_bits_resp), .auto_out_ar_ready(axi4yank_auto_out_ar_ready), .auto_out_ar_valid(axi4yank_auto_out_ar_valid), .auto_out_ar_bits_id(axi4yank_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4yank_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4yank_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4yank_auto_out_ar_bits_size), .auto_out_r_ready(axi4yank_auto_out_r_ready), .auto_out_r_valid(axi4yank_auto_out_r_valid), .auto_out_r_bits_id(axi4yank_auto_out_r_bits_id), .auto_out_r_bits_data(axi4yank_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4yank_auto_out_r_bits_resp), .auto_out_r_bits_last(axi4yank_auto_out_r_bits_last) ); AXI4Fragmenter axi4frag ( // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@28467.4] .clock(axi4frag_clock), .reset(axi4frag_reset), .auto_in_aw_ready(axi4frag_auto_in_aw_ready), .auto_in_aw_valid(axi4frag_auto_in_aw_valid), .auto_in_aw_bits_id(axi4frag_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4frag_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4frag_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4frag_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4frag_auto_in_aw_bits_burst), .auto_in_aw_bits_user(axi4frag_auto_in_aw_bits_user), .auto_in_w_ready(axi4frag_auto_in_w_ready), .auto_in_w_valid(axi4frag_auto_in_w_valid), .auto_in_w_bits_data(axi4frag_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4frag_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4frag_auto_in_w_bits_last), .auto_in_b_ready(axi4frag_auto_in_b_ready), .auto_in_b_valid(axi4frag_auto_in_b_valid), .auto_in_b_bits_id(axi4frag_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4frag_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4frag_auto_in_b_bits_user), .auto_in_ar_ready(axi4frag_auto_in_ar_ready), .auto_in_ar_valid(axi4frag_auto_in_ar_valid), .auto_in_ar_bits_id(axi4frag_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4frag_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4frag_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4frag_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4frag_auto_in_ar_bits_burst), .auto_in_ar_bits_user(axi4frag_auto_in_ar_bits_user), .auto_in_r_ready(axi4frag_auto_in_r_ready), .auto_in_r_valid(axi4frag_auto_in_r_valid), .auto_in_r_bits_id(axi4frag_auto_in_r_bits_id), .auto_in_r_bits_data(axi4frag_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4frag_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4frag_auto_in_r_bits_user), .auto_in_r_bits_last(axi4frag_auto_in_r_bits_last), .auto_out_aw_ready(axi4frag_auto_out_aw_ready), .auto_out_aw_valid(axi4frag_auto_out_aw_valid), .auto_out_aw_bits_id(axi4frag_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4frag_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4frag_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4frag_auto_out_aw_bits_size), .auto_out_aw_bits_user(axi4frag_auto_out_aw_bits_user), .auto_out_w_ready(axi4frag_auto_out_w_ready), .auto_out_w_valid(axi4frag_auto_out_w_valid), .auto_out_w_bits_data(axi4frag_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4frag_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4frag_auto_out_w_bits_last), .auto_out_b_ready(axi4frag_auto_out_b_ready), .auto_out_b_valid(axi4frag_auto_out_b_valid), .auto_out_b_bits_id(axi4frag_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4frag_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4frag_auto_out_b_bits_user), .auto_out_ar_ready(axi4frag_auto_out_ar_ready), .auto_out_ar_valid(axi4frag_auto_out_ar_valid), .auto_out_ar_bits_id(axi4frag_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4frag_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4frag_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4frag_auto_out_ar_bits_size), .auto_out_ar_bits_user(axi4frag_auto_out_ar_bits_user), .auto_out_r_ready(axi4frag_auto_out_r_ready), .auto_out_r_valid(axi4frag_auto_out_r_valid), .auto_out_r_bits_id(axi4frag_auto_out_r_bits_id), .auto_out_r_bits_data(axi4frag_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4frag_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4frag_auto_out_r_bits_user), .auto_out_r_bits_last(axi4frag_auto_out_r_bits_last) ); AXI4IdIndexer_1 axi4index ( // @[IdIndexer.scala 80:31:freechips.rocketchip.system.TinyConfig.fir@28473.4] .auto_in_aw_ready(axi4index_auto_in_aw_ready), .auto_in_aw_valid(axi4index_auto_in_aw_valid), .auto_in_aw_bits_id(axi4index_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4index_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4index_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4index_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4index_auto_in_aw_bits_burst), .auto_in_w_ready(axi4index_auto_in_w_ready), .auto_in_w_valid(axi4index_auto_in_w_valid), .auto_in_w_bits_data(axi4index_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4index_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4index_auto_in_w_bits_last), .auto_in_b_ready(axi4index_auto_in_b_ready), .auto_in_b_valid(axi4index_auto_in_b_valid), .auto_in_b_bits_id(axi4index_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4index_auto_in_b_bits_resp), .auto_in_ar_ready(axi4index_auto_in_ar_ready), .auto_in_ar_valid(axi4index_auto_in_ar_valid), .auto_in_ar_bits_id(axi4index_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4index_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4index_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4index_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4index_auto_in_ar_bits_burst), .auto_in_r_ready(axi4index_auto_in_r_ready), .auto_in_r_valid(axi4index_auto_in_r_valid), .auto_in_r_bits_id(axi4index_auto_in_r_bits_id), .auto_in_r_bits_data(axi4index_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4index_auto_in_r_bits_resp), .auto_in_r_bits_last(axi4index_auto_in_r_bits_last), .auto_out_aw_ready(axi4index_auto_out_aw_ready), .auto_out_aw_valid(axi4index_auto_out_aw_valid), .auto_out_aw_bits_id(axi4index_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4index_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4index_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4index_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4index_auto_out_aw_bits_burst), .auto_out_aw_bits_user(axi4index_auto_out_aw_bits_user), .auto_out_w_ready(axi4index_auto_out_w_ready), .auto_out_w_valid(axi4index_auto_out_w_valid), .auto_out_w_bits_data(axi4index_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4index_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4index_auto_out_w_bits_last), .auto_out_b_ready(axi4index_auto_out_b_ready), .auto_out_b_valid(axi4index_auto_out_b_valid), .auto_out_b_bits_id(axi4index_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4index_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4index_auto_out_b_bits_user), .auto_out_ar_ready(axi4index_auto_out_ar_ready), .auto_out_ar_valid(axi4index_auto_out_ar_valid), .auto_out_ar_bits_id(axi4index_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4index_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4index_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4index_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4index_auto_out_ar_bits_burst), .auto_out_ar_bits_user(axi4index_auto_out_ar_bits_user), .auto_out_r_ready(axi4index_auto_out_r_ready), .auto_out_r_valid(axi4index_auto_out_r_valid), .auto_out_r_bits_id(axi4index_auto_out_r_bits_id), .auto_out_r_bits_data(axi4index_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4index_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4index_auto_out_r_bits_user), .auto_out_r_bits_last(axi4index_auto_out_r_bits_last) ); assign auto_axi4index_in_aw_ready = axi4index_auto_in_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_w_ready = axi4index_auto_in_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_b_valid = axi4index_auto_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_b_bits_id = axi4index_auto_in_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_b_bits_resp = axi4index_auto_in_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_ar_ready = axi4index_auto_in_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_r_valid = axi4index_auto_in_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_r_bits_id = axi4index_auto_in_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_r_bits_data = axi4index_auto_in_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_r_bits_resp = axi4index_auto_in_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_axi4index_in_r_bits_last = axi4index_auto_in_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28441.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28442.4] assign buffer_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28485.4] assign fixer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28447.4] assign fixer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28448.4] assign fixer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign fixer_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign fixer_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28479.4] assign widget_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28453.4] assign widget_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28454.4] assign widget_auto_in_a_valid = axi42tl_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_opcode = axi42tl_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_param = axi42tl_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_size = axi42tl_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_source = axi42tl_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_address = axi42tl_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_mask = axi42tl_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_data = axi42tl_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_a_bits_corrupt = axi42tl_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_in_d_ready = axi42tl_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign widget_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign widget_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28480.4] assign axi42tl_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28459.4] assign axi42tl_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28460.4] assign axi42tl_auto_in_aw_valid = axi4yank_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_aw_bits_id = axi4yank_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_aw_bits_addr = axi4yank_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_aw_bits_len = axi4yank_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_aw_bits_size = axi4yank_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_w_valid = axi4yank_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_w_bits_data = axi4yank_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_w_bits_strb = axi4yank_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_w_bits_last = axi4yank_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_b_ready = axi4yank_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_ar_valid = axi4yank_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_ar_bits_id = axi4yank_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_ar_bits_addr = axi4yank_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_ar_bits_len = axi4yank_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_ar_bits_size = axi4yank_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_in_r_ready = axi4yank_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi42tl_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi42tl_auto_out_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28481.4] assign axi4yank_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28465.4] assign axi4yank_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28466.4] assign axi4yank_auto_in_aw_valid = axi4frag_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_aw_bits_id = axi4frag_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_aw_bits_addr = axi4frag_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_aw_bits_len = axi4frag_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_aw_bits_size = axi4frag_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_aw_bits_user = axi4frag_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_w_valid = axi4frag_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_w_bits_data = axi4frag_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_w_bits_strb = axi4frag_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_w_bits_last = axi4frag_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_b_ready = axi4frag_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_valid = axi4frag_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_bits_id = axi4frag_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_bits_addr = axi4frag_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_bits_len = axi4frag_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_bits_size = axi4frag_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_ar_bits_user = axi4frag_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_in_r_ready = axi4frag_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4yank_auto_out_aw_ready = axi42tl_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_w_ready = axi42tl_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_b_valid = axi42tl_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_b_bits_id = axi42tl_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_b_bits_resp = axi42tl_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_ar_ready = axi42tl_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_r_valid = axi42tl_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_r_bits_id = axi42tl_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_r_bits_data = axi42tl_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_r_bits_resp = axi42tl_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4yank_auto_out_r_bits_last = axi42tl_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28482.4] assign axi4frag_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28471.4] assign axi4frag_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28472.4] assign axi4frag_auto_in_aw_valid = axi4index_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_id = axi4index_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_addr = axi4index_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_len = axi4index_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_size = axi4index_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_burst = axi4index_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_aw_bits_user = axi4index_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_w_valid = axi4index_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_w_bits_data = axi4index_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_w_bits_strb = axi4index_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_w_bits_last = axi4index_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_b_ready = axi4index_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_valid = axi4index_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_id = axi4index_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_addr = axi4index_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_len = axi4index_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_size = axi4index_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_burst = axi4index_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_ar_bits_user = axi4index_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_in_r_ready = axi4index_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4frag_auto_out_aw_ready = axi4yank_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_w_ready = axi4yank_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_b_valid = axi4yank_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_b_bits_id = axi4yank_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_b_bits_resp = axi4yank_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_b_bits_user = axi4yank_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_ar_ready = axi4yank_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_valid = axi4yank_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_bits_id = axi4yank_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_bits_data = axi4yank_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_bits_resp = axi4yank_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_bits_user = axi4yank_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4frag_auto_out_r_bits_last = axi4yank_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28483.4] assign axi4index_auto_in_aw_valid = auto_axi4index_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_aw_bits_id = auto_axi4index_in_aw_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_aw_bits_addr = auto_axi4index_in_aw_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_aw_bits_len = auto_axi4index_in_aw_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_aw_bits_size = auto_axi4index_in_aw_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_aw_bits_burst = auto_axi4index_in_aw_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_w_valid = auto_axi4index_in_w_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_w_bits_data = auto_axi4index_in_w_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_w_bits_strb = auto_axi4index_in_w_bits_strb; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_w_bits_last = auto_axi4index_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_b_ready = auto_axi4index_in_b_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_valid = auto_axi4index_in_ar_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_bits_id = auto_axi4index_in_ar_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_bits_addr = auto_axi4index_in_ar_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_bits_len = auto_axi4index_in_ar_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_bits_size = auto_axi4index_in_ar_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_ar_bits_burst = auto_axi4index_in_ar_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_in_r_ready = auto_axi4index_in_r_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28486.4] assign axi4index_auto_out_aw_ready = axi4frag_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_w_ready = axi4frag_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_b_valid = axi4frag_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_b_bits_id = axi4frag_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_b_bits_resp = axi4frag_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_b_bits_user = axi4frag_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_ar_ready = axi4frag_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_valid = axi4frag_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_bits_id = axi4frag_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_bits_data = axi4frag_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_bits_resp = axi4frag_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_bits_user = axi4frag_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] assign axi4index_auto_out_r_bits_last = axi4frag_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28484.4] endmodule module FrontBus( // @[:freechips.rocketchip.system.TinyConfig.fir@28488.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@28489.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@28490.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [31:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [2:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [63:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [31:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [2:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [63:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [2:0] auto_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [3:0] auto_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [3:0] auto_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [31:0] auto_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [3:0] auto_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output [31:0] auto_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] output auto_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [1:0] auto_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [3:0] auto_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [3:0] auto_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input [31:0] auto_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] input auto_bus_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@28491.4] ); wire front_bus_xbar_clock; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_reset; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_in_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_in_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_in_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_in_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_in_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_in_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_in_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_in_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [1:0] front_bus_xbar_auto_in_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_in_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_in_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_in_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_in_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_out_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_out_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_out_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_out_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_out_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_out_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_out_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [2:0] front_bus_xbar_auto_out_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [1:0] front_bus_xbar_auto_out_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_out_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [3:0] front_bus_xbar_auto_out_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire [31:0] front_bus_xbar_auto_out_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire front_bus_xbar_auto_out_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] wire coupler_from_port_named_slave_port_axi4_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [31:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [2:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [63:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [31:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [2:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [63:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [31:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [31:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [1:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire [31:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] TLXbar_3 front_bus_xbar ( // @[BusWrapper.scala 179:32:freechips.rocketchip.system.TinyConfig.fir@28496.4] .clock(front_bus_xbar_clock), .reset(front_bus_xbar_reset), .auto_in_a_ready(front_bus_xbar_auto_in_a_ready), .auto_in_a_valid(front_bus_xbar_auto_in_a_valid), .auto_in_a_bits_opcode(front_bus_xbar_auto_in_a_bits_opcode), .auto_in_a_bits_param(front_bus_xbar_auto_in_a_bits_param), .auto_in_a_bits_size(front_bus_xbar_auto_in_a_bits_size), .auto_in_a_bits_source(front_bus_xbar_auto_in_a_bits_source), .auto_in_a_bits_address(front_bus_xbar_auto_in_a_bits_address), .auto_in_a_bits_mask(front_bus_xbar_auto_in_a_bits_mask), .auto_in_a_bits_data(front_bus_xbar_auto_in_a_bits_data), .auto_in_a_bits_corrupt(front_bus_xbar_auto_in_a_bits_corrupt), .auto_in_d_ready(front_bus_xbar_auto_in_d_ready), .auto_in_d_valid(front_bus_xbar_auto_in_d_valid), .auto_in_d_bits_opcode(front_bus_xbar_auto_in_d_bits_opcode), .auto_in_d_bits_param(front_bus_xbar_auto_in_d_bits_param), .auto_in_d_bits_size(front_bus_xbar_auto_in_d_bits_size), .auto_in_d_bits_source(front_bus_xbar_auto_in_d_bits_source), .auto_in_d_bits_sink(front_bus_xbar_auto_in_d_bits_sink), .auto_in_d_bits_denied(front_bus_xbar_auto_in_d_bits_denied), .auto_in_d_bits_data(front_bus_xbar_auto_in_d_bits_data), .auto_in_d_bits_corrupt(front_bus_xbar_auto_in_d_bits_corrupt), .auto_out_a_ready(front_bus_xbar_auto_out_a_ready), .auto_out_a_valid(front_bus_xbar_auto_out_a_valid), .auto_out_a_bits_opcode(front_bus_xbar_auto_out_a_bits_opcode), .auto_out_a_bits_param(front_bus_xbar_auto_out_a_bits_param), .auto_out_a_bits_size(front_bus_xbar_auto_out_a_bits_size), .auto_out_a_bits_source(front_bus_xbar_auto_out_a_bits_source), .auto_out_a_bits_address(front_bus_xbar_auto_out_a_bits_address), .auto_out_a_bits_mask(front_bus_xbar_auto_out_a_bits_mask), .auto_out_a_bits_data(front_bus_xbar_auto_out_a_bits_data), .auto_out_a_bits_corrupt(front_bus_xbar_auto_out_a_bits_corrupt), .auto_out_d_ready(front_bus_xbar_auto_out_d_ready), .auto_out_d_valid(front_bus_xbar_auto_out_d_valid), .auto_out_d_bits_opcode(front_bus_xbar_auto_out_d_bits_opcode), .auto_out_d_bits_param(front_bus_xbar_auto_out_d_bits_param), .auto_out_d_bits_size(front_bus_xbar_auto_out_d_bits_size), .auto_out_d_bits_source(front_bus_xbar_auto_out_d_bits_source), .auto_out_d_bits_sink(front_bus_xbar_auto_out_d_bits_sink), .auto_out_d_bits_denied(front_bus_xbar_auto_out_d_bits_denied), .auto_out_d_bits_data(front_bus_xbar_auto_out_d_bits_data), .auto_out_d_bits_corrupt(front_bus_xbar_auto_out_d_bits_corrupt) ); TLBuffer_4 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@28502.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); SimpleLazyModule_4 coupler_from_port_named_slave_port_axi4 ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@28508.4] .clock(coupler_from_port_named_slave_port_axi4_clock), .reset(coupler_from_port_named_slave_port_axi4_reset), .auto_axi4index_in_aw_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready), .auto_axi4index_in_aw_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid), .auto_axi4index_in_aw_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id), .auto_axi4index_in_aw_bits_addr(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr), .auto_axi4index_in_aw_bits_len(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len), .auto_axi4index_in_aw_bits_size(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size), .auto_axi4index_in_aw_bits_burst(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst), .auto_axi4index_in_w_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready), .auto_axi4index_in_w_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid), .auto_axi4index_in_w_bits_data(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data), .auto_axi4index_in_w_bits_strb(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb), .auto_axi4index_in_w_bits_last(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last), .auto_axi4index_in_b_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready), .auto_axi4index_in_b_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid), .auto_axi4index_in_b_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id), .auto_axi4index_in_b_bits_resp(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp), .auto_axi4index_in_ar_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready), .auto_axi4index_in_ar_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid), .auto_axi4index_in_ar_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id), .auto_axi4index_in_ar_bits_addr(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr), .auto_axi4index_in_ar_bits_len(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len), .auto_axi4index_in_ar_bits_size(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size), .auto_axi4index_in_ar_bits_burst(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst), .auto_axi4index_in_r_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready), .auto_axi4index_in_r_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid), .auto_axi4index_in_r_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id), .auto_axi4index_in_r_bits_data(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data), .auto_axi4index_in_r_bits_resp(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp), .auto_axi4index_in_r_bits_last(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last), .auto_buffer_out_a_ready(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready), .auto_buffer_out_a_valid(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready), .auto_buffer_out_d_valid(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid), .auto_buffer_out_d_bits_opcode(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode), .auto_buffer_out_d_bits_param(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param), .auto_buffer_out_d_bits_size(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size), .auto_buffer_out_d_bits_source(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source), .auto_buffer_out_d_bits_sink(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink), .auto_buffer_out_d_bits_denied(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied), .auto_buffer_out_d_bits_data(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data), .auto_buffer_out_d_bits_corrupt(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt) ); assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign auto_bus_xing_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign auto_bus_xing_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@28522.4] assign front_bus_xbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28500.4] assign front_bus_xbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28501.4] assign front_bus_xbar_auto_in_a_valid = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_opcode = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_param = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_size = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_source = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_address = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_mask = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_data = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_a_bits_corrupt = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_in_d_ready = coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign front_bus_xbar_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign front_bus_xbar_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28506.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28507.4] assign buffer_auto_in_a_valid = front_bus_xbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_opcode = front_bus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_param = front_bus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_size = front_bus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_source = front_bus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_address = front_bus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_mask = front_bus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_data = front_bus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_a_bits_corrupt = front_bus_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_in_d_ready = front_bus_xbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@28519.4] assign buffer_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign buffer_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28520.4] assign coupler_from_port_named_slave_port_axi4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@28512.4] assign coupler_from_port_named_slave_port_axi4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@28513.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@28523.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready = front_bus_xbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid = front_bus_xbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode = front_bus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param = front_bus_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size = front_bus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source = front_bus_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink = front_bus_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied = front_bus_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data = front_bus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt = front_bus_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@28521.4] endmodule module TLMonitor_14( // @[:freechips.rocketchip.system.TinyConfig.fir@28561.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@28562.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@28563.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@28564.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@30033.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@28579.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@28580.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@28583.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@28584.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@28592.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28603.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28604.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28605.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28607.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28608.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28609.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@28610.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@28610.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@28611.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@28613.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@28614.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@28616.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@28617.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@28618.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@28619.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@28620.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28622.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28623.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28625.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28626.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@28627.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@28628.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@28629.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28630.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28631.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28632.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28633.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28634.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28635.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28636.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28637.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28638.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28639.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28640.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28641.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28644.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28648.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@28701.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28704.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28705.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28706.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28707.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28708.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28709.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28710.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28711.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28712.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28713.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28714.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28715.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28716.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28717.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28718.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28721.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28722.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28723.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28724.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28725.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28726.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28727.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28728.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28729.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28730.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28731.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28732.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28733.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28743.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28756.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28757.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28764.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28765.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28771.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28772.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@28777.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28779.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28780.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@28785.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@28786.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28788.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28789.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@28794.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28796.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28797.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@28803.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@28887.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28889.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28890.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@28913.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@28916.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@28924.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@28926.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28954.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28955.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28956.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28957.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@28958.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@28960.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28962.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28963.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@28982.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28984.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28985.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@28990.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28992.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28993.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@29007.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29046.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@29055.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29058.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29059.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@29095.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@29174.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@29175.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@29176.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29178.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29179.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@29185.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@29188.8] wire _T_470; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29196.8] wire _T_496; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@29222.8] wire _T_503; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29229.8] wire _T_506; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@29232.8] wire _T_508; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29234.8] wire _T_509; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29235.8] wire _T_516; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@29254.8] wire _T_518; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29256.8] wire _T_519; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29257.8] wire _T_524; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@29271.6] wire _T_580; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@29340.8] wire _T_582; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29342.8] wire _T_583; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29343.8] wire _T_588; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@29357.6] wire _T_633; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29403.8] wire _T_634; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29404.8] wire _T_649; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@29442.6] wire _T_651; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29444.6] wire _T_652; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29445.6] wire _T_653; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@29450.6] wire _T_654; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@29451.6] wire [1:0] _T_657; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@29454.6] wire _T_658; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@29455.6] wire _T_666; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@29463.6] wire _T_672; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29474.6] wire _T_673; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29475.6] wire _T_674; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29476.6] wire _T_676; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@29478.6] wire _T_678; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29481.8] wire _T_679; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29482.8] wire _T_680; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@29487.8] wire _T_682; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29489.8] wire _T_683; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29490.8] wire _T_684; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@29495.8] wire _T_686; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29497.8] wire _T_687; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29498.8] wire _T_688; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@29503.8] wire _T_690; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29505.8] wire _T_691; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29506.8] wire _T_692; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@29511.8] wire _T_694; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29513.8] wire _T_695; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29514.8] wire _T_696; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@29520.6] wire _T_707; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@29544.8] wire _T_709; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29546.8] wire _T_710; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29547.8] wire _T_711; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@29552.8] wire _T_713; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29554.8] wire _T_714; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29555.8] wire _T_724; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@29578.6] wire _T_744; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@29619.8] wire _T_746; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29621.8] wire _T_747; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29622.8] wire _T_753; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@29637.6] wire _T_770; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@29672.6] wire _T_788; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@29708.6] wire _T_817; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@29768.4] wire [9:0] _T_822; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@29773.4] wire _T_823; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@29774.4] wire _T_824; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@29775.4] reg [9:0] _T_826; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@29777.4] reg [31:0] _RAND_0; wire [9:0] _T_828; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29779.4] wire _T_829; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29780.4] reg [2:0] _T_837; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@29791.4] reg [31:0] _RAND_1; reg [2:0] _T_838; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@29792.4] reg [31:0] _RAND_2; reg [3:0] _T_839; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@29793.4] reg [31:0] _RAND_3; reg [4:0] _T_840; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@29794.4] reg [31:0] _RAND_4; reg [31:0] _T_841; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@29795.4] reg [31:0] _RAND_5; wire _T_842; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@29796.4] wire _T_843; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@29797.4] wire _T_844; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@29799.6] wire _T_846; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29801.6] wire _T_847; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29802.6] wire _T_848; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@29807.6] wire _T_850; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29809.6] wire _T_851; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29810.6] wire _T_852; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@29815.6] wire _T_854; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29817.6] wire _T_855; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29818.6] wire _T_856; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@29823.6] wire _T_858; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29825.6] wire _T_859; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29826.6] wire _T_860; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@29831.6] wire _T_862; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29833.6] wire _T_863; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29834.6] wire _T_865; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@29841.4] wire _T_866; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@29849.4] wire [26:0] _T_868; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@29851.4] wire [11:0] _T_869; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@29852.4] wire [11:0] _T_870; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@29853.4] wire [9:0] _T_871; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@29854.4] wire _T_872; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@29855.4] reg [9:0] _T_874; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@29857.4] reg [31:0] _RAND_6; wire [9:0] _T_876; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29859.4] wire _T_877; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29860.4] reg [2:0] _T_885; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@29871.4] reg [31:0] _RAND_7; reg [1:0] _T_886; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@29872.4] reg [31:0] _RAND_8; reg [3:0] _T_887; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@29873.4] reg [31:0] _RAND_9; reg [4:0] _T_888; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@29874.4] reg [31:0] _RAND_10; reg _T_889; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@29875.4] reg [31:0] _RAND_11; reg _T_890; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@29876.4] reg [31:0] _RAND_12; wire _T_891; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@29877.4] wire _T_892; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@29878.4] wire _T_893; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@29880.6] wire _T_895; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29882.6] wire _T_896; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29883.6] wire _T_897; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@29888.6] wire _T_899; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29890.6] wire _T_900; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29891.6] wire _T_901; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@29896.6] wire _T_903; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29898.6] wire _T_904; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29899.6] wire _T_905; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@29904.6] wire _T_907; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29906.6] wire _T_908; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29907.6] wire _T_909; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@29912.6] wire _T_911; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29914.6] wire _T_912; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29915.6] wire _T_913; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@29920.6] wire _T_915; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29922.6] wire _T_916; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29923.6] wire _T_918; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@29930.4] reg [17:0] _T_919; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@29939.4] reg [31:0] _RAND_13; reg [9:0] _T_929; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@29949.4] reg [31:0] _RAND_14; wire [9:0] _T_931; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29951.4] wire _T_932; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29952.4] reg [9:0] _T_948; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@29971.4] reg [31:0] _RAND_15; wire [9:0] _T_950; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29973.4] wire _T_951; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29974.4] wire _T_961; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@29989.4] wire [31:0] _T_963; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@29992.6] wire [17:0] _T_964; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@29994.6] wire _T_965; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@29995.6] wire _T_966; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@29996.6] wire _T_968; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@29998.6] wire _T_969; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@29999.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@29991.4] wire _T_973; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@30010.4] wire _T_975; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@30012.4] wire _T_976; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@30013.4] wire [31:0] _T_977; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@30015.6] wire [17:0] _T_959; // @[:freechips.rocketchip.system.TinyConfig.fir@29985.4 :freechips.rocketchip.system.TinyConfig.fir@29987.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@29993.6] wire [17:0] _T_978; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@30017.6] wire [17:0] _T_979; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@30018.6] wire _T_980; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@30019.6] wire _T_982; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30021.6] wire _T_983; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30022.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@30014.4] wire [17:0] _T_984; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@30028.4] wire [17:0] _T_970; // @[:freechips.rocketchip.system.TinyConfig.fir@30005.4 :freechips.rocketchip.system.TinyConfig.fir@30007.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@30016.6] wire [17:0] _T_985; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@30029.4] wire [17:0] _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@30030.4] reg [31:0] _T_987; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@30032.4] reg [31:0] _RAND_16; wire _T_988; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@30035.4] wire _T_989; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@30036.4] wire _T_990; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@30037.4] wire _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@30038.4] wire _T_992; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@30039.4] wire _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@30040.4] wire _T_995; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30042.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30043.4] wire [31:0] _T_998; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@30049.4] wire _T_1001; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@30053.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28745.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@28847.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28965.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29061.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@29149.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29237.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@29323.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29406.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29484.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@29526.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@29584.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@29643.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@29678.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@29714.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@30033.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@28579.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@28580.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@28583.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@28584.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@28592.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28603.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28604.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@28605.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@28607.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@28608.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@28609.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@28610.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@28610.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@28611.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@28613.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@28614.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@28616.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@28617.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@28618.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@28619.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@28620.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28622.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28623.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28625.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28626.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@28627.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@28628.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@28629.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28630.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28631.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28632.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28633.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28634.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28635.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28636.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28637.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28638.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@28639.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@28640.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@28641.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@28644.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28648.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@28701.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28704.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28705.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28706.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28707.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28708.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28709.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28710.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28711.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28712.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28713.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28714.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28715.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28716.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28717.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28718.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28721.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28722.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28723.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28724.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28725.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28726.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28727.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28728.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@28729.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@28730.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28731.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@28732.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@28733.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28743.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28756.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28757.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28764.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28765.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28771.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28772.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@28777.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28779.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28780.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@28785.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@28786.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28788.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28789.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@28794.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28796.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28797.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@28803.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@28887.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28889.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28890.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@28913.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@28916.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@28924.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@28926.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28954.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28955.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28956.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@28957.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@28958.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@28960.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28962.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28963.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@28982.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28984.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28985.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@28990.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28992.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28993.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@29007.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29046.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@29055.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29058.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29059.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@29095.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@29174.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@29175.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@29176.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29178.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29179.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@29185.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@29188.8] assign _T_470 = _T_462 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29196.8] assign _T_496 = 4'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@29222.8] assign _T_503 = _T_496 & _T_144; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@29229.8] assign _T_506 = _T_470 | _T_503; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@29232.8] assign _T_508 = _T_506 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29234.8] assign _T_509 = _T_508 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29235.8] assign _T_516 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@29254.8] assign _T_518 = _T_516 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29256.8] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29257.8] assign _T_524 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@29271.6] assign _T_580 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@29340.8] assign _T_582 = _T_580 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29342.8] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29343.8] assign _T_588 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@29357.6] assign _T_633 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29403.8] assign _T_634 = _T_633 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29404.8] assign _T_649 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@29442.6] assign _T_651 = _T_649 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29444.6] assign _T_652 = _T_651 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29445.6] assign _T_653 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@29450.6] assign _T_654 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@29451.6] assign _T_657 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@29454.6] assign _T_658 = _T_657 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@29455.6] assign _T_666 = _T_657 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@29463.6] assign _T_672 = _T_653 | _T_654; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29474.6] assign _T_673 = _T_672 | _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29475.6] assign _T_674 = _T_673 | _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@29476.6] assign _T_676 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@29478.6] assign _T_678 = _T_674 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29481.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29482.8] assign _T_680 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@29487.8] assign _T_682 = _T_680 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29489.8] assign _T_683 = _T_682 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29490.8] assign _T_684 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@29495.8] assign _T_686 = _T_684 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29497.8] assign _T_687 = _T_686 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29498.8] assign _T_688 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@29503.8] assign _T_690 = _T_688 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29505.8] assign _T_691 = _T_690 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29506.8] assign _T_692 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@29511.8] assign _T_694 = _T_692 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29513.8] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29514.8] assign _T_696 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@29520.6] assign _T_707 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@29544.8] assign _T_709 = _T_707 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29546.8] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29547.8] assign _T_711 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@29552.8] assign _T_713 = _T_711 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29554.8] assign _T_714 = _T_713 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29555.8] assign _T_724 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@29578.6] assign _T_744 = _T_692 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@29619.8] assign _T_746 = _T_744 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29621.8] assign _T_747 = _T_746 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29622.8] assign _T_753 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@29637.6] assign _T_770 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@29672.6] assign _T_788 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@29708.6] assign _T_817 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@29768.4] assign _T_822 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@29773.4] assign _T_823 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@29774.4] assign _T_824 = _T_823 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@29775.4] assign _T_828 = _T_826 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29779.4] assign _T_829 = _T_826 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29780.4] assign _T_842 = _T_829 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@29796.4] assign _T_843 = io_in_a_valid & _T_842; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@29797.4] assign _T_844 = io_in_a_bits_opcode == _T_837; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@29799.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29801.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29802.6] assign _T_848 = io_in_a_bits_param == _T_838; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@29807.6] assign _T_850 = _T_848 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29809.6] assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29810.6] assign _T_852 = io_in_a_bits_size == _T_839; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@29815.6] assign _T_854 = _T_852 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29817.6] assign _T_855 = _T_854 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29818.6] assign _T_856 = io_in_a_bits_source == _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@29823.6] assign _T_858 = _T_856 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29825.6] assign _T_859 = _T_858 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29826.6] assign _T_860 = io_in_a_bits_address == _T_841; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@29831.6] assign _T_862 = _T_860 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29833.6] assign _T_863 = _T_862 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29834.6] assign _T_865 = _T_817 & _T_829; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@29841.4] assign _T_866 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@29849.4] assign _T_868 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@29851.4] assign _T_869 = _T_868[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@29852.4] assign _T_870 = ~ _T_869; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@29853.4] assign _T_871 = _T_870[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@29854.4] assign _T_872 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@29855.4] assign _T_876 = _T_874 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29859.4] assign _T_877 = _T_874 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29860.4] assign _T_891 = _T_877 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@29877.4] assign _T_892 = io_in_d_valid & _T_891; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@29878.4] assign _T_893 = io_in_d_bits_opcode == _T_885; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@29880.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29882.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29883.6] assign _T_897 = io_in_d_bits_param == _T_886; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@29888.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29890.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29891.6] assign _T_901 = io_in_d_bits_size == _T_887; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@29896.6] assign _T_903 = _T_901 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29898.6] assign _T_904 = _T_903 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29899.6] assign _T_905 = io_in_d_bits_source == _T_888; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@29904.6] assign _T_907 = _T_905 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29906.6] assign _T_908 = _T_907 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29907.6] assign _T_909 = io_in_d_bits_sink == _T_889; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@29912.6] assign _T_911 = _T_909 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29914.6] assign _T_912 = _T_911 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29915.6] assign _T_913 = io_in_d_bits_denied == _T_890; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@29920.6] assign _T_915 = _T_913 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29922.6] assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29923.6] assign _T_918 = _T_866 & _T_877; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@29930.4] assign _T_931 = _T_929 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29951.4] assign _T_932 = _T_929 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29952.4] assign _T_950 = _T_948 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@29973.4] assign _T_951 = _T_948 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@29974.4] assign _T_961 = _T_817 & _T_932; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@29989.4] assign _T_963 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@29992.6] assign _T_964 = _T_919 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@29994.6] assign _T_965 = _T_964[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@29995.6] assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@29996.6] assign _T_968 = _T_966 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@29998.6] assign _T_969 = _T_968 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@29999.6] assign _GEN_15 = _T_961 ? _T_963 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@29991.4] assign _T_973 = _T_866 & _T_951; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@30010.4] assign _T_975 = _T_676 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@30012.4] assign _T_976 = _T_973 & _T_975; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@30013.4] assign _T_977 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@30015.6] assign _T_959 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@29985.4 :freechips.rocketchip.system.TinyConfig.fir@29987.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@29993.6] assign _T_978 = _T_959 | _T_919; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@30017.6] assign _T_979 = _T_978 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@30018.6] assign _T_980 = _T_979[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@30019.6] assign _T_982 = _T_980 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30021.6] assign _T_983 = _T_982 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30022.6] assign _GEN_16 = _T_976 ? _T_977 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@30014.4] assign _T_984 = _T_919 | _T_959; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@30028.4] assign _T_970 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@30005.4 :freechips.rocketchip.system.TinyConfig.fir@30007.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@30016.6] assign _T_985 = ~ _T_970; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@30029.4] assign _T_986 = _T_984 & _T_985; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@30030.4] assign _T_988 = _T_919 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@30035.4] assign _T_989 = _T_988 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@30036.4] assign _T_990 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@30037.4] assign _T_991 = _T_989 | _T_990; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@30038.4] assign _T_992 = _T_987 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@30039.4] assign _T_993 = _T_991 | _T_992; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@30040.4] assign _T_995 = _T_993 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30042.4] assign _T_996 = _T_995 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30043.4] assign _T_998 = _T_987 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@30049.4] assign _T_1001 = _T_817 | _T_866; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@30053.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28745.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@28847.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28965.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29061.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@29149.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29237.10] assign _GEN_95 = io_in_a_valid & _T_524; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@29323.10] assign _GEN_105 = io_in_a_valid & _T_588; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29406.10] assign _GEN_115 = io_in_d_valid & _T_676; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29484.10] assign _GEN_125 = io_in_d_valid & _T_696; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@29526.10] assign _GEN_137 = io_in_d_valid & _T_724; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@29584.10] assign _GEN_149 = io_in_d_valid & _T_753; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@29643.10] assign _GEN_155 = io_in_d_valid & _T_770; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@29678.10] assign _GEN_161 = io_in_d_valid & _T_788; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@29714.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_826 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_837 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_838 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_839 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_840 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_841 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_874 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_885 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_886 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_887 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_888 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_889 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_890 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_919 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_929 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_948 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_987 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_826 <= 10'h0; end else begin if (_T_817) begin if (_T_829) begin if (_T_824) begin _T_826 <= _T_822; end else begin _T_826 <= 10'h0; end end else begin _T_826 <= _T_828; end end end if (_T_865) begin _T_837 <= io_in_a_bits_opcode; end if (_T_865) begin _T_838 <= io_in_a_bits_param; end if (_T_865) begin _T_839 <= io_in_a_bits_size; end if (_T_865) begin _T_840 <= io_in_a_bits_source; end if (_T_865) begin _T_841 <= io_in_a_bits_address; end if (reset) begin _T_874 <= 10'h0; end else begin if (_T_866) begin if (_T_877) begin if (_T_872) begin _T_874 <= _T_871; end else begin _T_874 <= 10'h0; end end else begin _T_874 <= _T_876; end end end if (_T_918) begin _T_885 <= io_in_d_bits_opcode; end if (_T_918) begin _T_886 <= io_in_d_bits_param; end if (_T_918) begin _T_887 <= io_in_d_bits_size; end if (_T_918) begin _T_888 <= io_in_d_bits_source; end if (_T_918) begin _T_889 <= io_in_d_bits_sink; end if (_T_918) begin _T_890 <= io_in_d_bits_denied; end if (reset) begin _T_919 <= 18'h0; end else begin _T_919 <= _T_986; end if (reset) begin _T_929 <= 10'h0; end else begin if (_T_817) begin if (_T_932) begin if (_T_824) begin _T_929 <= _T_822; end else begin _T_929 <= 10'h0; end end else begin _T_929 <= _T_931; end end end if (reset) begin _T_948 <= 10'h0; end else begin if (_T_866) begin if (_T_951) begin if (_T_872) begin _T_948 <= _T_871; end else begin _T_948 <= 10'h0; end end else begin _T_948 <= _T_950; end end end if (reset) begin _T_987 <= 32'h0; end else begin if (_T_1001) begin _T_987 <= 32'h0; end else begin _T_987 <= _T_998; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28745.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@28746.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@28752.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@28753.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28759.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@28760.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28767.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@28768.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28774.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@28775.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28782.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@28783.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28791.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@28792.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28799.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@28800.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@28847.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@28848.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@28854.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@28855.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@28861.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@28862.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@28869.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@28870.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@28876.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@28877.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@28884.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@28885.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28892.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@28893.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@28901.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@28902.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@28909.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@28910.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28965.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@28966.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@28972.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@28973.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@28979.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@28980.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28987.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@28988.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28995.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@28996.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@29003.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@29004.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29061.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@29062.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@29068.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@29069.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@29075.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@29076.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@29083.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@29084.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@29091.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@29092.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@29149.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@29150.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@29156.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@29157.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@29163.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@29164.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@29171.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@29172.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29181.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@29182.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29237.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_509) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@29238.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@29244.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@29245.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@29251.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@29252.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29259.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_519) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@29260.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@29267.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@29268.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@29323.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_509) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@29324.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@29330.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@29331.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@29337.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@29338.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29345.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_583) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@29346.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@29353.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@29354.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_634) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29406.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_634) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@29407.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@29413.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@29414.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@29420.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@29421.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@29428.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@29429.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@29436.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@29437.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_652) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29447.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_652) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@29448.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29484.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@29485.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29492.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_683) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@29493.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29500.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_687) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@29501.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29508.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_691) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@29509.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_695) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29516.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_695) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@29517.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@29526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_679) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@29527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@29533.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@29534.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@29541.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_683) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@29542.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29549.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_710) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@29550.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29557.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_714) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@29558.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@29565.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_691) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@29566.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@29584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_679) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@29585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@29591.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@29592.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@29599.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_683) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@29600.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@29607.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_710) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@29608.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@29615.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_714) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@29616.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29624.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_747) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@29625.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@29643.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_679) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@29644.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@29651.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_687) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@29652.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@29659.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_691) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@29660.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@29678.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_679) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@29679.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@29686.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_687) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@29687.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@29695.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_747) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@29696.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@29714.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_679) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@29715.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@29722.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_687) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@29723.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@29730.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_691) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@29731.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29804.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_847) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@29805.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_851) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29812.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_851) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@29813.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_855) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29820.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_855) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@29821.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_859) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29828.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_859) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@29829.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_863) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29836.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_863) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@29837.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29885.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_896) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@29886.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29893.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_900) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@29894.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_904) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29901.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_904) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@29902.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_908) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29909.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_908) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@29910.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_912) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29917.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_912) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@29918.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_916) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29925.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_916) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@29926.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_961 & _T_969) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@30001.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_961 & _T_969) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@30002.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_976 & _T_983) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30024.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_976 & _T_983) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@30025.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_996) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30045.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_996) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@30046.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLFIFOFixer_3( // @[:freechips.rocketchip.system.TinyConfig.fir@30058.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@30059.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@30060.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@30061.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] wire [32:0] _T_15; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30122.4] wire [31:0] _T_19; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30126.4] wire [32:0] _T_20; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30127.4] wire [32:0] _T_21; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30128.4] wire [32:0] _T_22; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30129.4] wire _T_23; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30130.4] wire [31:0] _T_24; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30131.4] wire [32:0] _T_25; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30132.4] wire [32:0] _T_26; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30133.4] wire [32:0] _T_27; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30134.4] wire _T_28; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30135.4] wire [31:0] _T_29; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30136.4] wire [32:0] _T_30; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30137.4] wire [32:0] _T_31; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30138.4] wire [32:0] _T_32; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30139.4] wire _T_33; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30140.4] wire [32:0] _T_36; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30143.4] wire [32:0] _T_37; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30144.4] wire _T_38; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30145.4] wire [31:0] _T_39; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30146.4] wire [32:0] _T_40; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30147.4] wire [32:0] _T_41; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30148.4] wire [32:0] _T_42; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30149.4] wire _T_43; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30150.4] wire [31:0] _T_44; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30151.4] wire [32:0] _T_45; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30152.4] wire [32:0] _T_46; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30153.4] wire [32:0] _T_47; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30154.4] wire _T_48; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30155.4] wire [1:0] _T_50; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30157.4] wire [2:0] _T_51; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30158.4] wire [2:0] _T_52; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30159.4] wire [2:0] _T_53; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30160.4] wire [1:0] _T_54; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30161.4] wire [1:0] _GEN_78; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30162.4] wire [1:0] _T_55; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30162.4] wire [2:0] _GEN_79; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30163.4] wire [2:0] _T_56; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30163.4] wire [2:0] _T_57; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30164.4] wire [2:0] _T_58; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30165.4] wire [2:0] _GEN_80; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30166.4] wire [2:0] _T_59; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30166.4] wire _T_61; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.TinyConfig.fir@30169.4] wire [1:0] _T_112; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@30251.4] wire _T_113; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30252.4] reg [9:0] _T_71; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@30179.4] reg [31:0] _RAND_0; wire _T_74; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@30182.4] wire _T_123; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@30265.4] reg _T_104_0; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_1; reg _T_104_1; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_2; wire _T_124; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30266.4] reg _T_104_2; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_3; wire _T_125; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30267.4] reg _T_104_3; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_4; wire _T_126; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30268.4] reg _T_104_4; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_5; wire _T_127; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30269.4] reg _T_104_5; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_6; wire _T_128; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30270.4] reg _T_104_6; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_7; wire _T_129; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30271.4] reg _T_104_7; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_8; wire _T_130; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30272.4] wire _T_131; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@30273.4] reg [2:0] _T_122; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@30261.4] reg [31:0] _RAND_9; wire _T_132; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@30274.4] wire _T_133; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@30275.4] wire _T_134; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@30276.4] wire _T_138; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30280.4] wire _T_148; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@30293.4] reg _T_104_8; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_10; reg _T_104_9; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_11; wire _T_149; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30294.4] reg _T_104_10; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_12; wire _T_150; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30295.4] reg _T_104_11; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_13; wire _T_151; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30296.4] reg _T_104_12; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_14; wire _T_152; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30297.4] reg _T_104_13; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_15; wire _T_153; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30298.4] reg _T_104_14; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_16; wire _T_154; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30299.4] reg _T_104_15; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.TinyConfig.fir@30237.4] reg [31:0] _RAND_17; wire _T_155; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30300.4] wire _T_156; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@30301.4] reg [2:0] _T_147; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@30289.4] reg [31:0] _RAND_18; wire _T_157; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@30302.4] wire _T_158; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@30303.4] wire _T_159; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@30304.4] wire _T_161; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.TinyConfig.fir@30306.4] wire _T_165; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.TinyConfig.fir@30313.4] wire _T_167; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.TinyConfig.fir@30315.4] wire _T_62; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@30170.4] wire [26:0] _T_64; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30172.4] wire [11:0] _T_65; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30173.4] wire [11:0] _T_66; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30174.4] wire [9:0] _T_67; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@30175.4] wire _T_68; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@30176.4] wire _T_69; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@30177.4] wire [9:0] _T_73; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@30181.4] wire _T_82; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@30193.4] wire [26:0] _T_84; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30195.4] wire [11:0] _T_85; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30196.4] wire [11:0] _T_86; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30197.4] wire [9:0] _T_87; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@30198.4] wire _T_88; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@30199.4] reg [9:0] _T_90; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@30201.4] reg [31:0] _RAND_19; wire [9:0] _T_92; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@30203.4] wire _T_93; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@30204.4] wire _T_101; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.TinyConfig.fir@30215.4] wire _T_102; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.TinyConfig.fir@30216.4] wire _T_106; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.TinyConfig.fir@30239.4] wire _T_109; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.TinyConfig.fir@30245.4] wire _T_119; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@30258.4] wire _T_144; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@30286.4] TLMonitor_14 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@30068.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign _T_15 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30122.4] assign _T_19 = auto_in_a_bits_address ^ 32'h2000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30126.4] assign _T_20 = {1'b0,$signed(_T_19)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30127.4] assign _T_21 = $signed(_T_20) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30128.4] assign _T_22 = $signed(_T_21); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30129.4] assign _T_23 = $signed(_T_22) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30130.4] assign _T_24 = auto_in_a_bits_address ^ 32'h8000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30131.4] assign _T_25 = {1'b0,$signed(_T_24)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30132.4] assign _T_26 = $signed(_T_25) & $signed(33'sh88000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30133.4] assign _T_27 = $signed(_T_26); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30134.4] assign _T_28 = $signed(_T_27) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30135.4] assign _T_29 = auto_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30136.4] assign _T_30 = {1'b0,$signed(_T_29)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30137.4] assign _T_31 = $signed(_T_30) & $signed(33'sh8a010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30138.4] assign _T_32 = $signed(_T_31); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30139.4] assign _T_33 = $signed(_T_32) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30140.4] assign _T_36 = $signed(_T_15) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30143.4] assign _T_37 = $signed(_T_36); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30144.4] assign _T_38 = $signed(_T_37) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30145.4] assign _T_39 = auto_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30146.4] assign _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30147.4] assign _T_41 = $signed(_T_40) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30148.4] assign _T_42 = $signed(_T_41); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30149.4] assign _T_43 = $signed(_T_42) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30150.4] assign _T_44 = auto_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30151.4] assign _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30152.4] assign _T_46 = $signed(_T_45) & $signed(33'sh8a010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30153.4] assign _T_47 = $signed(_T_46); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30154.4] assign _T_48 = $signed(_T_47) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30155.4] assign _T_50 = _T_28 ? 2'h3 : 2'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30157.4] assign _T_51 = _T_33 ? 3'h4 : 3'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30158.4] assign _T_52 = _T_38 ? 3'h5 : 3'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30159.4] assign _T_53 = _T_43 ? 3'h6 : 3'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30160.4] assign _T_54 = _T_48 ? 2'h2 : 2'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30161.4] assign _GEN_78 = {{1'd0}, _T_23}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30162.4] assign _T_55 = _GEN_78 | _T_50; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30162.4] assign _GEN_79 = {{1'd0}, _T_55}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30163.4] assign _T_56 = _GEN_79 | _T_51; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30163.4] assign _T_57 = _T_56 | _T_52; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30164.4] assign _T_58 = _T_57 | _T_53; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30165.4] assign _GEN_80 = {{1'd0}, _T_54}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30166.4] assign _T_59 = _T_58 | _GEN_80; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@30166.4] assign _T_61 = _T_59 == 3'h0; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.TinyConfig.fir@30169.4] assign _T_112 = auto_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@30251.4] assign _T_113 = _T_112 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30252.4] assign _T_74 = _T_71 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@30182.4] assign _T_123 = _T_113 & _T_74; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@30265.4] assign _T_124 = _T_104_0 | _T_104_1; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30266.4] assign _T_125 = _T_124 | _T_104_2; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30267.4] assign _T_126 = _T_125 | _T_104_3; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30268.4] assign _T_127 = _T_126 | _T_104_4; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30269.4] assign _T_128 = _T_127 | _T_104_5; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30270.4] assign _T_129 = _T_128 | _T_104_6; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30271.4] assign _T_130 = _T_129 | _T_104_7; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30272.4] assign _T_131 = _T_123 & _T_130; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@30273.4] assign _T_132 = _T_122 != _T_59; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@30274.4] assign _T_133 = _T_61 | _T_132; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@30275.4] assign _T_134 = _T_131 & _T_133; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@30276.4] assign _T_138 = _T_112 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30280.4] assign _T_148 = _T_138 & _T_74; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.TinyConfig.fir@30293.4] assign _T_149 = _T_104_8 | _T_104_9; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30294.4] assign _T_150 = _T_149 | _T_104_10; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30295.4] assign _T_151 = _T_150 | _T_104_11; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30296.4] assign _T_152 = _T_151 | _T_104_12; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30297.4] assign _T_153 = _T_152 | _T_104_13; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30298.4] assign _T_154 = _T_153 | _T_104_14; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30299.4] assign _T_155 = _T_154 | _T_104_15; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@30300.4] assign _T_156 = _T_148 & _T_155; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@30301.4] assign _T_157 = _T_147 != _T_59; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.TinyConfig.fir@30302.4] assign _T_158 = _T_61 | _T_157; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.TinyConfig.fir@30303.4] assign _T_159 = _T_156 & _T_158; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.TinyConfig.fir@30304.4] assign _T_161 = _T_134 | _T_159; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.TinyConfig.fir@30306.4] assign _T_165 = _T_161 == 1'h0; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.TinyConfig.fir@30313.4] assign _T_167 = auto_out_a_ready & _T_165; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.TinyConfig.fir@30315.4] assign _T_62 = _T_167 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@30170.4] assign _T_64 = 27'hfff << auto_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30172.4] assign _T_65 = _T_64[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30173.4] assign _T_66 = ~ _T_65; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30174.4] assign _T_67 = _T_66[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@30175.4] assign _T_68 = auto_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@30176.4] assign _T_69 = _T_68 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@30177.4] assign _T_73 = _T_71 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@30181.4] assign _T_82 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@30193.4] assign _T_84 = 27'hfff << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30195.4] assign _T_85 = _T_84[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30196.4] assign _T_86 = ~ _T_85; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30197.4] assign _T_87 = _T_86[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@30198.4] assign _T_88 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@30199.4] assign _T_92 = _T_90 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@30203.4] assign _T_93 = _T_90 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@30204.4] assign _T_101 = auto_out_d_bits_opcode != 3'h6; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.TinyConfig.fir@30215.4] assign _T_102 = _T_93 & _T_101; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.TinyConfig.fir@30216.4] assign _T_106 = _T_74 & _T_62; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.TinyConfig.fir@30239.4] assign _T_109 = _T_102 & _T_82; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.TinyConfig.fir@30245.4] assign _T_119 = _T_62 & _T_113; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@30258.4] assign _T_144 = _T_62 & _T_138; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.TinyConfig.fir@30286.4] assign auto_in_a_ready = auto_out_a_ready & _T_165; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@30120.4] assign auto_out_a_valid = auto_in_a_valid & _T_165; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@30119.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@30070.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@30071.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready & _T_165; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@30116.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_71 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_104_0 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_104_1 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_104_2 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_104_3 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_104_4 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_104_5 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_104_6 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_104_7 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_122 = _RAND_9[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_104_8 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_104_9 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_104_10 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_104_11 = _RAND_13[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_104_12 = _RAND_14[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_104_13 = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_104_14 = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; _T_104_15 = _RAND_17[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; _T_147 = _RAND_18[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; _T_90 = _RAND_19[9:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_71 <= 10'h0; end else begin if (_T_62) begin if (_T_74) begin if (_T_69) begin _T_71 <= _T_67; end else begin _T_71 <= 10'h0; end end else begin _T_71 <= _T_73; end end end if (reset) begin _T_104_0 <= 1'h0; end else begin if (_T_109) begin if (5'h0 == auto_out_d_bits_source) begin _T_104_0 <= 1'h0; end else begin if (_T_106) begin if (5'h0 == auto_in_a_bits_source) begin _T_104_0 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h0 == auto_in_a_bits_source) begin _T_104_0 <= 1'h1; end end end end if (reset) begin _T_104_1 <= 1'h0; end else begin if (_T_109) begin if (5'h1 == auto_out_d_bits_source) begin _T_104_1 <= 1'h0; end else begin if (_T_106) begin if (5'h1 == auto_in_a_bits_source) begin _T_104_1 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h1 == auto_in_a_bits_source) begin _T_104_1 <= 1'h1; end end end end if (reset) begin _T_104_2 <= 1'h0; end else begin if (_T_109) begin if (5'h2 == auto_out_d_bits_source) begin _T_104_2 <= 1'h0; end else begin if (_T_106) begin if (5'h2 == auto_in_a_bits_source) begin _T_104_2 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h2 == auto_in_a_bits_source) begin _T_104_2 <= 1'h1; end end end end if (reset) begin _T_104_3 <= 1'h0; end else begin if (_T_109) begin if (5'h3 == auto_out_d_bits_source) begin _T_104_3 <= 1'h0; end else begin if (_T_106) begin if (5'h3 == auto_in_a_bits_source) begin _T_104_3 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h3 == auto_in_a_bits_source) begin _T_104_3 <= 1'h1; end end end end if (reset) begin _T_104_4 <= 1'h0; end else begin if (_T_109) begin if (5'h4 == auto_out_d_bits_source) begin _T_104_4 <= 1'h0; end else begin if (_T_106) begin if (5'h4 == auto_in_a_bits_source) begin _T_104_4 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h4 == auto_in_a_bits_source) begin _T_104_4 <= 1'h1; end end end end if (reset) begin _T_104_5 <= 1'h0; end else begin if (_T_109) begin if (5'h5 == auto_out_d_bits_source) begin _T_104_5 <= 1'h0; end else begin if (_T_106) begin if (5'h5 == auto_in_a_bits_source) begin _T_104_5 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h5 == auto_in_a_bits_source) begin _T_104_5 <= 1'h1; end end end end if (reset) begin _T_104_6 <= 1'h0; end else begin if (_T_109) begin if (5'h6 == auto_out_d_bits_source) begin _T_104_6 <= 1'h0; end else begin if (_T_106) begin if (5'h6 == auto_in_a_bits_source) begin _T_104_6 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h6 == auto_in_a_bits_source) begin _T_104_6 <= 1'h1; end end end end if (reset) begin _T_104_7 <= 1'h0; end else begin if (_T_109) begin if (5'h7 == auto_out_d_bits_source) begin _T_104_7 <= 1'h0; end else begin if (_T_106) begin if (5'h7 == auto_in_a_bits_source) begin _T_104_7 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h7 == auto_in_a_bits_source) begin _T_104_7 <= 1'h1; end end end end if (_T_119) begin _T_122 <= _T_59; end if (reset) begin _T_104_8 <= 1'h0; end else begin if (_T_109) begin if (5'h8 == auto_out_d_bits_source) begin _T_104_8 <= 1'h0; end else begin if (_T_106) begin if (5'h8 == auto_in_a_bits_source) begin _T_104_8 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h8 == auto_in_a_bits_source) begin _T_104_8 <= 1'h1; end end end end if (reset) begin _T_104_9 <= 1'h0; end else begin if (_T_109) begin if (5'h9 == auto_out_d_bits_source) begin _T_104_9 <= 1'h0; end else begin if (_T_106) begin if (5'h9 == auto_in_a_bits_source) begin _T_104_9 <= 1'h1; end end end end else begin if (_T_106) begin if (5'h9 == auto_in_a_bits_source) begin _T_104_9 <= 1'h1; end end end end if (reset) begin _T_104_10 <= 1'h0; end else begin if (_T_109) begin if (5'ha == auto_out_d_bits_source) begin _T_104_10 <= 1'h0; end else begin if (_T_106) begin if (5'ha == auto_in_a_bits_source) begin _T_104_10 <= 1'h1; end end end end else begin if (_T_106) begin if (5'ha == auto_in_a_bits_source) begin _T_104_10 <= 1'h1; end end end end if (reset) begin _T_104_11 <= 1'h0; end else begin if (_T_109) begin if (5'hb == auto_out_d_bits_source) begin _T_104_11 <= 1'h0; end else begin if (_T_106) begin if (5'hb == auto_in_a_bits_source) begin _T_104_11 <= 1'h1; end end end end else begin if (_T_106) begin if (5'hb == auto_in_a_bits_source) begin _T_104_11 <= 1'h1; end end end end if (reset) begin _T_104_12 <= 1'h0; end else begin if (_T_109) begin if (5'hc == auto_out_d_bits_source) begin _T_104_12 <= 1'h0; end else begin if (_T_106) begin if (5'hc == auto_in_a_bits_source) begin _T_104_12 <= 1'h1; end end end end else begin if (_T_106) begin if (5'hc == auto_in_a_bits_source) begin _T_104_12 <= 1'h1; end end end end if (reset) begin _T_104_13 <= 1'h0; end else begin if (_T_109) begin if (5'hd == auto_out_d_bits_source) begin _T_104_13 <= 1'h0; end else begin if (_T_106) begin if (5'hd == auto_in_a_bits_source) begin _T_104_13 <= 1'h1; end end end end else begin if (_T_106) begin if (5'hd == auto_in_a_bits_source) begin _T_104_13 <= 1'h1; end end end end if (reset) begin _T_104_14 <= 1'h0; end else begin if (_T_109) begin if (5'he == auto_out_d_bits_source) begin _T_104_14 <= 1'h0; end else begin if (_T_106) begin if (5'he == auto_in_a_bits_source) begin _T_104_14 <= 1'h1; end end end end else begin if (_T_106) begin if (5'he == auto_in_a_bits_source) begin _T_104_14 <= 1'h1; end end end end if (reset) begin _T_104_15 <= 1'h0; end else begin if (_T_109) begin if (5'hf == auto_out_d_bits_source) begin _T_104_15 <= 1'h0; end else begin if (_T_106) begin if (5'hf == auto_in_a_bits_source) begin _T_104_15 <= 1'h1; end end end end else begin if (_T_106) begin if (5'hf == auto_in_a_bits_source) begin _T_104_15 <= 1'h1; end end end end if (_T_144) begin _T_147 <= _T_59; end if (reset) begin _T_90 <= 10'h0; end else begin if (_T_82) begin if (_T_93) begin if (_T_88) begin _T_90 <= _T_87; end else begin _T_90 <= 10'h0; end end else begin _T_90 <= _T_92; end end end end endmodule module TLMonitor_15( // @[:freechips.rocketchip.system.TinyConfig.fir@30390.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@30391.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@30392.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@30393.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@31867.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@30408.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@30409.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@30412.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30413.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30421.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30432.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30433.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30434.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30436.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30437.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30438.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@30439.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@30439.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@30440.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@30442.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@30443.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@30445.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@30446.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@30447.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@30448.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@30449.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30451.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30452.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30454.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30455.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@30456.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@30457.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@30458.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30459.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30460.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30461.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30462.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30463.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30464.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30465.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30466.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30467.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30468.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30469.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30470.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@30473.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30477.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@30530.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30533.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30534.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30535.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30536.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30537.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30538.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30539.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30540.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30541.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30542.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30543.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30544.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30545.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30546.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30547.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30550.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30551.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30552.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30553.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30554.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30555.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30556.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30557.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30558.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30559.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30560.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30561.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30562.8] wire _T_150; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30563.8] wire _T_151; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30564.8] wire _T_152; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30565.8] wire _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30566.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30572.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30585.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30586.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30593.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30594.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30600.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30601.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@30606.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30608.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30609.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@30614.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@30615.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30617.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30618.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@30623.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30625.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30626.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@30632.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@30716.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30718.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30719.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@30742.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@30745.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30753.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@30755.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30783.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30784.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30785.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30786.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30787.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@30789.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30791.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30792.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@30811.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30813.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30814.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@30819.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30821.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30822.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@30836.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30875.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@30884.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30887.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30888.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@30924.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@31003.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@31004.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@31005.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31007.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31008.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@31014.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@31017.8] wire _T_494; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@31049.8] wire _T_505; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31060.8] wire _T_506; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31061.8] wire _T_513; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@31080.8] wire _T_515; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31082.8] wire _T_516; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31083.8] wire _T_521; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@31097.6] wire _T_574; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@31163.8] wire _T_576; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31165.8] wire _T_577; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31166.8] wire _T_582; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@31180.6] wire _T_627; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31226.8] wire _T_628; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31227.8] wire _T_643; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@31265.6] wire _T_645; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31267.6] wire _T_646; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31268.6] wire _T_647; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@31273.6] wire _T_648; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@31274.6] wire [1:0] _T_651; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@31277.6] wire _T_652; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@31278.6] wire _T_660; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@31286.6] wire _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31297.6] wire _T_667; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31298.6] wire _T_668; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31299.6] wire _T_670; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@31301.6] wire _T_672; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31304.8] wire _T_673; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31305.8] wire _T_674; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@31310.8] wire _T_676; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31312.8] wire _T_677; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31313.8] wire _T_678; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@31318.8] wire _T_680; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31320.8] wire _T_681; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31321.8] wire _T_682; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@31326.8] wire _T_684; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31328.8] wire _T_685; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31329.8] wire _T_686; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@31334.8] wire _T_688; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31336.8] wire _T_689; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31337.8] wire _T_690; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@31343.6] wire _T_701; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@31367.8] wire _T_703; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31369.8] wire _T_704; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31370.8] wire _T_705; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@31375.8] wire _T_707; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31377.8] wire _T_708; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31378.8] wire _T_718; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@31401.6] wire _T_738; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@31442.8] wire _T_740; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31444.8] wire _T_741; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31445.8] wire _T_747; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@31460.6] wire _T_764; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@31495.6] wire _T_782; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@31531.6] wire _T_811; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@31591.4] wire [9:0] _T_816; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@31596.4] wire _T_817; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@31597.4] wire _T_818; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@31598.4] reg [9:0] _T_820; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@31600.4] reg [31:0] _RAND_0; wire [9:0] _T_822; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31602.4] wire _T_823; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31603.4] reg [2:0] _T_831; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@31614.4] reg [31:0] _RAND_1; reg [2:0] _T_832; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@31615.4] reg [31:0] _RAND_2; reg [3:0] _T_833; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@31616.4] reg [31:0] _RAND_3; reg [4:0] _T_834; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@31617.4] reg [31:0] _RAND_4; reg [31:0] _T_835; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@31618.4] reg [31:0] _RAND_5; wire _T_836; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@31619.4] wire _T_837; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@31620.4] wire _T_838; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@31622.6] wire _T_840; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31624.6] wire _T_841; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31625.6] wire _T_842; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@31630.6] wire _T_844; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31632.6] wire _T_845; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31633.6] wire _T_846; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@31638.6] wire _T_848; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31640.6] wire _T_849; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31641.6] wire _T_850; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@31646.6] wire _T_852; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31648.6] wire _T_853; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31649.6] wire _T_854; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@31654.6] wire _T_856; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31656.6] wire _T_857; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31657.6] wire _T_859; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@31664.4] wire _T_860; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@31672.4] wire [26:0] _T_862; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@31674.4] wire [11:0] _T_863; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@31675.4] wire [11:0] _T_864; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@31676.4] wire [9:0] _T_865; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@31677.4] wire _T_866; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@31678.4] reg [9:0] _T_868; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@31680.4] reg [31:0] _RAND_6; wire [9:0] _T_870; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31682.4] wire _T_871; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31683.4] reg [2:0] _T_879; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@31694.4] reg [31:0] _RAND_7; reg [1:0] _T_880; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@31695.4] reg [31:0] _RAND_8; reg [3:0] _T_881; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@31696.4] reg [31:0] _RAND_9; reg [4:0] _T_882; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@31697.4] reg [31:0] _RAND_10; reg _T_883; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@31698.4] reg [31:0] _RAND_11; reg _T_884; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@31699.4] reg [31:0] _RAND_12; wire _T_885; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@31700.4] wire _T_886; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@31701.4] wire _T_887; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@31703.6] wire _T_889; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31705.6] wire _T_890; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31706.6] wire _T_891; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@31711.6] wire _T_893; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31713.6] wire _T_894; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31714.6] wire _T_895; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@31719.6] wire _T_897; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31721.6] wire _T_898; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31722.6] wire _T_899; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@31727.6] wire _T_901; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31729.6] wire _T_902; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31730.6] wire _T_903; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@31735.6] wire _T_905; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31737.6] wire _T_906; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31738.6] wire _T_907; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@31743.6] wire _T_909; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31745.6] wire _T_910; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31746.6] wire _T_912; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@31753.4] reg [17:0] _T_913; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@31762.4] reg [31:0] _RAND_13; reg [9:0] _T_923; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@31772.4] reg [31:0] _RAND_14; wire [9:0] _T_925; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31774.4] wire _T_926; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31775.4] reg [9:0] _T_942; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@31794.4] reg [31:0] _RAND_15; wire [9:0] _T_944; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31796.4] wire _T_945; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31797.4] wire _T_955; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@31812.4] wire [31:0] _T_957; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@31815.6] wire [17:0] _T_958; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@31817.6] wire _T_959; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@31818.6] wire _T_960; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@31819.6] wire _T_962; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31821.6] wire _T_963; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31822.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@31814.4] wire _T_967; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@31833.4] wire _T_969; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@31835.4] wire _T_970; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@31836.4] wire [31:0] _T_971; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@31838.6] wire [17:0] _T_953; // @[:freechips.rocketchip.system.TinyConfig.fir@31808.4 :freechips.rocketchip.system.TinyConfig.fir@31810.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@31816.6] wire [17:0] _T_972; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@31840.6] wire [17:0] _T_973; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@31841.6] wire _T_974; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@31842.6] wire _T_976; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31844.6] wire _T_977; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31845.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@31837.4] wire [17:0] _T_964; // @[:freechips.rocketchip.system.TinyConfig.fir@31828.4 :freechips.rocketchip.system.TinyConfig.fir@31830.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@31839.6] wire _T_978; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@31851.4] wire _T_979; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@31852.4] wire _T_980; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@31853.4] wire _T_981; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@31854.4] wire _T_983; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31856.4] wire _T_984; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31857.4] wire [17:0] _T_985; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@31862.4] wire [17:0] _T_986; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@31863.4] wire [17:0] _T_987; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@31864.4] reg [31:0] _T_988; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@31866.4] reg [31:0] _RAND_16; wire _T_989; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@31869.4] wire _T_990; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@31870.4] wire _T_991; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@31871.4] wire _T_992; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@31872.4] wire _T_993; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@31873.4] wire _T_994; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@31874.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31876.4] wire _T_997; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31877.4] wire [31:0] _T_999; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@31883.4] wire _T_1002; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@31887.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30574.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@30676.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30794.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30890.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@30978.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31063.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@31146.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31229.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31307.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@31349.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@31407.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@31466.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@31501.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@31537.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@31867.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@30408.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@30409.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@30412.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30413.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@30421.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30432.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30433.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@30434.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@30436.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@30437.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@30438.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@30439.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@30439.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@30440.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@30442.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@30443.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@30445.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@30446.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@30447.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@30448.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@30449.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30451.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30452.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30454.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30455.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@30456.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@30457.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@30458.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30459.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30460.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30461.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30462.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30463.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30464.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30465.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30466.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30467.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@30468.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@30469.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@30470.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@30473.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30477.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@30530.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30533.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30534.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30535.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30536.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30537.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30538.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30539.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30540.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30541.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30542.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30543.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30544.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30545.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30546.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30547.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30550.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30551.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30552.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30553.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30554.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30555.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30556.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30557.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@30558.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@30559.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30560.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@30561.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@30562.8] assign _T_150 = _T_124 | _T_129; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30563.8] assign _T_151 = _T_150 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30564.8] assign _T_152 = _T_151 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30565.8] assign _T_153 = _T_152 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30566.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30572.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30585.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30586.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30593.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30594.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30600.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30601.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@30606.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30608.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30609.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@30614.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@30615.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30617.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30618.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@30623.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30625.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30626.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@30632.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@30716.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30718.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30719.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@30742.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@30745.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30753.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@30755.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30783.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30784.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30785.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@30786.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30787.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@30789.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30791.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30792.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@30811.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30813.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30814.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@30819.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30821.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30822.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@30836.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@30875.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@30884.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30887.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30888.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@30924.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@31003.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@31004.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@31005.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31007.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31008.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@31014.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@31017.8] assign _T_494 = _T_462 & _T_153; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@31049.8] assign _T_505 = _T_494 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31060.8] assign _T_506 = _T_505 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31061.8] assign _T_513 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@31080.8] assign _T_515 = _T_513 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31082.8] assign _T_516 = _T_515 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31083.8] assign _T_521 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@31097.6] assign _T_574 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@31163.8] assign _T_576 = _T_574 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31165.8] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31166.8] assign _T_582 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@31180.6] assign _T_627 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31226.8] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31227.8] assign _T_643 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@31265.6] assign _T_645 = _T_643 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31267.6] assign _T_646 = _T_645 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31268.6] assign _T_647 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@31273.6] assign _T_648 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@31274.6] assign _T_651 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@31277.6] assign _T_652 = _T_651 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@31278.6] assign _T_660 = _T_651 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@31286.6] assign _T_666 = _T_647 | _T_648; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31297.6] assign _T_667 = _T_666 | _T_652; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31298.6] assign _T_668 = _T_667 | _T_660; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@31299.6] assign _T_670 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@31301.6] assign _T_672 = _T_668 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31304.8] assign _T_673 = _T_672 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31305.8] assign _T_674 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@31310.8] assign _T_676 = _T_674 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31312.8] assign _T_677 = _T_676 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31313.8] assign _T_678 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@31318.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31320.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31321.8] assign _T_682 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@31326.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31328.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31329.8] assign _T_686 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@31334.8] assign _T_688 = _T_686 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31336.8] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31337.8] assign _T_690 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@31343.6] assign _T_701 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@31367.8] assign _T_703 = _T_701 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31369.8] assign _T_704 = _T_703 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31370.8] assign _T_705 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@31375.8] assign _T_707 = _T_705 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31377.8] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31378.8] assign _T_718 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@31401.6] assign _T_738 = _T_686 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@31442.8] assign _T_740 = _T_738 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31444.8] assign _T_741 = _T_740 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31445.8] assign _T_747 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@31460.6] assign _T_764 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@31495.6] assign _T_782 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@31531.6] assign _T_811 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@31591.4] assign _T_816 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@31596.4] assign _T_817 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@31597.4] assign _T_818 = _T_817 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@31598.4] assign _T_822 = _T_820 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31602.4] assign _T_823 = _T_820 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31603.4] assign _T_836 = _T_823 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@31619.4] assign _T_837 = io_in_a_valid & _T_836; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@31620.4] assign _T_838 = io_in_a_bits_opcode == _T_831; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@31622.6] assign _T_840 = _T_838 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31624.6] assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31625.6] assign _T_842 = io_in_a_bits_param == _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@31630.6] assign _T_844 = _T_842 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31632.6] assign _T_845 = _T_844 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31633.6] assign _T_846 = io_in_a_bits_size == _T_833; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@31638.6] assign _T_848 = _T_846 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31640.6] assign _T_849 = _T_848 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31641.6] assign _T_850 = io_in_a_bits_source == _T_834; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@31646.6] assign _T_852 = _T_850 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31648.6] assign _T_853 = _T_852 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31649.6] assign _T_854 = io_in_a_bits_address == _T_835; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@31654.6] assign _T_856 = _T_854 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31656.6] assign _T_857 = _T_856 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31657.6] assign _T_859 = _T_811 & _T_823; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@31664.4] assign _T_860 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@31672.4] assign _T_862 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@31674.4] assign _T_863 = _T_862[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@31675.4] assign _T_864 = ~ _T_863; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@31676.4] assign _T_865 = _T_864[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@31677.4] assign _T_866 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@31678.4] assign _T_870 = _T_868 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31682.4] assign _T_871 = _T_868 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31683.4] assign _T_885 = _T_871 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@31700.4] assign _T_886 = io_in_d_valid & _T_885; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@31701.4] assign _T_887 = io_in_d_bits_opcode == _T_879; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@31703.6] assign _T_889 = _T_887 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31705.6] assign _T_890 = _T_889 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31706.6] assign _T_891 = io_in_d_bits_param == _T_880; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@31711.6] assign _T_893 = _T_891 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31713.6] assign _T_894 = _T_893 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31714.6] assign _T_895 = io_in_d_bits_size == _T_881; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@31719.6] assign _T_897 = _T_895 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31721.6] assign _T_898 = _T_897 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31722.6] assign _T_899 = io_in_d_bits_source == _T_882; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@31727.6] assign _T_901 = _T_899 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31729.6] assign _T_902 = _T_901 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31730.6] assign _T_903 = io_in_d_bits_sink == _T_883; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@31735.6] assign _T_905 = _T_903 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31737.6] assign _T_906 = _T_905 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31738.6] assign _T_907 = io_in_d_bits_denied == _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@31743.6] assign _T_909 = _T_907 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31745.6] assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31746.6] assign _T_912 = _T_860 & _T_871; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@31753.4] assign _T_925 = _T_923 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31774.4] assign _T_926 = _T_923 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31775.4] assign _T_944 = _T_942 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@31796.4] assign _T_945 = _T_942 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@31797.4] assign _T_955 = _T_811 & _T_926; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@31812.4] assign _T_957 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@31815.6] assign _T_958 = _T_913 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@31817.6] assign _T_959 = _T_958[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@31818.6] assign _T_960 = _T_959 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@31819.6] assign _T_962 = _T_960 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31821.6] assign _T_963 = _T_962 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31822.6] assign _GEN_15 = _T_955 ? _T_957 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@31814.4] assign _T_967 = _T_860 & _T_945; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@31833.4] assign _T_969 = _T_670 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@31835.4] assign _T_970 = _T_967 & _T_969; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@31836.4] assign _T_971 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@31838.6] assign _T_953 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@31808.4 :freechips.rocketchip.system.TinyConfig.fir@31810.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@31816.6] assign _T_972 = _T_953 | _T_913; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@31840.6] assign _T_973 = _T_972 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@31841.6] assign _T_974 = _T_973[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@31842.6] assign _T_976 = _T_974 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31844.6] assign _T_977 = _T_976 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31845.6] assign _GEN_16 = _T_970 ? _T_971 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@31837.4] assign _T_964 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@31828.4 :freechips.rocketchip.system.TinyConfig.fir@31830.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@31839.6] assign _T_978 = _T_953 != _T_964; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@31851.4] assign _T_979 = _T_953 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@31852.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@31853.4] assign _T_981 = _T_978 | _T_980; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@31854.4] assign _T_983 = _T_981 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31856.4] assign _T_984 = _T_983 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31857.4] assign _T_985 = _T_913 | _T_953; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@31862.4] assign _T_986 = ~ _T_964; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@31863.4] assign _T_987 = _T_985 & _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@31864.4] assign _T_989 = _T_913 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@31869.4] assign _T_990 = _T_989 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@31870.4] assign _T_991 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@31871.4] assign _T_992 = _T_990 | _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@31872.4] assign _T_993 = _T_988 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@31873.4] assign _T_994 = _T_992 | _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@31874.4] assign _T_996 = _T_994 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31876.4] assign _T_997 = _T_996 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31877.4] assign _T_999 = _T_988 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@31883.4] assign _T_1002 = _T_811 | _T_860; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@31887.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30574.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@30676.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30794.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30890.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@30978.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31063.10] assign _GEN_95 = io_in_a_valid & _T_521; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@31146.10] assign _GEN_105 = io_in_a_valid & _T_582; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31229.10] assign _GEN_115 = io_in_d_valid & _T_670; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31307.10] assign _GEN_125 = io_in_d_valid & _T_690; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@31349.10] assign _GEN_137 = io_in_d_valid & _T_718; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@31407.10] assign _GEN_149 = io_in_d_valid & _T_747; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@31466.10] assign _GEN_155 = io_in_d_valid & _T_764; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@31501.10] assign _GEN_161 = io_in_d_valid & _T_782; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@31537.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_820 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_831 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_832 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_833 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_834 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_835 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_868 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_879 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_880 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_881 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_882 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_883 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_884 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_913 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_923 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_942 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_988 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_820 <= 10'h0; end else begin if (_T_811) begin if (_T_823) begin if (_T_818) begin _T_820 <= _T_816; end else begin _T_820 <= 10'h0; end end else begin _T_820 <= _T_822; end end end if (_T_859) begin _T_831 <= io_in_a_bits_opcode; end if (_T_859) begin _T_832 <= io_in_a_bits_param; end if (_T_859) begin _T_833 <= io_in_a_bits_size; end if (_T_859) begin _T_834 <= io_in_a_bits_source; end if (_T_859) begin _T_835 <= io_in_a_bits_address; end if (reset) begin _T_868 <= 10'h0; end else begin if (_T_860) begin if (_T_871) begin if (_T_866) begin _T_868 <= _T_865; end else begin _T_868 <= 10'h0; end end else begin _T_868 <= _T_870; end end end if (_T_912) begin _T_879 <= io_in_d_bits_opcode; end if (_T_912) begin _T_880 <= io_in_d_bits_param; end if (_T_912) begin _T_881 <= io_in_d_bits_size; end if (_T_912) begin _T_882 <= io_in_d_bits_source; end if (_T_912) begin _T_883 <= io_in_d_bits_sink; end if (_T_912) begin _T_884 <= io_in_d_bits_denied; end if (reset) begin _T_913 <= 18'h0; end else begin _T_913 <= _T_987; end if (reset) begin _T_923 <= 10'h0; end else begin if (_T_811) begin if (_T_926) begin if (_T_818) begin _T_923 <= _T_816; end else begin _T_923 <= 10'h0; end end else begin _T_923 <= _T_925; end end end if (reset) begin _T_942 <= 10'h0; end else begin if (_T_860) begin if (_T_945) begin if (_T_866) begin _T_942 <= _T_865; end else begin _T_942 <= 10'h0; end end else begin _T_942 <= _T_944; end end end if (reset) begin _T_988 <= 32'h0; end else begin if (_T_1002) begin _T_988 <= 32'h0; end else begin _T_988 <= _T_999; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30574.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@30575.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@30581.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@30582.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30588.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@30589.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30596.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@30597.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30603.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@30604.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30611.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@30612.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30620.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@30621.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30628.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@30629.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@30676.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@30677.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@30683.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@30684.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@30690.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@30691.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@30698.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@30699.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@30705.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@30706.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@30713.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@30714.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30721.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@30722.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@30730.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@30731.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@30738.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@30739.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30794.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@30795.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@30801.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@30802.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@30808.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@30809.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30816.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@30817.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30824.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@30825.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@30832.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@30833.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30890.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@30891.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@30897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@30898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@30904.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@30905.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@30912.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@30913.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@30920.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@30921.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@30978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@30979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@30985.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@30986.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@30992.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@30993.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@31000.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@31001.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31010.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@31011.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31063.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_506) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@31064.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@31070.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@31071.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@31077.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@31078.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_516) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31085.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_516) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@31086.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@31093.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@31094.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@31146.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_506) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@31147.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@31153.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@31154.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@31160.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@31161.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31168.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_577) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@31169.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@31176.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@31177.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31229.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_628) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@31230.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@31236.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@31237.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@31243.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@31244.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@31251.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@31252.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@31259.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@31260.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_646) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31270.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_646) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@31271.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31307.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_673) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@31308.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_677) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@31316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31323.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_681) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@31324.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31331.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_685) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@31332.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31339.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_689) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@31340.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@31349.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_673) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@31350.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@31356.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@31357.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@31364.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_677) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@31365.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31372.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_704) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@31373.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31380.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_708) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@31381.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@31388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_685) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@31389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@31407.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_673) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@31408.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@31414.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@31415.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@31422.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_677) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@31423.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@31430.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_704) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@31431.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@31438.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_708) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@31439.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31447.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_741) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@31448.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@31466.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_673) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@31467.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@31474.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_681) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@31475.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@31482.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_685) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@31483.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@31501.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_673) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@31502.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@31509.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_681) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@31510.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@31518.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_741) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@31519.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@31537.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_673) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@31538.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@31545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_681) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@31546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@31553.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_685) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@31554.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_841) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31627.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_841) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@31628.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_845) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31635.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_845) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@31636.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_849) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31643.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_849) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@31644.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_853) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31651.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_853) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@31652.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_857) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31659.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_857) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@31660.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_890) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31708.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_890) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@31709.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_894) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31716.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_894) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@31717.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_898) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31724.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_898) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@31725.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_902) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31732.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_902) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@31733.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_906) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31740.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_906) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@31741.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_910) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31748.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_910) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@31749.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_955 & _T_963) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31824.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_955 & _T_963) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@31825.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_970 & _T_977) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31847.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_970 & _T_977) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@31848.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_984) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31859.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_984) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@31860.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_997) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31879.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_997) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@31880.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_5( // @[:freechips.rocketchip.system.TinyConfig.fir@31892.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@31893.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@31894.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@31895.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] TLMonitor_15 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@31902.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@31954.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@31953.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@31904.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@31905.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@31950.4] endmodule module TLMonitor_16( // @[:freechips.rocketchip.system.TinyConfig.fir@32136.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@32137.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@32138.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@32139.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@33608.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@32154.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@32155.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@32158.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@32159.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@32167.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32178.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32179.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32180.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@32182.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@32183.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@32184.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@32185.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@32185.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@32186.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@32188.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@32189.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@32191.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@32192.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@32193.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@32194.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@32195.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32197.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32198.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32200.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32201.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@32202.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@32203.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@32204.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32205.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32206.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32207.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32208.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32209.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32210.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32211.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32212.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32213.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32214.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32215.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32216.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@32219.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32223.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@32276.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32279.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32280.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32281.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32282.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32283.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32284.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32285.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32286.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32287.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32288.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32289.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32290.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32291.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32292.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32293.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32296.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32297.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32298.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32299.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32300.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32301.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32302.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32303.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32304.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32305.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32306.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32307.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32308.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32318.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32331.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32332.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32339.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32340.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32346.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32347.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@32352.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32354.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32355.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@32360.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@32361.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32363.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32364.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@32369.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32371.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32372.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@32378.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@32462.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32464.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32465.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@32488.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32491.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32499.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32501.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32529.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32530.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32531.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32532.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32533.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32535.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32537.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32538.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@32557.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32559.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32560.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@32565.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32567.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32568.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@32582.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32621.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32630.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32633.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32634.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@32670.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@32749.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@32750.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@32751.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32753.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32754.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@32760.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32763.8] wire _T_470; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32771.8] wire _T_496; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@32797.8] wire _T_503; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32804.8] wire _T_506; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32807.8] wire _T_508; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32809.8] wire _T_509; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32810.8] wire _T_516; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@32829.8] wire _T_518; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32831.8] wire _T_519; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32832.8] wire _T_524; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@32846.6] wire _T_580; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@32915.8] wire _T_582; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32917.8] wire _T_583; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32918.8] wire _T_588; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@32932.6] wire _T_633; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32978.8] wire _T_634; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32979.8] wire _T_649; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@33017.6] wire _T_651; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33019.6] wire _T_652; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33020.6] wire _T_653; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@33025.6] wire _T_654; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@33026.6] wire [1:0] _T_657; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@33029.6] wire _T_658; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@33030.6] wire _T_666; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@33038.6] wire _T_672; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33049.6] wire _T_673; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33050.6] wire _T_674; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33051.6] wire _T_676; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@33053.6] wire _T_678; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33056.8] wire _T_679; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33057.8] wire _T_680; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@33062.8] wire _T_682; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33064.8] wire _T_683; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33065.8] wire _T_684; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@33070.8] wire _T_686; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33072.8] wire _T_687; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33073.8] wire _T_688; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@33078.8] wire _T_690; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33080.8] wire _T_691; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33081.8] wire _T_692; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@33086.8] wire _T_694; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33088.8] wire _T_695; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33089.8] wire _T_696; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@33095.6] wire _T_707; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@33119.8] wire _T_709; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33121.8] wire _T_710; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33122.8] wire _T_711; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@33127.8] wire _T_713; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33129.8] wire _T_714; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33130.8] wire _T_724; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@33153.6] wire _T_744; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@33194.8] wire _T_746; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33196.8] wire _T_747; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33197.8] wire _T_753; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@33212.6] wire _T_770; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@33247.6] wire _T_788; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@33283.6] wire _T_817; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@33343.4] wire [9:0] _T_822; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@33348.4] wire _T_823; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@33349.4] wire _T_824; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@33350.4] reg [9:0] _T_826; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@33352.4] reg [31:0] _RAND_0; wire [9:0] _T_828; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33354.4] wire _T_829; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33355.4] reg [2:0] _T_837; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@33366.4] reg [31:0] _RAND_1; reg [2:0] _T_838; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@33367.4] reg [31:0] _RAND_2; reg [3:0] _T_839; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@33368.4] reg [31:0] _RAND_3; reg [4:0] _T_840; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@33369.4] reg [31:0] _RAND_4; reg [31:0] _T_841; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@33370.4] reg [31:0] _RAND_5; wire _T_842; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@33371.4] wire _T_843; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@33372.4] wire _T_844; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@33374.6] wire _T_846; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33376.6] wire _T_847; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33377.6] wire _T_848; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@33382.6] wire _T_850; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33384.6] wire _T_851; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33385.6] wire _T_852; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@33390.6] wire _T_854; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33392.6] wire _T_855; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33393.6] wire _T_856; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@33398.6] wire _T_858; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33400.6] wire _T_859; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33401.6] wire _T_860; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@33406.6] wire _T_862; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33408.6] wire _T_863; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33409.6] wire _T_865; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@33416.4] wire _T_866; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@33424.4] wire [26:0] _T_868; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@33426.4] wire [11:0] _T_869; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@33427.4] wire [11:0] _T_870; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@33428.4] wire [9:0] _T_871; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@33429.4] wire _T_872; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@33430.4] reg [9:0] _T_874; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@33432.4] reg [31:0] _RAND_6; wire [9:0] _T_876; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33434.4] wire _T_877; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33435.4] reg [2:0] _T_885; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@33446.4] reg [31:0] _RAND_7; reg [1:0] _T_886; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@33447.4] reg [31:0] _RAND_8; reg [3:0] _T_887; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@33448.4] reg [31:0] _RAND_9; reg [4:0] _T_888; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@33449.4] reg [31:0] _RAND_10; reg _T_889; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@33450.4] reg [31:0] _RAND_11; reg _T_890; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@33451.4] reg [31:0] _RAND_12; wire _T_891; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@33452.4] wire _T_892; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@33453.4] wire _T_893; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@33455.6] wire _T_895; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33457.6] wire _T_896; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33458.6] wire _T_897; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@33463.6] wire _T_899; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33465.6] wire _T_900; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33466.6] wire _T_901; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@33471.6] wire _T_903; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33473.6] wire _T_904; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33474.6] wire _T_905; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@33479.6] wire _T_907; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33481.6] wire _T_908; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33482.6] wire _T_909; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@33487.6] wire _T_911; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33489.6] wire _T_912; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33490.6] wire _T_913; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@33495.6] wire _T_915; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33497.6] wire _T_916; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33498.6] wire _T_918; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@33505.4] reg [17:0] _T_919; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@33514.4] reg [31:0] _RAND_13; reg [9:0] _T_929; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@33524.4] reg [31:0] _RAND_14; wire [9:0] _T_931; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33526.4] wire _T_932; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33527.4] reg [9:0] _T_948; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@33546.4] reg [31:0] _RAND_15; wire [9:0] _T_950; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33548.4] wire _T_951; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33549.4] wire _T_961; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@33564.4] wire [31:0] _T_963; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@33567.6] wire [17:0] _T_964; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@33569.6] wire _T_965; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@33570.6] wire _T_966; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@33571.6] wire _T_968; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33573.6] wire _T_969; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33574.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@33566.4] wire _T_973; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@33585.4] wire _T_975; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@33587.4] wire _T_976; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@33588.4] wire [31:0] _T_977; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@33590.6] wire [17:0] _T_959; // @[:freechips.rocketchip.system.TinyConfig.fir@33560.4 :freechips.rocketchip.system.TinyConfig.fir@33562.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@33568.6] wire [17:0] _T_978; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@33592.6] wire [17:0] _T_979; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@33593.6] wire _T_980; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@33594.6] wire _T_982; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33596.6] wire _T_983; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33597.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@33589.4] wire [17:0] _T_984; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@33603.4] wire [17:0] _T_970; // @[:freechips.rocketchip.system.TinyConfig.fir@33580.4 :freechips.rocketchip.system.TinyConfig.fir@33582.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@33591.6] wire [17:0] _T_985; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@33604.4] wire [17:0] _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@33605.4] reg [31:0] _T_987; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@33607.4] reg [31:0] _RAND_16; wire _T_988; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@33610.4] wire _T_989; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@33611.4] wire _T_990; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@33612.4] wire _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@33613.4] wire _T_992; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@33614.4] wire _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@33615.4] wire _T_995; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33617.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33618.4] wire [31:0] _T_998; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@33624.4] wire _T_1001; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@33628.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32320.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@32422.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32540.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32636.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@32724.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32812.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@32898.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32981.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33059.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@33101.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@33159.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@33218.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@33253.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@33289.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@33608.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@32154.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@32155.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@32158.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@32159.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@32167.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32178.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32179.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@32180.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@32182.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@32183.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@32184.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@32185.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@32185.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@32186.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@32188.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@32189.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@32191.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@32192.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@32193.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@32194.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@32195.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32197.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32198.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32200.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32201.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@32202.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@32203.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@32204.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32205.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32206.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32207.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32208.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32209.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32210.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32211.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32212.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32213.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@32214.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@32215.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@32216.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@32219.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32223.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@32276.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32279.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32280.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32281.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32282.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32283.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32284.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32285.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32286.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32287.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32288.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32289.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32290.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32291.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32292.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32293.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32296.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32297.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32298.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32299.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32300.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32301.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32302.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32303.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@32304.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@32305.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32306.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@32307.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@32308.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32318.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32331.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32332.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32339.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32340.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32346.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32347.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@32352.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32354.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32355.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@32360.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@32361.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32363.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32364.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@32369.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32371.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32372.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@32378.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@32462.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32464.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32465.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@32488.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32491.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32499.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32501.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32529.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32530.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32531.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@32532.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32533.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32535.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32537.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32538.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@32557.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32559.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32560.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@32565.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32567.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32568.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@32582.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32621.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32630.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32633.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32634.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@32670.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@32749.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@32750.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@32751.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32753.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32754.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@32760.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@32763.8] assign _T_470 = _T_462 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32771.8] assign _T_496 = 4'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@32797.8] assign _T_503 = _T_496 & _T_144; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@32804.8] assign _T_506 = _T_470 | _T_503; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@32807.8] assign _T_508 = _T_506 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32809.8] assign _T_509 = _T_508 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32810.8] assign _T_516 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@32829.8] assign _T_518 = _T_516 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32831.8] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32832.8] assign _T_524 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@32846.6] assign _T_580 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@32915.8] assign _T_582 = _T_580 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32917.8] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32918.8] assign _T_588 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@32932.6] assign _T_633 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32978.8] assign _T_634 = _T_633 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32979.8] assign _T_649 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@33017.6] assign _T_651 = _T_649 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33019.6] assign _T_652 = _T_651 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33020.6] assign _T_653 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@33025.6] assign _T_654 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@33026.6] assign _T_657 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@33029.6] assign _T_658 = _T_657 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@33030.6] assign _T_666 = _T_657 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@33038.6] assign _T_672 = _T_653 | _T_654; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33049.6] assign _T_673 = _T_672 | _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33050.6] assign _T_674 = _T_673 | _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@33051.6] assign _T_676 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@33053.6] assign _T_678 = _T_674 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33056.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33057.8] assign _T_680 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@33062.8] assign _T_682 = _T_680 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33064.8] assign _T_683 = _T_682 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33065.8] assign _T_684 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@33070.8] assign _T_686 = _T_684 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33072.8] assign _T_687 = _T_686 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33073.8] assign _T_688 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@33078.8] assign _T_690 = _T_688 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33080.8] assign _T_691 = _T_690 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33081.8] assign _T_692 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@33086.8] assign _T_694 = _T_692 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33088.8] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33089.8] assign _T_696 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@33095.6] assign _T_707 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@33119.8] assign _T_709 = _T_707 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33121.8] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33122.8] assign _T_711 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@33127.8] assign _T_713 = _T_711 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33129.8] assign _T_714 = _T_713 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33130.8] assign _T_724 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@33153.6] assign _T_744 = _T_692 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@33194.8] assign _T_746 = _T_744 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33196.8] assign _T_747 = _T_746 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33197.8] assign _T_753 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@33212.6] assign _T_770 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@33247.6] assign _T_788 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@33283.6] assign _T_817 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@33343.4] assign _T_822 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@33348.4] assign _T_823 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@33349.4] assign _T_824 = _T_823 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@33350.4] assign _T_828 = _T_826 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33354.4] assign _T_829 = _T_826 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33355.4] assign _T_842 = _T_829 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@33371.4] assign _T_843 = io_in_a_valid & _T_842; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@33372.4] assign _T_844 = io_in_a_bits_opcode == _T_837; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@33374.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33376.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33377.6] assign _T_848 = io_in_a_bits_param == _T_838; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@33382.6] assign _T_850 = _T_848 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33384.6] assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33385.6] assign _T_852 = io_in_a_bits_size == _T_839; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@33390.6] assign _T_854 = _T_852 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33392.6] assign _T_855 = _T_854 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33393.6] assign _T_856 = io_in_a_bits_source == _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@33398.6] assign _T_858 = _T_856 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33400.6] assign _T_859 = _T_858 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33401.6] assign _T_860 = io_in_a_bits_address == _T_841; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@33406.6] assign _T_862 = _T_860 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33408.6] assign _T_863 = _T_862 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33409.6] assign _T_865 = _T_817 & _T_829; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@33416.4] assign _T_866 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@33424.4] assign _T_868 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@33426.4] assign _T_869 = _T_868[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@33427.4] assign _T_870 = ~ _T_869; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@33428.4] assign _T_871 = _T_870[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@33429.4] assign _T_872 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@33430.4] assign _T_876 = _T_874 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33434.4] assign _T_877 = _T_874 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33435.4] assign _T_891 = _T_877 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@33452.4] assign _T_892 = io_in_d_valid & _T_891; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@33453.4] assign _T_893 = io_in_d_bits_opcode == _T_885; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@33455.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33457.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33458.6] assign _T_897 = io_in_d_bits_param == _T_886; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@33463.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33465.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33466.6] assign _T_901 = io_in_d_bits_size == _T_887; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@33471.6] assign _T_903 = _T_901 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33473.6] assign _T_904 = _T_903 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33474.6] assign _T_905 = io_in_d_bits_source == _T_888; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@33479.6] assign _T_907 = _T_905 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33481.6] assign _T_908 = _T_907 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33482.6] assign _T_909 = io_in_d_bits_sink == _T_889; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@33487.6] assign _T_911 = _T_909 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33489.6] assign _T_912 = _T_911 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33490.6] assign _T_913 = io_in_d_bits_denied == _T_890; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@33495.6] assign _T_915 = _T_913 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33497.6] assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33498.6] assign _T_918 = _T_866 & _T_877; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@33505.4] assign _T_931 = _T_929 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33526.4] assign _T_932 = _T_929 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33527.4] assign _T_950 = _T_948 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@33548.4] assign _T_951 = _T_948 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@33549.4] assign _T_961 = _T_817 & _T_932; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@33564.4] assign _T_963 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@33567.6] assign _T_964 = _T_919 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@33569.6] assign _T_965 = _T_964[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@33570.6] assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@33571.6] assign _T_968 = _T_966 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33573.6] assign _T_969 = _T_968 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33574.6] assign _GEN_15 = _T_961 ? _T_963 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@33566.4] assign _T_973 = _T_866 & _T_951; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@33585.4] assign _T_975 = _T_676 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@33587.4] assign _T_976 = _T_973 & _T_975; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@33588.4] assign _T_977 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@33590.6] assign _T_959 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@33560.4 :freechips.rocketchip.system.TinyConfig.fir@33562.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@33568.6] assign _T_978 = _T_959 | _T_919; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@33592.6] assign _T_979 = _T_978 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@33593.6] assign _T_980 = _T_979[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@33594.6] assign _T_982 = _T_980 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33596.6] assign _T_983 = _T_982 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33597.6] assign _GEN_16 = _T_976 ? _T_977 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@33589.4] assign _T_984 = _T_919 | _T_959; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@33603.4] assign _T_970 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@33580.4 :freechips.rocketchip.system.TinyConfig.fir@33582.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@33591.6] assign _T_985 = ~ _T_970; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@33604.4] assign _T_986 = _T_984 & _T_985; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@33605.4] assign _T_988 = _T_919 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@33610.4] assign _T_989 = _T_988 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@33611.4] assign _T_990 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@33612.4] assign _T_991 = _T_989 | _T_990; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@33613.4] assign _T_992 = _T_987 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@33614.4] assign _T_993 = _T_991 | _T_992; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@33615.4] assign _T_995 = _T_993 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33617.4] assign _T_996 = _T_995 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33618.4] assign _T_998 = _T_987 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@33624.4] assign _T_1001 = _T_817 | _T_866; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@33628.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32320.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@32422.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32540.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32636.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@32724.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32812.10] assign _GEN_95 = io_in_a_valid & _T_524; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@32898.10] assign _GEN_105 = io_in_a_valid & _T_588; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32981.10] assign _GEN_115 = io_in_d_valid & _T_676; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33059.10] assign _GEN_125 = io_in_d_valid & _T_696; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@33101.10] assign _GEN_137 = io_in_d_valid & _T_724; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@33159.10] assign _GEN_149 = io_in_d_valid & _T_753; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@33218.10] assign _GEN_155 = io_in_d_valid & _T_770; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@33253.10] assign _GEN_161 = io_in_d_valid & _T_788; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@33289.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_826 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_837 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_838 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_839 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_840 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_841 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_874 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_885 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_886 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_887 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_888 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_889 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_890 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_919 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_929 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_948 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_987 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_826 <= 10'h0; end else begin if (_T_817) begin if (_T_829) begin if (_T_824) begin _T_826 <= _T_822; end else begin _T_826 <= 10'h0; end end else begin _T_826 <= _T_828; end end end if (_T_865) begin _T_837 <= io_in_a_bits_opcode; end if (_T_865) begin _T_838 <= io_in_a_bits_param; end if (_T_865) begin _T_839 <= io_in_a_bits_size; end if (_T_865) begin _T_840 <= io_in_a_bits_source; end if (_T_865) begin _T_841 <= io_in_a_bits_address; end if (reset) begin _T_874 <= 10'h0; end else begin if (_T_866) begin if (_T_877) begin if (_T_872) begin _T_874 <= _T_871; end else begin _T_874 <= 10'h0; end end else begin _T_874 <= _T_876; end end end if (_T_918) begin _T_885 <= io_in_d_bits_opcode; end if (_T_918) begin _T_886 <= io_in_d_bits_param; end if (_T_918) begin _T_887 <= io_in_d_bits_size; end if (_T_918) begin _T_888 <= io_in_d_bits_source; end if (_T_918) begin _T_889 <= io_in_d_bits_sink; end if (_T_918) begin _T_890 <= io_in_d_bits_denied; end if (reset) begin _T_919 <= 18'h0; end else begin _T_919 <= _T_986; end if (reset) begin _T_929 <= 10'h0; end else begin if (_T_817) begin if (_T_932) begin if (_T_824) begin _T_929 <= _T_822; end else begin _T_929 <= 10'h0; end end else begin _T_929 <= _T_931; end end end if (reset) begin _T_948 <= 10'h0; end else begin if (_T_866) begin if (_T_951) begin if (_T_872) begin _T_948 <= _T_871; end else begin _T_948 <= 10'h0; end end else begin _T_948 <= _T_950; end end end if (reset) begin _T_987 <= 32'h0; end else begin if (_T_1001) begin _T_987 <= 32'h0; end else begin _T_987 <= _T_998; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32320.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@32321.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@32327.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@32328.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@32335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32342.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@32343.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32349.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@32350.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32357.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@32358.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32366.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@32367.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32374.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@32375.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@32422.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@32423.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@32429.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@32430.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@32436.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@32437.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@32444.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@32445.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@32451.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@32452.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@32459.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@32460.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32467.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@32468.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@32476.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@32477.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@32484.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@32485.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32540.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@32541.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@32547.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@32548.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@32554.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@32555.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32562.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@32563.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32570.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@32571.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@32578.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@32579.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32636.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@32637.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@32643.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@32644.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@32650.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@32651.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@32658.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@32659.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@32666.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@32667.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@32724.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@32725.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@32731.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@32732.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@32738.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@32739.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@32746.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@32747.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32756.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@32757.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32812.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_509) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@32813.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@32819.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@32820.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@32826.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@32827.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32834.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_519) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@32835.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@32842.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@32843.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@32898.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_509) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@32899.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@32905.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@32906.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@32912.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@32913.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32920.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_583) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@32921.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@32928.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@32929.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_634) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32981.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_634) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@32982.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@32988.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@32989.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@32995.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@32996.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@33003.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@33004.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@33011.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@33012.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_652) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33022.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_652) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@33023.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33059.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@33060.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33067.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_683) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@33068.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33075.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_687) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@33076.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33083.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_691) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@33084.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_695) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33091.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_695) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@33092.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@33101.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_679) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@33102.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@33108.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@33109.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@33116.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_683) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@33117.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33124.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_710) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@33125.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33132.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_714) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@33133.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@33140.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_691) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@33141.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@33159.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_679) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@33160.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@33166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@33167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@33174.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_683) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@33175.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@33182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_710) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@33183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@33190.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_714) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@33191.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33199.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_747) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@33200.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@33218.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_679) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@33219.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@33226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_687) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@33227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@33234.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_691) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@33235.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@33253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_679) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@33254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@33261.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_687) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@33262.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@33270.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_747) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@33271.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@33289.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_679) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@33290.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@33297.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_687) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@33298.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@33305.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_691) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@33306.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33379.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_847) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@33380.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_851) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33387.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_851) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@33388.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_855) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33395.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_855) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@33396.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_859) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33403.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_859) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@33404.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_863) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33411.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_863) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@33412.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33460.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_896) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@33461.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33468.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_900) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@33469.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_904) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33476.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_904) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@33477.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_908) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33484.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_908) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@33485.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_912) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33492.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_912) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@33493.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_916) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33500.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_916) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@33501.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_961 & _T_969) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33576.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_961 & _T_969) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@33577.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_976 & _T_983) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33599.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_976 & _T_983) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@33600.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_996) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33620.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_996) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@33621.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_6( // @[:freechips.rocketchip.system.TinyConfig.fir@33633.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@33634.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@33635.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_5_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_5_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_5_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_5_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_5_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_5_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [16:0] auto_out_5_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_5_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_5_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_5_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_5_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_5_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_5_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_5_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_4_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_4_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_4_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_4_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_4_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_4_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_out_4_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_4_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_out_4_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_4_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_4_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_4_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_4_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [1:0] auto_out_4_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_4_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_4_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_4_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_4_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_4_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_4_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_3_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_3_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_3_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_3_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_3_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_3_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [11:0] auto_out_3_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_3_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_out_3_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_3_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_3_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_3_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_3_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_3_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_3_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_3_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_2_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_2_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_2_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_2_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_2_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_2_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [25:0] auto_out_2_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_2_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_out_2_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_2_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_2_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_2_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_2_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_2_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_2_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_2_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_1_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_1_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_1_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_1_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_1_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [27:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [31:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_1_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_1_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_1_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_1_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_1_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_0_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_0_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [2:0] auto_out_0_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_0_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [4:0] auto_out_0_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [13:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output [3:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_0_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] output auto_out_0_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_0_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [1:0] auto_out_0_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [3:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [4:0] auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_0_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input [31:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@33636.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] reg [9:0] _T_450; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@34451.4] reg [31:0] _RAND_0; wire _T_451; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@34452.4] wire [5:0] _T_457; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34458.4] reg [5:0] _T_464; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@34469.4] reg [31:0] _RAND_1; wire [5:0] _T_465; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@34470.4] wire [5:0] _T_466; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@34471.4] wire [11:0] _T_467; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34472.4] wire [10:0] _T_468; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34473.4] wire [11:0] _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34474.4] wire [11:0] _T_469; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34474.4] wire [9:0] _T_470; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34475.4] wire [11:0] _GEN_2; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34476.4] wire [11:0] _T_471; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34476.4] wire [7:0] _T_472; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34477.4] wire [11:0] _GEN_3; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34478.4] wire [11:0] _T_473; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34478.4] wire [10:0] _T_475; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@34480.4] wire [11:0] _T_476; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@34481.4] wire [11:0] _GEN_4; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@34482.4] wire [11:0] _T_477; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@34482.4] wire [5:0] _T_478; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@34483.4] wire [5:0] _T_479; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@34484.4] wire [5:0] _T_480; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@34485.4] wire [5:0] _T_481; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@34486.4] wire _T_496; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34504.4] wire _T_503; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34518.4] reg _T_573_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_2; wire _T_574_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [48:0] _T_606; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34653.4] wire [48:0] _T_607; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34654.4] wire _T_497; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34505.4] wire _T_504; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34519.4] reg _T_573_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_3; wire _T_574_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [3:0] out_1_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33774.4] wire [48:0] _T_614; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34661.4] wire [48:0] _T_615; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34662.4] wire [48:0] _T_648; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34695.4] wire _T_498; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34506.4] wire _T_505; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34520.4] reg _T_573_2; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_4; wire _T_574_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [3:0] out_2_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33796.4] wire [48:0] _T_622; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34669.4] wire [48:0] _T_623; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34670.4] wire [48:0] _T_649; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34696.4] wire _T_499; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34507.4] wire _T_506; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34521.4] reg _T_573_3; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_5; wire _T_574_3; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [3:0] out_3_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33818.4] wire [48:0] _T_630; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34677.4] wire [48:0] _T_631; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34678.4] wire [48:0] _T_650; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34697.4] wire _T_500; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34508.4] wire _T_507; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34522.4] reg _T_573_4; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_6; wire _T_574_4; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [3:0] out_4_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33840.4] wire [48:0] _T_638; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34685.4] wire [48:0] _T_639; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34686.4] wire [48:0] _T_651; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34698.4] wire _T_501; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34509.4] wire _T_508; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34523.4] reg _T_573_5; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@34611.4] reg [31:0] _RAND_7; wire _T_574_5; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] wire [3:0] out_5_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33862.4] wire [48:0] _T_646; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34693.4] wire [48:0] _T_647; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34694.4] wire [48:0] _T_652; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34699.4] wire [31:0] _T_63; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33873.4] wire [32:0] _T_64; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33874.4] wire [32:0] _T_65; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33875.4] wire [32:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33876.4] wire requestAIO_0_0; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33877.4] wire [31:0] _T_68; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33879.4] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33880.4] wire [32:0] _T_70; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33881.4] wire [32:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33882.4] wire requestAIO_0_1; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33883.4] wire [31:0] _T_73; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33885.4] wire [32:0] _T_74; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33886.4] wire [32:0] _T_75; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33887.4] wire [32:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33888.4] wire requestAIO_0_2; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33889.4] wire [32:0] _T_79; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33892.4] wire [32:0] _T_80; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33893.4] wire [32:0] _T_81; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33894.4] wire requestAIO_0_3; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33895.4] wire [31:0] _T_83; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33897.4] wire [32:0] _T_84; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33898.4] wire [32:0] _T_85; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33899.4] wire [32:0] _T_86; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33900.4] wire requestAIO_0_4; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33901.4] wire [31:0] _T_88; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33903.4] wire [32:0] _T_89; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33904.4] wire [32:0] _T_90; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33905.4] wire [32:0] _T_91; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33906.4] wire requestAIO_0_5; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33907.4] wire [26:0] _T_282; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34143.4] wire [11:0] _T_283; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34144.4] wire [11:0] _T_284; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34145.4] wire [9:0] _T_285; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34146.4] wire _T_286; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34147.4] wire [9:0] beatsDO_0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34148.4] wire [20:0] _T_288; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34150.4] wire [5:0] _T_289; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34151.4] wire [5:0] _T_290; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34152.4] wire [3:0] _T_291; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34153.4] wire _T_292; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34154.4] wire [3:0] beatsDO_1; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34155.4] wire [20:0] _T_294; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34157.4] wire [5:0] _T_295; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34158.4] wire [5:0] _T_296; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34159.4] wire [3:0] _T_297; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34160.4] wire _T_298; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34161.4] wire [3:0] beatsDO_2; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34162.4] wire [20:0] _T_300; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34164.4] wire [5:0] _T_301; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34165.4] wire [5:0] _T_302; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34166.4] wire [3:0] _T_303; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34167.4] wire _T_304; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34168.4] wire [3:0] beatsDO_3; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34169.4] wire [20:0] _T_306; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34171.4] wire [5:0] _T_307; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34172.4] wire [5:0] _T_308; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34173.4] wire [3:0] _T_309; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34174.4] wire _T_310; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34175.4] wire [3:0] beatsDO_4; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34176.4] wire [20:0] _T_312; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34178.4] wire [5:0] _T_313; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34179.4] wire [5:0] _T_314; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34180.4] wire [3:0] beatsDO_5; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34181.4] wire _T_331; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34212.4] wire _T_332; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34213.4] wire _T_333; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34214.4] wire _T_334; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34215.4] wire _T_335; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34216.4] wire _T_336; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34217.4] wire _T_337; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34218.4] wire _T_338; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34219.4] wire _T_339; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34220.4] wire _T_340; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34221.4] wire _T_452; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@34453.4] wire _T_459; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@34460.4] wire _T_461; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34462.4] wire _T_462; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34463.4] wire _T_482; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@34487.4] wire _T_483; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@34488.4] wire [5:0] _T_484; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@34490.6] wire [6:0] _T_485; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34491.6] wire [5:0] _T_486; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34492.6] wire [5:0] _T_487; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34493.6] wire [7:0] _T_488; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34494.6] wire [5:0] _T_489; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34495.6] wire [5:0] _T_490; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34496.6] wire [9:0] _T_491; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34497.6] wire [5:0] _T_492; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34498.6] wire [5:0] _T_493; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34499.6] wire _T_511; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34533.4] wire _T_512; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34534.4] wire _T_513; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34535.4] wire _T_514; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34536.4] wire _T_515; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34537.4] wire _T_517; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34539.4] wire _T_520; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34542.4] wire _T_521; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34543.4] wire _T_522; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34544.4] wire _T_523; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34545.4] wire _T_524; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34546.4] wire _T_525; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34547.4] wire _T_526; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34548.4] wire _T_527; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34549.4] wire _T_528; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34550.4] wire _T_529; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34551.4] wire _T_530; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34552.4] wire _T_531; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34553.4] wire _T_532; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34554.4] wire _T_533; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34555.4] wire _T_535; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34557.4] wire _T_536; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34558.4] wire _T_537; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34559.4] wire _T_538; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34560.4] wire _T_540; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34562.4] wire _T_541; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34563.4] wire _T_542; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34568.4] wire _T_543; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34569.4] wire _T_544; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34570.4] wire _T_545; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34571.4] wire _T_546; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34572.4] wire _T_547; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@34573.4] wire _T_553; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@34579.4] wire _T_555; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34581.4] wire _T_556; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34582.4] wire [9:0] _T_557; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34587.4] wire [3:0] _T_558; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34588.4] wire [3:0] _T_559; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34589.4] wire [3:0] _T_560; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34590.4] wire [3:0] _T_561; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34591.4] wire [3:0] _T_562; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34592.4] wire [9:0] _GEN_5; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34593.4] wire [9:0] _T_563; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34593.4] wire [9:0] _GEN_6; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34594.4] wire [9:0] _T_564; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34594.4] wire [9:0] _GEN_7; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34595.4] wire [9:0] _T_565; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34595.4] wire [9:0] _GEN_8; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34596.4] wire [9:0] _T_566; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34596.4] wire [9:0] _GEN_9; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34597.4] wire [9:0] _T_567; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34597.4] wire _T_587; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34632.4] wire _T_588; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34633.4] wire _T_593; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34638.4] wire _T_589; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34634.4] wire _T_594; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34639.4] wire _T_590; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34635.4] wire _T_595; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34640.4] wire _T_591; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34636.4] wire _T_596; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34641.4] wire _T_592; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34637.4] wire _T_597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34642.4] wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@34645.4] wire _T_568; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@34598.4] wire [9:0] _GEN_10; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@34599.4] wire [9:0] _T_570; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@34600.4] wire _T_575_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] wire _T_575_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] wire _T_575_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] wire _T_575_3; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] wire _T_575_4; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] wire _T_575_5; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] TLMonitor_16 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@33643.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign _T_451 = _T_450 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@34452.4] assign _T_457 = {auto_out_5_d_valid,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34458.4] assign _T_465 = ~ _T_464; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@34470.4] assign _T_466 = _T_457 & _T_465; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@34471.4] assign _T_467 = {_T_466,auto_out_5_d_valid,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34472.4] assign _T_468 = _T_467[11:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34473.4] assign _GEN_1 = {{1'd0}, _T_468}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34474.4] assign _T_469 = _T_467 | _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34474.4] assign _T_470 = _T_469[11:2]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34475.4] assign _GEN_2 = {{2'd0}, _T_470}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34476.4] assign _T_471 = _T_469 | _GEN_2; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34476.4] assign _T_472 = _T_471[11:4]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@34477.4] assign _GEN_3 = {{4'd0}, _T_472}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34478.4] assign _T_473 = _T_471 | _GEN_3; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@34478.4] assign _T_475 = _T_473[11:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@34480.4] assign _T_476 = {_T_464, 6'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@34481.4] assign _GEN_4 = {{1'd0}, _T_475}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@34482.4] assign _T_477 = _GEN_4 | _T_476; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@34482.4] assign _T_478 = _T_477[11:6]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@34483.4] assign _T_479 = _T_477[5:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@34484.4] assign _T_480 = _T_478 & _T_479; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@34485.4] assign _T_481 = ~ _T_480; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@34486.4] assign _T_496 = _T_481[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34504.4] assign _T_503 = _T_496 & auto_out_0_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34518.4] assign _T_574_0 = _T_451 ? _T_503 : _T_573_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign _T_606 = {auto_out_0_d_bits_opcode,auto_out_0_d_bits_param,auto_out_0_d_bits_size,auto_out_0_d_bits_source,auto_out_0_d_bits_sink,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34653.4] assign _T_607 = _T_574_0 ? _T_606 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34654.4] assign _T_497 = _T_481[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34505.4] assign _T_504 = _T_497 & auto_out_1_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34519.4] assign _T_574_1 = _T_451 ? _T_504 : _T_573_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign out_1_d_bits_size = {{1'd0}, auto_out_1_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33774.4] assign _T_614 = {auto_out_1_d_bits_opcode,2'h0,out_1_d_bits_size,auto_out_1_d_bits_source,2'h0,auto_out_1_d_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34661.4] assign _T_615 = _T_574_1 ? _T_614 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34662.4] assign _T_648 = _T_607 | _T_615; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34695.4] assign _T_498 = _T_481[2]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34506.4] assign _T_505 = _T_498 & auto_out_2_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34520.4] assign _T_574_2 = _T_451 ? _T_505 : _T_573_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign out_2_d_bits_size = {{1'd0}, auto_out_2_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33796.4] assign _T_622 = {auto_out_2_d_bits_opcode,2'h0,out_2_d_bits_size,auto_out_2_d_bits_source,2'h0,auto_out_2_d_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34669.4] assign _T_623 = _T_574_2 ? _T_622 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34670.4] assign _T_649 = _T_648 | _T_623; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34696.4] assign _T_499 = _T_481[3]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34507.4] assign _T_506 = _T_499 & auto_out_3_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34521.4] assign _T_574_3 = _T_451 ? _T_506 : _T_573_3; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign out_3_d_bits_size = {{1'd0}, auto_out_3_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33818.4] assign _T_630 = {auto_out_3_d_bits_opcode,2'h0,out_3_d_bits_size,auto_out_3_d_bits_source,2'h0,auto_out_3_d_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34677.4] assign _T_631 = _T_574_3 ? _T_630 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34678.4] assign _T_650 = _T_649 | _T_631; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34697.4] assign _T_500 = _T_481[4]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34508.4] assign _T_507 = _T_500 & auto_out_4_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34522.4] assign _T_574_4 = _T_451 ? _T_507 : _T_573_4; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign out_4_d_bits_size = {{1'd0}, auto_out_4_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33840.4] assign _T_638 = {auto_out_4_d_bits_opcode,auto_out_4_d_bits_param,out_4_d_bits_size,auto_out_4_d_bits_source,auto_out_4_d_bits_sink,auto_out_4_d_bits_denied,auto_out_4_d_bits_data,auto_out_4_d_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34685.4] assign _T_639 = _T_574_4 ? _T_638 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34686.4] assign _T_651 = _T_650 | _T_639; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34698.4] assign _T_501 = _T_481[5]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@34509.4] assign _T_508 = _T_501 & auto_out_5_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@34523.4] assign _T_574_5 = _T_451 ? _T_508 : _T_573_5; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@34612.4] assign out_5_d_bits_size = {{1'd0}, auto_out_5_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.TinyConfig.fir@33737.4 Xbar.scala 180:18:freechips.rocketchip.system.TinyConfig.fir@33862.4] assign _T_646 = {5'h4,out_5_d_bits_size,auto_out_5_d_bits_source,2'h0,auto_out_5_d_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34693.4] assign _T_647 = _T_574_5 ? _T_646 : 49'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34694.4] assign _T_652 = _T_651 | _T_647; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34699.4] assign _T_63 = auto_in_a_bits_address ^ 32'h2000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33873.4] assign _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33874.4] assign _T_65 = $signed(_T_64) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33875.4] assign _T_66 = $signed(_T_65); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33876.4] assign requestAIO_0_0 = $signed(_T_66) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33877.4] assign _T_68 = auto_in_a_bits_address ^ 32'h8000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33879.4] assign _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33880.4] assign _T_70 = $signed(_T_69) & $signed(33'sh88000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33881.4] assign _T_71 = $signed(_T_70); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33882.4] assign requestAIO_0_1 = $signed(_T_71) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33883.4] assign _T_73 = auto_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33885.4] assign _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33886.4] assign _T_75 = $signed(_T_74) & $signed(33'sh8a010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33887.4] assign _T_76 = $signed(_T_75); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33888.4] assign requestAIO_0_2 = $signed(_T_76) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33889.4] assign _T_79 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33892.4] assign _T_80 = $signed(_T_79) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33893.4] assign _T_81 = $signed(_T_80); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33894.4] assign requestAIO_0_3 = $signed(_T_81) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33895.4] assign _T_83 = auto_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33897.4] assign _T_84 = {1'b0,$signed(_T_83)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33898.4] assign _T_85 = $signed(_T_84) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33899.4] assign _T_86 = $signed(_T_85); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33900.4] assign requestAIO_0_4 = $signed(_T_86) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33901.4] assign _T_88 = auto_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@33903.4] assign _T_89 = {1'b0,$signed(_T_88)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@33904.4] assign _T_90 = $signed(_T_89) & $signed(33'sh8a010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33905.4] assign _T_91 = $signed(_T_90); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@33906.4] assign requestAIO_0_5 = $signed(_T_91) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@33907.4] assign _T_282 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34143.4] assign _T_283 = _T_282[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34144.4] assign _T_284 = ~ _T_283; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34145.4] assign _T_285 = _T_284[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34146.4] assign _T_286 = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34147.4] assign beatsDO_0 = _T_286 ? _T_285 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34148.4] assign _T_288 = 21'h3f << out_1_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34150.4] assign _T_289 = _T_288[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34151.4] assign _T_290 = ~ _T_289; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34152.4] assign _T_291 = _T_290[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34153.4] assign _T_292 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34154.4] assign beatsDO_1 = _T_292 ? _T_291 : 4'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34155.4] assign _T_294 = 21'h3f << out_2_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34157.4] assign _T_295 = _T_294[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34158.4] assign _T_296 = ~ _T_295; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34159.4] assign _T_297 = _T_296[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34160.4] assign _T_298 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34161.4] assign beatsDO_2 = _T_298 ? _T_297 : 4'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34162.4] assign _T_300 = 21'h3f << out_3_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34164.4] assign _T_301 = _T_300[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34165.4] assign _T_302 = ~ _T_301; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34166.4] assign _T_303 = _T_302[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34167.4] assign _T_304 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34168.4] assign beatsDO_3 = _T_304 ? _T_303 : 4'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34169.4] assign _T_306 = 21'h3f << out_4_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34171.4] assign _T_307 = _T_306[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34172.4] assign _T_308 = ~ _T_307; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34173.4] assign _T_309 = _T_308[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34174.4] assign _T_310 = auto_out_4_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@34175.4] assign beatsDO_4 = _T_310 ? _T_309 : 4'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@34176.4] assign _T_312 = 21'h3f << out_5_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34178.4] assign _T_313 = _T_312[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34179.4] assign _T_314 = ~ _T_313; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34180.4] assign beatsDO_5 = _T_314[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@34181.4] assign _T_331 = requestAIO_0_0 ? auto_out_0_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34212.4] assign _T_332 = requestAIO_0_1 ? auto_out_1_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34213.4] assign _T_333 = requestAIO_0_2 ? auto_out_2_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34214.4] assign _T_334 = requestAIO_0_3 ? auto_out_3_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34215.4] assign _T_335 = requestAIO_0_4 ? auto_out_4_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34216.4] assign _T_336 = requestAIO_0_5 ? auto_out_5_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34217.4] assign _T_337 = _T_331 | _T_332; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34218.4] assign _T_338 = _T_337 | _T_333; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34219.4] assign _T_339 = _T_338 | _T_334; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34220.4] assign _T_340 = _T_339 | _T_335; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34221.4] assign _T_452 = _T_451 & auto_in_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@34453.4] assign _T_459 = _T_457 == _T_457; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@34460.4] assign _T_461 = _T_459 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34462.4] assign _T_462 = _T_461 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34463.4] assign _T_482 = _T_457 != 6'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@34487.4] assign _T_483 = _T_452 & _T_482; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@34488.4] assign _T_484 = _T_481 & _T_457; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@34490.6] assign _T_485 = {_T_484, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34491.6] assign _T_486 = _T_485[5:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34492.6] assign _T_487 = _T_484 | _T_486; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34493.6] assign _T_488 = {_T_487, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34494.6] assign _T_489 = _T_488[5:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34495.6] assign _T_490 = _T_487 | _T_489; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34496.6] assign _T_491 = {_T_490, 4'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@34497.6] assign _T_492 = _T_491[5:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@34498.6] assign _T_493 = _T_490 | _T_492; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@34499.6] assign _T_511 = _T_503 | _T_504; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34533.4] assign _T_512 = _T_511 | _T_505; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34534.4] assign _T_513 = _T_512 | _T_506; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34535.4] assign _T_514 = _T_513 | _T_507; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34536.4] assign _T_515 = _T_514 | _T_508; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@34537.4] assign _T_517 = _T_503 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34539.4] assign _T_520 = _T_504 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34542.4] assign _T_521 = _T_517 | _T_520; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34543.4] assign _T_522 = _T_511 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34544.4] assign _T_523 = _T_505 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34545.4] assign _T_524 = _T_522 | _T_523; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34546.4] assign _T_525 = _T_512 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34547.4] assign _T_526 = _T_506 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34548.4] assign _T_527 = _T_525 | _T_526; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34549.4] assign _T_528 = _T_513 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34550.4] assign _T_529 = _T_507 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34551.4] assign _T_530 = _T_528 | _T_529; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34552.4] assign _T_531 = _T_514 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@34553.4] assign _T_532 = _T_508 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@34554.4] assign _T_533 = _T_531 | _T_532; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@34555.4] assign _T_535 = _T_521 & _T_524; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34557.4] assign _T_536 = _T_535 & _T_527; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34558.4] assign _T_537 = _T_536 & _T_530; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34559.4] assign _T_538 = _T_537 & _T_533; // @[Arbiter.scala 68:77:freechips.rocketchip.system.TinyConfig.fir@34560.4] assign _T_540 = _T_538 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34562.4] assign _T_541 = _T_540 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34563.4] assign _T_542 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34568.4] assign _T_543 = _T_542 | auto_out_2_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34569.4] assign _T_544 = _T_543 | auto_out_3_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34570.4] assign _T_545 = _T_544 | auto_out_4_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34571.4] assign _T_546 = _T_545 | auto_out_5_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@34572.4] assign _T_547 = _T_546 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@34573.4] assign _T_553 = _T_547 | _T_515; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@34579.4] assign _T_555 = _T_553 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34581.4] assign _T_556 = _T_555 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34582.4] assign _T_557 = _T_503 ? beatsDO_0 : 10'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34587.4] assign _T_558 = _T_504 ? beatsDO_1 : 4'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34588.4] assign _T_559 = _T_505 ? beatsDO_2 : 4'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34589.4] assign _T_560 = _T_506 ? beatsDO_3 : 4'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34590.4] assign _T_561 = _T_507 ? beatsDO_4 : 4'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34591.4] assign _T_562 = _T_508 ? beatsDO_5 : 4'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.TinyConfig.fir@34592.4] assign _GEN_5 = {{6'd0}, _T_558}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34593.4] assign _T_563 = _T_557 | _GEN_5; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34593.4] assign _GEN_6 = {{6'd0}, _T_559}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34594.4] assign _T_564 = _T_563 | _GEN_6; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34594.4] assign _GEN_7 = {{6'd0}, _T_560}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34595.4] assign _T_565 = _T_564 | _GEN_7; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34595.4] assign _GEN_8 = {{6'd0}, _T_561}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34596.4] assign _T_566 = _T_565 | _GEN_8; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34596.4] assign _GEN_9 = {{6'd0}, _T_562}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34597.4] assign _T_567 = _T_566 | _GEN_9; // @[Arbiter.scala 74:44:freechips.rocketchip.system.TinyConfig.fir@34597.4] assign _T_587 = _T_573_0 ? auto_out_0_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34632.4] assign _T_588 = _T_573_1 ? auto_out_1_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34633.4] assign _T_593 = _T_587 | _T_588; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34638.4] assign _T_589 = _T_573_2 ? auto_out_2_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34634.4] assign _T_594 = _T_593 | _T_589; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34639.4] assign _T_590 = _T_573_3 ? auto_out_3_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34635.4] assign _T_595 = _T_594 | _T_590; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34640.4] assign _T_591 = _T_573_4 ? auto_out_4_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34636.4] assign _T_596 = _T_595 | _T_591; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34641.4] assign _T_592 = _T_573_5 ? auto_out_5_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34637.4] assign _T_597 = _T_596 | _T_592; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@34642.4] assign in_0_d_valid = _T_451 ? _T_546 : _T_597; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@34645.4] assign _T_568 = auto_in_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@34598.4] assign _GEN_10 = {{9'd0}, _T_568}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@34599.4] assign _T_570 = _T_450 - _GEN_10; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@34600.4] assign _T_575_0 = _T_451 ? _T_496 : _T_573_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign _T_575_1 = _T_451 ? _T_497 : _T_573_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign _T_575_2 = _T_451 ? _T_498 : _T_573_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign _T_575_3 = _T_451 ? _T_499 : _T_573_3; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign _T_575_4 = _T_451 ? _T_500 : _T_573_4; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign _T_575_5 = _T_451 ? _T_501 : _T_573_5; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@34614.4] assign auto_in_a_ready = _T_340 | _T_336; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_valid = _T_451 ? _T_546 : _T_597; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_opcode = _T_652[48:46]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_param = _T_652[45:44]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_size = _T_652[43:40]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_source = _T_652[39:35]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_sink = _T_652[34]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_denied = _T_652[33]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_data = _T_652[32:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_in_d_bits_corrupt = _T_652[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@33710.4] assign auto_out_5_a_valid = auto_in_a_valid & requestAIO_0_5; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_address = auto_in_a_bits_address[16:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_5_d_ready = auto_in_d_ready & _T_575_5; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33709.4] assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_4_d_ready = auto_in_d_ready & _T_575_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33708.4] assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_address = auto_in_a_bits_address[11:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_3_d_ready = auto_in_d_ready & _T_575_3; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33707.4] assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_address = auto_in_a_bits_address[25:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_2_d_ready = auto_in_d_ready & _T_575_2; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33706.4] assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_address = auto_in_a_bits_address[27:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_1_d_ready = auto_in_d_ready & _T_575_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33705.4] assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_address = auto_in_a_bits_address[13:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign auto_out_0_d_ready = auto_in_d_ready & _T_575_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@33704.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@33645.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@33646.4] assign TLMonitor_io_in_a_ready = _T_340 | _T_336; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_valid = _T_451 ? _T_546 : _T_597; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_opcode = _T_652[48:46]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_param = _T_652[45:44]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_size = _T_652[43:40]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_source = _T_652[39:35]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_sink = _T_652[34]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_denied = _T_652[33]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] assign TLMonitor_io_in_d_bits_corrupt = _T_652[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@33691.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_450 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_464 = _RAND_1[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_573_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_573_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_573_2 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_573_3 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_573_4 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_573_5 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_450 <= 10'h0; end else begin if (_T_452) begin _T_450 <= _T_567; end else begin _T_450 <= _T_570; end end if (reset) begin _T_464 <= 6'h3f; end else begin if (_T_483) begin _T_464 <= _T_493; end end if (reset) begin _T_573_0 <= 1'h0; end else begin if (_T_451) begin _T_573_0 <= _T_503; end end if (reset) begin _T_573_1 <= 1'h0; end else begin if (_T_451) begin _T_573_1 <= _T_504; end end if (reset) begin _T_573_2 <= 1'h0; end else begin if (_T_451) begin _T_573_2 <= _T_505; end end if (reset) begin _T_573_3 <= 1'h0; end else begin if (_T_451) begin _T_573_3 <= _T_506; end end if (reset) begin _T_573_4 <= 1'h0; end else begin if (_T_451) begin _T_573_4 <= _T_507; end end if (reset) begin _T_573_5 <= 1'h0; end else begin if (_T_451) begin _T_573_5 <= _T_508; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_462) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34465.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_462) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@34466.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_541) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34565.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_541) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@34566.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_556) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34584.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_556) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@34585.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_17( // @[:freechips.rocketchip.system.TinyConfig.fir@34729.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@34730.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@34731.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@34732.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@36212.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@34747.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@34748.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@34751.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@34752.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@34760.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34771.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34772.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34773.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34775.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34776.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34777.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@34778.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@34778.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@34779.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@34781.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@34782.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@34784.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@34785.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@34786.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@34787.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@34788.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34790.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34791.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34793.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34794.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@34795.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@34796.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@34797.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34798.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34799.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34800.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34801.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34802.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34803.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34804.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34805.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34806.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34807.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34808.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34809.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34812.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34816.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@34869.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34872.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34873.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34874.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34875.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34876.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34877.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34878.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34879.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34880.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34881.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34882.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34883.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34884.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34885.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34886.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34889.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34890.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34891.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34892.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34893.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34894.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34895.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34896.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34897.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34898.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34899.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34900.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34901.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34911.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34924.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34925.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34932.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34933.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34939.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34940.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@34945.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34947.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34948.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@34953.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@34954.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34956.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34957.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@34962.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34964.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34965.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@34971.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@35055.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35057.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35058.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@35081.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35084.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35092.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35094.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35122.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35123.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35124.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35125.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35126.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35128.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35130.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35131.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@35150.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35152.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35153.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@35158.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35160.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35161.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@35175.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35214.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35223.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35226.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35227.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@35263.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@35342.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@35343.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@35344.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35346.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35347.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@35353.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35356.8] wire _T_470; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35364.8] wire _T_496; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@35390.8] wire _T_503; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35397.8] wire _T_506; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35400.8] wire _T_508; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35402.8] wire _T_509; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35403.8] wire _T_516; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@35422.8] wire _T_518; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35424.8] wire _T_519; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35425.8] wire _T_524; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@35439.6] wire _T_580; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@35508.8] wire _T_582; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35510.8] wire _T_583; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35511.8] wire _T_588; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@35525.6] wire _T_633; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35571.8] wire _T_634; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35572.8] wire _T_649; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@35610.6] wire _T_651; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35612.6] wire _T_652; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35613.6] wire _T_653; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@35618.6] wire _T_654; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@35619.6] wire [1:0] _T_657; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@35622.6] wire _T_658; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@35623.6] wire _T_666; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@35631.6] wire _T_672; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35642.6] wire _T_673; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35643.6] wire _T_674; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35644.6] wire _T_676; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@35646.6] wire _T_678; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35649.8] wire _T_679; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35650.8] wire _T_680; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@35655.8] wire _T_682; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35657.8] wire _T_683; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35658.8] wire _T_684; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@35663.8] wire _T_686; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35665.8] wire _T_687; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35666.8] wire _T_688; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@35671.8] wire _T_690; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35673.8] wire _T_691; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35674.8] wire _T_692; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@35679.8] wire _T_694; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35681.8] wire _T_695; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35682.8] wire _T_696; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@35688.6] wire _T_707; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@35712.8] wire _T_709; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35714.8] wire _T_710; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35715.8] wire _T_711; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@35720.8] wire _T_713; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35722.8] wire _T_714; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35723.8] wire _T_724; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@35746.6] wire _T_744; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@35787.8] wire _T_746; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35789.8] wire _T_747; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35790.8] wire _T_753; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@35805.6] wire _T_770; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@35840.6] wire _T_788; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@35876.6] wire _T_817; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@35936.4] wire [9:0] _T_822; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@35941.4] wire _T_823; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@35942.4] wire _T_824; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@35943.4] reg [9:0] _T_826; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@35945.4] reg [31:0] _RAND_0; wire [9:0] _T_828; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@35947.4] wire _T_829; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@35948.4] reg [2:0] _T_837; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@35959.4] reg [31:0] _RAND_1; reg [2:0] _T_838; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@35960.4] reg [31:0] _RAND_2; reg [3:0] _T_839; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@35961.4] reg [31:0] _RAND_3; reg [4:0] _T_840; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@35962.4] reg [31:0] _RAND_4; reg [31:0] _T_841; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@35963.4] reg [31:0] _RAND_5; wire _T_842; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@35964.4] wire _T_843; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@35965.4] wire _T_844; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@35967.6] wire _T_846; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35969.6] wire _T_847; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35970.6] wire _T_848; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@35975.6] wire _T_850; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35977.6] wire _T_851; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35978.6] wire _T_852; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@35983.6] wire _T_854; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35985.6] wire _T_855; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35986.6] wire _T_856; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@35991.6] wire _T_858; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35993.6] wire _T_859; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35994.6] wire _T_860; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@35999.6] wire _T_862; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36001.6] wire _T_863; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36002.6] wire _T_865; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@36009.4] wire _T_866; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@36017.4] wire [26:0] _T_868; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@36019.4] wire [11:0] _T_869; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@36020.4] wire [11:0] _T_870; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@36021.4] wire [9:0] _T_871; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@36022.4] wire _T_872; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@36023.4] reg [9:0] _T_874; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@36025.4] reg [31:0] _RAND_6; wire [9:0] _T_876; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36027.4] wire _T_877; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36028.4] reg [2:0] _T_885; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@36039.4] reg [31:0] _RAND_7; reg [1:0] _T_886; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@36040.4] reg [31:0] _RAND_8; reg [3:0] _T_887; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@36041.4] reg [31:0] _RAND_9; reg [4:0] _T_888; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@36042.4] reg [31:0] _RAND_10; reg _T_889; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@36043.4] reg [31:0] _RAND_11; reg _T_890; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@36044.4] reg [31:0] _RAND_12; wire _T_891; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@36045.4] wire _T_892; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@36046.4] wire _T_893; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@36048.6] wire _T_895; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36050.6] wire _T_896; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36051.6] wire _T_897; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@36056.6] wire _T_899; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36058.6] wire _T_900; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36059.6] wire _T_901; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@36064.6] wire _T_903; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36066.6] wire _T_904; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36067.6] wire _T_905; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@36072.6] wire _T_907; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36074.6] wire _T_908; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36075.6] wire _T_909; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@36080.6] wire _T_911; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36082.6] wire _T_912; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36083.6] wire _T_913; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@36088.6] wire _T_915; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36090.6] wire _T_916; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36091.6] wire _T_918; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@36098.4] reg [17:0] _T_919; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@36107.4] reg [31:0] _RAND_13; reg [9:0] _T_929; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@36117.4] reg [31:0] _RAND_14; wire [9:0] _T_931; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36119.4] wire _T_932; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36120.4] reg [9:0] _T_948; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@36139.4] reg [31:0] _RAND_15; wire [9:0] _T_950; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36141.4] wire _T_951; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36142.4] wire _T_961; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@36157.4] wire [31:0] _T_963; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@36160.6] wire [17:0] _T_964; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@36162.6] wire _T_965; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@36163.6] wire _T_966; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@36164.6] wire _T_968; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36166.6] wire _T_969; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36167.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@36159.4] wire _T_973; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@36178.4] wire _T_975; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@36180.4] wire _T_976; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@36181.4] wire [31:0] _T_977; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@36183.6] wire [17:0] _T_959; // @[:freechips.rocketchip.system.TinyConfig.fir@36153.4 :freechips.rocketchip.system.TinyConfig.fir@36155.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@36161.6] wire [17:0] _T_978; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@36185.6] wire [17:0] _T_979; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@36186.6] wire _T_980; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@36187.6] wire _T_982; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36189.6] wire _T_983; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36190.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@36182.4] wire [17:0] _T_970; // @[:freechips.rocketchip.system.TinyConfig.fir@36173.4 :freechips.rocketchip.system.TinyConfig.fir@36175.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@36184.6] wire _T_984; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@36196.4] wire _T_985; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@36197.4] wire _T_986; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@36198.4] wire _T_987; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@36199.4] wire _T_989; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36201.4] wire _T_990; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36202.4] wire [17:0] _T_991; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@36207.4] wire [17:0] _T_992; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@36208.4] wire [17:0] _T_993; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@36209.4] reg [31:0] _T_994; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@36211.4] reg [31:0] _RAND_16; wire _T_995; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@36214.4] wire _T_996; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@36215.4] wire _T_997; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@36216.4] wire _T_998; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@36217.4] wire _T_999; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@36218.4] wire _T_1000; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@36219.4] wire _T_1002; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36221.4] wire _T_1003; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36222.4] wire [31:0] _T_1005; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@36228.4] wire _T_1008; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@36232.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34913.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@35015.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35133.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35229.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@35317.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35405.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@35491.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35574.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35652.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@35694.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@35752.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@35811.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@35846.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@35882.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@36212.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@34747.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@34748.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@34751.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@34752.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@34760.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34771.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34772.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@34773.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@34775.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@34776.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@34777.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@34778.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@34778.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@34779.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@34781.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@34782.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@34784.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@34785.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@34786.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@34787.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@34788.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34790.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34791.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34793.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34794.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@34795.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@34796.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@34797.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34798.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34799.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34800.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34801.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34802.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34803.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34804.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34805.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34806.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@34807.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@34808.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@34809.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@34812.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34816.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@34869.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34872.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34873.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34874.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34875.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34876.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34877.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34878.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34879.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34880.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34881.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34882.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34883.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34884.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34885.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34886.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34889.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34890.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34891.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34892.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34893.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34894.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34895.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34896.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@34897.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@34898.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34899.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@34900.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@34901.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34911.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34924.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34925.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34932.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34933.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34939.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34940.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@34945.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34947.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34948.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@34953.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@34954.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34956.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34957.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@34962.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34964.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34965.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@34971.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@35055.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35057.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35058.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@35081.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35084.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35092.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35094.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35122.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35123.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35124.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@35125.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35126.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35128.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35130.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35131.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@35150.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35152.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35153.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@35158.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35160.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35161.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@35175.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35214.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35223.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35226.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35227.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@35263.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@35342.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@35343.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@35344.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35346.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35347.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@35353.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@35356.8] assign _T_470 = _T_462 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35364.8] assign _T_496 = 4'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@35390.8] assign _T_503 = _T_496 & _T_144; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@35397.8] assign _T_506 = _T_470 | _T_503; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@35400.8] assign _T_508 = _T_506 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35402.8] assign _T_509 = _T_508 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35403.8] assign _T_516 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@35422.8] assign _T_518 = _T_516 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35424.8] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35425.8] assign _T_524 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@35439.6] assign _T_580 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@35508.8] assign _T_582 = _T_580 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35510.8] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35511.8] assign _T_588 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@35525.6] assign _T_633 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35571.8] assign _T_634 = _T_633 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35572.8] assign _T_649 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@35610.6] assign _T_651 = _T_649 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35612.6] assign _T_652 = _T_651 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35613.6] assign _T_653 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@35618.6] assign _T_654 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@35619.6] assign _T_657 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@35622.6] assign _T_658 = _T_657 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@35623.6] assign _T_666 = _T_657 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@35631.6] assign _T_672 = _T_653 | _T_654; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35642.6] assign _T_673 = _T_672 | _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35643.6] assign _T_674 = _T_673 | _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@35644.6] assign _T_676 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@35646.6] assign _T_678 = _T_674 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35649.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35650.8] assign _T_680 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@35655.8] assign _T_682 = _T_680 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35657.8] assign _T_683 = _T_682 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35658.8] assign _T_684 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@35663.8] assign _T_686 = _T_684 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35665.8] assign _T_687 = _T_686 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35666.8] assign _T_688 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@35671.8] assign _T_690 = _T_688 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35673.8] assign _T_691 = _T_690 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35674.8] assign _T_692 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@35679.8] assign _T_694 = _T_692 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35681.8] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35682.8] assign _T_696 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@35688.6] assign _T_707 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@35712.8] assign _T_709 = _T_707 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35714.8] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35715.8] assign _T_711 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@35720.8] assign _T_713 = _T_711 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35722.8] assign _T_714 = _T_713 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35723.8] assign _T_724 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@35746.6] assign _T_744 = _T_692 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@35787.8] assign _T_746 = _T_744 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35789.8] assign _T_747 = _T_746 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35790.8] assign _T_753 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@35805.6] assign _T_770 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@35840.6] assign _T_788 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@35876.6] assign _T_817 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@35936.4] assign _T_822 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@35941.4] assign _T_823 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@35942.4] assign _T_824 = _T_823 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@35943.4] assign _T_828 = _T_826 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@35947.4] assign _T_829 = _T_826 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@35948.4] assign _T_842 = _T_829 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@35964.4] assign _T_843 = io_in_a_valid & _T_842; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@35965.4] assign _T_844 = io_in_a_bits_opcode == _T_837; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@35967.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35969.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35970.6] assign _T_848 = io_in_a_bits_param == _T_838; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@35975.6] assign _T_850 = _T_848 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35977.6] assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35978.6] assign _T_852 = io_in_a_bits_size == _T_839; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@35983.6] assign _T_854 = _T_852 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35985.6] assign _T_855 = _T_854 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35986.6] assign _T_856 = io_in_a_bits_source == _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@35991.6] assign _T_858 = _T_856 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35993.6] assign _T_859 = _T_858 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35994.6] assign _T_860 = io_in_a_bits_address == _T_841; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@35999.6] assign _T_862 = _T_860 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36001.6] assign _T_863 = _T_862 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36002.6] assign _T_865 = _T_817 & _T_829; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@36009.4] assign _T_866 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@36017.4] assign _T_868 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@36019.4] assign _T_869 = _T_868[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@36020.4] assign _T_870 = ~ _T_869; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@36021.4] assign _T_871 = _T_870[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@36022.4] assign _T_872 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@36023.4] assign _T_876 = _T_874 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36027.4] assign _T_877 = _T_874 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36028.4] assign _T_891 = _T_877 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@36045.4] assign _T_892 = io_in_d_valid & _T_891; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@36046.4] assign _T_893 = io_in_d_bits_opcode == _T_885; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@36048.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36050.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36051.6] assign _T_897 = io_in_d_bits_param == _T_886; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@36056.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36058.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36059.6] assign _T_901 = io_in_d_bits_size == _T_887; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@36064.6] assign _T_903 = _T_901 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36066.6] assign _T_904 = _T_903 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36067.6] assign _T_905 = io_in_d_bits_source == _T_888; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@36072.6] assign _T_907 = _T_905 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36074.6] assign _T_908 = _T_907 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36075.6] assign _T_909 = io_in_d_bits_sink == _T_889; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@36080.6] assign _T_911 = _T_909 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36082.6] assign _T_912 = _T_911 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36083.6] assign _T_913 = io_in_d_bits_denied == _T_890; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@36088.6] assign _T_915 = _T_913 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36090.6] assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36091.6] assign _T_918 = _T_866 & _T_877; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@36098.4] assign _T_931 = _T_929 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36119.4] assign _T_932 = _T_929 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36120.4] assign _T_950 = _T_948 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@36141.4] assign _T_951 = _T_948 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@36142.4] assign _T_961 = _T_817 & _T_932; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@36157.4] assign _T_963 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@36160.6] assign _T_964 = _T_919 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@36162.6] assign _T_965 = _T_964[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@36163.6] assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@36164.6] assign _T_968 = _T_966 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36166.6] assign _T_969 = _T_968 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36167.6] assign _GEN_15 = _T_961 ? _T_963 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@36159.4] assign _T_973 = _T_866 & _T_951; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@36178.4] assign _T_975 = _T_676 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@36180.4] assign _T_976 = _T_973 & _T_975; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@36181.4] assign _T_977 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@36183.6] assign _T_959 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@36153.4 :freechips.rocketchip.system.TinyConfig.fir@36155.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@36161.6] assign _T_978 = _T_959 | _T_919; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@36185.6] assign _T_979 = _T_978 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@36186.6] assign _T_980 = _T_979[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@36187.6] assign _T_982 = _T_980 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36189.6] assign _T_983 = _T_982 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36190.6] assign _GEN_16 = _T_976 ? _T_977 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@36182.4] assign _T_970 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@36173.4 :freechips.rocketchip.system.TinyConfig.fir@36175.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@36184.6] assign _T_984 = _T_959 != _T_970; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@36196.4] assign _T_985 = _T_959 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@36197.4] assign _T_986 = _T_985 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@36198.4] assign _T_987 = _T_984 | _T_986; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@36199.4] assign _T_989 = _T_987 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36201.4] assign _T_990 = _T_989 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36202.4] assign _T_991 = _T_919 | _T_959; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@36207.4] assign _T_992 = ~ _T_970; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@36208.4] assign _T_993 = _T_991 & _T_992; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@36209.4] assign _T_995 = _T_919 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@36214.4] assign _T_996 = _T_995 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@36215.4] assign _T_997 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@36216.4] assign _T_998 = _T_996 | _T_997; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@36217.4] assign _T_999 = _T_994 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@36218.4] assign _T_1000 = _T_998 | _T_999; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@36219.4] assign _T_1002 = _T_1000 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36221.4] assign _T_1003 = _T_1002 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36222.4] assign _T_1005 = _T_994 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@36228.4] assign _T_1008 = _T_817 | _T_866; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@36232.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34913.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@35015.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35133.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35229.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@35317.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35405.10] assign _GEN_95 = io_in_a_valid & _T_524; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@35491.10] assign _GEN_105 = io_in_a_valid & _T_588; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35574.10] assign _GEN_115 = io_in_d_valid & _T_676; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35652.10] assign _GEN_125 = io_in_d_valid & _T_696; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@35694.10] assign _GEN_137 = io_in_d_valid & _T_724; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@35752.10] assign _GEN_149 = io_in_d_valid & _T_753; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@35811.10] assign _GEN_155 = io_in_d_valid & _T_770; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@35846.10] assign _GEN_161 = io_in_d_valid & _T_788; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@35882.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_826 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_837 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_838 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_839 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_840 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_841 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_874 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_885 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_886 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_887 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_888 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_889 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_890 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_919 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_929 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_948 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_994 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_826 <= 10'h0; end else begin if (_T_817) begin if (_T_829) begin if (_T_824) begin _T_826 <= _T_822; end else begin _T_826 <= 10'h0; end end else begin _T_826 <= _T_828; end end end if (_T_865) begin _T_837 <= io_in_a_bits_opcode; end if (_T_865) begin _T_838 <= io_in_a_bits_param; end if (_T_865) begin _T_839 <= io_in_a_bits_size; end if (_T_865) begin _T_840 <= io_in_a_bits_source; end if (_T_865) begin _T_841 <= io_in_a_bits_address; end if (reset) begin _T_874 <= 10'h0; end else begin if (_T_866) begin if (_T_877) begin if (_T_872) begin _T_874 <= _T_871; end else begin _T_874 <= 10'h0; end end else begin _T_874 <= _T_876; end end end if (_T_918) begin _T_885 <= io_in_d_bits_opcode; end if (_T_918) begin _T_886 <= io_in_d_bits_param; end if (_T_918) begin _T_887 <= io_in_d_bits_size; end if (_T_918) begin _T_888 <= io_in_d_bits_source; end if (_T_918) begin _T_889 <= io_in_d_bits_sink; end if (_T_918) begin _T_890 <= io_in_d_bits_denied; end if (reset) begin _T_919 <= 18'h0; end else begin _T_919 <= _T_993; end if (reset) begin _T_929 <= 10'h0; end else begin if (_T_817) begin if (_T_932) begin if (_T_824) begin _T_929 <= _T_822; end else begin _T_929 <= 10'h0; end end else begin _T_929 <= _T_931; end end end if (reset) begin _T_948 <= 10'h0; end else begin if (_T_866) begin if (_T_951) begin if (_T_872) begin _T_948 <= _T_871; end else begin _T_948 <= 10'h0; end end else begin _T_948 <= _T_950; end end end if (reset) begin _T_994 <= 32'h0; end else begin if (_T_1008) begin _T_994 <= 32'h0; end else begin _T_994 <= _T_1005; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34913.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@34914.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@34920.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@34921.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34927.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@34928.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34935.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@34936.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34942.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@34943.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34950.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@34951.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34959.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@34960.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34967.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@34968.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@35015.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@35016.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@35022.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@35023.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@35029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@35030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@35037.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@35038.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@35044.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@35045.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@35052.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@35053.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35060.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@35061.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@35069.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@35070.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@35077.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@35078.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@35134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@35140.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@35141.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@35147.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@35148.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35155.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@35156.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35163.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@35164.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@35171.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@35172.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35229.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@35230.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@35236.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@35237.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@35243.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@35244.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@35251.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@35252.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@35259.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@35260.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@35317.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@35318.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@35324.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@35325.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@35331.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@35332.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@35339.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@35340.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35349.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@35350.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35405.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_509) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@35406.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@35412.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@35413.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@35419.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@35420.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_519) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@35428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@35435.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@35436.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@35491.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_509) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@35492.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@35498.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@35499.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@35505.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@35506.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35513.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_583) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@35514.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@35521.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@35522.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_634) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35574.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_634) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@35575.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@35581.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@35582.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@35588.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@35589.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@35596.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@35597.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@35604.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@35605.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_652) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35615.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_652) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@35616.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35652.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@35653.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35660.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_683) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@35661.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35668.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_687) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@35669.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35676.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_691) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@35677.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_695) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35684.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_695) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@35685.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@35694.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_679) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@35695.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@35701.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@35702.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@35709.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_683) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@35710.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35717.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_710) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@35718.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35725.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_714) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@35726.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@35733.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_691) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@35734.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@35752.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_679) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@35753.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@35759.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@35760.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@35767.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_683) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@35768.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_710) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@35775.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_710) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@35776.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_714) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@35783.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_714) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@35784.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35792.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_747) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@35793.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@35811.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_679) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@35812.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@35819.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_687) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@35820.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@35827.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_691) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@35828.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@35846.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_679) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@35847.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@35854.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_687) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@35855.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_747) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@35863.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_747) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@35864.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@35882.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_679) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@35883.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_687) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@35890.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_687) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@35891.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@35898.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_691) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@35899.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35972.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_847) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@35973.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_851) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35980.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_851) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@35981.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_855) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35988.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_855) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@35989.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_859) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35996.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_859) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@35997.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_843 & _T_863) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36004.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_843 & _T_863) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@36005.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36053.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_896) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@36054.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36061.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_900) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@36062.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_904) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36069.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_904) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@36070.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_908) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36077.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_908) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@36078.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_912) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36085.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_912) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@36086.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_892 & _T_916) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36093.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_892 & _T_916) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@36094.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_961 & _T_969) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36169.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_961 & _T_969) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@36170.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_976 & _T_983) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36192.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_976 & _T_983) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@36193.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_990) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36204.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_990) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@36205.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1003) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36224.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1003) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@36225.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_32( // @[:freechips.rocketchip.system.TinyConfig.fir@36237.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@36238.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@36239.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@36240.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_1; wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_3; wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_4; wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_address__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_5; wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@36243.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@36244.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@36245.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@36246.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@36247.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@36248.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@36249.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36250.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36253.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36268.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36274.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@36277.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_address__T_18_addr = value_1; assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_address__T_10_data = io_enq_bits_address; assign _T_address__T_10_addr = value; assign _T_address__T_10_mask = 1'h1; assign _T_address__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_18_addr = value_1; assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = value; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@36246.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@36247.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@36248.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@36249.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36250.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36253.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36268.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36274.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@36277.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@36284.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@36282.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36293.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36292.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36291.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36290.4] assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36289.4] assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36288.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36287.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36286.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[4:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_address[initvar] = _RAND_4[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_mask[initvar] = _RAND_5[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_address__T_10_en & _T_address__T_10_mask) begin _T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36242.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_33( // @[:freechips.rocketchip.system.TinyConfig.fir@36301.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@36302.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@36303.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input [1:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input io_enq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input io_enq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output io_deq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output io_deq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@36304.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_1; wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_3; wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg _T_sink [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_4; wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg _T_denied [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_5; wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@36307.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@36308.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@36309.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@36310.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@36311.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@36312.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@36313.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36314.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36317.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36332.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36338.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@36341.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_sink__T_18_addr = value_1; assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_sink__T_10_data = io_enq_bits_sink; assign _T_sink__T_10_addr = value; assign _T_sink__T_10_mask = 1'h1; assign _T_sink__T_10_en = io_enq_ready & io_enq_valid; assign _T_denied__T_18_addr = value_1; assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_denied__T_10_data = io_enq_bits_denied; assign _T_denied__T_10_addr = value; assign _T_denied__T_10_mask = 1'h1; assign _T_denied__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@36310.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@36311.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@36312.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@36313.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36314.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@36317.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36332.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@36338.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@36341.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@36348.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@36346.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36357.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36356.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36355.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36354.4] assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36353.4] assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36352.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36351.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@36350.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[4:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_sink[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_denied[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_sink__T_10_en & _T_sink__T_10_mask) begin _T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_denied__T_10_en & _T_denied__T_10_mask) begin _T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@36306.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module TLBuffer_6( // @[:freechips.rocketchip.system.TinyConfig.fir@36365.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@36366.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@36367.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@36368.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [4:0] Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [4:0] Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [4:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [4:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] TLMonitor_17 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@36375.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_32 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36428.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_corrupt(Queue_io_enq_bits_corrupt), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_corrupt(Queue_io_deq_bits_corrupt) ); Queue_33 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@36442.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_param(Queue_1_io_enq_bits_param), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_sink(Queue_1_io_enq_bits_sink), .io_enq_bits_denied(Queue_1_io_enq_bits_denied), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@36427.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@36426.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@36377.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@36378.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@36423.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@36429.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@36430.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@36431.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36439.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36438.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36437.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36436.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36435.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36434.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36433.4] assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36432.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@36441.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@36443.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@36444.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@36445.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36453.4] assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36452.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36451.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36450.4] assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36449.4] assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36448.4] assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36447.4] assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@36446.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@36455.4] endmodule module TLMonitor_18( // @[:freechips.rocketchip.system.TinyConfig.fir@36483.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@36484.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@36485.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@36486.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@37960.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@36501.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@36502.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@36505.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@36506.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@36514.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36525.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36526.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36527.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@36529.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@36530.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@36531.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@36532.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@36532.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@36533.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@36535.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@36536.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@36538.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@36539.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@36540.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@36541.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@36542.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36544.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36545.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36547.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36548.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@36549.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@36550.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@36551.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36552.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36553.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36554.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36555.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36556.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36557.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36558.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36559.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36560.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36561.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36562.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36563.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@36566.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36570.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@36623.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36626.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36627.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36628.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36629.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36630.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36631.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36632.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36633.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36634.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36635.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36636.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36637.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36638.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36639.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36640.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36643.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36644.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36645.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36646.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36647.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36648.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36649.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36650.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36651.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36652.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36653.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36654.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36655.8] wire _T_150; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36656.8] wire _T_151; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36657.8] wire _T_152; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36658.8] wire _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36659.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36665.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36678.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36679.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36686.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36687.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36693.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36694.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@36699.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36701.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36702.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@36707.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@36708.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36710.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36711.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@36716.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36718.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36719.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@36725.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@36809.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36811.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36812.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@36835.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@36838.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36846.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@36848.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36876.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36877.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36878.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36879.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36880.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@36882.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36884.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36885.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@36904.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36906.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36907.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@36912.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36914.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36915.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@36929.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36968.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@36977.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36980.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36981.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@37017.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@37096.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@37097.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@37098.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37100.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37101.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@37107.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@37110.8] wire _T_494; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@37142.8] wire _T_505; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37153.8] wire _T_506; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37154.8] wire _T_513; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@37173.8] wire _T_515; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37175.8] wire _T_516; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37176.8] wire _T_521; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@37190.6] wire _T_574; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@37256.8] wire _T_576; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37258.8] wire _T_577; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37259.8] wire _T_582; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@37273.6] wire _T_627; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37319.8] wire _T_628; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37320.8] wire _T_643; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@37358.6] wire _T_645; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37360.6] wire _T_646; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37361.6] wire _T_647; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@37366.6] wire _T_648; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@37367.6] wire [1:0] _T_651; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@37370.6] wire _T_652; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@37371.6] wire _T_660; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@37379.6] wire _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37390.6] wire _T_667; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37391.6] wire _T_668; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37392.6] wire _T_670; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@37394.6] wire _T_672; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37397.8] wire _T_673; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37398.8] wire _T_674; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@37403.8] wire _T_676; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37405.8] wire _T_677; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37406.8] wire _T_678; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@37411.8] wire _T_680; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37413.8] wire _T_681; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37414.8] wire _T_682; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@37419.8] wire _T_684; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37421.8] wire _T_685; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37422.8] wire _T_686; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@37427.8] wire _T_688; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37429.8] wire _T_689; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37430.8] wire _T_690; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@37436.6] wire _T_701; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@37460.8] wire _T_703; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37462.8] wire _T_704; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37463.8] wire _T_705; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@37468.8] wire _T_707; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37470.8] wire _T_708; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37471.8] wire _T_718; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@37494.6] wire _T_738; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@37535.8] wire _T_740; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37537.8] wire _T_741; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37538.8] wire _T_747; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@37553.6] wire _T_764; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@37588.6] wire _T_782; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@37624.6] wire _T_811; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@37684.4] wire [9:0] _T_816; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@37689.4] wire _T_817; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@37690.4] wire _T_818; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@37691.4] reg [9:0] _T_820; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@37693.4] reg [31:0] _RAND_0; wire [9:0] _T_822; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37695.4] wire _T_823; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37696.4] reg [2:0] _T_831; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@37707.4] reg [31:0] _RAND_1; reg [2:0] _T_832; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@37708.4] reg [31:0] _RAND_2; reg [3:0] _T_833; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@37709.4] reg [31:0] _RAND_3; reg [4:0] _T_834; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@37710.4] reg [31:0] _RAND_4; reg [31:0] _T_835; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@37711.4] reg [31:0] _RAND_5; wire _T_836; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@37712.4] wire _T_837; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@37713.4] wire _T_838; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@37715.6] wire _T_840; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37717.6] wire _T_841; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37718.6] wire _T_842; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@37723.6] wire _T_844; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37725.6] wire _T_845; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37726.6] wire _T_846; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@37731.6] wire _T_848; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37733.6] wire _T_849; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37734.6] wire _T_850; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@37739.6] wire _T_852; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37741.6] wire _T_853; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37742.6] wire _T_854; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@37747.6] wire _T_856; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37749.6] wire _T_857; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37750.6] wire _T_859; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@37757.4] wire _T_860; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@37765.4] wire [26:0] _T_862; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@37767.4] wire [11:0] _T_863; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@37768.4] wire [11:0] _T_864; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@37769.4] wire [9:0] _T_865; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@37770.4] wire _T_866; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@37771.4] reg [9:0] _T_868; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@37773.4] reg [31:0] _RAND_6; wire [9:0] _T_870; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37775.4] wire _T_871; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37776.4] reg [2:0] _T_879; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@37787.4] reg [31:0] _RAND_7; reg [1:0] _T_880; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@37788.4] reg [31:0] _RAND_8; reg [3:0] _T_881; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@37789.4] reg [31:0] _RAND_9; reg [4:0] _T_882; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@37790.4] reg [31:0] _RAND_10; reg _T_883; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@37791.4] reg [31:0] _RAND_11; reg _T_884; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@37792.4] reg [31:0] _RAND_12; wire _T_885; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@37793.4] wire _T_886; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@37794.4] wire _T_887; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@37796.6] wire _T_889; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37798.6] wire _T_890; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37799.6] wire _T_891; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@37804.6] wire _T_893; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37806.6] wire _T_894; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37807.6] wire _T_895; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@37812.6] wire _T_897; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37814.6] wire _T_898; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37815.6] wire _T_899; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@37820.6] wire _T_901; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37822.6] wire _T_902; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37823.6] wire _T_903; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@37828.6] wire _T_905; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37830.6] wire _T_906; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37831.6] wire _T_907; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@37836.6] wire _T_909; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37838.6] wire _T_910; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37839.6] wire _T_912; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@37846.4] reg [17:0] _T_913; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@37855.4] reg [31:0] _RAND_13; reg [9:0] _T_923; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@37865.4] reg [31:0] _RAND_14; wire [9:0] _T_925; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37867.4] wire _T_926; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37868.4] reg [9:0] _T_942; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@37887.4] reg [31:0] _RAND_15; wire [9:0] _T_944; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37889.4] wire _T_945; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37890.4] wire _T_955; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@37905.4] wire [31:0] _T_957; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@37908.6] wire [17:0] _T_958; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@37910.6] wire _T_959; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@37911.6] wire _T_960; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@37912.6] wire _T_962; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37914.6] wire _T_963; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37915.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@37907.4] wire _T_967; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@37926.4] wire _T_969; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@37928.4] wire _T_970; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@37929.4] wire [31:0] _T_971; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@37931.6] wire [17:0] _T_953; // @[:freechips.rocketchip.system.TinyConfig.fir@37901.4 :freechips.rocketchip.system.TinyConfig.fir@37903.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@37909.6] wire [17:0] _T_972; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@37933.6] wire [17:0] _T_973; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@37934.6] wire _T_974; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@37935.6] wire _T_976; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37937.6] wire _T_977; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37938.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@37930.4] wire [17:0] _T_964; // @[:freechips.rocketchip.system.TinyConfig.fir@37921.4 :freechips.rocketchip.system.TinyConfig.fir@37923.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@37932.6] wire _T_978; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@37944.4] wire _T_979; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@37945.4] wire _T_980; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@37946.4] wire _T_981; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@37947.4] wire _T_983; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37949.4] wire _T_984; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37950.4] wire [17:0] _T_985; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@37955.4] wire [17:0] _T_986; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@37956.4] wire [17:0] _T_987; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@37957.4] reg [31:0] _T_988; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@37959.4] reg [31:0] _RAND_16; wire _T_989; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@37962.4] wire _T_990; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@37963.4] wire _T_991; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@37964.4] wire _T_992; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@37965.4] wire _T_993; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@37966.4] wire _T_994; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@37967.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37969.4] wire _T_997; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37970.4] wire [31:0] _T_999; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@37976.4] wire _T_1002; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@37980.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36667.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@36769.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36887.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36983.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@37071.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37156.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@37239.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37322.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37400.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@37442.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@37500.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@37559.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@37594.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@37630.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@37960.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@36501.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@36502.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@36505.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@36506.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@36514.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36525.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36526.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@36527.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@36529.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@36530.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@36531.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@36532.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@36532.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@36533.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@36535.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@36536.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@36538.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@36539.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@36540.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@36541.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@36542.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36544.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36545.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36547.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36548.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@36549.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@36550.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@36551.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36552.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36553.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36554.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36555.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36556.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36557.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36558.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36559.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36560.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@36561.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@36562.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@36563.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@36566.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36570.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@36623.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36626.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36627.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36628.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36629.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36630.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36631.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36632.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36633.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36634.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36635.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36636.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36637.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36638.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36639.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36640.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36643.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36644.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36645.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36646.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36647.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36648.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36649.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36650.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@36651.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@36652.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36653.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@36654.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@36655.8] assign _T_150 = _T_124 | _T_129; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36656.8] assign _T_151 = _T_150 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36657.8] assign _T_152 = _T_151 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36658.8] assign _T_153 = _T_152 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36659.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36665.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36678.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36679.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36686.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36687.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36693.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36694.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@36699.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36701.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36702.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@36707.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@36708.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36710.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36711.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@36716.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36718.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36719.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@36725.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@36809.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36811.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36812.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@36835.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@36838.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36846.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@36848.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36876.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36877.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36878.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@36879.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36880.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@36882.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36884.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36885.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@36904.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36906.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36907.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@36912.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36914.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36915.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@36929.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@36968.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@36977.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36980.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36981.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@37017.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@37096.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@37097.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@37098.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37100.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37101.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@37107.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@37110.8] assign _T_494 = _T_462 & _T_153; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@37142.8] assign _T_505 = _T_494 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37153.8] assign _T_506 = _T_505 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37154.8] assign _T_513 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@37173.8] assign _T_515 = _T_513 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37175.8] assign _T_516 = _T_515 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37176.8] assign _T_521 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@37190.6] assign _T_574 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@37256.8] assign _T_576 = _T_574 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37258.8] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37259.8] assign _T_582 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@37273.6] assign _T_627 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37319.8] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37320.8] assign _T_643 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@37358.6] assign _T_645 = _T_643 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37360.6] assign _T_646 = _T_645 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37361.6] assign _T_647 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@37366.6] assign _T_648 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@37367.6] assign _T_651 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@37370.6] assign _T_652 = _T_651 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@37371.6] assign _T_660 = _T_651 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@37379.6] assign _T_666 = _T_647 | _T_648; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37390.6] assign _T_667 = _T_666 | _T_652; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37391.6] assign _T_668 = _T_667 | _T_660; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@37392.6] assign _T_670 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@37394.6] assign _T_672 = _T_668 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37397.8] assign _T_673 = _T_672 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37398.8] assign _T_674 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@37403.8] assign _T_676 = _T_674 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37405.8] assign _T_677 = _T_676 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37406.8] assign _T_678 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@37411.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37413.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37414.8] assign _T_682 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@37419.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37421.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37422.8] assign _T_686 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@37427.8] assign _T_688 = _T_686 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37429.8] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37430.8] assign _T_690 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@37436.6] assign _T_701 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@37460.8] assign _T_703 = _T_701 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37462.8] assign _T_704 = _T_703 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37463.8] assign _T_705 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@37468.8] assign _T_707 = _T_705 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37470.8] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37471.8] assign _T_718 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@37494.6] assign _T_738 = _T_686 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@37535.8] assign _T_740 = _T_738 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37537.8] assign _T_741 = _T_740 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37538.8] assign _T_747 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@37553.6] assign _T_764 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@37588.6] assign _T_782 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@37624.6] assign _T_811 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@37684.4] assign _T_816 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@37689.4] assign _T_817 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@37690.4] assign _T_818 = _T_817 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@37691.4] assign _T_822 = _T_820 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37695.4] assign _T_823 = _T_820 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37696.4] assign _T_836 = _T_823 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@37712.4] assign _T_837 = io_in_a_valid & _T_836; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@37713.4] assign _T_838 = io_in_a_bits_opcode == _T_831; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@37715.6] assign _T_840 = _T_838 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37717.6] assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37718.6] assign _T_842 = io_in_a_bits_param == _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@37723.6] assign _T_844 = _T_842 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37725.6] assign _T_845 = _T_844 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37726.6] assign _T_846 = io_in_a_bits_size == _T_833; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@37731.6] assign _T_848 = _T_846 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37733.6] assign _T_849 = _T_848 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37734.6] assign _T_850 = io_in_a_bits_source == _T_834; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@37739.6] assign _T_852 = _T_850 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37741.6] assign _T_853 = _T_852 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37742.6] assign _T_854 = io_in_a_bits_address == _T_835; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@37747.6] assign _T_856 = _T_854 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37749.6] assign _T_857 = _T_856 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37750.6] assign _T_859 = _T_811 & _T_823; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@37757.4] assign _T_860 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@37765.4] assign _T_862 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@37767.4] assign _T_863 = _T_862[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@37768.4] assign _T_864 = ~ _T_863; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@37769.4] assign _T_865 = _T_864[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@37770.4] assign _T_866 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@37771.4] assign _T_870 = _T_868 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37775.4] assign _T_871 = _T_868 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37776.4] assign _T_885 = _T_871 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@37793.4] assign _T_886 = io_in_d_valid & _T_885; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@37794.4] assign _T_887 = io_in_d_bits_opcode == _T_879; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@37796.6] assign _T_889 = _T_887 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37798.6] assign _T_890 = _T_889 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37799.6] assign _T_891 = io_in_d_bits_param == _T_880; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@37804.6] assign _T_893 = _T_891 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37806.6] assign _T_894 = _T_893 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37807.6] assign _T_895 = io_in_d_bits_size == _T_881; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@37812.6] assign _T_897 = _T_895 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37814.6] assign _T_898 = _T_897 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37815.6] assign _T_899 = io_in_d_bits_source == _T_882; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@37820.6] assign _T_901 = _T_899 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37822.6] assign _T_902 = _T_901 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37823.6] assign _T_903 = io_in_d_bits_sink == _T_883; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@37828.6] assign _T_905 = _T_903 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37830.6] assign _T_906 = _T_905 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37831.6] assign _T_907 = io_in_d_bits_denied == _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@37836.6] assign _T_909 = _T_907 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37838.6] assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37839.6] assign _T_912 = _T_860 & _T_871; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@37846.4] assign _T_925 = _T_923 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37867.4] assign _T_926 = _T_923 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37868.4] assign _T_944 = _T_942 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@37889.4] assign _T_945 = _T_942 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@37890.4] assign _T_955 = _T_811 & _T_926; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@37905.4] assign _T_957 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@37908.6] assign _T_958 = _T_913 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@37910.6] assign _T_959 = _T_958[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@37911.6] assign _T_960 = _T_959 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@37912.6] assign _T_962 = _T_960 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37914.6] assign _T_963 = _T_962 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37915.6] assign _GEN_15 = _T_955 ? _T_957 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@37907.4] assign _T_967 = _T_860 & _T_945; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@37926.4] assign _T_969 = _T_670 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@37928.4] assign _T_970 = _T_967 & _T_969; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@37929.4] assign _T_971 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@37931.6] assign _T_953 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@37901.4 :freechips.rocketchip.system.TinyConfig.fir@37903.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@37909.6] assign _T_972 = _T_953 | _T_913; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@37933.6] assign _T_973 = _T_972 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@37934.6] assign _T_974 = _T_973[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@37935.6] assign _T_976 = _T_974 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37937.6] assign _T_977 = _T_976 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37938.6] assign _GEN_16 = _T_970 ? _T_971 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@37930.4] assign _T_964 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@37921.4 :freechips.rocketchip.system.TinyConfig.fir@37923.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@37932.6] assign _T_978 = _T_953 != _T_964; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@37944.4] assign _T_979 = _T_953 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@37945.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@37946.4] assign _T_981 = _T_978 | _T_980; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@37947.4] assign _T_983 = _T_981 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37949.4] assign _T_984 = _T_983 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37950.4] assign _T_985 = _T_913 | _T_953; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@37955.4] assign _T_986 = ~ _T_964; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@37956.4] assign _T_987 = _T_985 & _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@37957.4] assign _T_989 = _T_913 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@37962.4] assign _T_990 = _T_989 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@37963.4] assign _T_991 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@37964.4] assign _T_992 = _T_990 | _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@37965.4] assign _T_993 = _T_988 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@37966.4] assign _T_994 = _T_992 | _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@37967.4] assign _T_996 = _T_994 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37969.4] assign _T_997 = _T_996 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37970.4] assign _T_999 = _T_988 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@37976.4] assign _T_1002 = _T_811 | _T_860; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@37980.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36667.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@36769.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36887.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36983.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@37071.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37156.10] assign _GEN_95 = io_in_a_valid & _T_521; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@37239.10] assign _GEN_105 = io_in_a_valid & _T_582; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37322.10] assign _GEN_115 = io_in_d_valid & _T_670; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37400.10] assign _GEN_125 = io_in_d_valid & _T_690; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@37442.10] assign _GEN_137 = io_in_d_valid & _T_718; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@37500.10] assign _GEN_149 = io_in_d_valid & _T_747; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@37559.10] assign _GEN_155 = io_in_d_valid & _T_764; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@37594.10] assign _GEN_161 = io_in_d_valid & _T_782; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@37630.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_820 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_831 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_832 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_833 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_834 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_835 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_868 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_879 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_880 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_881 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_882 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_883 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_884 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_913 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_923 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_942 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_988 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_820 <= 10'h0; end else begin if (_T_811) begin if (_T_823) begin if (_T_818) begin _T_820 <= _T_816; end else begin _T_820 <= 10'h0; end end else begin _T_820 <= _T_822; end end end if (_T_859) begin _T_831 <= io_in_a_bits_opcode; end if (_T_859) begin _T_832 <= io_in_a_bits_param; end if (_T_859) begin _T_833 <= io_in_a_bits_size; end if (_T_859) begin _T_834 <= io_in_a_bits_source; end if (_T_859) begin _T_835 <= io_in_a_bits_address; end if (reset) begin _T_868 <= 10'h0; end else begin if (_T_860) begin if (_T_871) begin if (_T_866) begin _T_868 <= _T_865; end else begin _T_868 <= 10'h0; end end else begin _T_868 <= _T_870; end end end if (_T_912) begin _T_879 <= io_in_d_bits_opcode; end if (_T_912) begin _T_880 <= io_in_d_bits_param; end if (_T_912) begin _T_881 <= io_in_d_bits_size; end if (_T_912) begin _T_882 <= io_in_d_bits_source; end if (_T_912) begin _T_883 <= io_in_d_bits_sink; end if (_T_912) begin _T_884 <= io_in_d_bits_denied; end if (reset) begin _T_913 <= 18'h0; end else begin _T_913 <= _T_987; end if (reset) begin _T_923 <= 10'h0; end else begin if (_T_811) begin if (_T_926) begin if (_T_818) begin _T_923 <= _T_816; end else begin _T_923 <= 10'h0; end end else begin _T_923 <= _T_925; end end end if (reset) begin _T_942 <= 10'h0; end else begin if (_T_860) begin if (_T_945) begin if (_T_866) begin _T_942 <= _T_865; end else begin _T_942 <= 10'h0; end end else begin _T_942 <= _T_944; end end end if (reset) begin _T_988 <= 32'h0; end else begin if (_T_1002) begin _T_988 <= 32'h0; end else begin _T_988 <= _T_999; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36667.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@36668.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@36674.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@36675.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36681.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@36682.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36689.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@36690.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36696.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@36697.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36704.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@36705.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36713.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@36714.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36721.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@36722.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@36769.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@36770.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@36776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@36777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@36783.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@36784.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@36791.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@36792.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@36798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@36799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@36806.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@36807.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36814.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@36815.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@36823.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@36824.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@36831.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@36832.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36887.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@36888.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@36894.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@36895.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@36901.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@36902.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36909.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@36910.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36917.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@36918.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@36925.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@36926.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36983.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@36984.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@36990.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@36991.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@36997.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@36998.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@37005.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@37006.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@37013.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@37014.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@37071.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@37072.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@37078.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@37079.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@37085.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@37086.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@37093.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@37094.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37103.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@37104.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37156.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_506) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@37157.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@37163.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@37164.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@37170.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@37171.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_516) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37178.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_516) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@37179.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@37186.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@37187.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@37239.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_506) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@37240.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@37246.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@37247.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@37253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@37254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37261.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_577) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@37262.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@37269.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@37270.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_628) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@37323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@37329.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@37330.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@37336.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@37337.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@37344.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@37345.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@37352.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@37353.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_646) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37363.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_646) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@37364.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37400.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_673) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@37401.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37408.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_677) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@37409.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37416.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_681) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@37417.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37424.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_685) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@37425.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37432.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_689) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@37433.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@37442.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_673) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@37443.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@37449.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@37450.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@37457.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_677) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@37458.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37465.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_704) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@37466.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37473.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_708) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@37474.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@37481.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_685) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@37482.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@37500.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_673) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@37501.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@37507.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@37508.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@37515.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_677) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@37516.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@37523.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_704) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@37524.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@37531.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_708) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@37532.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37540.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_741) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@37541.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@37559.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_673) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@37560.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@37567.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_681) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@37568.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@37575.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_685) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@37576.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@37594.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_673) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@37595.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@37602.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_681) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@37603.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@37611.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_741) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@37612.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@37630.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_673) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@37631.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@37638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_681) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@37639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@37646.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_685) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@37647.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_841) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37720.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_841) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@37721.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_845) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37728.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_845) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@37729.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_849) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37736.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_849) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@37737.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_853) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37744.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_853) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@37745.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_857) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37752.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_857) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@37753.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_890) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37801.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_890) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@37802.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_894) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37809.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_894) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@37810.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_898) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37817.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_898) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@37818.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_902) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37825.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_902) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@37826.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_906) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37833.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_906) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@37834.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_910) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37841.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_910) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@37842.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_955 & _T_963) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37917.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_955 & _T_963) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@37918.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_970 & _T_977) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37940.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_970 & _T_977) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@37941.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_984) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37952.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_984) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@37953.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_997) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37972.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_997) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@37973.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLAtomicAutomata_1( // @[:freechips.rocketchip.system.TinyConfig.fir@37985.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@37986.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@37987.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@37988.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] reg [1:0] _T_16_0_state; // @[AtomicAutomata.scala 76:28:freechips.rocketchip.system.TinyConfig.fir@38054.4] reg [31:0] _RAND_0; reg [2:0] _T_17_0_bits_opcode; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_1; reg [2:0] _T_17_0_bits_param; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_2; reg [3:0] _T_17_0_bits_size; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_3; reg [4:0] _T_17_0_bits_source; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_4; reg [31:0] _T_17_0_bits_address; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_5; reg [3:0] _T_17_0_bits_mask; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_6; reg [31:0] _T_17_0_bits_data; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_7; reg _T_17_0_bits_corrupt; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_8; reg [3:0] _T_17_0_lut; // @[AtomicAutomata.scala 77:24:freechips.rocketchip.system.TinyConfig.fir@38055.4] reg [31:0] _RAND_9; reg [31:0] _T_18_0_data; // @[AtomicAutomata.scala 78:24:freechips.rocketchip.system.TinyConfig.fir@38056.4] reg [31:0] _RAND_10; reg _T_18_0_denied; // @[AtomicAutomata.scala 78:24:freechips.rocketchip.system.TinyConfig.fir@38056.4] reg [31:0] _RAND_11; reg _T_18_0_corrupt; // @[AtomicAutomata.scala 78:24:freechips.rocketchip.system.TinyConfig.fir@38056.4] reg [31:0] _RAND_12; wire _T_19; // @[AtomicAutomata.scala 80:44:freechips.rocketchip.system.TinyConfig.fir@38057.4] wire _T_20; // @[AtomicAutomata.scala 81:44:freechips.rocketchip.system.TinyConfig.fir@38058.4] wire _T_21; // @[AtomicAutomata.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@38059.4] wire _T_23; // @[AtomicAutomata.scala 82:57:freechips.rocketchip.system.TinyConfig.fir@38061.4] wire _T_24; // @[AtomicAutomata.scala 83:49:freechips.rocketchip.system.TinyConfig.fir@38062.4] wire _T_26; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@38064.4] wire [31:0] _T_29; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38067.4] wire [32:0] _T_30; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38068.4] wire [32:0] _T_31; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38069.4] wire [32:0] _T_32; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38070.4] wire _T_33; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38071.4] wire _T_34; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@38072.4] wire _T_60; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@38098.4] wire [31:0] _T_62; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38100.4] wire [32:0] _T_63; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38101.4] wire [32:0] _T_64; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38102.4] wire [32:0] _T_65; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38103.4] wire _T_66; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38104.4] wire _T_67; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@38105.4] wire _T_70; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@38108.4] wire _T_119; // @[AtomicAutomata.scala 90:47:freechips.rocketchip.system.TinyConfig.fir@38157.4] wire _T_120; // @[AtomicAutomata.scala 91:47:freechips.rocketchip.system.TinyConfig.fir@38158.4] wire _T_121; // @[AtomicAutomata.scala 92:63:freechips.rocketchip.system.TinyConfig.fir@38159.4] wire _T_122; // @[AtomicAutomata.scala 92:32:freechips.rocketchip.system.TinyConfig.fir@38160.4] wire _T_136; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38174.4] wire _T_137; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38175.4] wire [1:0] _T_138; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38176.4] wire _T_139; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38177.4] wire _T_140; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38178.4] wire [1:0] _T_141; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38179.4] wire _T_142; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38180.4] wire _T_143; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38181.4] wire [1:0] _T_144; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38182.4] wire _T_145; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38183.4] wire _T_146; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38184.4] wire [1:0] _T_147; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38185.4] wire _T_148; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38186.4] wire _T_149; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38187.4] wire [1:0] _T_150; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38188.4] wire _T_151; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38189.4] wire _T_152; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38190.4] wire [1:0] _T_153; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38191.4] wire _T_154; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38192.4] wire _T_155; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38193.4] wire [1:0] _T_156; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38194.4] wire _T_157; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38195.4] wire _T_158; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38196.4] wire [1:0] _T_159; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38197.4] wire _T_160; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38198.4] wire _T_161; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38199.4] wire [1:0] _T_162; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38200.4] wire _T_163; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38201.4] wire _T_164; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38202.4] wire [1:0] _T_165; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38203.4] wire _T_166; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38204.4] wire _T_167; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38205.4] wire [1:0] _T_168; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38206.4] wire _T_169; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38207.4] wire _T_170; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38208.4] wire [1:0] _T_171; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38209.4] wire _T_172; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38210.4] wire _T_173; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38211.4] wire [1:0] _T_174; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38212.4] wire _T_175; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38213.4] wire _T_176; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38214.4] wire [1:0] _T_177; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38215.4] wire _T_178; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38216.4] wire _T_179; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38217.4] wire [1:0] _T_180; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38218.4] wire _T_181; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38219.4] wire _T_182; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38220.4] wire [1:0] _T_183; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38221.4] wire _T_184; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38222.4] wire _T_185; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38223.4] wire [1:0] _T_186; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38224.4] wire _T_187; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38225.4] wire _T_188; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38226.4] wire [1:0] _T_189; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38227.4] wire _T_190; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38228.4] wire _T_191; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38229.4] wire [1:0] _T_192; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38230.4] wire _T_193; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38231.4] wire _T_194; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38232.4] wire [1:0] _T_195; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38233.4] wire _T_196; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38234.4] wire _T_197; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38235.4] wire [1:0] _T_198; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38236.4] wire _T_199; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38237.4] wire _T_200; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38238.4] wire [1:0] _T_201; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38239.4] wire _T_202; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38240.4] wire _T_203; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38241.4] wire [1:0] _T_204; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38242.4] wire _T_205; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38243.4] wire _T_206; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38244.4] wire [1:0] _T_207; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38245.4] wire _T_208; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38246.4] wire _T_209; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38247.4] wire [1:0] _T_210; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38248.4] wire _T_211; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38249.4] wire _T_212; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38250.4] wire [1:0] _T_213; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38251.4] wire _T_214; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38252.4] wire _T_215; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38253.4] wire [1:0] _T_216; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38254.4] wire _T_217; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38255.4] wire _T_218; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38256.4] wire [1:0] _T_219; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38257.4] wire _T_220; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38258.4] wire _T_221; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38259.4] wire [1:0] _T_222; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38260.4] wire _T_223; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38261.4] wire _T_224; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38262.4] wire [1:0] _T_225; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38263.4] wire _T_226; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38264.4] wire _T_227; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38265.4] wire [1:0] _T_228; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38266.4] wire _T_229; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38267.4] wire _T_230; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38268.4] wire [1:0] _T_231; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38269.4] wire [3:0] _T_232; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38270.4] wire _T_233; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38271.4] wire [3:0] _T_234; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38272.4] wire _T_235; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38273.4] wire [3:0] _T_236; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38274.4] wire _T_237; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38275.4] wire [3:0] _T_238; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38276.4] wire _T_239; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38277.4] wire [3:0] _T_240; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38278.4] wire _T_241; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38279.4] wire [3:0] _T_242; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38280.4] wire _T_243; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38281.4] wire [3:0] _T_244; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38282.4] wire _T_245; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38283.4] wire [3:0] _T_246; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38284.4] wire _T_247; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38285.4] wire [3:0] _T_248; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38286.4] wire _T_249; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38287.4] wire [3:0] _T_250; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38288.4] wire _T_251; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38289.4] wire [3:0] _T_252; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38290.4] wire _T_253; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38291.4] wire [3:0] _T_254; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38292.4] wire _T_255; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38293.4] wire [3:0] _T_256; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38294.4] wire _T_257; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38295.4] wire [3:0] _T_258; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38296.4] wire _T_259; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38297.4] wire [3:0] _T_260; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38298.4] wire _T_261; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38299.4] wire [3:0] _T_262; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38300.4] wire _T_263; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38301.4] wire [3:0] _T_264; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38302.4] wire _T_265; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38303.4] wire [3:0] _T_266; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38304.4] wire _T_267; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38305.4] wire [3:0] _T_268; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38306.4] wire _T_269; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38307.4] wire [3:0] _T_270; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38308.4] wire _T_271; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38309.4] wire [3:0] _T_272; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38310.4] wire _T_273; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38311.4] wire [3:0] _T_274; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38312.4] wire _T_275; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38313.4] wire [3:0] _T_276; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38314.4] wire _T_277; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38315.4] wire [3:0] _T_278; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38316.4] wire _T_279; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38317.4] wire [3:0] _T_280; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38318.4] wire _T_281; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38319.4] wire [3:0] _T_282; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38320.4] wire _T_283; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38321.4] wire [3:0] _T_284; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38322.4] wire _T_285; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38323.4] wire [3:0] _T_286; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38324.4] wire _T_287; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38325.4] wire [3:0] _T_288; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38326.4] wire _T_289; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38327.4] wire [3:0] _T_290; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38328.4] wire _T_291; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38329.4] wire [3:0] _T_292; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38330.4] wire _T_293; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38331.4] wire [3:0] _T_294; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38332.4] wire _T_295; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38333.4] wire [7:0] _T_302; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38340.4] wire [15:0] _T_310; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38348.4] wire [7:0] _T_317; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38355.4] wire [31:0] _T_326; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38364.4] wire _T_327; // @[AtomicAutomata.scala 117:42:freechips.rocketchip.system.TinyConfig.fir@38365.4] wire _T_328; // @[AtomicAutomata.scala 118:42:freechips.rocketchip.system.TinyConfig.fir@38366.4] wire _T_329; // @[AtomicAutomata.scala 119:39:freechips.rocketchip.system.TinyConfig.fir@38367.4] wire [3:0] _T_330; // @[AtomicAutomata.scala 121:25:freechips.rocketchip.system.TinyConfig.fir@38368.4] wire [2:0] _T_331; // @[AtomicAutomata.scala 121:39:freechips.rocketchip.system.TinyConfig.fir@38369.4] wire [3:0] _GEN_39; // @[AtomicAutomata.scala 121:31:freechips.rocketchip.system.TinyConfig.fir@38370.4] wire [3:0] _T_332; // @[AtomicAutomata.scala 121:31:freechips.rocketchip.system.TinyConfig.fir@38370.4] wire [3:0] _T_333; // @[AtomicAutomata.scala 121:23:freechips.rocketchip.system.TinyConfig.fir@38371.4] wire [3:0] _T_340; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38378.4] wire [3:0] _T_347; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38385.4] wire [3:0] _T_348; // @[AtomicAutomata.scala 125:38:freechips.rocketchip.system.TinyConfig.fir@38386.4] wire [4:0] _T_349; // @[AtomicAutomata.scala 125:49:freechips.rocketchip.system.TinyConfig.fir@38387.4] wire [3:0] _T_350; // @[AtomicAutomata.scala 125:54:freechips.rocketchip.system.TinyConfig.fir@38388.4] wire [3:0] _T_351; // @[AtomicAutomata.scala 126:38:freechips.rocketchip.system.TinyConfig.fir@38389.4] wire [4:0] _T_352; // @[AtomicAutomata.scala 126:49:freechips.rocketchip.system.TinyConfig.fir@38390.4] wire [3:0] _T_353; // @[AtomicAutomata.scala 126:54:freechips.rocketchip.system.TinyConfig.fir@38391.4] wire [4:0] _T_354; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38392.4] wire [3:0] _T_355; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38393.4] wire [3:0] _T_356; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38394.4] wire [5:0] _T_357; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38395.4] wire [3:0] _T_358; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38396.4] wire [3:0] _T_359; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38397.4] wire _T_361; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38399.4] wire _T_362; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38400.4] wire _T_363; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38401.4] wire _T_364; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38402.4] wire [7:0] _T_366; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38404.4] wire [7:0] _T_368; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38406.4] wire [7:0] _T_370; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38408.4] wire [7:0] _T_372; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38410.4] wire [31:0] _T_375; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38413.4] wire [4:0] _T_376; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38414.4] wire [3:0] _T_377; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38415.4] wire [3:0] _T_378; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38416.4] wire [5:0] _T_379; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38417.4] wire [3:0] _T_380; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38418.4] wire [3:0] _T_381; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38419.4] wire _T_383; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38421.4] wire _T_384; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38422.4] wire _T_385; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38423.4] wire _T_386; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38424.4] wire [7:0] _T_388; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38426.4] wire [7:0] _T_390; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38428.4] wire [7:0] _T_392; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38430.4] wire [7:0] _T_394; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38432.4] wire [31:0] _T_397; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38435.4] wire _T_398; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38436.4] wire _T_399; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38437.4] wire _T_400; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38438.4] wire _T_401; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38439.4] wire [7:0] _T_403; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38441.4] wire [7:0] _T_405; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38443.4] wire [7:0] _T_407; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38445.4] wire [7:0] _T_409; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38447.4] wire [31:0] _T_412; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38450.4] wire [31:0] _T_413; // @[AtomicAutomata.scala 131:28:freechips.rocketchip.system.TinyConfig.fir@38451.4] wire [31:0] _T_414; // @[AtomicAutomata.scala 131:41:freechips.rocketchip.system.TinyConfig.fir@38452.4] wire [31:0] _T_415; // @[AtomicAutomata.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@38453.4] wire [31:0] _T_416; // @[AtomicAutomata.scala 132:41:freechips.rocketchip.system.TinyConfig.fir@38454.4] wire [31:0] _T_417; // @[AtomicAutomata.scala 133:43:freechips.rocketchip.system.TinyConfig.fir@38455.4] wire [31:0] _T_418; // @[AtomicAutomata.scala 133:26:freechips.rocketchip.system.TinyConfig.fir@38456.4] wire [31:0] _T_420; // @[AtomicAutomata.scala 134:33:freechips.rocketchip.system.TinyConfig.fir@38458.4] wire _T_421; // @[AtomicAutomata.scala 136:49:freechips.rocketchip.system.TinyConfig.fir@38459.4] wire _T_422; // @[AtomicAutomata.scala 136:38:freechips.rocketchip.system.TinyConfig.fir@38460.4] wire _T_424; // @[AtomicAutomata.scala 137:50:freechips.rocketchip.system.TinyConfig.fir@38462.4] wire _T_425; // @[AtomicAutomata.scala 137:39:freechips.rocketchip.system.TinyConfig.fir@38463.4] wire _T_426; // @[AtomicAutomata.scala 137:65:freechips.rocketchip.system.TinyConfig.fir@38464.4] wire _T_427; // @[AtomicAutomata.scala 137:55:freechips.rocketchip.system.TinyConfig.fir@38465.4] wire _T_428; // @[AtomicAutomata.scala 137:27:freechips.rocketchip.system.TinyConfig.fir@38466.4] wire _T_429; // @[AtomicAutomata.scala 138:31:freechips.rocketchip.system.TinyConfig.fir@38467.4] wire [31:0] _T_430; // @[AtomicAutomata.scala 139:50:freechips.rocketchip.system.TinyConfig.fir@38468.4] wire [31:0] _T_431; // @[AtomicAutomata.scala 139:28:freechips.rocketchip.system.TinyConfig.fir@38469.4] wire _T_432; // @[AtomicAutomata.scala 145:34:freechips.rocketchip.system.TinyConfig.fir@38470.4] wire [31:0] _T_433; // @[AtomicAutomata.scala 145:14:freechips.rocketchip.system.TinyConfig.fir@38471.4] wire _T_435; // @[AtomicAutomata.scala 149:23:freechips.rocketchip.system.TinyConfig.fir@38474.4] wire _T_436; // @[AtomicAutomata.scala 149:53:freechips.rocketchip.system.TinyConfig.fir@38475.4] wire _T_437; // @[AtomicAutomata.scala 149:35:freechips.rocketchip.system.TinyConfig.fir@38476.4] reg [9:0] _T_527; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@38585.4] reg [31:0] _RAND_13; wire _T_528; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@38586.4] wire _T_439; // @[AtomicAutomata.scala 151:38:freechips.rocketchip.system.TinyConfig.fir@38479.4] wire [1:0] _T_530; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38588.4] wire [2:0] _T_531; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38589.4] wire [1:0] _T_532; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38590.4] wire [1:0] _T_533; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38591.4] wire [2:0] _T_535; // @[Arbiter.scala 15:78:freechips.rocketchip.system.TinyConfig.fir@38593.4] wire [1:0] _T_536; // @[Arbiter.scala 15:83:freechips.rocketchip.system.TinyConfig.fir@38594.4] wire [1:0] _T_537; // @[Arbiter.scala 15:61:freechips.rocketchip.system.TinyConfig.fir@38595.4] wire _T_539; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@38597.4] reg _T_571_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@38647.4] reg [31:0] _RAND_14; wire _T_573_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@38650.4] wire _T_575; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@38653.4] wire _T_440; // @[AtomicAutomata.scala 153:15:freechips.rocketchip.system.TinyConfig.fir@38482.4] wire [2:0] _GEN_0; // @[AtomicAutomata.scala 153:31:freechips.rocketchip.system.TinyConfig.fir@38483.4] wire [2:0] _GEN_1; // @[AtomicAutomata.scala 153:31:freechips.rocketchip.system.TinyConfig.fir@38483.4] wire _T_442; // @[AtomicAutomata.scala 166:45:freechips.rocketchip.system.TinyConfig.fir@38490.4] wire _T_487; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@38541.4] wire [1:0] _T_488; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@38542.4] wire [1:0] _T_490; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@38544.4] wire _T_491; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@38545.4] wire _T_492; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38546.4] wire _T_493; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38547.4] wire _T_494; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38548.4] wire _T_496; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38550.4] wire _T_497; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38551.4] wire _T_499; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38553.4] wire _T_500; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38554.4] wire _T_501; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38555.4] wire _T_502; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38556.4] wire _T_503; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38557.4] wire _T_504; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38558.4] wire _T_505; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38559.4] wire _T_506; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38560.4] wire _T_507; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38561.4] wire _T_508; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38562.4] wire _T_509; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38563.4] wire _T_510; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38564.4] wire _T_511; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38565.4] wire _T_512; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38566.4] wire _T_513; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38567.4] wire _T_514; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38568.4] wire _T_515; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38569.4] wire [26:0] _T_520; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38578.4] wire [11:0] _T_521; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38579.4] wire [11:0] _T_522; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38580.4] wire [9:0] _T_523; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@38581.4] wire _T_524; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@38582.4] wire _T_525; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@38583.4] wire _T_529; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@38587.4] wire _T_538; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@38596.4] wire _T_541; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@38602.4] wire _T_542; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@38603.4] wire _T_545; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@38609.4] wire _T_547; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@38611.4] wire _T_550; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@38614.4] wire _T_551; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@38615.4] wire _T_554; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38618.4] wire _T_555; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38619.4] wire _T_556; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@38624.4] wire _T_557; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@38625.4] wire _T_559; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@38627.4] wire _T_561; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38629.4] wire _T_562; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38630.4] reg _T_571_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@38647.4] reg [31:0] _RAND_15; wire _T_577; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38656.4] wire _T_578; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38657.4] wire _T_579; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38658.4] wire _T_581; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@38661.4] wire _T_566; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38638.4] wire [9:0] _GEN_40; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@38639.4] wire [9:0] _T_568; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@38640.4] wire _T_572_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@38648.4] wire _T_572_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@38648.4] wire _T_573_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@38650.4] wire _T_574; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@38651.4] wire [83:0] _T_588; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38669.4] wire [83:0] _T_589; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38670.4] wire [83:0] _T_596; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38677.4] wire [83:0] _T_597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38678.4] wire [83:0] _T_598; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38679.4] wire _T_609; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38700.4] wire _T_611; // @[AtomicAutomata.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38702.4] wire [1:0] _T_612; // @[AtomicAutomata.scala 178:52:freechips.rocketchip.system.TinyConfig.fir@38707.8] wire [2:0] _GEN_41; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38708.8] wire _T_613; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38708.8] wire _T_615; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38710.8] wire _T_617; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38712.8] wire _T_619; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38714.8] wire _T_621; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38722.4] reg [9:0] _T_630; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@38736.4] reg [31:0] _RAND_16; wire _T_633; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@38739.4] wire _T_645; // @[AtomicAutomata.scala 212:40:freechips.rocketchip.system.TinyConfig.fir@38754.4] wire _T_651; // @[AtomicAutomata.scala 231:30:freechips.rocketchip.system.TinyConfig.fir@38770.4] wire _T_641; // @[AtomicAutomata.scala 203:53:freechips.rocketchip.system.TinyConfig.fir@38750.4] wire _T_642; // @[AtomicAutomata.scala 204:83:freechips.rocketchip.system.TinyConfig.fir@38751.4] wire _T_652; // @[AtomicAutomata.scala 231:40:freechips.rocketchip.system.TinyConfig.fir@38771.4] wire _T_657; // @[AtomicAutomata.scala 235:35:freechips.rocketchip.system.TinyConfig.fir@38777.4] wire _T_622; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38728.4] wire [26:0] _T_624; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38730.4] wire [11:0] _T_625; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38731.4] wire [11:0] _T_626; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38732.4] wire [9:0] _T_627; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@38733.4] wire _T_628; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@38734.4] wire [9:0] _T_632; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@38738.4] wire _T_646; // @[AtomicAutomata.scala 213:40:freechips.rocketchip.system.TinyConfig.fir@38755.4] wire _T_648; // @[AtomicAutomata.scala 215:28:freechips.rocketchip.system.TinyConfig.fir@38757.4] wire _T_649; // @[AtomicAutomata.scala 217:22:freechips.rocketchip.system.TinyConfig.fir@38759.6] wire _T_653; // @[AtomicAutomata.scala 232:33:freechips.rocketchip.system.TinyConfig.fir@38772.4] wire _T_654; // @[AtomicAutomata.scala 232:42:freechips.rocketchip.system.TinyConfig.fir@38773.4] wire _T_655; // @[AtomicAutomata.scala 234:38:freechips.rocketchip.system.TinyConfig.fir@38774.4] wire _T_658; // @[AtomicAutomata.scala 241:46:freechips.rocketchip.system.TinyConfig.fir@38783.6] wire _T_659; // @[AtomicAutomata.scala 242:46:freechips.rocketchip.system.TinyConfig.fir@38785.6] TLMonitor_18 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@37995.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign _T_19 = _T_16_0_state == 2'h0; // @[AtomicAutomata.scala 80:44:freechips.rocketchip.system.TinyConfig.fir@38057.4] assign _T_20 = _T_16_0_state == 2'h2; // @[AtomicAutomata.scala 81:44:freechips.rocketchip.system.TinyConfig.fir@38058.4] assign _T_21 = _T_16_0_state == 2'h3; // @[AtomicAutomata.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@38059.4] assign _T_23 = _T_21 | _T_20; // @[AtomicAutomata.scala 82:57:freechips.rocketchip.system.TinyConfig.fir@38061.4] assign _T_24 = _T_16_0_state != 2'h0; // @[AtomicAutomata.scala 83:49:freechips.rocketchip.system.TinyConfig.fir@38062.4] assign _T_26 = auto_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@38064.4] assign _T_29 = auto_in_a_bits_address ^ 32'h2000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38067.4] assign _T_30 = {1'b0,$signed(_T_29)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38068.4] assign _T_31 = $signed(_T_30) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38069.4] assign _T_32 = $signed(_T_31); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38070.4] assign _T_33 = $signed(_T_32) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38071.4] assign _T_34 = _T_26 & _T_33; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@38072.4] assign _T_60 = 4'h2 == auto_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@38098.4] assign _T_62 = auto_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38100.4] assign _T_63 = {1'b0,$signed(_T_62)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38101.4] assign _T_64 = $signed(_T_63) & $signed(33'sh8a012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38102.4] assign _T_65 = $signed(_T_64); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38103.4] assign _T_66 = $signed(_T_65) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38104.4] assign _T_67 = _T_60 & _T_66; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@38105.4] assign _T_70 = _T_34 | _T_67; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@38108.4] assign _T_119 = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 90:47:freechips.rocketchip.system.TinyConfig.fir@38157.4] assign _T_120 = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 91:47:freechips.rocketchip.system.TinyConfig.fir@38158.4] assign _T_121 = _T_120 ? _T_70 : 1'h1; // @[AtomicAutomata.scala 92:63:freechips.rocketchip.system.TinyConfig.fir@38159.4] assign _T_122 = _T_119 ? _T_70 : _T_121; // @[AtomicAutomata.scala 92:32:freechips.rocketchip.system.TinyConfig.fir@38160.4] assign _T_136 = _T_17_0_bits_data[0]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38174.4] assign _T_137 = _T_18_0_data[0]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38175.4] assign _T_138 = {_T_136,_T_137}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38176.4] assign _T_139 = _T_17_0_bits_data[1]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38177.4] assign _T_140 = _T_18_0_data[1]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38178.4] assign _T_141 = {_T_139,_T_140}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38179.4] assign _T_142 = _T_17_0_bits_data[2]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38180.4] assign _T_143 = _T_18_0_data[2]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38181.4] assign _T_144 = {_T_142,_T_143}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38182.4] assign _T_145 = _T_17_0_bits_data[3]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38183.4] assign _T_146 = _T_18_0_data[3]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38184.4] assign _T_147 = {_T_145,_T_146}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38185.4] assign _T_148 = _T_17_0_bits_data[4]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38186.4] assign _T_149 = _T_18_0_data[4]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38187.4] assign _T_150 = {_T_148,_T_149}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38188.4] assign _T_151 = _T_17_0_bits_data[5]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38189.4] assign _T_152 = _T_18_0_data[5]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38190.4] assign _T_153 = {_T_151,_T_152}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38191.4] assign _T_154 = _T_17_0_bits_data[6]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38192.4] assign _T_155 = _T_18_0_data[6]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38193.4] assign _T_156 = {_T_154,_T_155}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38194.4] assign _T_157 = _T_17_0_bits_data[7]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38195.4] assign _T_158 = _T_18_0_data[7]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38196.4] assign _T_159 = {_T_157,_T_158}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38197.4] assign _T_160 = _T_17_0_bits_data[8]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38198.4] assign _T_161 = _T_18_0_data[8]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38199.4] assign _T_162 = {_T_160,_T_161}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38200.4] assign _T_163 = _T_17_0_bits_data[9]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38201.4] assign _T_164 = _T_18_0_data[9]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38202.4] assign _T_165 = {_T_163,_T_164}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38203.4] assign _T_166 = _T_17_0_bits_data[10]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38204.4] assign _T_167 = _T_18_0_data[10]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38205.4] assign _T_168 = {_T_166,_T_167}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38206.4] assign _T_169 = _T_17_0_bits_data[11]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38207.4] assign _T_170 = _T_18_0_data[11]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38208.4] assign _T_171 = {_T_169,_T_170}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38209.4] assign _T_172 = _T_17_0_bits_data[12]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38210.4] assign _T_173 = _T_18_0_data[12]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38211.4] assign _T_174 = {_T_172,_T_173}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38212.4] assign _T_175 = _T_17_0_bits_data[13]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38213.4] assign _T_176 = _T_18_0_data[13]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38214.4] assign _T_177 = {_T_175,_T_176}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38215.4] assign _T_178 = _T_17_0_bits_data[14]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38216.4] assign _T_179 = _T_18_0_data[14]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38217.4] assign _T_180 = {_T_178,_T_179}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38218.4] assign _T_181 = _T_17_0_bits_data[15]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38219.4] assign _T_182 = _T_18_0_data[15]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38220.4] assign _T_183 = {_T_181,_T_182}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38221.4] assign _T_184 = _T_17_0_bits_data[16]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38222.4] assign _T_185 = _T_18_0_data[16]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38223.4] assign _T_186 = {_T_184,_T_185}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38224.4] assign _T_187 = _T_17_0_bits_data[17]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38225.4] assign _T_188 = _T_18_0_data[17]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38226.4] assign _T_189 = {_T_187,_T_188}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38227.4] assign _T_190 = _T_17_0_bits_data[18]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38228.4] assign _T_191 = _T_18_0_data[18]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38229.4] assign _T_192 = {_T_190,_T_191}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38230.4] assign _T_193 = _T_17_0_bits_data[19]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38231.4] assign _T_194 = _T_18_0_data[19]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38232.4] assign _T_195 = {_T_193,_T_194}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38233.4] assign _T_196 = _T_17_0_bits_data[20]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38234.4] assign _T_197 = _T_18_0_data[20]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38235.4] assign _T_198 = {_T_196,_T_197}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38236.4] assign _T_199 = _T_17_0_bits_data[21]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38237.4] assign _T_200 = _T_18_0_data[21]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38238.4] assign _T_201 = {_T_199,_T_200}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38239.4] assign _T_202 = _T_17_0_bits_data[22]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38240.4] assign _T_203 = _T_18_0_data[22]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38241.4] assign _T_204 = {_T_202,_T_203}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38242.4] assign _T_205 = _T_17_0_bits_data[23]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38243.4] assign _T_206 = _T_18_0_data[23]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38244.4] assign _T_207 = {_T_205,_T_206}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38245.4] assign _T_208 = _T_17_0_bits_data[24]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38246.4] assign _T_209 = _T_18_0_data[24]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38247.4] assign _T_210 = {_T_208,_T_209}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38248.4] assign _T_211 = _T_17_0_bits_data[25]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38249.4] assign _T_212 = _T_18_0_data[25]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38250.4] assign _T_213 = {_T_211,_T_212}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38251.4] assign _T_214 = _T_17_0_bits_data[26]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38252.4] assign _T_215 = _T_18_0_data[26]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38253.4] assign _T_216 = {_T_214,_T_215}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38254.4] assign _T_217 = _T_17_0_bits_data[27]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38255.4] assign _T_218 = _T_18_0_data[27]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38256.4] assign _T_219 = {_T_217,_T_218}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38257.4] assign _T_220 = _T_17_0_bits_data[28]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38258.4] assign _T_221 = _T_18_0_data[28]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38259.4] assign _T_222 = {_T_220,_T_221}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38260.4] assign _T_223 = _T_17_0_bits_data[29]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38261.4] assign _T_224 = _T_18_0_data[29]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38262.4] assign _T_225 = {_T_223,_T_224}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38263.4] assign _T_226 = _T_17_0_bits_data[30]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38264.4] assign _T_227 = _T_18_0_data[30]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38265.4] assign _T_228 = {_T_226,_T_227}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38266.4] assign _T_229 = _T_17_0_bits_data[31]; // @[AtomicAutomata.scala 113:63:freechips.rocketchip.system.TinyConfig.fir@38267.4] assign _T_230 = _T_18_0_data[31]; // @[AtomicAutomata.scala 113:73:freechips.rocketchip.system.TinyConfig.fir@38268.4] assign _T_231 = {_T_229,_T_230}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38269.4] assign _T_232 = _T_17_0_lut >> _T_138; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38270.4] assign _T_233 = _T_232[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38271.4] assign _T_234 = _T_17_0_lut >> _T_141; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38272.4] assign _T_235 = _T_234[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38273.4] assign _T_236 = _T_17_0_lut >> _T_144; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38274.4] assign _T_237 = _T_236[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38275.4] assign _T_238 = _T_17_0_lut >> _T_147; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38276.4] assign _T_239 = _T_238[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38277.4] assign _T_240 = _T_17_0_lut >> _T_150; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38278.4] assign _T_241 = _T_240[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38279.4] assign _T_242 = _T_17_0_lut >> _T_153; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38280.4] assign _T_243 = _T_242[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38281.4] assign _T_244 = _T_17_0_lut >> _T_156; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38282.4] assign _T_245 = _T_244[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38283.4] assign _T_246 = _T_17_0_lut >> _T_159; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38284.4] assign _T_247 = _T_246[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38285.4] assign _T_248 = _T_17_0_lut >> _T_162; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38286.4] assign _T_249 = _T_248[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38287.4] assign _T_250 = _T_17_0_lut >> _T_165; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38288.4] assign _T_251 = _T_250[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38289.4] assign _T_252 = _T_17_0_lut >> _T_168; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38290.4] assign _T_253 = _T_252[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38291.4] assign _T_254 = _T_17_0_lut >> _T_171; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38292.4] assign _T_255 = _T_254[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38293.4] assign _T_256 = _T_17_0_lut >> _T_174; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38294.4] assign _T_257 = _T_256[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38295.4] assign _T_258 = _T_17_0_lut >> _T_177; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38296.4] assign _T_259 = _T_258[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38297.4] assign _T_260 = _T_17_0_lut >> _T_180; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38298.4] assign _T_261 = _T_260[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38299.4] assign _T_262 = _T_17_0_lut >> _T_183; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38300.4] assign _T_263 = _T_262[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38301.4] assign _T_264 = _T_17_0_lut >> _T_186; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38302.4] assign _T_265 = _T_264[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38303.4] assign _T_266 = _T_17_0_lut >> _T_189; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38304.4] assign _T_267 = _T_266[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38305.4] assign _T_268 = _T_17_0_lut >> _T_192; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38306.4] assign _T_269 = _T_268[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38307.4] assign _T_270 = _T_17_0_lut >> _T_195; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38308.4] assign _T_271 = _T_270[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38309.4] assign _T_272 = _T_17_0_lut >> _T_198; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38310.4] assign _T_273 = _T_272[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38311.4] assign _T_274 = _T_17_0_lut >> _T_201; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38312.4] assign _T_275 = _T_274[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38313.4] assign _T_276 = _T_17_0_lut >> _T_204; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38314.4] assign _T_277 = _T_276[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38315.4] assign _T_278 = _T_17_0_lut >> _T_207; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38316.4] assign _T_279 = _T_278[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38317.4] assign _T_280 = _T_17_0_lut >> _T_210; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38318.4] assign _T_281 = _T_280[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38319.4] assign _T_282 = _T_17_0_lut >> _T_213; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38320.4] assign _T_283 = _T_282[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38321.4] assign _T_284 = _T_17_0_lut >> _T_216; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38322.4] assign _T_285 = _T_284[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38323.4] assign _T_286 = _T_17_0_lut >> _T_219; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38324.4] assign _T_287 = _T_286[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38325.4] assign _T_288 = _T_17_0_lut >> _T_222; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38326.4] assign _T_289 = _T_288[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38327.4] assign _T_290 = _T_17_0_lut >> _T_225; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38328.4] assign _T_291 = _T_290[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38329.4] assign _T_292 = _T_17_0_lut >> _T_228; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38330.4] assign _T_293 = _T_292[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38331.4] assign _T_294 = _T_17_0_lut >> _T_231; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38332.4] assign _T_295 = _T_294[0]; // @[AtomicAutomata.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@38333.4] assign _T_302 = {_T_247,_T_245,_T_243,_T_241,_T_239,_T_237,_T_235,_T_233}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38340.4] assign _T_310 = {_T_263,_T_261,_T_259,_T_257,_T_255,_T_253,_T_251,_T_249,_T_302}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38348.4] assign _T_317 = {_T_279,_T_277,_T_275,_T_273,_T_271,_T_269,_T_267,_T_265}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38355.4] assign _T_326 = {_T_295,_T_293,_T_291,_T_289,_T_287,_T_285,_T_283,_T_281,_T_317,_T_310}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38364.4] assign _T_327 = _T_17_0_bits_param[1]; // @[AtomicAutomata.scala 117:42:freechips.rocketchip.system.TinyConfig.fir@38365.4] assign _T_328 = _T_17_0_bits_param[0]; // @[AtomicAutomata.scala 118:42:freechips.rocketchip.system.TinyConfig.fir@38366.4] assign _T_329 = _T_17_0_bits_param[2]; // @[AtomicAutomata.scala 119:39:freechips.rocketchip.system.TinyConfig.fir@38367.4] assign _T_330 = ~ _T_17_0_bits_mask; // @[AtomicAutomata.scala 121:25:freechips.rocketchip.system.TinyConfig.fir@38368.4] assign _T_331 = _T_17_0_bits_mask[3:1]; // @[AtomicAutomata.scala 121:39:freechips.rocketchip.system.TinyConfig.fir@38369.4] assign _GEN_39 = {{1'd0}, _T_331}; // @[AtomicAutomata.scala 121:31:freechips.rocketchip.system.TinyConfig.fir@38370.4] assign _T_332 = _T_330 | _GEN_39; // @[AtomicAutomata.scala 121:31:freechips.rocketchip.system.TinyConfig.fir@38370.4] assign _T_333 = ~ _T_332; // @[AtomicAutomata.scala 121:23:freechips.rocketchip.system.TinyConfig.fir@38371.4] assign _T_340 = {_T_229,_T_205,_T_181,_T_157}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38378.4] assign _T_347 = {_T_230,_T_206,_T_182,_T_158}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38385.4] assign _T_348 = _T_340 & _T_333; // @[AtomicAutomata.scala 125:38:freechips.rocketchip.system.TinyConfig.fir@38386.4] assign _T_349 = {_T_348, 1'h0}; // @[AtomicAutomata.scala 125:49:freechips.rocketchip.system.TinyConfig.fir@38387.4] assign _T_350 = _T_349[3:0]; // @[AtomicAutomata.scala 125:54:freechips.rocketchip.system.TinyConfig.fir@38388.4] assign _T_351 = _T_347 & _T_333; // @[AtomicAutomata.scala 126:38:freechips.rocketchip.system.TinyConfig.fir@38389.4] assign _T_352 = {_T_351, 1'h0}; // @[AtomicAutomata.scala 126:49:freechips.rocketchip.system.TinyConfig.fir@38390.4] assign _T_353 = _T_352[3:0]; // @[AtomicAutomata.scala 126:54:freechips.rocketchip.system.TinyConfig.fir@38391.4] assign _T_354 = {_T_350, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38392.4] assign _T_355 = _T_354[3:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38393.4] assign _T_356 = _T_350 | _T_355; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38394.4] assign _T_357 = {_T_356, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38395.4] assign _T_358 = _T_357[3:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38396.4] assign _T_359 = _T_356 | _T_358; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38397.4] assign _T_361 = _T_359[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38399.4] assign _T_362 = _T_359[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38400.4] assign _T_363 = _T_359[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38401.4] assign _T_364 = _T_359[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38402.4] assign _T_366 = _T_361 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38404.4] assign _T_368 = _T_362 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38406.4] assign _T_370 = _T_363 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38408.4] assign _T_372 = _T_364 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38410.4] assign _T_375 = {_T_372,_T_370,_T_368,_T_366}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38413.4] assign _T_376 = {_T_353, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38414.4] assign _T_377 = _T_376[3:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38415.4] assign _T_378 = _T_353 | _T_377; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38416.4] assign _T_379 = {_T_378, 2'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38417.4] assign _T_380 = _T_379[3:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38418.4] assign _T_381 = _T_378 | _T_380; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38419.4] assign _T_383 = _T_381[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38421.4] assign _T_384 = _T_381[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38422.4] assign _T_385 = _T_381[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38423.4] assign _T_386 = _T_381[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38424.4] assign _T_388 = _T_383 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38426.4] assign _T_390 = _T_384 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38428.4] assign _T_392 = _T_385 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38430.4] assign _T_394 = _T_386 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38432.4] assign _T_397 = {_T_394,_T_392,_T_390,_T_388}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38435.4] assign _T_398 = _T_17_0_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38436.4] assign _T_399 = _T_17_0_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38437.4] assign _T_400 = _T_17_0_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38438.4] assign _T_401 = _T_17_0_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@38439.4] assign _T_403 = _T_398 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38441.4] assign _T_405 = _T_399 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38443.4] assign _T_407 = _T_400 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38445.4] assign _T_409 = _T_401 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@38447.4] assign _T_412 = {_T_409,_T_407,_T_405,_T_403}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38450.4] assign _T_413 = _T_17_0_bits_data & _T_412; // @[AtomicAutomata.scala 131:28:freechips.rocketchip.system.TinyConfig.fir@38451.4] assign _T_414 = _T_413 | _T_375; // @[AtomicAutomata.scala 131:41:freechips.rocketchip.system.TinyConfig.fir@38452.4] assign _T_415 = _T_18_0_data & _T_412; // @[AtomicAutomata.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@38453.4] assign _T_416 = _T_415 | _T_397; // @[AtomicAutomata.scala 132:41:freechips.rocketchip.system.TinyConfig.fir@38454.4] assign _T_417 = ~ _T_416; // @[AtomicAutomata.scala 133:43:freechips.rocketchip.system.TinyConfig.fir@38455.4] assign _T_418 = _T_329 ? _T_416 : _T_417; // @[AtomicAutomata.scala 133:26:freechips.rocketchip.system.TinyConfig.fir@38456.4] assign _T_420 = _T_414 + _T_418; // @[AtomicAutomata.scala 134:33:freechips.rocketchip.system.TinyConfig.fir@38458.4] assign _T_421 = _T_414[31]; // @[AtomicAutomata.scala 136:49:freechips.rocketchip.system.TinyConfig.fir@38459.4] assign _T_422 = _T_327 == _T_421; // @[AtomicAutomata.scala 136:38:freechips.rocketchip.system.TinyConfig.fir@38460.4] assign _T_424 = _T_416[31]; // @[AtomicAutomata.scala 137:50:freechips.rocketchip.system.TinyConfig.fir@38462.4] assign _T_425 = _T_421 == _T_424; // @[AtomicAutomata.scala 137:39:freechips.rocketchip.system.TinyConfig.fir@38463.4] assign _T_426 = _T_420[31]; // @[AtomicAutomata.scala 137:65:freechips.rocketchip.system.TinyConfig.fir@38464.4] assign _T_427 = _T_426 == 1'h0; // @[AtomicAutomata.scala 137:55:freechips.rocketchip.system.TinyConfig.fir@38465.4] assign _T_428 = _T_425 ? _T_427 : _T_422; // @[AtomicAutomata.scala 137:27:freechips.rocketchip.system.TinyConfig.fir@38466.4] assign _T_429 = _T_328 == _T_428; // @[AtomicAutomata.scala 138:31:freechips.rocketchip.system.TinyConfig.fir@38467.4] assign _T_430 = _T_429 ? _T_17_0_bits_data : _T_18_0_data; // @[AtomicAutomata.scala 139:50:freechips.rocketchip.system.TinyConfig.fir@38468.4] assign _T_431 = _T_329 ? _T_420 : _T_430; // @[AtomicAutomata.scala 139:28:freechips.rocketchip.system.TinyConfig.fir@38469.4] assign _T_432 = _T_17_0_bits_opcode[0]; // @[AtomicAutomata.scala 145:34:freechips.rocketchip.system.TinyConfig.fir@38470.4] assign _T_433 = _T_432 ? _T_326 : _T_431; // @[AtomicAutomata.scala 145:14:freechips.rocketchip.system.TinyConfig.fir@38471.4] assign _T_435 = _T_23 == 1'h0; // @[AtomicAutomata.scala 149:23:freechips.rocketchip.system.TinyConfig.fir@38474.4] assign _T_436 = _T_122 | _T_19; // @[AtomicAutomata.scala 149:53:freechips.rocketchip.system.TinyConfig.fir@38475.4] assign _T_437 = _T_435 & _T_436; // @[AtomicAutomata.scala 149:35:freechips.rocketchip.system.TinyConfig.fir@38476.4] assign _T_528 = _T_527 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@38586.4] assign _T_439 = auto_in_a_valid & _T_437; // @[AtomicAutomata.scala 151:38:freechips.rocketchip.system.TinyConfig.fir@38479.4] assign _T_530 = {_T_439,_T_20}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38588.4] assign _T_531 = {_T_530, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@38589.4] assign _T_532 = _T_531[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@38590.4] assign _T_533 = _T_530 | _T_532; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@38591.4] assign _T_535 = {_T_533, 1'h0}; // @[Arbiter.scala 15:78:freechips.rocketchip.system.TinyConfig.fir@38593.4] assign _T_536 = _T_535[1:0]; // @[Arbiter.scala 15:83:freechips.rocketchip.system.TinyConfig.fir@38594.4] assign _T_537 = ~ _T_536; // @[Arbiter.scala 15:61:freechips.rocketchip.system.TinyConfig.fir@38595.4] assign _T_539 = _T_537[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@38597.4] assign _T_573_1 = _T_528 ? _T_539 : _T_571_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@38650.4] assign _T_575 = auto_out_a_ready & _T_573_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@38653.4] assign _T_440 = _T_122 == 1'h0; // @[AtomicAutomata.scala 153:15:freechips.rocketchip.system.TinyConfig.fir@38482.4] assign _GEN_0 = _T_440 ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 153:31:freechips.rocketchip.system.TinyConfig.fir@38483.4] assign _GEN_1 = _T_440 ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 153:31:freechips.rocketchip.system.TinyConfig.fir@38483.4] assign _T_442 = _T_17_0_bits_corrupt | _T_18_0_corrupt; // @[AtomicAutomata.scala 166:45:freechips.rocketchip.system.TinyConfig.fir@38490.4] assign _T_487 = _T_17_0_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@38541.4] assign _T_488 = 2'h1 << _T_487; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@38542.4] assign _T_490 = _T_488 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@38544.4] assign _T_491 = _T_17_0_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@38545.4] assign _T_492 = _T_490[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38546.4] assign _T_493 = _T_17_0_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38547.4] assign _T_494 = _T_493 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38548.4] assign _T_496 = _T_492 & _T_494; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38550.4] assign _T_497 = _T_491 | _T_496; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38551.4] assign _T_499 = _T_492 & _T_493; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38553.4] assign _T_500 = _T_491 | _T_499; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38554.4] assign _T_501 = _T_490[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38555.4] assign _T_502 = _T_17_0_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38556.4] assign _T_503 = _T_502 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38557.4] assign _T_504 = _T_494 & _T_503; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38558.4] assign _T_505 = _T_501 & _T_504; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38559.4] assign _T_506 = _T_497 | _T_505; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38560.4] assign _T_507 = _T_494 & _T_502; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38561.4] assign _T_508 = _T_501 & _T_507; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38562.4] assign _T_509 = _T_497 | _T_508; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38563.4] assign _T_510 = _T_493 & _T_503; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38564.4] assign _T_511 = _T_501 & _T_510; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38565.4] assign _T_512 = _T_500 | _T_511; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38566.4] assign _T_513 = _T_493 & _T_502; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38567.4] assign _T_514 = _T_501 & _T_513; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38568.4] assign _T_515 = _T_500 | _T_514; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38569.4] assign _T_520 = 27'hfff << auto_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38578.4] assign _T_521 = _T_520[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38579.4] assign _T_522 = ~ _T_521; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38580.4] assign _T_523 = _T_522[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@38581.4] assign _T_524 = auto_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@38582.4] assign _T_525 = _T_524 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@38583.4] assign _T_529 = _T_528 & auto_out_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@38587.4] assign _T_538 = _T_537[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@38596.4] assign _T_541 = _T_538 & _T_20; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@38602.4] assign _T_542 = _T_539 & _T_439; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@38603.4] assign _T_545 = _T_541 | _T_542; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@38609.4] assign _T_547 = _T_541 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@38611.4] assign _T_550 = _T_542 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@38614.4] assign _T_551 = _T_547 | _T_550; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@38615.4] assign _T_554 = _T_551 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38618.4] assign _T_555 = _T_554 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38619.4] assign _T_556 = _T_20 | _T_439; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@38624.4] assign _T_557 = _T_556 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@38625.4] assign _T_559 = _T_557 | _T_545; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@38627.4] assign _T_561 = _T_559 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38629.4] assign _T_562 = _T_561 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38630.4] assign _T_577 = _T_571_0 ? _T_20 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38656.4] assign _T_578 = _T_571_1 ? _T_439 : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38657.4] assign _T_579 = _T_577 | _T_578; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38658.4] assign _T_581 = _T_528 ? _T_556 : _T_579; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@38661.4] assign _T_566 = auto_out_a_ready & _T_581; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38638.4] assign _GEN_40 = {{9'd0}, _T_566}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@38639.4] assign _T_568 = _T_527 - _GEN_40; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@38640.4] assign _T_572_0 = _T_528 ? _T_541 : _T_571_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@38648.4] assign _T_572_1 = _T_528 ? _T_542 : _T_571_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@38648.4] assign _T_573_0 = _T_528 ? _T_538 : _T_571_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@38650.4] assign _T_574 = auto_out_a_ready & _T_573_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.TinyConfig.fir@38651.4] assign _T_588 = {6'h0,_T_17_0_bits_size,_T_17_0_bits_source,_T_17_0_bits_address,_T_515,_T_512,_T_509,_T_506,_T_433,_T_442}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38669.4] assign _T_589 = _T_572_0 ? _T_588 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38670.4] assign _T_596 = {_GEN_0,_GEN_1,auto_in_a_bits_size,auto_in_a_bits_source,auto_in_a_bits_address,auto_in_a_bits_mask,auto_in_a_bits_data,auto_in_a_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38677.4] assign _T_597 = _T_572_1 ? _T_596 : 84'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38678.4] assign _T_598 = _T_589 | _T_597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@38679.4] assign _T_609 = _T_575 & _T_439; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38700.4] assign _T_611 = _T_609 & _T_440; // @[AtomicAutomata.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38702.4] assign _T_612 = auto_in_a_bits_param[1:0]; // @[AtomicAutomata.scala 178:52:freechips.rocketchip.system.TinyConfig.fir@38707.8] assign _GEN_41 = {{1'd0}, _T_612}; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38708.8] assign _T_613 = 3'h3 == _GEN_41; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38708.8] assign _T_615 = 3'h0 == _GEN_41; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38710.8] assign _T_617 = 3'h1 == _GEN_41; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38712.8] assign _T_619 = 3'h2 == _GEN_41; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@38714.8] assign _T_621 = _T_574 & _T_20; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38722.4] assign _T_633 = _T_630 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@38739.4] assign _T_645 = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 212:40:freechips.rocketchip.system.TinyConfig.fir@38754.4] assign _T_651 = _T_633 & _T_645; // @[AtomicAutomata.scala 231:30:freechips.rocketchip.system.TinyConfig.fir@38770.4] assign _T_641 = _T_17_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 203:53:freechips.rocketchip.system.TinyConfig.fir@38750.4] assign _T_642 = _T_641 & _T_24; // @[AtomicAutomata.scala 204:83:freechips.rocketchip.system.TinyConfig.fir@38751.4] assign _T_652 = _T_651 & _T_642; // @[AtomicAutomata.scala 231:40:freechips.rocketchip.system.TinyConfig.fir@38771.4] assign _T_657 = auto_in_d_ready | _T_652; // @[AtomicAutomata.scala 235:35:freechips.rocketchip.system.TinyConfig.fir@38777.4] assign _T_622 = _T_657 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@38728.4] assign _T_624 = 27'hfff << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38730.4] assign _T_625 = _T_624[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38731.4] assign _T_626 = ~ _T_625; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38732.4] assign _T_627 = _T_626[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@38733.4] assign _T_628 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@38734.4] assign _T_632 = _T_630 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@38738.4] assign _T_646 = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 213:40:freechips.rocketchip.system.TinyConfig.fir@38755.4] assign _T_648 = _T_622 & _T_633; // @[AtomicAutomata.scala 215:28:freechips.rocketchip.system.TinyConfig.fir@38757.4] assign _T_649 = _T_642 & _T_645; // @[AtomicAutomata.scala 217:22:freechips.rocketchip.system.TinyConfig.fir@38759.6] assign _T_653 = _T_633 & _T_646; // @[AtomicAutomata.scala 232:33:freechips.rocketchip.system.TinyConfig.fir@38772.4] assign _T_654 = _T_653 & _T_642; // @[AtomicAutomata.scala 232:42:freechips.rocketchip.system.TinyConfig.fir@38773.4] assign _T_655 = _T_652 == 1'h0; // @[AtomicAutomata.scala 234:38:freechips.rocketchip.system.TinyConfig.fir@38774.4] assign _T_658 = _T_18_0_corrupt | auto_out_d_bits_denied; // @[AtomicAutomata.scala 241:46:freechips.rocketchip.system.TinyConfig.fir@38783.6] assign _T_659 = _T_18_0_denied | auto_out_d_bits_denied; // @[AtomicAutomata.scala 242:46:freechips.rocketchip.system.TinyConfig.fir@38785.6] assign auto_in_a_ready = _T_575 & _T_437; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_valid = auto_out_d_valid & _T_655; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_opcode = _T_654 ? 3'h1 : auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_denied = _T_654 ? _T_659 : auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_data = _T_654 ? _T_18_0_data : auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_in_d_bits_corrupt = _T_654 ? _T_658 : auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@38047.4] assign auto_out_a_valid = _T_528 ? _T_556 : _T_579; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_opcode = _T_598[83:81]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_param = _T_598[80:78]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_size = _T_598[77:74]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_source = _T_598[73:69]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_address = _T_598[68:37]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_mask = _T_598[36:33]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_data = _T_598[32:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_a_bits_corrupt = _T_598[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign auto_out_d_ready = auto_in_d_ready | _T_652; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@38046.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@37997.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@37998.4] assign TLMonitor_io_in_a_ready = _T_575 & _T_437; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_655; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_opcode = _T_654 ? 3'h1 : auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_denied = _T_654 ? _T_659 : auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] assign TLMonitor_io_in_d_bits_corrupt = _T_654 ? _T_658 : auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@38043.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_16_0_state = _RAND_0[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_17_0_bits_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_17_0_bits_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_17_0_bits_size = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_17_0_bits_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_17_0_bits_address = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_17_0_bits_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_17_0_bits_data = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_17_0_bits_corrupt = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_17_0_lut = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_18_0_data = _RAND_10[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_18_0_denied = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_18_0_corrupt = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_527 = _RAND_13[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_571_1 = _RAND_14[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_571_0 = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_630 = _RAND_16[9:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_16_0_state <= 2'h0; end else begin if (_T_648) begin if (_T_642) begin if (_T_645) begin _T_16_0_state <= 2'h2; end else begin _T_16_0_state <= 2'h0; end end else begin if (_T_621) begin if (_T_20) begin _T_16_0_state <= 2'h1; end else begin if (_T_611) begin if (_T_19) begin _T_16_0_state <= 2'h3; end end end end else begin if (_T_611) begin if (_T_19) begin _T_16_0_state <= 2'h3; end end end end end else begin if (_T_621) begin if (_T_20) begin _T_16_0_state <= 2'h1; end else begin if (_T_611) begin if (_T_19) begin _T_16_0_state <= 2'h3; end end end end else begin if (_T_611) begin if (_T_19) begin _T_16_0_state <= 2'h3; end end end end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_opcode <= auto_in_a_bits_opcode; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_param <= auto_in_a_bits_param; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_size <= auto_in_a_bits_size; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_source <= auto_in_a_bits_source; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_address <= auto_in_a_bits_address; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_mask <= auto_in_a_bits_mask; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_data <= auto_in_a_bits_data; end end if (_T_611) begin if (_T_19) begin _T_17_0_bits_corrupt <= auto_in_a_bits_corrupt; end end if (_T_611) begin if (_T_19) begin if (_T_619) begin _T_17_0_lut <= 4'h8; end else begin if (_T_617) begin _T_17_0_lut <= 4'he; end else begin if (_T_615) begin _T_17_0_lut <= 4'h6; end else begin if (_T_613) begin _T_17_0_lut <= 4'hc; end else begin _T_17_0_lut <= 4'h0; end end end end end end if (_T_648) begin if (_T_649) begin _T_18_0_data <= auto_out_d_bits_data; end end if (_T_648) begin if (_T_649) begin _T_18_0_denied <= auto_out_d_bits_denied; end end if (_T_648) begin if (_T_649) begin _T_18_0_corrupt <= auto_out_d_bits_corrupt; end end if (reset) begin _T_527 <= 10'h0; end else begin if (_T_529) begin if (_T_542) begin if (_T_525) begin _T_527 <= _T_523; end else begin _T_527 <= 10'h0; end end else begin _T_527 <= 10'h0; end end else begin _T_527 <= _T_568; end end if (reset) begin _T_571_1 <= 1'h0; end else begin if (_T_528) begin _T_571_1 <= _T_542; end end if (reset) begin _T_571_0 <= 1'h0; end else begin if (_T_528) begin _T_571_0 <= _T_541; end end if (reset) begin _T_630 <= 10'h0; end else begin if (_T_622) begin if (_T_633) begin if (_T_628) begin _T_630 <= _T_627; end else begin _T_630 <= 10'h0; end end else begin _T_630 <= _T_632; end end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_555) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38621.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_555) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@38622.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_562) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38632.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_562) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@38633.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_19( // @[:freechips.rocketchip.system.TinyConfig.fir@38815.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@38816.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@38817.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [13:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@38818.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@40027.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@38833.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@38834.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@38837.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@38838.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@38846.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38857.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38858.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38859.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38861.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38862.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38863.6] wire [13:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@38864.6] wire [13:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@38864.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@38865.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@38867.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@38868.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@38870.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@38871.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38872.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38873.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38874.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38876.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38877.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38879.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38880.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38881.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38882.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38883.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38884.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38885.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38886.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38887.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38888.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38889.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38890.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38891.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38892.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38893.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38894.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38895.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38898.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@38955.6] wire [13:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38958.8] wire [14:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38959.8] wire [14:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38960.8] wire [14:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38961.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38962.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38967.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38980.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38981.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38988.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38989.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38995.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38996.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@39001.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39003.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39004.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@39009.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@39010.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39012.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39013.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@39018.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39020.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39021.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@39027.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@39081.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39083.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39084.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@39107.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@39110.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@39118.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39121.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39122.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@39141.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39143.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39144.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@39149.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39151.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39152.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@39166.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@39217.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@39259.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@39260.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@39261.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39263.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39264.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@39270.6] wire _T_293; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@39273.8] wire _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@39281.8] wire _T_304; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39284.8] wire _T_305; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39285.8] wire _T_312; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@39304.8] wire _T_314; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39306.8] wire _T_315; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39307.8] wire _T_320; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@39321.6] wire _T_341; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@39355.8] wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39357.8] wire _T_344; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39358.8] wire _T_349; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@39372.6] wire _T_378; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@39425.6] wire _T_380; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39427.6] wire _T_381; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39428.6] wire _T_382; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@39433.6] wire _T_383; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@39434.6] wire [1:0] _T_386; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@39437.6] wire _T_387; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@39438.6] wire _T_395; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@39446.6] wire _T_401; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39457.6] wire _T_402; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39458.6] wire _T_403; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39459.6] wire _T_405; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@39461.6] wire _T_407; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39464.8] wire _T_408; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39465.8] wire _T_409; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@39470.8] wire _T_411; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39472.8] wire _T_412; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39473.8] wire _T_417; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@39486.8] wire _T_419; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39488.8] wire _T_420; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39489.8] wire _T_425; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@39503.6] wire _T_453; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@39561.6] wire _T_475; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39604.8] wire _T_476; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39605.8] wire _T_482; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@39620.6] wire _T_499; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@39655.6] wire _T_517; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@39691.6] wire _T_546; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@39751.4] wire [9:0] _T_551; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@39756.4] wire _T_552; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@39757.4] wire _T_553; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@39758.4] reg [9:0] _T_555; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@39760.4] reg [31:0] _RAND_0; wire [9:0] _T_557; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39762.4] wire _T_558; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39763.4] reg [2:0] _T_566; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@39774.4] reg [31:0] _RAND_1; reg [2:0] _T_567; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@39775.4] reg [31:0] _RAND_2; reg [3:0] _T_568; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@39776.4] reg [31:0] _RAND_3; reg [4:0] _T_569; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@39777.4] reg [31:0] _RAND_4; reg [13:0] _T_570; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@39778.4] reg [31:0] _RAND_5; wire _T_571; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@39779.4] wire _T_572; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@39780.4] wire _T_573; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@39782.6] wire _T_575; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39784.6] wire _T_576; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39785.6] wire _T_577; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@39790.6] wire _T_579; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39792.6] wire _T_580; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39793.6] wire _T_581; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@39798.6] wire _T_583; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39800.6] wire _T_584; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39801.6] wire _T_585; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@39806.6] wire _T_587; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39808.6] wire _T_588; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39809.6] wire _T_589; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@39814.6] wire _T_591; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39816.6] wire _T_592; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39817.6] wire _T_594; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@39824.4] wire _T_595; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@39832.4] wire [26:0] _T_597; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@39834.4] wire [11:0] _T_598; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@39835.4] wire [11:0] _T_599; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@39836.4] wire [9:0] _T_600; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@39837.4] wire _T_601; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@39838.4] reg [9:0] _T_603; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@39840.4] reg [31:0] _RAND_6; wire [9:0] _T_605; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39842.4] wire _T_606; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39843.4] reg [2:0] _T_614; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@39854.4] reg [31:0] _RAND_7; reg [3:0] _T_616; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@39856.4] reg [31:0] _RAND_8; reg [4:0] _T_617; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@39857.4] reg [31:0] _RAND_9; wire _T_620; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@39860.4] wire _T_621; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@39861.4] wire _T_622; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@39863.6] wire _T_624; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39865.6] wire _T_625; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39866.6] wire _T_630; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@39879.6] wire _T_632; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39881.6] wire _T_633; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39882.6] wire _T_634; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@39887.6] wire _T_636; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39889.6] wire _T_637; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39890.6] wire _T_647; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@39913.4] reg [17:0] _T_648; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@39922.4] reg [31:0] _RAND_10; reg [9:0] _T_658; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@39932.4] reg [31:0] _RAND_11; wire [9:0] _T_660; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39934.4] wire _T_661; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39935.4] reg [9:0] _T_677; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@39954.4] reg [31:0] _RAND_12; wire [9:0] _T_679; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39956.4] wire _T_680; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39957.4] wire _T_690; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@39972.4] wire [31:0] _T_692; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@39975.6] wire [17:0] _T_693; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@39977.6] wire _T_694; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@39978.6] wire _T_695; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@39979.6] wire _T_697; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39981.6] wire _T_698; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39982.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@39974.4] wire _T_702; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@39993.4] wire _T_704; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@39995.4] wire _T_705; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@39996.4] wire [31:0] _T_706; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@39998.6] wire [17:0] _T_688; // @[:freechips.rocketchip.system.TinyConfig.fir@39968.4 :freechips.rocketchip.system.TinyConfig.fir@39970.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@39976.6] wire [17:0] _T_707; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@40000.6] wire [17:0] _T_708; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@40001.6] wire _T_709; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@40002.6] wire _T_711; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40004.6] wire _T_712; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40005.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@39997.4] wire [17:0] _T_699; // @[:freechips.rocketchip.system.TinyConfig.fir@39988.4 :freechips.rocketchip.system.TinyConfig.fir@39990.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@39999.6] wire _T_713; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@40011.4] wire _T_714; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@40012.4] wire _T_715; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@40013.4] wire _T_716; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@40014.4] wire _T_718; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40016.4] wire _T_719; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40017.4] wire [17:0] _T_720; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@40022.4] wire [17:0] _T_721; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@40023.4] wire [17:0] _T_722; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@40024.4] reg [31:0] _T_723; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@40026.4] reg [31:0] _RAND_13; wire _T_724; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@40029.4] wire _T_725; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@40030.4] wire _T_726; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@40031.4] wire _T_727; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@40032.4] wire _T_728; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@40033.4] wire _T_729; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@40034.4] wire _T_731; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40036.4] wire _T_732; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40037.4] wire [31:0] _T_734; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@40043.4] wire _T_737; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@40047.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38969.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@39041.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39124.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@39183.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@39234.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39287.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@39338.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@39389.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39467.10] wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@39509.10] wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@39567.10] wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@39626.10] wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@39661.10] wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@39697.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@40027.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@38833.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@38834.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@38837.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@38838.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@38846.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38857.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38858.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@38859.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@38861.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@38862.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@38863.6] assign _GEN_18 = {{2'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@38864.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@38864.6] assign _T_32 = _T_31 == 14'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@38865.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@38867.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@38868.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@38870.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@38871.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38872.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38873.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38874.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38876.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38877.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38879.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38880.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@38881.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@38882.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@38883.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38884.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38885.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38886.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38887.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38888.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38889.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38890.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38891.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38892.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@38893.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@38894.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@38895.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@38898.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@38955.6] assign _T_120 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@38958.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@38959.8] assign _T_122 = $signed(_T_121) & $signed(-15'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38960.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@38961.8] assign _T_124 = $signed(_T_123) == $signed(15'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@38962.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38967.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38980.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38981.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38988.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38989.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38995.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38996.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@39001.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39003.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39004.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@39009.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@39010.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39012.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39013.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@39018.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39020.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39021.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@39027.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@39081.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39083.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39084.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@39107.6] assign _T_200 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@39110.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@39118.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39121.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39122.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@39141.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39143.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39144.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@39149.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39151.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39152.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@39166.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@39217.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@39259.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@39260.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@39261.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39263.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39264.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@39270.6] assign _T_293 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@39273.8] assign _T_301 = _T_293 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@39281.8] assign _T_304 = _T_301 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39284.8] assign _T_305 = _T_304 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39285.8] assign _T_312 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@39304.8] assign _T_314 = _T_312 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39306.8] assign _T_315 = _T_314 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39307.8] assign _T_320 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@39321.6] assign _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@39355.8] assign _T_343 = _T_341 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39357.8] assign _T_344 = _T_343 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39358.8] assign _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@39372.6] assign _T_378 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@39425.6] assign _T_380 = _T_378 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39427.6] assign _T_381 = _T_380 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39428.6] assign _T_382 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@39433.6] assign _T_383 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@39434.6] assign _T_386 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@39437.6] assign _T_387 = _T_386 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@39438.6] assign _T_395 = _T_386 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@39446.6] assign _T_401 = _T_382 | _T_383; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39457.6] assign _T_402 = _T_401 | _T_387; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39458.6] assign _T_403 = _T_402 | _T_395; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@39459.6] assign _T_405 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@39461.6] assign _T_407 = _T_403 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39464.8] assign _T_408 = _T_407 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39465.8] assign _T_409 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@39470.8] assign _T_411 = _T_409 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39472.8] assign _T_412 = _T_411 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39473.8] assign _T_417 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@39486.8] assign _T_419 = _T_417 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39488.8] assign _T_420 = _T_419 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39489.8] assign _T_425 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@39503.6] assign _T_453 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@39561.6] assign _T_475 = io_in_d_bits_corrupt | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39604.8] assign _T_476 = _T_475 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39605.8] assign _T_482 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@39620.6] assign _T_499 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@39655.6] assign _T_517 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@39691.6] assign _T_546 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@39751.4] assign _T_551 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@39756.4] assign _T_552 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@39757.4] assign _T_553 = _T_552 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@39758.4] assign _T_557 = _T_555 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39762.4] assign _T_558 = _T_555 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39763.4] assign _T_571 = _T_558 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@39779.4] assign _T_572 = io_in_a_valid & _T_571; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@39780.4] assign _T_573 = io_in_a_bits_opcode == _T_566; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@39782.6] assign _T_575 = _T_573 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39784.6] assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39785.6] assign _T_577 = io_in_a_bits_param == _T_567; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@39790.6] assign _T_579 = _T_577 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39792.6] assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39793.6] assign _T_581 = io_in_a_bits_size == _T_568; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@39798.6] assign _T_583 = _T_581 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39800.6] assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39801.6] assign _T_585 = io_in_a_bits_source == _T_569; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@39806.6] assign _T_587 = _T_585 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39808.6] assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39809.6] assign _T_589 = io_in_a_bits_address == _T_570; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@39814.6] assign _T_591 = _T_589 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39816.6] assign _T_592 = _T_591 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39817.6] assign _T_594 = _T_546 & _T_558; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@39824.4] assign _T_595 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@39832.4] assign _T_597 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@39834.4] assign _T_598 = _T_597[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@39835.4] assign _T_599 = ~ _T_598; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@39836.4] assign _T_600 = _T_599[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@39837.4] assign _T_601 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@39838.4] assign _T_605 = _T_603 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39842.4] assign _T_606 = _T_603 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39843.4] assign _T_620 = _T_606 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@39860.4] assign _T_621 = io_in_d_valid & _T_620; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@39861.4] assign _T_622 = io_in_d_bits_opcode == _T_614; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@39863.6] assign _T_624 = _T_622 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39865.6] assign _T_625 = _T_624 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39866.6] assign _T_630 = io_in_d_bits_size == _T_616; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@39879.6] assign _T_632 = _T_630 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39881.6] assign _T_633 = _T_632 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39882.6] assign _T_634 = io_in_d_bits_source == _T_617; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@39887.6] assign _T_636 = _T_634 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39889.6] assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39890.6] assign _T_647 = _T_595 & _T_606; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@39913.4] assign _T_660 = _T_658 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39934.4] assign _T_661 = _T_658 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39935.4] assign _T_679 = _T_677 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@39956.4] assign _T_680 = _T_677 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@39957.4] assign _T_690 = _T_546 & _T_661; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@39972.4] assign _T_692 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@39975.6] assign _T_693 = _T_648 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@39977.6] assign _T_694 = _T_693[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@39978.6] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@39979.6] assign _T_697 = _T_695 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39981.6] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39982.6] assign _GEN_15 = _T_690 ? _T_692 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@39974.4] assign _T_702 = _T_595 & _T_680; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@39993.4] assign _T_704 = _T_405 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@39995.4] assign _T_705 = _T_702 & _T_704; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@39996.4] assign _T_706 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@39998.6] assign _T_688 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@39968.4 :freechips.rocketchip.system.TinyConfig.fir@39970.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@39976.6] assign _T_707 = _T_688 | _T_648; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@40000.6] assign _T_708 = _T_707 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@40001.6] assign _T_709 = _T_708[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@40002.6] assign _T_711 = _T_709 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40004.6] assign _T_712 = _T_711 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40005.6] assign _GEN_16 = _T_705 ? _T_706 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@39997.4] assign _T_699 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@39988.4 :freechips.rocketchip.system.TinyConfig.fir@39990.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@39999.6] assign _T_713 = _T_688 != _T_699; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@40011.4] assign _T_714 = _T_688 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@40012.4] assign _T_715 = _T_714 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@40013.4] assign _T_716 = _T_713 | _T_715; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@40014.4] assign _T_718 = _T_716 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40016.4] assign _T_719 = _T_718 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40017.4] assign _T_720 = _T_648 | _T_688; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@40022.4] assign _T_721 = ~ _T_699; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@40023.4] assign _T_722 = _T_720 & _T_721; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@40024.4] assign _T_724 = _T_648 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@40029.4] assign _T_725 = _T_724 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@40030.4] assign _T_726 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@40031.4] assign _T_727 = _T_725 | _T_726; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@40032.4] assign _T_728 = _T_723 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@40033.4] assign _T_729 = _T_727 | _T_728; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@40034.4] assign _T_731 = _T_729 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40036.4] assign _T_732 = _T_731 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40037.4] assign _T_734 = _T_723 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@40043.4] assign _T_737 = _T_546 | _T_595; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@40047.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38969.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@39041.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39124.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@39183.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@39234.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39287.10] assign _GEN_95 = io_in_a_valid & _T_320; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@39338.10] assign _GEN_105 = io_in_a_valid & _T_349; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@39389.10] assign _GEN_115 = io_in_d_valid & _T_405; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39467.10] assign _GEN_123 = io_in_d_valid & _T_425; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@39509.10] assign _GEN_131 = io_in_d_valid & _T_453; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@39567.10] assign _GEN_139 = io_in_d_valid & _T_482; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@39626.10] assign _GEN_143 = io_in_d_valid & _T_499; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@39661.10] assign _GEN_147 = io_in_d_valid & _T_517; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@39697.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_555 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_566 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_567 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_568 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_569 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_570 = _RAND_5[13:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_603 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_614 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_616 = _RAND_8[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_617 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_648 = _RAND_10[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_658 = _RAND_11[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_677 = _RAND_12[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_723 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_555 <= 10'h0; end else begin if (_T_546) begin if (_T_558) begin if (_T_553) begin _T_555 <= _T_551; end else begin _T_555 <= 10'h0; end end else begin _T_555 <= _T_557; end end end if (_T_594) begin _T_566 <= io_in_a_bits_opcode; end if (_T_594) begin _T_567 <= io_in_a_bits_param; end if (_T_594) begin _T_568 <= io_in_a_bits_size; end if (_T_594) begin _T_569 <= io_in_a_bits_source; end if (_T_594) begin _T_570 <= io_in_a_bits_address; end if (reset) begin _T_603 <= 10'h0; end else begin if (_T_595) begin if (_T_606) begin if (_T_601) begin _T_603 <= _T_600; end else begin _T_603 <= 10'h0; end end else begin _T_603 <= _T_605; end end end if (_T_647) begin _T_614 <= io_in_d_bits_opcode; end if (_T_647) begin _T_616 <= io_in_d_bits_size; end if (_T_647) begin _T_617 <= io_in_d_bits_source; end if (reset) begin _T_648 <= 18'h0; end else begin _T_648 <= _T_722; end if (reset) begin _T_658 <= 10'h0; end else begin if (_T_546) begin if (_T_661) begin if (_T_553) begin _T_658 <= _T_551; end else begin _T_658 <= 10'h0; end end else begin _T_658 <= _T_660; end end end if (reset) begin _T_677 <= 10'h0; end else begin if (_T_595) begin if (_T_680) begin if (_T_601) begin _T_677 <= _T_600; end else begin _T_677 <= 10'h0; end end else begin _T_677 <= _T_679; end end end if (reset) begin _T_723 <= 32'h0; end else begin if (_T_737) begin _T_723 <= 32'h0; end else begin _T_723 <= _T_734; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38969.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@38970.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@38976.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@38977.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38983.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@38984.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38991.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@38992.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38998.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@38999.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39006.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@39007.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39015.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@39016.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39023.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@39024.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@39041.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@39042.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@39048.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@39049.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@39055.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@39056.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@39063.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@39064.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@39070.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@39071.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@39078.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@39079.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39086.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@39087.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@39095.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@39096.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@39103.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@39104.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39124.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@39125.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@39131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@39132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@39138.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@39139.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39146.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@39147.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39154.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@39155.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@39162.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@39163.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@39183.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@39184.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@39190.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@39191.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@39197.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@39198.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@39205.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@39206.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@39213.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@39214.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@39234.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@39235.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@39241.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@39242.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@39248.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@39249.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@39256.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@39257.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39266.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@39267.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_305) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39287.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_305) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@39288.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@39294.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@39295.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@39301.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@39302.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_315) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39309.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_315) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@39310.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@39317.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@39318.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_305) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@39338.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_305) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@39339.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@39345.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@39346.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@39352.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@39353.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_344) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39360.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_344) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@39361.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@39368.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@39369.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@39389.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_212) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@39390.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@39396.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@39397.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@39403.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@39404.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@39411.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@39412.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@39419.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@39420.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_381) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39430.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_381) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@39431.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39467.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_408) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@39468.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39475.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_412) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@39476.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39491.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_420) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@39492.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@39499.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_129) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@39500.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@39509.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_408) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@39510.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@39516.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@39517.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@39524.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_412) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@39525.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@39548.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_420) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@39549.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@39567.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_408) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@39568.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@39574.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@39575.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@39582.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_412) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@39583.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_476) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39607.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_476) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@39608.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@39626.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_408) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@39627.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@39642.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_420) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@39643.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@39661.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_408) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@39662.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_143 & _T_476) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@39678.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_143 & _T_476) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@39679.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@39697.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_408) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@39698.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_147 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@39713.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_147 & _T_420) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@39714.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_576) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39787.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_576) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@39788.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_580) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39795.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_580) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@39796.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_584) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39803.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_584) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@39804.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_588) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39811.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_588) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@39812.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_592) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39819.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_592) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@39820.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_625) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39868.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_625) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@39869.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_633) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39884.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_633) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@39885.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_637) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39892.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_637) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@39893.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_690 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39984.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_690 & _T_698) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@39985.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_705 & _T_712) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40007.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_705 & _T_712) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@40008.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_719) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40019.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_719) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@40020.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_732) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40039.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_732) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@40040.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_34( // @[:freechips.rocketchip.system.TinyConfig.fir@40052.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@40053.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@40054.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] output [4:0] io_deq_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@40055.4] ); reg [2:0] _T_opcode [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_opcode__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg [3:0] _T_size [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg [31:0] _RAND_1; wire [3:0] _T_size__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_size__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg [4:0] _T_source [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg [31:0] _RAND_2; wire [4:0] _T_source__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_source__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@40058.4] reg [31:0] _RAND_3; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@40060.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40063.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40066.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@40082.4] assign _T_opcode__T_14_addr = 1'h0; assign _T_opcode__T_14_data = _T_opcode[_T_opcode__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = 1'h0; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_14_addr = 1'h0; assign _T_size__T_14_data = _T_size[_T_size__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = 1'h0; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_14_addr = 1'h0; assign _T_source__T_14_data = _T_source[_T_source__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = 1'h0; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@40060.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40063.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40066.4] assign _T_11 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@40082.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@40089.4] assign io_deq_valid = _T_3 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@40087.4] assign io_deq_bits_opcode = _T_opcode__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@40098.4] assign io_deq_bits_size = _T_size__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@40096.4] assign io_deq_bits_source = _T_source__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@40095.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_size[initvar] = _RAND_1[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_source[initvar] = _RAND_2[4:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@40057.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin _T_1 <= _T_6; end end end endmodule module TLError( // @[:freechips.rocketchip.system.TinyConfig.fir@40106.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@40107.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@40108.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [13:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] output auto_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@40109.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [13:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] wire a_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire a_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire a_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire a_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [2:0] a_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [3:0] a_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [4:0] a_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire a_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire a_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [2:0] a_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [3:0] a_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire [4:0] a_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] wire _T_12; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40182.4] wire [26:0] _T_14; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40184.4] wire [11:0] _T_15; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40185.4] wire [11:0] _T_16; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40186.4] wire [9:0] _T_17; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@40187.4] wire _T_18; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@40188.4] wire _T_19; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@40189.4] wire [9:0] _T_20; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@40190.4] reg [9:0] _T_21; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@40191.4] reg [31:0] _RAND_0; wire [9:0] _T_23; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@40193.4] wire _T_24; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@40194.4] wire _T_25; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@40195.4] wire _T_26; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@40196.4] wire a_last; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@40197.4] wire da_valid; // @[Error.scala 30:25:freechips.rocketchip.system.TinyConfig.fir@40240.4] wire _T_31; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40205.4] wire [3:0] da_bits_size; // @[Error.scala 22:18:freechips.rocketchip.system.TinyConfig.fir@40179.4 Error.scala 34:21:freechips.rocketchip.system.TinyConfig.fir@40255.4] wire [26:0] _T_33; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40207.4] wire [11:0] _T_34; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40208.4] wire [11:0] _T_35; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40209.4] wire [9:0] _T_36; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@40210.4] wire [2:0] _GEN_4; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire [2:0] _GEN_5; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire [2:0] _GEN_6; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire [2:0] _GEN_7; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire [2:0] _GEN_8; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire [2:0] da_bits_opcode; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] wire _T_37; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@40211.4] wire [9:0] _T_38; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@40212.4] reg [9:0] _T_39; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@40213.4] reg [31:0] _RAND_1; wire [9:0] _T_41; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@40215.4] wire da_first; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@40216.4] wire _T_42; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@40217.4] wire _T_43; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@40218.4] wire da_last; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@40219.4] wire _T_52; // @[Error.scala 29:26:freechips.rocketchip.system.TinyConfig.fir@40235.4] wire _T_54; // @[Error.scala 29:49:freechips.rocketchip.system.TinyConfig.fir@40237.4] TLMonitor_19 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@40116.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_34 a ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@40166.4] .clock(a_clock), .reset(a_reset), .io_enq_ready(a_io_enq_ready), .io_enq_valid(a_io_enq_valid), .io_enq_bits_opcode(a_io_enq_bits_opcode), .io_enq_bits_size(a_io_enq_bits_size), .io_enq_bits_source(a_io_enq_bits_source), .io_deq_ready(a_io_deq_ready), .io_deq_valid(a_io_deq_valid), .io_deq_bits_opcode(a_io_deq_bits_opcode), .io_deq_bits_size(a_io_deq_bits_size), .io_deq_bits_source(a_io_deq_bits_source) ); assign _T_12 = a_io_deq_ready & a_io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40182.4] assign _T_14 = 27'hfff << a_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40184.4] assign _T_15 = _T_14[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40185.4] assign _T_16 = ~ _T_15; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40186.4] assign _T_17 = _T_16[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@40187.4] assign _T_18 = a_io_deq_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@40188.4] assign _T_19 = _T_18 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@40189.4] assign _T_20 = _T_19 ? _T_17 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@40190.4] assign _T_23 = _T_21 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@40193.4] assign _T_24 = _T_21 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@40194.4] assign _T_25 = _T_21 == 10'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@40195.4] assign _T_26 = _T_20 == 10'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@40196.4] assign a_last = _T_25 | _T_26; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@40197.4] assign da_valid = a_io_deq_valid & a_last; // @[Error.scala 30:25:freechips.rocketchip.system.TinyConfig.fir@40240.4] assign _T_31 = auto_in_d_ready & da_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@40205.4] assign da_bits_size = a_io_deq_bits_size; // @[Error.scala 22:18:freechips.rocketchip.system.TinyConfig.fir@40179.4 Error.scala 34:21:freechips.rocketchip.system.TinyConfig.fir@40255.4] assign _T_33 = 27'hfff << da_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40207.4] assign _T_34 = _T_33[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40208.4] assign _T_35 = ~ _T_34; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40209.4] assign _T_36 = _T_35[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@40210.4] assign _GEN_4 = 3'h2 == a_io_deq_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign _GEN_5 = 3'h3 == a_io_deq_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign _GEN_6 = 3'h4 == a_io_deq_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign _GEN_7 = 3'h5 == a_io_deq_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign _GEN_8 = 3'h6 == a_io_deq_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign da_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@40253.4] assign _T_37 = da_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@40211.4] assign _T_38 = _T_37 ? _T_36 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@40212.4] assign _T_41 = _T_39 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@40215.4] assign da_first = _T_39 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@40216.4] assign _T_42 = _T_39 == 10'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@40217.4] assign _T_43 = _T_38 == 10'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@40218.4] assign da_last = _T_42 | _T_43; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@40219.4] assign _T_52 = auto_in_d_ready & da_last; // @[Error.scala 29:26:freechips.rocketchip.system.TinyConfig.fir@40235.4] assign _T_54 = a_last == 1'h0; // @[Error.scala 29:49:freechips.rocketchip.system.TinyConfig.fir@40237.4] assign auto_in_a_ready = a_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign auto_in_d_valid = a_io_deq_valid & a_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign auto_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign auto_in_d_bits_size = a_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign auto_in_d_bits_source = a_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign auto_in_d_bits_corrupt = da_bits_opcode[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@40165.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@40118.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@40119.4] assign TLMonitor_io_in_a_ready = a_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_valid = a_io_deq_valid & a_last; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_bits_size = a_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_bits_source = a_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign TLMonitor_io_in_d_bits_corrupt = da_bits_opcode[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@40164.4] assign a_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@40167.4] assign a_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@40168.4] assign a_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@40169.4] assign a_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@40177.4] assign a_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@40175.4] assign a_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@40174.4] assign a_io_deq_ready = _T_52 | _T_54; // @[Error.scala 29:13:freechips.rocketchip.system.TinyConfig.fir@40239.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_21 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_39 = _RAND_1[9:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_21 <= 10'h0; end else begin if (_T_12) begin if (_T_24) begin if (_T_19) begin _T_21 <= _T_17; end else begin _T_21 <= 10'h0; end end else begin _T_21 <= _T_23; end end end if (reset) begin _T_39 <= 10'h0; end else begin if (_T_31) begin if (da_first) begin if (_T_37) begin _T_39 <= _T_36; end else begin _T_39 <= 10'h0; end end else begin _T_39 <= _T_41; end end end end endmodule module TLMonitor_20( // @[:freechips.rocketchip.system.TinyConfig.fir@40278.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@40279.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@40280.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [13:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@40281.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@41490.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40296.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40297.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@40300.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40301.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40309.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40320.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40321.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40322.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40324.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40325.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40326.6] wire [13:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@40327.6] wire [13:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@40327.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@40328.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@40330.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@40331.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@40333.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@40334.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@40335.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@40336.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@40337.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40339.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40340.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40342.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40343.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@40344.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@40345.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@40346.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40347.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40348.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40349.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40350.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40351.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40352.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40353.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40354.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40355.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40356.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40357.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40358.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@40361.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@40418.6] wire [13:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@40421.8] wire [14:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@40422.8] wire [14:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@40423.8] wire [14:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@40424.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@40425.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40430.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40443.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40444.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40451.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40452.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40458.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40459.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@40464.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40466.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40467.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@40472.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@40473.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40475.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40476.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@40481.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40483.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40484.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@40490.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@40544.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40546.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40547.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@40570.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@40573.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@40581.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40584.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40585.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@40604.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40606.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40607.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@40612.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40614.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40615.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@40629.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@40680.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@40722.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@40723.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@40724.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40726.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40727.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@40733.6] wire _T_293; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@40736.8] wire _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@40744.8] wire _T_304; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40747.8] wire _T_305; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40748.8] wire _T_312; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@40767.8] wire _T_314; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40769.8] wire _T_315; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40770.8] wire _T_320; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@40784.6] wire _T_341; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@40818.8] wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40820.8] wire _T_344; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40821.8] wire _T_349; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@40835.6] wire _T_378; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@40888.6] wire _T_380; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40890.6] wire _T_381; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40891.6] wire _T_382; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40896.6] wire _T_383; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40897.6] wire [1:0] _T_386; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@40900.6] wire _T_387; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40901.6] wire _T_395; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40909.6] wire _T_401; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40920.6] wire _T_402; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40921.6] wire _T_403; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40922.6] wire _T_405; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@40924.6] wire _T_407; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40927.8] wire _T_408; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40928.8] wire _T_409; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@40933.8] wire _T_411; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40935.8] wire _T_412; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40936.8] wire _T_413; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@40941.8] wire _T_415; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40943.8] wire _T_416; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40944.8] wire _T_417; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@40949.8] wire _T_419; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40951.8] wire _T_420; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40952.8] wire _T_421; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@40957.8] wire _T_423; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40959.8] wire _T_424; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40960.8] wire _T_425; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@40966.6] wire _T_436; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@40990.8] wire _T_438; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40992.8] wire _T_439; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40993.8] wire _T_440; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@40998.8] wire _T_442; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41000.8] wire _T_443; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41001.8] wire _T_453; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@41024.6] wire _T_473; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@41065.8] wire _T_475; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41067.8] wire _T_476; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41068.8] wire _T_482; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@41083.6] wire _T_499; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@41118.6] wire _T_517; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@41154.6] wire _T_546; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@41214.4] wire [9:0] _T_551; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@41219.4] wire _T_552; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@41220.4] wire _T_553; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@41221.4] reg [9:0] _T_555; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@41223.4] reg [31:0] _RAND_0; wire [9:0] _T_557; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41225.4] wire _T_558; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41226.4] reg [2:0] _T_566; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@41237.4] reg [31:0] _RAND_1; reg [2:0] _T_567; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@41238.4] reg [31:0] _RAND_2; reg [3:0] _T_568; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@41239.4] reg [31:0] _RAND_3; reg [4:0] _T_569; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@41240.4] reg [31:0] _RAND_4; reg [13:0] _T_570; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@41241.4] reg [31:0] _RAND_5; wire _T_571; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@41242.4] wire _T_572; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@41243.4] wire _T_573; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@41245.6] wire _T_575; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41247.6] wire _T_576; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41248.6] wire _T_577; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@41253.6] wire _T_579; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41255.6] wire _T_580; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41256.6] wire _T_581; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@41261.6] wire _T_583; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41263.6] wire _T_584; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41264.6] wire _T_585; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@41269.6] wire _T_587; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41271.6] wire _T_588; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41272.6] wire _T_589; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@41277.6] wire _T_591; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41279.6] wire _T_592; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41280.6] wire _T_594; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@41287.4] wire _T_595; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@41295.4] wire [26:0] _T_597; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@41297.4] wire [11:0] _T_598; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@41298.4] wire [11:0] _T_599; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@41299.4] wire [9:0] _T_600; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@41300.4] wire _T_601; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@41301.4] reg [9:0] _T_603; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@41303.4] reg [31:0] _RAND_6; wire [9:0] _T_605; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41305.4] wire _T_606; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41306.4] reg [2:0] _T_614; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@41317.4] reg [31:0] _RAND_7; reg [1:0] _T_615; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@41318.4] reg [31:0] _RAND_8; reg [3:0] _T_616; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@41319.4] reg [31:0] _RAND_9; reg [4:0] _T_617; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@41320.4] reg [31:0] _RAND_10; reg _T_618; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@41321.4] reg [31:0] _RAND_11; reg _T_619; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@41322.4] reg [31:0] _RAND_12; wire _T_620; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@41323.4] wire _T_621; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@41324.4] wire _T_622; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@41326.6] wire _T_624; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41328.6] wire _T_625; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41329.6] wire _T_626; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@41334.6] wire _T_628; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41336.6] wire _T_629; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41337.6] wire _T_630; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@41342.6] wire _T_632; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41344.6] wire _T_633; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41345.6] wire _T_634; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@41350.6] wire _T_636; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41352.6] wire _T_637; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41353.6] wire _T_638; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@41358.6] wire _T_640; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41360.6] wire _T_641; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41361.6] wire _T_642; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@41366.6] wire _T_644; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41368.6] wire _T_645; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41369.6] wire _T_647; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@41376.4] reg [17:0] _T_648; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@41385.4] reg [31:0] _RAND_13; reg [9:0] _T_658; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@41395.4] reg [31:0] _RAND_14; wire [9:0] _T_660; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41397.4] wire _T_661; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41398.4] reg [9:0] _T_677; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@41417.4] reg [31:0] _RAND_15; wire [9:0] _T_679; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41419.4] wire _T_680; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41420.4] wire _T_690; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@41435.4] wire [31:0] _T_692; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@41438.6] wire [17:0] _T_693; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@41440.6] wire _T_694; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@41441.6] wire _T_695; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@41442.6] wire _T_697; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41444.6] wire _T_698; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41445.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@41437.4] wire _T_702; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@41456.4] wire _T_704; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@41458.4] wire _T_705; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@41459.4] wire [31:0] _T_706; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@41461.6] wire [17:0] _T_688; // @[:freechips.rocketchip.system.TinyConfig.fir@41431.4 :freechips.rocketchip.system.TinyConfig.fir@41433.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@41439.6] wire [17:0] _T_707; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@41463.6] wire [17:0] _T_708; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@41464.6] wire _T_709; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@41465.6] wire _T_711; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41467.6] wire _T_712; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41468.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@41460.4] wire [17:0] _T_699; // @[:freechips.rocketchip.system.TinyConfig.fir@41451.4 :freechips.rocketchip.system.TinyConfig.fir@41453.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@41462.6] wire _T_713; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@41474.4] wire _T_714; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@41475.4] wire _T_715; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@41476.4] wire _T_716; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@41477.4] wire _T_718; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41479.4] wire _T_719; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41480.4] wire [17:0] _T_720; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@41485.4] wire [17:0] _T_721; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@41486.4] wire [17:0] _T_722; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@41487.4] reg [31:0] _T_723; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@41489.4] reg [31:0] _RAND_16; wire _T_724; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@41492.4] wire _T_725; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@41493.4] wire _T_726; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@41494.4] wire _T_727; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@41495.4] wire _T_728; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@41496.4] wire _T_729; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@41497.4] wire _T_731; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41499.4] wire _T_732; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41500.4] wire [31:0] _T_734; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@41506.4] wire _T_737; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@41510.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40432.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@40504.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40587.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@40646.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@40697.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40750.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@40801.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@40852.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40930.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@40972.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@41030.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@41089.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@41124.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@41160.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@41490.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40296.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40297.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@40300.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40301.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40309.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40320.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40321.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40322.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@40324.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@40325.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@40326.6] assign _GEN_18 = {{2'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@40327.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@40327.6] assign _T_32 = _T_31 == 14'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@40328.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@40330.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@40331.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@40333.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@40334.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@40335.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@40336.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@40337.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40339.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40340.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40342.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40343.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@40344.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@40345.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@40346.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40347.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40348.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40349.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40350.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40351.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40352.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40353.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40354.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40355.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@40356.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@40357.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@40358.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@40361.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@40418.6] assign _T_120 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@40421.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@40422.8] assign _T_122 = $signed(_T_121) & $signed(-15'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@40423.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@40424.8] assign _T_124 = $signed(_T_123) == $signed(15'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@40425.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40430.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40443.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40444.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40451.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40452.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40458.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40459.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@40464.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40466.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40467.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@40472.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@40473.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40475.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40476.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@40481.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40483.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40484.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@40490.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@40544.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40546.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40547.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@40570.6] assign _T_200 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@40573.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@40581.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40584.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40585.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@40604.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40606.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40607.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@40612.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40614.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40615.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@40629.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@40680.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@40722.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@40723.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@40724.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40726.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40727.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@40733.6] assign _T_293 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@40736.8] assign _T_301 = _T_293 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@40744.8] assign _T_304 = _T_301 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40747.8] assign _T_305 = _T_304 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40748.8] assign _T_312 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@40767.8] assign _T_314 = _T_312 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40769.8] assign _T_315 = _T_314 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40770.8] assign _T_320 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@40784.6] assign _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@40818.8] assign _T_343 = _T_341 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40820.8] assign _T_344 = _T_343 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40821.8] assign _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@40835.6] assign _T_378 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@40888.6] assign _T_380 = _T_378 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40890.6] assign _T_381 = _T_380 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40891.6] assign _T_382 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40896.6] assign _T_383 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@40897.6] assign _T_386 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@40900.6] assign _T_387 = _T_386 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40901.6] assign _T_395 = _T_386 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@40909.6] assign _T_401 = _T_382 | _T_383; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40920.6] assign _T_402 = _T_401 | _T_387; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40921.6] assign _T_403 = _T_402 | _T_395; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@40922.6] assign _T_405 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@40924.6] assign _T_407 = _T_403 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40927.8] assign _T_408 = _T_407 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40928.8] assign _T_409 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@40933.8] assign _T_411 = _T_409 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40935.8] assign _T_412 = _T_411 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40936.8] assign _T_413 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@40941.8] assign _T_415 = _T_413 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40943.8] assign _T_416 = _T_415 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40944.8] assign _T_417 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@40949.8] assign _T_419 = _T_417 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40951.8] assign _T_420 = _T_419 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40952.8] assign _T_421 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@40957.8] assign _T_423 = _T_421 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40959.8] assign _T_424 = _T_423 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40960.8] assign _T_425 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@40966.6] assign _T_436 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@40990.8] assign _T_438 = _T_436 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40992.8] assign _T_439 = _T_438 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40993.8] assign _T_440 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@40998.8] assign _T_442 = _T_440 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41000.8] assign _T_443 = _T_442 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41001.8] assign _T_453 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@41024.6] assign _T_473 = _T_421 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@41065.8] assign _T_475 = _T_473 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41067.8] assign _T_476 = _T_475 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41068.8] assign _T_482 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@41083.6] assign _T_499 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@41118.6] assign _T_517 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@41154.6] assign _T_546 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@41214.4] assign _T_551 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@41219.4] assign _T_552 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@41220.4] assign _T_553 = _T_552 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@41221.4] assign _T_557 = _T_555 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41225.4] assign _T_558 = _T_555 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41226.4] assign _T_571 = _T_558 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@41242.4] assign _T_572 = io_in_a_valid & _T_571; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@41243.4] assign _T_573 = io_in_a_bits_opcode == _T_566; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@41245.6] assign _T_575 = _T_573 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41247.6] assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41248.6] assign _T_577 = io_in_a_bits_param == _T_567; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@41253.6] assign _T_579 = _T_577 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41255.6] assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41256.6] assign _T_581 = io_in_a_bits_size == _T_568; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@41261.6] assign _T_583 = _T_581 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41263.6] assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41264.6] assign _T_585 = io_in_a_bits_source == _T_569; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@41269.6] assign _T_587 = _T_585 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41271.6] assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41272.6] assign _T_589 = io_in_a_bits_address == _T_570; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@41277.6] assign _T_591 = _T_589 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41279.6] assign _T_592 = _T_591 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41280.6] assign _T_594 = _T_546 & _T_558; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@41287.4] assign _T_595 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@41295.4] assign _T_597 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@41297.4] assign _T_598 = _T_597[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@41298.4] assign _T_599 = ~ _T_598; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@41299.4] assign _T_600 = _T_599[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@41300.4] assign _T_601 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@41301.4] assign _T_605 = _T_603 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41305.4] assign _T_606 = _T_603 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41306.4] assign _T_620 = _T_606 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@41323.4] assign _T_621 = io_in_d_valid & _T_620; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@41324.4] assign _T_622 = io_in_d_bits_opcode == _T_614; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@41326.6] assign _T_624 = _T_622 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41328.6] assign _T_625 = _T_624 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41329.6] assign _T_626 = io_in_d_bits_param == _T_615; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@41334.6] assign _T_628 = _T_626 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41336.6] assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41337.6] assign _T_630 = io_in_d_bits_size == _T_616; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@41342.6] assign _T_632 = _T_630 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41344.6] assign _T_633 = _T_632 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41345.6] assign _T_634 = io_in_d_bits_source == _T_617; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@41350.6] assign _T_636 = _T_634 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41352.6] assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41353.6] assign _T_638 = io_in_d_bits_sink == _T_618; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@41358.6] assign _T_640 = _T_638 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41360.6] assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41361.6] assign _T_642 = io_in_d_bits_denied == _T_619; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@41366.6] assign _T_644 = _T_642 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41368.6] assign _T_645 = _T_644 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41369.6] assign _T_647 = _T_595 & _T_606; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@41376.4] assign _T_660 = _T_658 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41397.4] assign _T_661 = _T_658 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41398.4] assign _T_679 = _T_677 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@41419.4] assign _T_680 = _T_677 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@41420.4] assign _T_690 = _T_546 & _T_661; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@41435.4] assign _T_692 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@41438.6] assign _T_693 = _T_648 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@41440.6] assign _T_694 = _T_693[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@41441.6] assign _T_695 = _T_694 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@41442.6] assign _T_697 = _T_695 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41444.6] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41445.6] assign _GEN_15 = _T_690 ? _T_692 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@41437.4] assign _T_702 = _T_595 & _T_680; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@41456.4] assign _T_704 = _T_405 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@41458.4] assign _T_705 = _T_702 & _T_704; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@41459.4] assign _T_706 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@41461.6] assign _T_688 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@41431.4 :freechips.rocketchip.system.TinyConfig.fir@41433.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@41439.6] assign _T_707 = _T_688 | _T_648; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@41463.6] assign _T_708 = _T_707 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@41464.6] assign _T_709 = _T_708[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@41465.6] assign _T_711 = _T_709 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41467.6] assign _T_712 = _T_711 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41468.6] assign _GEN_16 = _T_705 ? _T_706 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@41460.4] assign _T_699 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@41451.4 :freechips.rocketchip.system.TinyConfig.fir@41453.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@41462.6] assign _T_713 = _T_688 != _T_699; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@41474.4] assign _T_714 = _T_688 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@41475.4] assign _T_715 = _T_714 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@41476.4] assign _T_716 = _T_713 | _T_715; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@41477.4] assign _T_718 = _T_716 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41479.4] assign _T_719 = _T_718 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41480.4] assign _T_720 = _T_648 | _T_688; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@41485.4] assign _T_721 = ~ _T_699; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@41486.4] assign _T_722 = _T_720 & _T_721; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@41487.4] assign _T_724 = _T_648 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@41492.4] assign _T_725 = _T_724 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@41493.4] assign _T_726 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@41494.4] assign _T_727 = _T_725 | _T_726; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@41495.4] assign _T_728 = _T_723 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@41496.4] assign _T_729 = _T_727 | _T_728; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@41497.4] assign _T_731 = _T_729 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41499.4] assign _T_732 = _T_731 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41500.4] assign _T_734 = _T_723 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@41506.4] assign _T_737 = _T_546 | _T_595; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@41510.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40432.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@40504.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40587.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@40646.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@40697.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40750.10] assign _GEN_95 = io_in_a_valid & _T_320; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@40801.10] assign _GEN_105 = io_in_a_valid & _T_349; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@40852.10] assign _GEN_115 = io_in_d_valid & _T_405; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40930.10] assign _GEN_125 = io_in_d_valid & _T_425; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@40972.10] assign _GEN_137 = io_in_d_valid & _T_453; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@41030.10] assign _GEN_149 = io_in_d_valid & _T_482; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@41089.10] assign _GEN_155 = io_in_d_valid & _T_499; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@41124.10] assign _GEN_161 = io_in_d_valid & _T_517; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@41160.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_555 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_566 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_567 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_568 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_569 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_570 = _RAND_5[13:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_603 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_614 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_615 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_616 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_617 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_618 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_619 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_648 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_658 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_677 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_723 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_555 <= 10'h0; end else begin if (_T_546) begin if (_T_558) begin if (_T_553) begin _T_555 <= _T_551; end else begin _T_555 <= 10'h0; end end else begin _T_555 <= _T_557; end end end if (_T_594) begin _T_566 <= io_in_a_bits_opcode; end if (_T_594) begin _T_567 <= io_in_a_bits_param; end if (_T_594) begin _T_568 <= io_in_a_bits_size; end if (_T_594) begin _T_569 <= io_in_a_bits_source; end if (_T_594) begin _T_570 <= io_in_a_bits_address; end if (reset) begin _T_603 <= 10'h0; end else begin if (_T_595) begin if (_T_606) begin if (_T_601) begin _T_603 <= _T_600; end else begin _T_603 <= 10'h0; end end else begin _T_603 <= _T_605; end end end if (_T_647) begin _T_614 <= io_in_d_bits_opcode; end if (_T_647) begin _T_615 <= io_in_d_bits_param; end if (_T_647) begin _T_616 <= io_in_d_bits_size; end if (_T_647) begin _T_617 <= io_in_d_bits_source; end if (_T_647) begin _T_618 <= io_in_d_bits_sink; end if (_T_647) begin _T_619 <= io_in_d_bits_denied; end if (reset) begin _T_648 <= 18'h0; end else begin _T_648 <= _T_722; end if (reset) begin _T_658 <= 10'h0; end else begin if (_T_546) begin if (_T_661) begin if (_T_553) begin _T_658 <= _T_551; end else begin _T_658 <= 10'h0; end end else begin _T_658 <= _T_660; end end end if (reset) begin _T_677 <= 10'h0; end else begin if (_T_595) begin if (_T_680) begin if (_T_601) begin _T_677 <= _T_600; end else begin _T_677 <= 10'h0; end end else begin _T_677 <= _T_679; end end end if (reset) begin _T_723 <= 32'h0; end else begin if (_T_737) begin _T_723 <= 32'h0; end else begin _T_723 <= _T_734; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40432.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@40433.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@40439.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@40440.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40446.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@40447.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40454.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@40455.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40461.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@40462.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@40470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40478.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@40479.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40486.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@40487.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@40504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@40505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@40511.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@40512.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@40518.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@40519.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@40526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@40527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@40533.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@40534.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@40541.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@40542.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40549.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@40550.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@40558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@40559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@40566.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@40567.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40587.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@40588.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@40594.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@40595.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@40601.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@40602.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40609.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@40610.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40617.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@40618.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@40625.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@40626.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@40646.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@40647.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@40653.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@40654.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@40660.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@40661.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@40668.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@40669.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@40676.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@40677.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@40697.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@40698.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@40704.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@40705.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@40711.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@40712.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@40719.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@40720.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40729.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@40730.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_305) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40750.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_305) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@40751.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@40757.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@40758.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@40764.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@40765.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_315) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40772.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_315) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@40773.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@40780.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@40781.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_305) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@40801.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_305) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@40802.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@40808.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@40809.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@40815.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@40816.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_344) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40823.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_344) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@40824.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@40831.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@40832.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@40852.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_212) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@40853.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@40859.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@40860.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@40866.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@40867.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@40874.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@40875.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@40882.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@40883.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_381) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40893.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_381) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@40894.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40930.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_408) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@40931.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40938.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_412) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@40939.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_416) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40946.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_416) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@40947.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40954.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_420) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@40955.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_424) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40962.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_424) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@40963.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@40972.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_408) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@40973.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@40979.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@40980.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@40987.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_412) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@40988.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_439) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40995.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_439) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@40996.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_443) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41003.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_443) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@41004.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@41011.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_420) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@41012.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@41030.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_408) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@41031.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@41037.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@41038.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_412) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@41045.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_412) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@41046.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_439) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@41053.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_439) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@41054.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_443) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@41061.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_443) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@41062.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_476) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41070.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_476) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@41071.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@41089.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_408) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@41090.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_416) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@41097.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_416) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@41098.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@41105.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_420) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@41106.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@41124.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_408) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@41125.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_416) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@41132.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_416) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@41133.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_476) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@41141.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_476) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@41142.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_408) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@41160.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_408) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@41161.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_416) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@41168.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_416) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@41169.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_420) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@41176.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_420) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@41177.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_576) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41250.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_576) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@41251.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_580) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41258.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_580) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@41259.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_584) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41266.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_584) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@41267.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_588) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41274.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_588) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@41275.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_572 & _T_592) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41282.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_572 & _T_592) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@41283.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_625) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41331.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_625) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@41332.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_629) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41339.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_629) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@41340.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_633) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41347.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_633) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@41348.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_637) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41355.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_637) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@41356.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_641) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41363.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_641) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@41364.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_645) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41371.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_645) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@41372.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_690 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41447.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_690 & _T_698) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@41448.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_705 & _T_712) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41470.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_705 & _T_712) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@41471.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_719) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41482.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_719) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@41483.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_732) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41502.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_732) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@41503.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_35( // @[:freechips.rocketchip.system.TinyConfig.fir@41515.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@41516.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@41517.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [13:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [13:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@41518.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_1; wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_3; wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [13:0] _T_address [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_4; wire [13:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [13:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_address__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_5; wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg [31:0] _RAND_6; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@41521.4] reg [31:0] _RAND_7; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@41522.4] reg [31:0] _RAND_8; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@41523.4] reg [31:0] _RAND_9; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@41524.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@41525.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@41526.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@41527.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@41528.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@41531.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@41546.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@41552.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@41555.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_address__T_18_addr = value_1; assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_address__T_10_data = io_enq_bits_address; assign _T_address__T_10_addr = value; assign _T_address__T_10_mask = 1'h1; assign _T_address__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_18_addr = value_1; assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = value; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@41524.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@41525.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@41526.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@41527.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@41528.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@41531.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@41546.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@41552.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@41555.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@41562.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@41560.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41571.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41570.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41569.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41568.4] assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41567.4] assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41566.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@41564.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[4:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_address[initvar] = _RAND_4[13:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_mask[initvar] = _RAND_5[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_6[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; value = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value_1 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_address__T_10_en & _T_address__T_10_mask) begin _T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@41520.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module TLBuffer_7( // @[:freechips.rocketchip.system.TinyConfig.fir@41643.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@41644.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@41645.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [13:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [13:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@41646.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [13:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [4:0] Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [13:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [4:0] Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [13:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [4:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [4:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] TLMonitor_20 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@41653.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_35 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41706.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_corrupt(Queue_io_enq_bits_corrupt), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_corrupt(Queue_io_deq_bits_corrupt) ); Queue_33 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@41720.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_param(Queue_1_io_enq_bits_param), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_sink(Queue_1_io_enq_bits_sink), .io_enq_bits_denied(Queue_1_io_enq_bits_denied), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41705.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@41704.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@41655.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@41656.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@41701.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@41707.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@41708.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@41709.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41717.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41716.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41715.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41714.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41713.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41712.4] assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41710.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@41719.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@41721.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@41722.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@41723.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41731.4] assign Queue_1_io_enq_bits_param = 2'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41730.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41729.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41728.4] assign Queue_1_io_enq_bits_sink = 1'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41727.4] assign Queue_1_io_enq_bits_denied = 1'h1; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41726.4] assign Queue_1_io_enq_bits_data = 32'h0; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41725.4] assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@41724.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@41733.4] endmodule module SimpleLazyModule_5( // @[:freechips.rocketchip.system.TinyConfig.fir@41753.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@41754.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@41755.4] output auto_buffer_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input auto_buffer_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [2:0] auto_buffer_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [2:0] auto_buffer_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [3:0] auto_buffer_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [4:0] auto_buffer_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [13:0] auto_buffer_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input [3:0] auto_buffer_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input auto_buffer_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] input auto_buffer_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output auto_buffer_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output [2:0] auto_buffer_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output [1:0] auto_buffer_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output [3:0] auto_buffer_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output [4:0] auto_buffer_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output auto_buffer_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output auto_buffer_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output [31:0] auto_buffer_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] output auto_buffer_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@41756.4] ); wire error_clock; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_reset; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_a_valid; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [2:0] error_auto_in_a_bits_opcode; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [2:0] error_auto_in_a_bits_param; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [3:0] error_auto_in_a_bits_size; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [4:0] error_auto_in_a_bits_source; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [13:0] error_auto_in_a_bits_address; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [3:0] error_auto_in_a_bits_mask; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_a_bits_corrupt; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_d_ready; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [2:0] error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [3:0] error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire [4:0] error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [13:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [13:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] TLError error ( // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.TinyConfig.fir@41761.4] .clock(error_clock), .reset(error_reset), .auto_in_a_ready(error_auto_in_a_ready), .auto_in_a_valid(error_auto_in_a_valid), .auto_in_a_bits_opcode(error_auto_in_a_bits_opcode), .auto_in_a_bits_param(error_auto_in_a_bits_param), .auto_in_a_bits_size(error_auto_in_a_bits_size), .auto_in_a_bits_source(error_auto_in_a_bits_source), .auto_in_a_bits_address(error_auto_in_a_bits_address), .auto_in_a_bits_mask(error_auto_in_a_bits_mask), .auto_in_a_bits_corrupt(error_auto_in_a_bits_corrupt), .auto_in_d_ready(error_auto_in_d_ready), .auto_in_d_valid(error_auto_in_d_valid), .auto_in_d_bits_opcode(error_auto_in_d_bits_opcode), .auto_in_d_bits_size(error_auto_in_d_bits_size), .auto_in_d_bits_source(error_auto_in_d_bits_source), .auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt) ); TLBuffer_7 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@41767.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign error_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@41765.4] assign error_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@41766.4] assign error_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign error_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@41771.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@41772.4] assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@41774.4] assign buffer_auto_out_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_auto_out_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_auto_out_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_auto_out_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_auto_out_d_bits_source = error_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] assign buffer_auto_out_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@41773.4] endmodule module TLMonitor_21( // @[:freechips.rocketchip.system.TinyConfig.fir@41784.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@41785.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@41786.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@41787.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@42987.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@41802.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@41803.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@41806.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@41807.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@41815.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41826.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41827.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41828.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@41830.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@41831.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@41832.6] wire [27:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@41833.6] wire [27:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@41833.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@41834.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@41836.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@41837.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@41839.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@41840.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@41841.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@41842.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@41843.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41845.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41846.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41848.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41849.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@41850.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@41851.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@41852.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41853.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41854.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41855.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41856.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41857.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41858.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41859.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41860.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41861.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41862.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41863.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41864.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@41867.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@41924.6] wire [27:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@41927.8] wire [28:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@41928.8] wire [28:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@41929.8] wire [28:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@41930.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@41931.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41936.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41949.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41950.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41957.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41958.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41964.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41965.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@41970.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41972.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41973.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@41978.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@41979.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41981.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41982.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@41987.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41989.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41990.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@41996.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@42050.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42052.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42053.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@42076.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@42079.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@42087.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42090.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42091.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@42110.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42112.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42113.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@42118.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42120.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42121.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@42135.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@42186.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@42228.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@42229.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@42230.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42232.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42233.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@42239.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@42270.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42272.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42273.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@42287.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@42318.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42320.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42321.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@42335.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@42385.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42387.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42388.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@42393.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@42394.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@42397.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@42398.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@42406.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42417.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42418.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42419.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@42421.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42424.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42425.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@42430.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42432.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42433.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@42463.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@42521.6] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@42580.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@42615.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@42651.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@42711.4] wire [3:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@42716.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@42717.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@42718.4] reg [3:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@42720.4] reg [31:0] _RAND_0; wire [3:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42722.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42723.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@42734.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@42735.4] reg [31:0] _RAND_2; reg [2:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@42736.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@42737.4] reg [31:0] _RAND_4; reg [27:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@42738.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@42739.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@42740.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@42742.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42744.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42745.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@42750.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42752.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42753.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@42758.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42760.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42761.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@42766.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42768.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42769.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@42774.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42776.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42777.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@42784.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@42792.4] wire [12:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@42794.4] wire [5:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@42795.4] wire [5:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@42796.4] wire [3:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@42797.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@42798.4] reg [3:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@42800.4] reg [31:0] _RAND_6; wire [3:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42802.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42803.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@42814.4] reg [31:0] _RAND_7; reg [2:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@42816.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@42817.4] reg [31:0] _RAND_9; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@42820.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@42821.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@42823.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42825.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42826.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@42839.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42841.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42842.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@42847.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42849.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42850.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@42873.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@42882.4] reg [31:0] _RAND_10; reg [3:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@42892.4] reg [31:0] _RAND_11; wire [3:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42894.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42895.4] reg [3:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@42914.4] reg [31:0] _RAND_12; wire [3:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42916.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42917.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@42932.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@42935.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@42937.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@42938.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@42939.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42941.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42942.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@42934.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@42953.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@42955.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@42956.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@42958.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@42928.4 :freechips.rocketchip.system.TinyConfig.fir@42930.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@42936.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@42960.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@42961.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@42962.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42964.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42965.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@42957.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@42948.4 :freechips.rocketchip.system.TinyConfig.fir@42950.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@42959.6] wire _T_704; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@42971.4] wire _T_705; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@42972.4] wire _T_706; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@42973.4] wire _T_707; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@42974.4] wire _T_709; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42976.4] wire _T_710; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42977.4] wire [17:0] _T_711; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@42982.4] wire [17:0] _T_712; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@42983.4] wire [17:0] _T_713; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@42984.4] reg [31:0] _T_714; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@42986.4] reg [31:0] _RAND_13; wire _T_715; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@42989.4] wire _T_716; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@42990.4] wire _T_717; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@42991.4] wire _T_718; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@42992.4] wire _T_719; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@42993.4] wire _T_720; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@42994.4] wire _T_722; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@42996.4] wire _T_723; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@42997.4] wire [31:0] _T_725; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@43003.4] wire _T_728; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@43007.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41938.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@42010.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42093.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@42152.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@42203.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@42253.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@42301.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@42349.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42427.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@42469.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@42527.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@42586.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@42621.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@42657.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@42987.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@41802.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@41803.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@41806.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@41807.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@41815.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41826.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41827.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@41828.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@41830.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@41831.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@41832.6] assign _GEN_18 = {{22'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@41833.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@41833.6] assign _T_32 = _T_31 == 28'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@41834.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@41836.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@41837.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@41839.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@41840.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@41841.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@41842.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@41843.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41845.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41846.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41848.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41849.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@41850.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@41851.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@41852.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41853.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41854.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41855.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41856.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41857.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41858.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41859.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41860.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41861.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@41862.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@41863.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@41864.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@41867.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@41924.6] assign _T_120 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@41927.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@41928.8] assign _T_122 = $signed(_T_121) & $signed(-29'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@41929.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@41930.8] assign _T_124 = $signed(_T_123) == $signed(29'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@41931.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41936.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41949.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41950.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41957.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41958.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41964.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41965.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@41970.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41972.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41973.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@41978.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@41979.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41981.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41982.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@41987.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41989.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41990.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@41996.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@42050.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42052.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42053.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@42076.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@42079.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@42087.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42090.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42091.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@42110.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42112.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42113.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@42118.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42120.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42121.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@42135.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@42186.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@42228.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@42229.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@42230.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42232.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42233.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@42239.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@42270.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42272.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42273.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@42287.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@42318.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42320.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42321.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@42335.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@42385.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42387.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42388.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@42393.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@42394.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@42397.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@42398.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@42406.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42417.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42418.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@42419.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@42421.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42424.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42425.8] assign _T_400 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@42430.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42432.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42433.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@42463.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@42521.6] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@42580.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@42615.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@42651.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@42711.4] assign _T_542 = _T_30[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@42716.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@42717.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@42718.4] assign _T_548 = _T_546 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42722.4] assign _T_549 = _T_546 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42723.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@42739.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@42740.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@42742.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42744.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42745.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@42750.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42752.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42753.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@42758.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42760.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42761.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@42766.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42768.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42769.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@42774.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42776.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42777.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@42784.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@42792.4] assign _T_588 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@42794.4] assign _T_589 = _T_588[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@42795.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@42796.4] assign _T_591 = _T_590[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@42797.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@42798.4] assign _T_596 = _T_594 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42802.4] assign _T_597 = _T_594 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42803.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@42820.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@42821.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@42823.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42825.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42826.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@42839.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42841.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42842.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@42847.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42849.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42850.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@42873.4] assign _T_651 = _T_649 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42894.4] assign _T_652 = _T_649 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42895.4] assign _T_670 = _T_668 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@42916.4] assign _T_671 = _T_668 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@42917.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@42932.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@42935.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@42937.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@42938.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@42939.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42941.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42942.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@42934.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@42953.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@42955.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@42956.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@42958.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@42928.4 :freechips.rocketchip.system.TinyConfig.fir@42930.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@42936.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@42960.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@42961.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@42962.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42964.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42965.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@42957.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@42948.4 :freechips.rocketchip.system.TinyConfig.fir@42950.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@42959.6] assign _T_704 = _T_679 != _T_690; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@42971.4] assign _T_705 = _T_679 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@42972.4] assign _T_706 = _T_705 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@42973.4] assign _T_707 = _T_704 | _T_706; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@42974.4] assign _T_709 = _T_707 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42976.4] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42977.4] assign _T_711 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@42982.4] assign _T_712 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@42983.4] assign _T_713 = _T_711 & _T_712; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@42984.4] assign _T_715 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@42989.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@42990.4] assign _T_717 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@42991.4] assign _T_718 = _T_716 | _T_717; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@42992.4] assign _T_719 = _T_714 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@42993.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@42994.4] assign _T_722 = _T_720 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@42996.4] assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@42997.4] assign _T_725 = _T_714 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@43003.4] assign _T_728 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@43007.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41938.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@42010.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42093.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@42152.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@42203.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@42253.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@42301.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@42349.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42427.10] assign _GEN_119 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@42469.10] assign _GEN_125 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@42527.10] assign _GEN_131 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@42586.10] assign _GEN_133 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@42621.10] assign _GEN_135 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@42657.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[27:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_639 = _RAND_10[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_649 = _RAND_11[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_668 = _RAND_12[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_714 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 4'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 4'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 4'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 4'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_713; end if (reset) begin _T_649 <= 4'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 4'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 4'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 4'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_714 <= 32'h0; end else begin if (_T_728) begin _T_714 <= 32'h0; end else begin _T_714 <= _T_725; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41938.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@41939.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:341:61)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@41945.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@41946.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@41953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:341:61)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41960.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@41961.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41967.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@41968.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:341:61)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41975.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@41976.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41984.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@41985.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:341:61)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41992.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@41993.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@42010.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@42011.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:341:61)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@42017.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@42018.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@42024.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@42025.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:341:61)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@42032.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@42033.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@42039.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@42040.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:341:61)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@42047.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@42048.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:341:61)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42055.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@42056.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@42064.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@42065.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:341:61)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@42072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@42073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42093.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@42094.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@42100.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@42101.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@42107.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@42108.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:341:61)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42115.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@42116.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42123.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@42124.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:341:61)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@42131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@42132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@42152.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@42153.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@42159.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@42160.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@42166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@42167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:341:61)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@42174.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@42175.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@42182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@42183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@42203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@42204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@42210.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@42211.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@42217.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@42218.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:341:61)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@42225.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@42226.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42235.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@42236.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@42253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@42254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@42260.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@42261.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@42267.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@42268.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:341:61)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42275.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@42276.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@42283.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@42284.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@42301.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@42302.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@42308.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@42309.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@42315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@42316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:341:61)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42323.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@42324.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@42331.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@42332.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Plic.scala:341:61)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@42349.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@42350.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@42356.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@42357.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:341:61)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@42363.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@42364.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:341:61)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@42371.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@42372.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:341:61)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@42379.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@42380.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:341:61)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42390.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@42391.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42427.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@42428.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:341:61)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42435.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@42436.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@42469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@42470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:341:61)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@42476.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@42477.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:341:61)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@42484.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@42485.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@42527.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@42528.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:341:61)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@42534.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@42535.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:341:61)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@42542.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@42543.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@42586.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@42587.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@42621.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@42622.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:341:61)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@42657.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@42658.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42747.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@42748.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42755.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@42756.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42763.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@42764.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42771.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@42772.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42779.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@42780.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42828.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@42829.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42844.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@42845.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:341:61)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42852.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@42853.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:341:61)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42944.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@42945.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:341:61)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42967.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@42968.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_710) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:341:61)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42979.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_710) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@42980.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_723) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Plic.scala:341:61)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@42999.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_723) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@43000.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Repeater_1( // @[:freechips.rocketchip.system.TinyConfig.fir@43012.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@43013.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@43014.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output io_full, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [27:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [27:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@43015.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@43020.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_2; reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_3; reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_4; reg [27:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_5; reg [3:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_6; reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@43021.4] reg [31:0] _RAND_7; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@43024.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43030.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@43031.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43036.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@43037.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@43038.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@43024.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43030.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@43031.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43036.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@43037.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@43038.4] assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.TinyConfig.fir@43029.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@43026.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@43023.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@43028.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[27:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; saved_corrupt = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end if (_T_5) begin saved_corrupt <= io_enq_bits_corrupt; end end endmodule module TLFragmenter( // @[:freechips.rocketchip.system.TinyConfig.fir@43043.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@43044.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@43045.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [9:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [9:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@43046.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [27:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [3:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [27:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire [3:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] reg [3:0] _T_14; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.TinyConfig.fir@43106.4] reg [31:0] _RAND_0; reg [2:0] _T_15; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.TinyConfig.fir@43107.4] reg [31:0] _RAND_1; reg _T_16; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.TinyConfig.fir@43108.4] reg [31:0] _RAND_2; wire [3:0] _T_17; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@43109.4] wire _T_18; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@43110.4] wire _T_19; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@43111.4] wire [3:0] _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@43113.4] wire [2:0] _T_22; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@43114.4] wire [4:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43116.4] wire [1:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43117.4] wire [1:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43118.4] wire _T_27; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@43119.4] wire _T_39; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@43135.4] wire _T_40; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@43136.4] wire [5:0] _T_41; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@43137.4] wire [5:0] _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@43138.4] wire [5:0] _T_42; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@43138.4] wire [6:0] _T_43; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@43139.4] wire [6:0] _T_44; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@43140.4] wire [6:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43141.4] wire [6:0] _T_46; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@43142.4] wire [6:0] _T_47; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@43143.4] wire [2:0] _T_48; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@43144.4] wire [3:0] _T_49; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@43145.4] wire _T_50; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@43146.4] wire [3:0] _GEN_8; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43147.4] wire [3:0] _T_51; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43147.4] wire [1:0] _T_52; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@43148.4] wire [1:0] _T_53; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@43149.4] wire _T_54; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@43150.4] wire [1:0] _T_55; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43151.4] wire _T_56; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@43152.4] wire [2:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43154.4] wire _T_64; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@43167.4] wire _T_66; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@43169.4] wire _T_67; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@43170.4] wire _T_68; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@43171.4] wire _T_59; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43155.4] wire [3:0] _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@43157.6] wire [3:0] _T_61; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@43158.6] wire _T_63; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@43163.8] wire _T_69; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@43173.4] wire _T_91; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@43206.4] wire [2:0] _T_92; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@43207.4] wire [12:0] _T_94; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43209.4] wire [5:0] _T_95; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43210.4] wire [5:0] _T_96; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43211.4] wire [8:0] _T_98; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43213.4] wire [1:0] _T_99; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43214.4] wire [1:0] _T_100; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43215.4] wire _T_101; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@43216.4] wire _T_102; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@43217.4] reg [3:0] _T_104; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.TinyConfig.fir@43219.4] reg [31:0] _RAND_3; wire _T_105; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@43220.4] wire [3:0] _T_106; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@43221.4] wire [3:0] _T_108; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@43223.4] wire [3:0] _T_109; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@43224.4] wire [3:0] _T_110; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@43225.4] wire [3:0] _T_113; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@43228.4] reg _T_120; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@43235.4] reg [31:0] _RAND_4; wire _GEN_5; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@43236.4] wire _T_122; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@43240.4] wire _T_13_a_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@43102.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@43249.4] wire _T_123; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43241.4] wire _T_124; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@43245.4] wire _T_125; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@43246.4] wire [5:0] _T_127; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@43250.4] wire [5:0] _T_128; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@43251.4] wire [5:0] _T_129; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@43252.4] wire [5:0] _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@43253.4] wire [5:0] _T_130; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@43253.4] wire [5:0] _T_131; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@43254.4] wire [5:0] _T_132; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@43255.4] wire [27:0] _GEN_11; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@43256.4] wire [5:0] _T_134; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43258.4] wire _T_136; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@43262.4] wire _T_138; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@43264.4] wire _T_140; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43266.4] wire _T_141; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43267.4] wire _T_143; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@43274.4] wire _T_144; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@43275.4] wire _T_146; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43277.4] wire _T_147; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43278.4] TLMonitor_21 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@43053.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); Repeater_1 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@43181.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_full(Repeater_io_full), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask), .io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt) ); assign _T_17 = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@43109.4] assign _T_18 = _T_14 == 4'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@43110.4] assign _T_19 = _T_17 == 4'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@43111.4] assign _T_21 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@43113.4] assign _T_22 = _T_21[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@43114.4] assign _T_24 = 5'h3 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43116.4] assign _T_25 = _T_24[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43117.4] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43118.4] assign _T_27 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@43119.4] assign _T_39 = _T_22[2:2]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@43135.4] assign _T_40 = _T_27 ? 1'h1 : _T_39; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@43136.4] assign _T_41 = {_T_17, 2'h0}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@43137.4] assign _GEN_7 = {{4'd0}, _T_26}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@43138.4] assign _T_42 = _T_41 | _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@43138.4] assign _T_43 = {_T_42, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@43139.4] assign _T_44 = _T_43 | 7'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@43140.4] assign _T_45 = {1'h0,_T_42}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43141.4] assign _T_46 = ~ _T_45; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@43142.4] assign _T_47 = _T_44 & _T_46; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@43143.4] assign _T_48 = _T_47[6:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@43144.4] assign _T_49 = _T_47[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@43145.4] assign _T_50 = _T_48 != 3'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@43146.4] assign _GEN_8 = {{1'd0}, _T_48}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43147.4] assign _T_51 = _GEN_8 | _T_49; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43147.4] assign _T_52 = _T_51[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@43148.4] assign _T_53 = _T_51[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@43149.4] assign _T_54 = _T_52 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@43150.4] assign _T_55 = _T_52 | _T_53; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@43151.4] assign _T_56 = _T_55[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@43152.4] assign _T_58 = {_T_50,_T_54,_T_56}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43154.4] assign _T_64 = _T_27 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@43167.4] assign _T_66 = _T_19 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@43169.4] assign _T_67 = _T_64 & _T_66; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@43170.4] assign _T_68 = auto_in_d_ready | _T_67; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@43171.4] assign _T_59 = _T_68 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43155.4] assign _GEN_9 = {{3'd0}, _T_40}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@43157.6] assign _T_61 = _T_14 - _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@43158.6] assign _T_63 = auto_out_d_bits_source[4]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@43163.8] assign _T_69 = _T_67 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@43173.4] assign _T_91 = Repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@43206.4] assign _T_92 = _T_91 ? 3'h2 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@43207.4] assign _T_94 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43209.4] assign _T_95 = _T_94[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43210.4] assign _T_96 = ~ _T_95; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43211.4] assign _T_98 = 9'h3 << _T_92; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43213.4] assign _T_99 = _T_98[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43214.4] assign _T_100 = ~ _T_99; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43215.4] assign _T_101 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@43216.4] assign _T_102 = _T_101 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@43217.4] assign _T_105 = _T_104 == 4'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@43220.4] assign _T_106 = _T_96[5:2]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@43221.4] assign _T_108 = _T_104 - 4'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@43223.4] assign _T_109 = _T_105 ? _T_106 : _T_108; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@43224.4] assign _T_110 = ~ _T_109; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@43225.4] assign _T_113 = ~ _T_110; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@43228.4] assign _GEN_5 = _T_105 ? _T_16 : _T_120; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@43236.4] assign _T_122 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@43240.4] assign _T_13_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@43102.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@43249.4] assign _T_123 = auto_out_a_ready & _T_13_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@43241.4] assign _T_124 = _T_102 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@43245.4] assign _T_125 = _T_113 != 4'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@43246.4] assign _T_127 = {_T_109, 2'h0}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@43250.4] assign _T_128 = ~ _T_96; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@43251.4] assign _T_129 = _T_127 | _T_128; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@43252.4] assign _GEN_10 = {{4'd0}, _T_100}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@43253.4] assign _T_130 = _T_129 | _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@43253.4] assign _T_131 = _T_130 | 6'h3; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@43254.4] assign _T_132 = ~ _T_131; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@43255.4] assign _GEN_11 = {{22'd0}, _T_132}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@43256.4] assign _T_134 = {Repeater_io_deq_bits_source,_T_122}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43258.4] assign _T_136 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@43262.4] assign _T_138 = _T_136 | _T_124; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@43264.4] assign _T_140 = _T_138 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43266.4] assign _T_141 = _T_140 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43267.4] assign _T_143 = Repeater_io_deq_bits_mask == 4'hf; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@43274.4] assign _T_144 = _T_136 | _T_143; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@43275.4] assign _T_146 = _T_144 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43277.4] assign _T_147 = _T_146 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43278.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_in_d_valid = auto_out_d_valid & _T_69; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43105.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_size = _T_92[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_source = {_T_134,_T_113}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_11; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_mask = Repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign auto_out_d_ready = auto_in_d_ready | _T_67; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43104.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@43055.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@43056.4] assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_69; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@43101.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@43183.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@43184.4] assign Repeater_io_repeat = _T_124 & _T_125; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.TinyConfig.fir@43248.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@43185.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@43249.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_14 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_15 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_16 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_104 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_120 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_14 <= 4'h0; end else begin if (_T_59) begin if (_T_18) begin _T_14 <= _T_17; end else begin _T_14 <= _T_61; end end end if (_T_59) begin if (_T_18) begin _T_15 <= _T_58; end end if (reset) begin _T_16 <= 1'h0; end else begin if (_T_59) begin if (_T_18) begin _T_16 <= _T_63; end end end if (reset) begin _T_104 <= 4'h0; end else begin if (_T_123) begin _T_104 <= _T_113; end end if (_T_105) begin _T_120 <= _T_16; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_141) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43269.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_141) begin $fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@43270.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_147) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43280.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_147) begin $fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@43281.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SimpleLazyModule_6( // @[:freechips.rocketchip.system.TinyConfig.fir@43304.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@43305.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@43306.4] output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [27:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [3:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [31:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [31:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [9:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [27:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [3:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output [31:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [9:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] input [31:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@43307.4] ); wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [27:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [27:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] TLFragmenter fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@43312.4] .clock(fragmenter_clock), .reset(fragmenter_reset), .auto_in_a_ready(fragmenter_auto_in_a_ready), .auto_in_a_valid(fragmenter_auto_in_a_valid), .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode), .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param), .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size), .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source), .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address), .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask), .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt), .auto_in_d_ready(fragmenter_auto_in_d_ready), .auto_in_d_valid(fragmenter_auto_in_d_valid), .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode), .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size), .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source), .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data), .auto_out_a_ready(fragmenter_auto_out_a_ready), .auto_out_a_valid(fragmenter_auto_out_a_valid), .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode), .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param), .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size), .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source), .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address), .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask), .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt), .auto_out_d_ready(fragmenter_auto_out_d_ready), .auto_out_d_valid(fragmenter_auto_out_d_valid), .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode), .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size), .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source), .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data) ); assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@43316.4] assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@43317.4] assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@43319.4] assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@43318.4] endmodule module TLMonitor_22( // @[:freechips.rocketchip.system.TinyConfig.fir@43329.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@43330.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@43331.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [25:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@43332.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@44521.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43347.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43348.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@43351.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43352.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43360.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43371.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43372.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43373.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43375.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43376.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43377.6] wire [25:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@43378.6] wire [25:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@43378.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@43379.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@43381.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@43382.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@43384.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@43385.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@43386.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@43387.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@43388.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43390.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43391.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43393.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43394.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@43395.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@43396.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@43397.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43398.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43399.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43400.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43401.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43402.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43403.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43404.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43405.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43406.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43407.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43408.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43409.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43412.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@43469.6] wire [25:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@43472.8] wire [26:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@43473.8] wire [26:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@43474.8] wire [26:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@43475.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@43476.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43481.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43494.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43495.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43502.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43503.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43509.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43510.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@43515.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43517.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43518.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@43523.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@43524.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43526.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43527.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@43532.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43534.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43535.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@43541.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@43595.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43597.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43598.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@43621.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@43624.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@43632.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43635.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43636.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@43655.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43657.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43658.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@43663.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43665.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43666.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@43680.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@43731.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@43773.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@43774.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@43775.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43777.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43778.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@43784.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@43815.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43817.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43818.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@43832.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@43863.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43865.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43866.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@43880.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@43930.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43932.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43933.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43938.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43939.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@43942.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43943.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43951.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43962.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43963.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43964.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@43966.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43969.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43970.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@43975.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43977.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43978.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@44008.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@44066.6] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@44125.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@44160.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@44196.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@44256.4] wire [3:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@44261.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@44262.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@44263.4] reg [3:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@44265.4] reg [31:0] _RAND_0; wire [3:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44267.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44268.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@44279.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@44280.4] reg [31:0] _RAND_2; reg [2:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@44281.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@44282.4] reg [31:0] _RAND_4; reg [25:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@44283.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@44284.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@44285.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@44287.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44289.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44290.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@44295.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44297.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44298.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@44303.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44305.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44306.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@44311.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44313.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44314.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@44319.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44321.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44322.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@44329.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@44337.4] wire [12:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44339.4] wire [5:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44340.4] wire [5:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44341.4] wire [3:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@44342.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@44343.4] reg [3:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@44345.4] reg [31:0] _RAND_6; wire [3:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44347.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44348.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@44359.4] reg [31:0] _RAND_7; reg [2:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@44361.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@44362.4] reg [31:0] _RAND_9; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@44365.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@44366.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@44368.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44370.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44371.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@44384.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44386.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44387.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@44392.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44394.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44395.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@44418.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@44427.4] reg [31:0] _RAND_10; reg [3:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@44437.4] reg [31:0] _RAND_11; wire [3:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44439.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44440.4] reg [3:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@44459.4] reg [31:0] _RAND_12; wire [3:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44461.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44462.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@44477.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@44480.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@44482.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@44483.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@44484.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44486.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44487.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@44479.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@44498.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@44500.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@44501.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@44503.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@44473.4 :freechips.rocketchip.system.TinyConfig.fir@44475.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@44481.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@44505.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@44506.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@44507.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44509.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44510.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@44502.4] wire [17:0] _T_704; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@44516.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@44493.4 :freechips.rocketchip.system.TinyConfig.fir@44495.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@44504.6] wire [17:0] _T_705; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@44517.4] wire [17:0] _T_706; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@44518.4] reg [31:0] _T_707; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@44520.4] reg [31:0] _RAND_13; wire _T_708; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@44523.4] wire _T_709; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@44524.4] wire _T_710; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@44525.4] wire _T_711; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@44526.4] wire _T_712; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@44527.4] wire _T_713; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@44528.4] wire _T_715; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44530.4] wire _T_716; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44531.4] wire [31:0] _T_718; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@44537.4] wire _T_721; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@44541.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43483.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@43555.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43638.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@43697.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@43748.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@43798.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@43846.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@43894.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43972.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@44014.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@44072.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@44131.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@44166.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@44202.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@44521.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43347.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43348.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@43351.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43352.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43360.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43371.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43372.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43373.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@43375.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@43376.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@43377.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@43378.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@43378.6] assign _T_32 = _T_31 == 26'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@43379.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@43381.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@43382.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@43384.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@43385.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@43386.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@43387.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@43388.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43390.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43391.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43393.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43394.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@43395.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@43396.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@43397.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43398.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43399.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43400.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43401.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43402.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43403.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43404.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43405.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43406.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@43407.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@43408.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@43409.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@43412.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@43469.6] assign _T_120 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@43472.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@43473.8] assign _T_122 = $signed(_T_121) & $signed(-27'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@43474.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@43475.8] assign _T_124 = $signed(_T_123) == $signed(27'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@43476.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43481.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43494.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43495.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43502.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43503.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43509.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43510.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@43515.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43517.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43518.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@43523.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@43524.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43526.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43527.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@43532.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43534.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43535.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@43541.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@43595.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43597.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43598.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@43621.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@43624.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@43632.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43635.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43636.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@43655.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43657.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43658.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@43663.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43665.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43666.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@43680.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@43731.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@43773.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@43774.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@43775.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43777.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43778.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@43784.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@43815.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43817.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43818.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@43832.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@43863.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43865.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43866.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@43880.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@43930.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43932.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43933.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43938.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@43939.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@43942.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43943.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@43951.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43962.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43963.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@43964.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@43966.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43969.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43970.8] assign _T_400 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@43975.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43977.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43978.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@44008.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@44066.6] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@44125.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@44160.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@44196.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@44256.4] assign _T_542 = _T_30[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@44261.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@44262.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@44263.4] assign _T_548 = _T_546 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44267.4] assign _T_549 = _T_546 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44268.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@44284.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@44285.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@44287.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44289.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44290.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@44295.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44297.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44298.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@44303.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44305.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44306.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@44311.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44313.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44314.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@44319.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44321.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44322.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@44329.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@44337.4] assign _T_588 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44339.4] assign _T_589 = _T_588[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44340.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44341.4] assign _T_591 = _T_590[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@44342.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@44343.4] assign _T_596 = _T_594 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44347.4] assign _T_597 = _T_594 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44348.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@44365.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@44366.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@44368.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44370.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44371.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@44384.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44386.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44387.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@44392.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44394.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44395.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@44418.4] assign _T_651 = _T_649 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44439.4] assign _T_652 = _T_649 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44440.4] assign _T_670 = _T_668 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@44461.4] assign _T_671 = _T_668 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@44462.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@44477.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@44480.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@44482.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@44483.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@44484.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44486.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44487.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@44479.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@44498.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@44500.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@44501.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@44503.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@44473.4 :freechips.rocketchip.system.TinyConfig.fir@44475.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@44481.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@44505.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@44506.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@44507.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44509.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44510.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@44502.4] assign _T_704 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@44516.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@44493.4 :freechips.rocketchip.system.TinyConfig.fir@44495.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@44504.6] assign _T_705 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@44517.4] assign _T_706 = _T_704 & _T_705; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@44518.4] assign _T_708 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@44523.4] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@44524.4] assign _T_710 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@44525.4] assign _T_711 = _T_709 | _T_710; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@44526.4] assign _T_712 = _T_707 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@44527.4] assign _T_713 = _T_711 | _T_712; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@44528.4] assign _T_715 = _T_713 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44530.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44531.4] assign _T_718 = _T_707 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@44537.4] assign _T_721 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@44541.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43483.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@43555.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43638.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@43697.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@43748.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@43798.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@43846.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@43894.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43972.10] assign _GEN_119 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@44014.10] assign _GEN_125 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@44072.10] assign _GEN_131 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@44131.10] assign _GEN_133 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@44166.10] assign _GEN_135 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@44202.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[25:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_639 = _RAND_10[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_649 = _RAND_11[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_668 = _RAND_12[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_707 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 4'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 4'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 4'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 4'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_706; end if (reset) begin _T_649 <= 4'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 4'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 4'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 4'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_707 <= 32'h0; end else begin if (_T_721) begin _T_707 <= 32'h0; end else begin _T_707 <= _T_718; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43483.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@43484.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:106:63)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@43490.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@43491.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43497.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@43498.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:106:63)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43505.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@43506.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43512.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@43513.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:106:63)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43520.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@43521.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43529.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@43530.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:106:63)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43537.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@43538.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@43555.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@43556.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:106:63)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@43562.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@43563.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@43569.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@43570.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:106:63)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@43577.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@43578.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@43584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@43585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:106:63)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@43592.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@43593.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:106:63)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43600.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@43601.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@43609.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@43610.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:106:63)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@43617.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@43618.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@43639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@43645.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@43646.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@43652.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@43653.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:106:63)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43660.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@43661.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43668.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@43669.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:106:63)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@43676.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@43677.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@43697.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@43698.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@43704.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@43705.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@43711.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@43712.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:106:63)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@43719.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@43720.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@43727.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@43728.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@43748.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@43749.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@43755.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@43756.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@43762.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@43763.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:106:63)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@43770.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@43771.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43780.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@43781.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@43798.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@43799.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@43805.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@43806.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@43812.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@43813.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:106:63)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43820.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@43821.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@43828.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@43829.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@43846.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@43847.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@43853.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@43854.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@43860.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@43861.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:106:63)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43868.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@43869.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@43876.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@43877.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CLINT.scala:106:63)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@43894.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@43895.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@43901.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@43902.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:106:63)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@43908.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@43909.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:106:63)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@43916.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@43917.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:106:63)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@43924.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@43925.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:106:63)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43935.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@43936.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43972.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@43973.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:106:63)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43980.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@43981.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@44014.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@44015.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:106:63)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@44021.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@44022.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:106:63)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@44029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@44030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@44072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@44073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:106:63)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@44079.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@44080.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:106:63)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@44087.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@44088.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@44131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@44132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@44166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@44167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@44202.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@44203.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44292.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@44293.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44300.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@44301.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44308.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@44309.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44316.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@44317.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44324.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@44325.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44373.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@44374.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44389.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@44390.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:106:63)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44397.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@44398.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:106:63)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44489.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@44490.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:106:63)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44512.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@44513.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_716) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CLINT.scala:106:63)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44533.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_716) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@44534.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Repeater_2( // @[:freechips.rocketchip.system.TinyConfig.fir@44546.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@44547.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@44548.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output io_full, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [25:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [25:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@44549.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@44554.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_2; reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_3; reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_4; reg [25:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_5; reg [3:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_6; reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@44555.4] reg [31:0] _RAND_7; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@44558.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44564.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@44565.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44570.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@44571.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@44572.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@44558.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44564.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@44565.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44570.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@44571.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@44572.4] assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.TinyConfig.fir@44563.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@44560.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@44557.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@44562.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[25:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; saved_corrupt = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end if (_T_5) begin saved_corrupt <= io_enq_bits_corrupt; end end endmodule module TLFragmenter_1( // @[:freechips.rocketchip.system.TinyConfig.fir@44577.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@44578.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@44579.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [25:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [9:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [25:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [9:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@44580.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [25:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [25:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [3:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [25:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire [3:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] reg [3:0] _T_14; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.TinyConfig.fir@44640.4] reg [31:0] _RAND_0; reg [2:0] _T_15; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.TinyConfig.fir@44641.4] reg [31:0] _RAND_1; reg _T_16; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.TinyConfig.fir@44642.4] reg [31:0] _RAND_2; wire [3:0] _T_17; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@44643.4] wire _T_18; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@44644.4] wire _T_19; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@44645.4] wire [3:0] _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@44647.4] wire [2:0] _T_22; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@44648.4] wire [4:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44650.4] wire [1:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44651.4] wire [1:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44652.4] wire _T_27; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@44653.4] wire _T_39; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@44669.4] wire _T_40; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@44670.4] wire [5:0] _T_41; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@44671.4] wire [5:0] _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@44672.4] wire [5:0] _T_42; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@44672.4] wire [6:0] _T_43; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@44673.4] wire [6:0] _T_44; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@44674.4] wire [6:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44675.4] wire [6:0] _T_46; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@44676.4] wire [6:0] _T_47; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@44677.4] wire [2:0] _T_48; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@44678.4] wire [3:0] _T_49; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@44679.4] wire _T_50; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@44680.4] wire [3:0] _GEN_8; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44681.4] wire [3:0] _T_51; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44681.4] wire [1:0] _T_52; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@44682.4] wire [1:0] _T_53; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@44683.4] wire _T_54; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@44684.4] wire [1:0] _T_55; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44685.4] wire _T_56; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@44686.4] wire [2:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44688.4] wire _T_64; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@44701.4] wire _T_66; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@44703.4] wire _T_67; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@44704.4] wire _T_68; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@44705.4] wire _T_59; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44689.4] wire [3:0] _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@44691.6] wire [3:0] _T_61; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@44692.6] wire _T_63; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@44697.8] wire _T_69; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@44707.4] wire _T_91; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@44740.4] wire [2:0] _T_92; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@44741.4] wire [12:0] _T_94; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44743.4] wire [5:0] _T_95; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44744.4] wire [5:0] _T_96; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44745.4] wire [8:0] _T_98; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44747.4] wire [1:0] _T_99; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44748.4] wire [1:0] _T_100; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44749.4] wire _T_101; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@44750.4] wire _T_102; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@44751.4] reg [3:0] _T_104; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.TinyConfig.fir@44753.4] reg [31:0] _RAND_3; wire _T_105; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@44754.4] wire [3:0] _T_106; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@44755.4] wire [3:0] _T_108; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@44757.4] wire [3:0] _T_109; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@44758.4] wire [3:0] _T_110; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@44759.4] wire [3:0] _T_113; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@44762.4] reg _T_120; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@44769.4] reg [31:0] _RAND_4; wire _GEN_5; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@44770.4] wire _T_122; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@44774.4] wire _T_13_a_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@44636.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@44783.4] wire _T_123; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44775.4] wire _T_124; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@44779.4] wire _T_125; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@44780.4] wire [5:0] _T_127; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@44784.4] wire [5:0] _T_128; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@44785.4] wire [5:0] _T_129; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@44786.4] wire [5:0] _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@44787.4] wire [5:0] _T_130; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@44787.4] wire [5:0] _T_131; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@44788.4] wire [5:0] _T_132; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@44789.4] wire [25:0] _GEN_11; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@44790.4] wire [5:0] _T_134; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44792.4] wire _T_136; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@44796.4] wire _T_138; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@44798.4] wire _T_140; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44800.4] wire _T_141; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44801.4] wire _T_143; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@44808.4] wire _T_144; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@44809.4] wire _T_146; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44811.4] wire _T_147; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44812.4] TLMonitor_22 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@44587.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); Repeater_2 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@44715.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_full(Repeater_io_full), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask), .io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt) ); assign _T_17 = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@44643.4] assign _T_18 = _T_14 == 4'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@44644.4] assign _T_19 = _T_17 == 4'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@44645.4] assign _T_21 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@44647.4] assign _T_22 = _T_21[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@44648.4] assign _T_24 = 5'h3 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44650.4] assign _T_25 = _T_24[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44651.4] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44652.4] assign _T_27 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@44653.4] assign _T_39 = _T_22[2:2]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@44669.4] assign _T_40 = _T_27 ? 1'h1 : _T_39; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@44670.4] assign _T_41 = {_T_17, 2'h0}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@44671.4] assign _GEN_7 = {{4'd0}, _T_26}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@44672.4] assign _T_42 = _T_41 | _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@44672.4] assign _T_43 = {_T_42, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@44673.4] assign _T_44 = _T_43 | 7'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@44674.4] assign _T_45 = {1'h0,_T_42}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44675.4] assign _T_46 = ~ _T_45; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@44676.4] assign _T_47 = _T_44 & _T_46; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@44677.4] assign _T_48 = _T_47[6:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@44678.4] assign _T_49 = _T_47[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@44679.4] assign _T_50 = _T_48 != 3'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@44680.4] assign _GEN_8 = {{1'd0}, _T_48}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44681.4] assign _T_51 = _GEN_8 | _T_49; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44681.4] assign _T_52 = _T_51[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@44682.4] assign _T_53 = _T_51[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@44683.4] assign _T_54 = _T_52 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@44684.4] assign _T_55 = _T_52 | _T_53; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@44685.4] assign _T_56 = _T_55[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@44686.4] assign _T_58 = {_T_50,_T_54,_T_56}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44688.4] assign _T_64 = _T_27 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@44701.4] assign _T_66 = _T_19 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@44703.4] assign _T_67 = _T_64 & _T_66; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@44704.4] assign _T_68 = auto_in_d_ready | _T_67; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@44705.4] assign _T_59 = _T_68 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44689.4] assign _GEN_9 = {{3'd0}, _T_40}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@44691.6] assign _T_61 = _T_14 - _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@44692.6] assign _T_63 = auto_out_d_bits_source[4]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@44697.8] assign _T_69 = _T_67 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@44707.4] assign _T_91 = Repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@44740.4] assign _T_92 = _T_91 ? 3'h2 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@44741.4] assign _T_94 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44743.4] assign _T_95 = _T_94[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44744.4] assign _T_96 = ~ _T_95; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44745.4] assign _T_98 = 9'h3 << _T_92; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44747.4] assign _T_99 = _T_98[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44748.4] assign _T_100 = ~ _T_99; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44749.4] assign _T_101 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@44750.4] assign _T_102 = _T_101 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@44751.4] assign _T_105 = _T_104 == 4'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@44754.4] assign _T_106 = _T_96[5:2]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@44755.4] assign _T_108 = _T_104 - 4'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@44757.4] assign _T_109 = _T_105 ? _T_106 : _T_108; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@44758.4] assign _T_110 = ~ _T_109; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@44759.4] assign _T_113 = ~ _T_110; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@44762.4] assign _GEN_5 = _T_105 ? _T_16 : _T_120; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@44770.4] assign _T_122 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@44774.4] assign _T_13_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@44636.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@44783.4] assign _T_123 = auto_out_a_ready & _T_13_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@44775.4] assign _T_124 = _T_102 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@44779.4] assign _T_125 = _T_113 != 4'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@44780.4] assign _T_127 = {_T_109, 2'h0}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@44784.4] assign _T_128 = ~ _T_96; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@44785.4] assign _T_129 = _T_127 | _T_128; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@44786.4] assign _GEN_10 = {{4'd0}, _T_100}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@44787.4] assign _T_130 = _T_129 | _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@44787.4] assign _T_131 = _T_130 | 6'h3; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@44788.4] assign _T_132 = ~ _T_131; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@44789.4] assign _GEN_11 = {{20'd0}, _T_132}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@44790.4] assign _T_134 = {Repeater_io_deq_bits_source,_T_122}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44792.4] assign _T_136 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@44796.4] assign _T_138 = _T_136 | _T_124; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@44798.4] assign _T_140 = _T_138 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44800.4] assign _T_141 = _T_140 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44801.4] assign _T_143 = Repeater_io_deq_bits_mask == 4'hf; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@44808.4] assign _T_144 = _T_136 | _T_143; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@44809.4] assign _T_146 = _T_144 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44811.4] assign _T_147 = _T_146 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44812.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_in_d_valid = auto_out_d_valid & _T_69; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44639.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_size = _T_92[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_source = {_T_134,_T_113}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_11; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_mask = Repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign auto_out_d_ready = auto_in_d_ready | _T_67; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44638.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@44589.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@44590.4] assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_69; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@44635.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@44717.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@44718.4] assign Repeater_io_repeat = _T_124 & _T_125; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.TinyConfig.fir@44782.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@44719.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@44783.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_14 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_15 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_16 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_104 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_120 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_14 <= 4'h0; end else begin if (_T_59) begin if (_T_18) begin _T_14 <= _T_17; end else begin _T_14 <= _T_61; end end end if (_T_59) begin if (_T_18) begin _T_15 <= _T_58; end end if (reset) begin _T_16 <= 1'h0; end else begin if (_T_59) begin if (_T_18) begin _T_16 <= _T_63; end end end if (reset) begin _T_104 <= 4'h0; end else begin if (_T_123) begin _T_104 <= _T_113; end end if (_T_105) begin _T_120 <= _T_16; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_141) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44803.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_141) begin $fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@44804.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_147) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44814.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_147) begin $fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@44815.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SimpleLazyModule_7( // @[:freechips.rocketchip.system.TinyConfig.fir@44838.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@44839.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@44840.4] output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [25:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [3:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [31:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [31:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [9:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [25:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [3:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output [31:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [9:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] input [31:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@44841.4] ); wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [25:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [25:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] TLFragmenter_1 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@44846.4] .clock(fragmenter_clock), .reset(fragmenter_reset), .auto_in_a_ready(fragmenter_auto_in_a_ready), .auto_in_a_valid(fragmenter_auto_in_a_valid), .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode), .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param), .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size), .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source), .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address), .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask), .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt), .auto_in_d_ready(fragmenter_auto_in_d_ready), .auto_in_d_valid(fragmenter_auto_in_d_valid), .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode), .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size), .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source), .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data), .auto_out_a_ready(fragmenter_auto_out_a_ready), .auto_out_a_valid(fragmenter_auto_out_a_valid), .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode), .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param), .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size), .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source), .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address), .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask), .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt), .auto_out_d_ready(fragmenter_auto_out_d_ready), .auto_out_d_valid(fragmenter_auto_out_d_valid), .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode), .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size), .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source), .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data) ); assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@44850.4] assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@44851.4] assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@44853.4] assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@44852.4] endmodule module TLMonitor_23( // @[:freechips.rocketchip.system.TinyConfig.fir@44863.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@44864.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@44865.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [11:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@44866.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@46055.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@44881.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@44882.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@44885.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@44886.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@44894.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44905.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44906.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44907.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44909.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44910.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44911.6] wire [11:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@44912.6] wire [11:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@44912.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@44913.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@44915.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@44916.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@44918.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@44919.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@44920.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@44921.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@44922.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44924.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44925.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44927.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44928.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@44929.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@44930.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@44931.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44932.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44933.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44934.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44935.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44936.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44937.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44938.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44939.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44940.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44941.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44942.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44943.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44946.6] wire [12:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@44950.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@45003.6] wire [12:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@45008.8] wire [12:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@45009.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@45010.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45015.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45028.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45029.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45036.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45037.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45043.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45044.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@45049.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45051.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45052.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@45057.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@45058.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45060.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45061.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@45066.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45068.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45069.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@45075.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@45129.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45131.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45132.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@45155.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@45158.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@45166.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45169.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45170.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@45189.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45191.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45192.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@45197.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45199.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45200.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@45214.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@45265.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@45307.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@45308.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@45309.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45311.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45312.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@45318.6] wire _T_309; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@45349.8] wire _T_311; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45351.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45352.8] wire _T_317; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@45366.6] wire _T_335; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@45397.8] wire _T_337; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45399.8] wire _T_338; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45400.8] wire _T_343; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@45414.6] wire _T_369; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@45464.6] wire _T_371; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45466.6] wire _T_372; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45467.6] wire _T_373; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@45472.6] wire _T_374; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@45473.6] wire [1:0] _T_377; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@45476.6] wire _T_378; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@45477.6] wire _T_386; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@45485.6] wire _T_392; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45496.6] wire _T_393; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45497.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45498.6] wire _T_396; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@45500.6] wire _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45503.8] wire _T_399; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45504.8] wire _T_400; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@45509.8] wire _T_402; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45511.8] wire _T_403; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45512.8] wire _T_416; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@45542.6] wire _T_444; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@45600.6] wire _T_473; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@45659.6] wire _T_490; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@45694.6] wire _T_508; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@45730.6] wire _T_537; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@45790.4] wire [3:0] _T_542; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@45795.4] wire _T_543; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@45796.4] wire _T_544; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@45797.4] reg [3:0] _T_546; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@45799.4] reg [31:0] _RAND_0; wire [3:0] _T_548; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45801.4] wire _T_549; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45802.4] reg [2:0] _T_557; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@45813.4] reg [31:0] _RAND_1; reg [2:0] _T_558; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@45814.4] reg [31:0] _RAND_2; reg [2:0] _T_559; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@45815.4] reg [31:0] _RAND_3; reg [4:0] _T_560; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@45816.4] reg [31:0] _RAND_4; reg [11:0] _T_561; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@45817.4] reg [31:0] _RAND_5; wire _T_562; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@45818.4] wire _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@45819.4] wire _T_564; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@45821.6] wire _T_566; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45823.6] wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45824.6] wire _T_568; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@45829.6] wire _T_570; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45831.6] wire _T_571; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45832.6] wire _T_572; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@45837.6] wire _T_574; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45839.6] wire _T_575; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45840.6] wire _T_576; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@45845.6] wire _T_578; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45847.6] wire _T_579; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45848.6] wire _T_580; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@45853.6] wire _T_582; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45855.6] wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45856.6] wire _T_585; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@45863.4] wire _T_586; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@45871.4] wire [12:0] _T_588; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@45873.4] wire [5:0] _T_589; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@45874.4] wire [5:0] _T_590; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@45875.4] wire [3:0] _T_591; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@45876.4] wire _T_592; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@45877.4] reg [3:0] _T_594; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@45879.4] reg [31:0] _RAND_6; wire [3:0] _T_596; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45881.4] wire _T_597; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45882.4] reg [2:0] _T_605; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@45893.4] reg [31:0] _RAND_7; reg [2:0] _T_607; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@45895.4] reg [31:0] _RAND_8; reg [4:0] _T_608; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@45896.4] reg [31:0] _RAND_9; wire _T_611; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@45899.4] wire _T_612; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@45900.4] wire _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@45902.6] wire _T_615; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45904.6] wire _T_616; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45905.6] wire _T_621; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@45918.6] wire _T_623; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45920.6] wire _T_624; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45921.6] wire _T_625; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@45926.6] wire _T_627; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45928.6] wire _T_628; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45929.6] wire _T_638; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@45952.4] reg [17:0] _T_639; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@45961.4] reg [31:0] _RAND_10; reg [3:0] _T_649; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@45971.4] reg [31:0] _RAND_11; wire [3:0] _T_651; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45973.4] wire _T_652; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45974.4] reg [3:0] _T_668; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@45993.4] reg [31:0] _RAND_12; wire [3:0] _T_670; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45995.4] wire _T_671; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45996.4] wire _T_681; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@46011.4] wire [31:0] _T_683; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@46014.6] wire [17:0] _T_684; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@46016.6] wire _T_685; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@46017.6] wire _T_686; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@46018.6] wire _T_688; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46020.6] wire _T_689; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46021.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@46013.4] wire _T_693; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@46032.4] wire _T_695; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@46034.4] wire _T_696; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@46035.4] wire [31:0] _T_697; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@46037.6] wire [17:0] _T_679; // @[:freechips.rocketchip.system.TinyConfig.fir@46007.4 :freechips.rocketchip.system.TinyConfig.fir@46009.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@46015.6] wire [17:0] _T_698; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@46039.6] wire [17:0] _T_699; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@46040.6] wire _T_700; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@46041.6] wire _T_702; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46043.6] wire _T_703; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46044.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@46036.4] wire [17:0] _T_704; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@46050.4] wire [17:0] _T_690; // @[:freechips.rocketchip.system.TinyConfig.fir@46027.4 :freechips.rocketchip.system.TinyConfig.fir@46029.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@46038.6] wire [17:0] _T_705; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@46051.4] wire [17:0] _T_706; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@46052.4] reg [31:0] _T_707; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@46054.4] reg [31:0] _RAND_13; wire _T_708; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@46057.4] wire _T_709; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@46058.4] wire _T_710; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@46059.4] wire _T_711; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@46060.4] wire _T_712; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@46061.4] wire _T_713; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@46062.4] wire _T_715; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46064.4] wire _T_716; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46065.4] wire [31:0] _T_718; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@46071.4] wire _T_721; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@46075.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45017.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@45089.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45172.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@45231.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@45282.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@45332.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@45380.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@45428.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45506.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@45548.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@45606.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@45665.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@45700.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@45736.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@46055.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@44881.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@44882.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@44885.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@44886.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@44894.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44905.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44906.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@44907.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@44909.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@44910.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@44911.6] assign _GEN_18 = {{6'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@44912.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@44912.6] assign _T_32 = _T_31 == 12'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@44913.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@44915.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@44916.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@44918.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@44919.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@44920.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@44921.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@44922.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44924.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44925.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44927.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44928.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@44929.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@44930.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@44931.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44932.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44933.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44934.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44935.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44936.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44937.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44938.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44939.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44940.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@44941.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@44942.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@44943.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@44946.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@44950.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@45003.6] assign _T_122 = $signed(_T_69) & $signed(-13'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@45008.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@45009.8] assign _T_124 = $signed(_T_123) == $signed(13'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@45010.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45015.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45028.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45029.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45036.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45037.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45043.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45044.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@45049.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45051.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45052.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@45057.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@45058.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45060.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45061.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@45066.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45068.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45069.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@45075.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@45129.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45131.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45132.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@45155.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@45158.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@45166.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45169.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45170.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@45189.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45191.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45192.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@45197.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45199.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45200.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@45214.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@45265.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@45307.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@45308.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@45309.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45311.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45312.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@45318.6] assign _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@45349.8] assign _T_311 = _T_309 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45351.8] assign _T_312 = _T_311 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45352.8] assign _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@45366.6] assign _T_335 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@45397.8] assign _T_337 = _T_335 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45399.8] assign _T_338 = _T_337 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45400.8] assign _T_343 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@45414.6] assign _T_369 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@45464.6] assign _T_371 = _T_369 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45466.6] assign _T_372 = _T_371 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45467.6] assign _T_373 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@45472.6] assign _T_374 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@45473.6] assign _T_377 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@45476.6] assign _T_378 = _T_377 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@45477.6] assign _T_386 = _T_377 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@45485.6] assign _T_392 = _T_373 | _T_374; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45496.6] assign _T_393 = _T_392 | _T_378; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45497.6] assign _T_394 = _T_393 | _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@45498.6] assign _T_396 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@45500.6] assign _T_398 = _T_394 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45503.8] assign _T_399 = _T_398 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45504.8] assign _T_400 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@45509.8] assign _T_402 = _T_400 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45511.8] assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45512.8] assign _T_416 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@45542.6] assign _T_444 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@45600.6] assign _T_473 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@45659.6] assign _T_490 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@45694.6] assign _T_508 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@45730.6] assign _T_537 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@45790.4] assign _T_542 = _T_30[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@45795.4] assign _T_543 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@45796.4] assign _T_544 = _T_543 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@45797.4] assign _T_548 = _T_546 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45801.4] assign _T_549 = _T_546 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45802.4] assign _T_562 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@45818.4] assign _T_563 = io_in_a_valid & _T_562; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@45819.4] assign _T_564 = io_in_a_bits_opcode == _T_557; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@45821.6] assign _T_566 = _T_564 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45823.6] assign _T_567 = _T_566 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45824.6] assign _T_568 = io_in_a_bits_param == _T_558; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@45829.6] assign _T_570 = _T_568 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45831.6] assign _T_571 = _T_570 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45832.6] assign _T_572 = io_in_a_bits_size == _T_559; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@45837.6] assign _T_574 = _T_572 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45839.6] assign _T_575 = _T_574 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45840.6] assign _T_576 = io_in_a_bits_source == _T_560; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@45845.6] assign _T_578 = _T_576 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45847.6] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45848.6] assign _T_580 = io_in_a_bits_address == _T_561; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@45853.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45855.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45856.6] assign _T_585 = _T_537 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@45863.4] assign _T_586 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@45871.4] assign _T_588 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@45873.4] assign _T_589 = _T_588[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@45874.4] assign _T_590 = ~ _T_589; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@45875.4] assign _T_591 = _T_590[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@45876.4] assign _T_592 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@45877.4] assign _T_596 = _T_594 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45881.4] assign _T_597 = _T_594 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45882.4] assign _T_611 = _T_597 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@45899.4] assign _T_612 = io_in_d_valid & _T_611; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@45900.4] assign _T_613 = io_in_d_bits_opcode == _T_605; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@45902.6] assign _T_615 = _T_613 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45904.6] assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45905.6] assign _T_621 = io_in_d_bits_size == _T_607; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@45918.6] assign _T_623 = _T_621 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45920.6] assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45921.6] assign _T_625 = io_in_d_bits_source == _T_608; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@45926.6] assign _T_627 = _T_625 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45928.6] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45929.6] assign _T_638 = _T_586 & _T_597; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@45952.4] assign _T_651 = _T_649 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45973.4] assign _T_652 = _T_649 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45974.4] assign _T_670 = _T_668 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@45995.4] assign _T_671 = _T_668 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@45996.4] assign _T_681 = _T_537 & _T_652; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@46011.4] assign _T_683 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@46014.6] assign _T_684 = _T_639 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@46016.6] assign _T_685 = _T_684[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@46017.6] assign _T_686 = _T_685 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@46018.6] assign _T_688 = _T_686 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46020.6] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46021.6] assign _GEN_15 = _T_681 ? _T_683 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@46013.4] assign _T_693 = _T_586 & _T_671; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@46032.4] assign _T_695 = _T_396 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@46034.4] assign _T_696 = _T_693 & _T_695; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@46035.4] assign _T_697 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@46037.6] assign _T_679 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@46007.4 :freechips.rocketchip.system.TinyConfig.fir@46009.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@46015.6] assign _T_698 = _T_679 | _T_639; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@46039.6] assign _T_699 = _T_698 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@46040.6] assign _T_700 = _T_699[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@46041.6] assign _T_702 = _T_700 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46043.6] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46044.6] assign _GEN_16 = _T_696 ? _T_697 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@46036.4] assign _T_704 = _T_639 | _T_679; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@46050.4] assign _T_690 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@46027.4 :freechips.rocketchip.system.TinyConfig.fir@46029.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@46038.6] assign _T_705 = ~ _T_690; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@46051.4] assign _T_706 = _T_704 & _T_705; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@46052.4] assign _T_708 = _T_639 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@46057.4] assign _T_709 = _T_708 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@46058.4] assign _T_710 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@46059.4] assign _T_711 = _T_709 | _T_710; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@46060.4] assign _T_712 = _T_707 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@46061.4] assign _T_713 = _T_711 | _T_712; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@46062.4] assign _T_715 = _T_713 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46064.4] assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46065.4] assign _T_718 = _T_707 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@46071.4] assign _T_721 = _T_537 | _T_586; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@46075.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45017.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@45089.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45172.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@45231.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@45282.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@45332.10] assign _GEN_95 = io_in_a_valid & _T_317; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@45380.10] assign _GEN_105 = io_in_a_valid & _T_343; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@45428.10] assign _GEN_115 = io_in_d_valid & _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45506.10] assign _GEN_119 = io_in_d_valid & _T_416; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@45548.10] assign _GEN_125 = io_in_d_valid & _T_444; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@45606.10] assign _GEN_131 = io_in_d_valid & _T_473; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@45665.10] assign _GEN_133 = io_in_d_valid & _T_490; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@45700.10] assign _GEN_135 = io_in_d_valid & _T_508; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@45736.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_546 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_557 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_558 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_559 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_560 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_561 = _RAND_5[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_594 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_605 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_607 = _RAND_8[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_608 = _RAND_9[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_639 = _RAND_10[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_649 = _RAND_11[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_668 = _RAND_12[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_707 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_546 <= 4'h0; end else begin if (_T_537) begin if (_T_549) begin if (_T_544) begin _T_546 <= _T_542; end else begin _T_546 <= 4'h0; end end else begin _T_546 <= _T_548; end end end if (_T_585) begin _T_557 <= io_in_a_bits_opcode; end if (_T_585) begin _T_558 <= io_in_a_bits_param; end if (_T_585) begin _T_559 <= io_in_a_bits_size; end if (_T_585) begin _T_560 <= io_in_a_bits_source; end if (_T_585) begin _T_561 <= io_in_a_bits_address; end if (reset) begin _T_594 <= 4'h0; end else begin if (_T_586) begin if (_T_597) begin if (_T_592) begin _T_594 <= _T_591; end else begin _T_594 <= 4'h0; end end else begin _T_594 <= _T_596; end end end if (_T_638) begin _T_605 <= io_in_d_bits_opcode; end if (_T_638) begin _T_607 <= io_in_d_bits_size; end if (_T_638) begin _T_608 <= io_in_d_bits_source; end if (reset) begin _T_639 <= 18'h0; end else begin _T_639 <= _T_706; end if (reset) begin _T_649 <= 4'h0; end else begin if (_T_537) begin if (_T_652) begin if (_T_544) begin _T_649 <= _T_542; end else begin _T_649 <= 4'h0; end end else begin _T_649 <= _T_651; end end end if (reset) begin _T_668 <= 4'h0; end else begin if (_T_586) begin if (_T_671) begin if (_T_592) begin _T_668 <= _T_591; end else begin _T_668 <= 4'h0; end end else begin _T_668 <= _T_670; end end end if (reset) begin _T_707 <= 32'h0; end else begin if (_T_721) begin _T_707 <= 32'h0; end else begin _T_707 <= _T_718; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45017.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@45018.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:49:60)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@45024.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@45025.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45031.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@45032.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:49:60)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45039.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@45040.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45046.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@45047.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:49:60)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45054.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@45055.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45063.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@45064.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:49:60)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45071.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@45072.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@45089.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@45090.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:49:60)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@45096.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@45097.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@45103.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@45104.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:49:60)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@45111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@45112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@45118.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@45119.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:49:60)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@45126.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@45127.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:49:60)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45134.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@45135.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@45143.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@45144.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:49:60)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@45151.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@45152.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45172.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@45173.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@45179.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@45180.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@45186.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@45187.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:49:60)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45194.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@45195.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45202.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@45203.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:49:60)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@45210.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@45211.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@45231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@45232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@45238.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@45239.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@45245.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@45246.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:49:60)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@45253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@45254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@45261.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@45262.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@45282.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@45283.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@45289.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@45290.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@45296.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@45297.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:49:60)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@45304.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@45305.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45314.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@45315.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@45332.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@45333.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@45339.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@45340.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@45346.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@45347.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_312) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:49:60)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45354.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_312) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@45355.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@45362.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@45363.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@45380.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@45381.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@45387.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@45388.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@45394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@45395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_338) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:49:60)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_338) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@45403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@45410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@45411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:49:60)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@45428.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@45429.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@45435.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@45436.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:49:60)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@45442.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@45443.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:49:60)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@45450.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@45451.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:49:60)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@45458.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@45459.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_372) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:49:60)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45469.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_372) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@45470.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45506.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_399) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@45507.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:49:60)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45514.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_403) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@45515.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@45548.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_399) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@45549.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:49:60)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@45555.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@45556.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:49:60)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@45563.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_403) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@45564.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@45606.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_399) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@45607.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:49:60)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@45613.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@45614.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_403) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:49:60)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@45621.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_403) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@45622.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@45665.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_399) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@45666.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@45700.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_399) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@45701.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_399) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@45736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_399) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@45737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_567) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45826.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_567) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@45827.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_571) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45834.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_571) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@45835.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_575) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45842.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_575) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@45843.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45850.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_579) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@45851.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_563 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45858.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_563 & _T_583) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@45859.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_616) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45907.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_616) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@45908.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_624) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45923.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_624) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@45924.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_612 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:49:60)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45931.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_612 & _T_628) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@45932.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_681 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:49:60)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46023.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_681 & _T_689) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@46024.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_696 & _T_703) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:49:60)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46046.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_696 & _T_703) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@46047.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_716) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Periphery.scala:49:60)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46067.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_716) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@46068.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Repeater_3( // @[:freechips.rocketchip.system.TinyConfig.fir@46080.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@46081.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@46082.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output io_full, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [11:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [11:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@46083.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@46088.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_2; reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_3; reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_4; reg [11:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_5; reg [3:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_6; reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@46089.4] reg [31:0] _RAND_7; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@46092.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46098.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@46099.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46104.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@46105.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@46106.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@46092.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46098.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@46099.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46104.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@46105.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@46106.4] assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.TinyConfig.fir@46097.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@46094.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@46091.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@46096.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; saved_corrupt = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end if (_T_5) begin saved_corrupt <= io_enq_bits_corrupt; end end endmodule module TLFragmenter_2( // @[:freechips.rocketchip.system.TinyConfig.fir@46111.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@46112.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@46113.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [11:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [9:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [11:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [9:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@46114.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [11:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [11:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [3:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [11:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire [3:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] reg [3:0] _T_14; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.TinyConfig.fir@46174.4] reg [31:0] _RAND_0; reg [2:0] _T_15; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.TinyConfig.fir@46175.4] reg [31:0] _RAND_1; reg _T_16; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.TinyConfig.fir@46176.4] reg [31:0] _RAND_2; wire [3:0] _T_17; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@46177.4] wire _T_18; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@46178.4] wire _T_19; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@46179.4] wire [3:0] _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@46181.4] wire [2:0] _T_22; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@46182.4] wire [4:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46184.4] wire [1:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46185.4] wire [1:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46186.4] wire _T_27; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@46187.4] wire _T_39; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@46203.4] wire _T_40; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@46204.4] wire [5:0] _T_41; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@46205.4] wire [5:0] _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@46206.4] wire [5:0] _T_42; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@46206.4] wire [6:0] _T_43; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@46207.4] wire [6:0] _T_44; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@46208.4] wire [6:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46209.4] wire [6:0] _T_46; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@46210.4] wire [6:0] _T_47; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@46211.4] wire [2:0] _T_48; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@46212.4] wire [3:0] _T_49; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@46213.4] wire _T_50; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@46214.4] wire [3:0] _GEN_8; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46215.4] wire [3:0] _T_51; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46215.4] wire [1:0] _T_52; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@46216.4] wire [1:0] _T_53; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@46217.4] wire _T_54; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@46218.4] wire [1:0] _T_55; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46219.4] wire _T_56; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@46220.4] wire [2:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46222.4] wire _T_64; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@46235.4] wire _T_66; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@46237.4] wire _T_67; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@46238.4] wire _T_68; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@46239.4] wire _T_59; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46223.4] wire [3:0] _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@46225.6] wire [3:0] _T_61; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@46226.6] wire _T_63; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@46231.8] wire _T_69; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@46241.4] wire _T_91; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@46274.4] wire [2:0] _T_92; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@46275.4] wire [12:0] _T_94; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46277.4] wire [5:0] _T_95; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46278.4] wire [5:0] _T_96; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46279.4] wire [8:0] _T_98; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46281.4] wire [1:0] _T_99; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46282.4] wire [1:0] _T_100; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46283.4] wire _T_101; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@46284.4] wire _T_102; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@46285.4] reg [3:0] _T_104; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.TinyConfig.fir@46287.4] reg [31:0] _RAND_3; wire _T_105; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@46288.4] wire [3:0] _T_106; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@46289.4] wire [3:0] _T_108; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@46291.4] wire [3:0] _T_109; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@46292.4] wire [3:0] _T_110; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@46293.4] wire [3:0] _T_113; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@46296.4] reg _T_120; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@46303.4] reg [31:0] _RAND_4; wire _GEN_5; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@46304.4] wire _T_122; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@46308.4] wire _T_13_a_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@46170.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@46317.4] wire _T_123; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46309.4] wire _T_124; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@46313.4] wire _T_125; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@46314.4] wire [5:0] _T_127; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@46318.4] wire [5:0] _T_128; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@46319.4] wire [5:0] _T_129; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@46320.4] wire [5:0] _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@46321.4] wire [5:0] _T_130; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@46321.4] wire [5:0] _T_131; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@46322.4] wire [5:0] _T_132; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@46323.4] wire [11:0] _GEN_11; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@46324.4] wire [5:0] _T_134; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46326.4] wire _T_136; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@46330.4] wire _T_138; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@46332.4] wire _T_140; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46334.4] wire _T_141; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46335.4] wire _T_143; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@46342.4] wire _T_144; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@46343.4] wire _T_146; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46345.4] wire _T_147; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46346.4] TLMonitor_23 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@46121.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); Repeater_3 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@46249.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_full(Repeater_io_full), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask), .io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt) ); assign _T_17 = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@46177.4] assign _T_18 = _T_14 == 4'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@46178.4] assign _T_19 = _T_17 == 4'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@46179.4] assign _T_21 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@46181.4] assign _T_22 = _T_21[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@46182.4] assign _T_24 = 5'h3 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46184.4] assign _T_25 = _T_24[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46185.4] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46186.4] assign _T_27 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@46187.4] assign _T_39 = _T_22[2:2]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@46203.4] assign _T_40 = _T_27 ? 1'h1 : _T_39; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@46204.4] assign _T_41 = {_T_17, 2'h0}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@46205.4] assign _GEN_7 = {{4'd0}, _T_26}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@46206.4] assign _T_42 = _T_41 | _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@46206.4] assign _T_43 = {_T_42, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@46207.4] assign _T_44 = _T_43 | 7'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@46208.4] assign _T_45 = {1'h0,_T_42}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46209.4] assign _T_46 = ~ _T_45; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@46210.4] assign _T_47 = _T_44 & _T_46; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@46211.4] assign _T_48 = _T_47[6:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@46212.4] assign _T_49 = _T_47[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@46213.4] assign _T_50 = _T_48 != 3'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@46214.4] assign _GEN_8 = {{1'd0}, _T_48}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46215.4] assign _T_51 = _GEN_8 | _T_49; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46215.4] assign _T_52 = _T_51[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@46216.4] assign _T_53 = _T_51[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@46217.4] assign _T_54 = _T_52 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@46218.4] assign _T_55 = _T_52 | _T_53; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@46219.4] assign _T_56 = _T_55[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@46220.4] assign _T_58 = {_T_50,_T_54,_T_56}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46222.4] assign _T_64 = _T_27 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@46235.4] assign _T_66 = _T_19 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@46237.4] assign _T_67 = _T_64 & _T_66; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@46238.4] assign _T_68 = auto_in_d_ready | _T_67; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@46239.4] assign _T_59 = _T_68 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46223.4] assign _GEN_9 = {{3'd0}, _T_40}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@46225.6] assign _T_61 = _T_14 - _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@46226.6] assign _T_63 = auto_out_d_bits_source[4]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@46231.8] assign _T_69 = _T_67 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@46241.4] assign _T_91 = Repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@46274.4] assign _T_92 = _T_91 ? 3'h2 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@46275.4] assign _T_94 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46277.4] assign _T_95 = _T_94[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46278.4] assign _T_96 = ~ _T_95; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46279.4] assign _T_98 = 9'h3 << _T_92; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46281.4] assign _T_99 = _T_98[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46282.4] assign _T_100 = ~ _T_99; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46283.4] assign _T_101 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@46284.4] assign _T_102 = _T_101 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@46285.4] assign _T_105 = _T_104 == 4'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@46288.4] assign _T_106 = _T_96[5:2]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@46289.4] assign _T_108 = _T_104 - 4'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@46291.4] assign _T_109 = _T_105 ? _T_106 : _T_108; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@46292.4] assign _T_110 = ~ _T_109; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@46293.4] assign _T_113 = ~ _T_110; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@46296.4] assign _GEN_5 = _T_105 ? _T_16 : _T_120; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@46304.4] assign _T_122 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@46308.4] assign _T_13_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@46170.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@46317.4] assign _T_123 = auto_out_a_ready & _T_13_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@46309.4] assign _T_124 = _T_102 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@46313.4] assign _T_125 = _T_113 != 4'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@46314.4] assign _T_127 = {_T_109, 2'h0}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@46318.4] assign _T_128 = ~ _T_96; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@46319.4] assign _T_129 = _T_127 | _T_128; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@46320.4] assign _GEN_10 = {{4'd0}, _T_100}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@46321.4] assign _T_130 = _T_129 | _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@46321.4] assign _T_131 = _T_130 | 6'h3; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@46322.4] assign _T_132 = ~ _T_131; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@46323.4] assign _GEN_11 = {{6'd0}, _T_132}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@46324.4] assign _T_134 = {Repeater_io_deq_bits_source,_T_122}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46326.4] assign _T_136 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@46330.4] assign _T_138 = _T_136 | _T_124; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@46332.4] assign _T_140 = _T_138 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46334.4] assign _T_141 = _T_140 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46335.4] assign _T_143 = Repeater_io_deq_bits_mask == 4'hf; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@46342.4] assign _T_144 = _T_136 | _T_143; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@46343.4] assign _T_146 = _T_144 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46345.4] assign _T_147 = _T_146 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46346.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_in_d_valid = auto_out_d_valid & _T_69; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46173.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_size = _T_92[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_source = {_T_134,_T_113}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_11; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_mask = Repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign auto_out_d_ready = auto_in_d_ready | _T_67; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46172.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@46123.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@46124.4] assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_69; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@46169.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@46251.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@46252.4] assign Repeater_io_repeat = _T_124 & _T_125; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.TinyConfig.fir@46316.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@46253.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@46317.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_14 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_15 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_16 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_104 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_120 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_14 <= 4'h0; end else begin if (_T_59) begin if (_T_18) begin _T_14 <= _T_17; end else begin _T_14 <= _T_61; end end end if (_T_59) begin if (_T_18) begin _T_15 <= _T_58; end end if (reset) begin _T_16 <= 1'h0; end else begin if (_T_59) begin if (_T_18) begin _T_16 <= _T_63; end end end if (reset) begin _T_104 <= 4'h0; end else begin if (_T_123) begin _T_104 <= _T_113; end end if (_T_105) begin _T_120 <= _T_16; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_141) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46337.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_141) begin $fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@46338.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_147) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46348.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_147) begin $fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@46349.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SimpleLazyModule_8( // @[:freechips.rocketchip.system.TinyConfig.fir@46372.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@46373.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@46374.4] output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [11:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [3:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [31:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [31:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [9:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [11:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [3:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output [31:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [9:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] input [31:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@46375.4] ); wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [11:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [11:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] TLFragmenter_2 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@46380.4] .clock(fragmenter_clock), .reset(fragmenter_reset), .auto_in_a_ready(fragmenter_auto_in_a_ready), .auto_in_a_valid(fragmenter_auto_in_a_valid), .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode), .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param), .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size), .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source), .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address), .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask), .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt), .auto_in_d_ready(fragmenter_auto_in_d_ready), .auto_in_d_valid(fragmenter_auto_in_d_valid), .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode), .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size), .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source), .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data), .auto_out_a_ready(fragmenter_auto_out_a_ready), .auto_out_a_valid(fragmenter_auto_out_a_valid), .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode), .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param), .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size), .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source), .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address), .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask), .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt), .auto_out_d_ready(fragmenter_auto_out_d_ready), .auto_out_d_valid(fragmenter_auto_out_d_valid), .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode), .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size), .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source), .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data) ); assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@46384.4] assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@46385.4] assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@46387.4] assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@46386.4] endmodule module TLMonitor_24( // @[:freechips.rocketchip.system.TinyConfig.fir@46397.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@46398.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@46399.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@46400.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@47602.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@46415.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@46416.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@46419.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@46420.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@46428.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46439.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46440.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46441.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46443.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46444.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46445.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@46446.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@46446.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@46447.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@46449.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@46450.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@46452.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@46453.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@46454.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@46455.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@46456.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46458.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46459.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46461.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46462.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@46463.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@46464.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@46465.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46466.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46467.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46468.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46469.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46470.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46471.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46472.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46473.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46474.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46475.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46476.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46477.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46480.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@46537.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@46540.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@46541.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@46542.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@46543.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@46544.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46549.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46562.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46563.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46570.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46571.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46577.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46578.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@46583.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46585.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46586.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@46591.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@46592.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46594.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46595.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@46600.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46602.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46603.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@46609.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@46663.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46665.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46666.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@46689.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@46692.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@46700.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46703.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46704.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@46723.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46725.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46726.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@46731.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46733.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46734.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@46748.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@46799.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@46841.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@46842.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@46843.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46845.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46846.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@46852.6] wire _T_292; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@46854.8] wire _T_299; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@46861.8] wire _T_302; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46864.8] wire _T_303; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46865.8] wire _T_310; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@46884.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46886.8] wire _T_313; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46887.8] wire _T_318; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@46901.6] wire _T_337; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@46933.8] wire _T_339; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46935.8] wire _T_340; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46936.8] wire _T_345; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@46950.6] wire _T_371; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@47000.6] wire _T_373; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47002.6] wire _T_374; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47003.6] wire _T_375; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47008.6] wire _T_376; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47009.6] wire [1:0] _T_379; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@47012.6] wire _T_380; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47013.6] wire _T_388; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47021.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47032.6] wire _T_395; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47033.6] wire _T_396; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47034.6] wire _T_398; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@47036.6] wire _T_400; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47039.8] wire _T_401; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47040.8] wire _T_402; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@47045.8] wire _T_404; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47047.8] wire _T_405; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47048.8] wire _T_406; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@47053.8] wire _T_408; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47055.8] wire _T_409; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47056.8] wire _T_410; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@47061.8] wire _T_412; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47063.8] wire _T_413; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47064.8] wire _T_414; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@47069.8] wire _T_416; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47071.8] wire _T_417; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47072.8] wire _T_418; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@47078.6] wire _T_429; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@47102.8] wire _T_431; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47104.8] wire _T_432; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47105.8] wire _T_433; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@47110.8] wire _T_435; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47112.8] wire _T_436; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47113.8] wire _T_446; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@47136.6] wire _T_466; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@47177.8] wire _T_468; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47179.8] wire _T_469; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47180.8] wire _T_475; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@47195.6] wire _T_492; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@47230.6] wire _T_510; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@47266.6] wire _T_539; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@47326.4] wire [3:0] _T_544; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@47331.4] wire _T_545; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@47332.4] wire _T_546; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@47333.4] reg [3:0] _T_548; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@47335.4] reg [31:0] _RAND_0; wire [3:0] _T_550; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47337.4] wire _T_551; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47338.4] reg [2:0] _T_559; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@47349.4] reg [31:0] _RAND_1; reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@47350.4] reg [31:0] _RAND_2; reg [2:0] _T_561; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@47351.4] reg [31:0] _RAND_3; reg [4:0] _T_562; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@47352.4] reg [31:0] _RAND_4; reg [31:0] _T_563; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@47353.4] reg [31:0] _RAND_5; wire _T_564; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@47354.4] wire _T_565; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@47355.4] wire _T_566; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@47357.6] wire _T_568; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47359.6] wire _T_569; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47360.6] wire _T_570; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@47365.6] wire _T_572; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47367.6] wire _T_573; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47368.6] wire _T_574; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@47373.6] wire _T_576; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47375.6] wire _T_577; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47376.6] wire _T_578; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@47381.6] wire _T_580; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47383.6] wire _T_581; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47384.6] wire _T_582; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@47389.6] wire _T_584; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47391.6] wire _T_585; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47392.6] wire _T_587; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@47399.4] wire _T_588; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@47407.4] wire [12:0] _T_590; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@47409.4] wire [5:0] _T_591; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@47410.4] wire [5:0] _T_592; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@47411.4] wire [3:0] _T_593; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@47412.4] wire _T_594; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@47413.4] reg [3:0] _T_596; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@47415.4] reg [31:0] _RAND_6; wire [3:0] _T_598; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47417.4] wire _T_599; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47418.4] reg [2:0] _T_607; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@47429.4] reg [31:0] _RAND_7; reg [1:0] _T_608; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@47430.4] reg [31:0] _RAND_8; reg [2:0] _T_609; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@47431.4] reg [31:0] _RAND_9; reg [4:0] _T_610; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@47432.4] reg [31:0] _RAND_10; reg _T_611; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@47433.4] reg [31:0] _RAND_11; reg _T_612; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@47434.4] reg [31:0] _RAND_12; wire _T_613; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@47435.4] wire _T_614; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@47436.4] wire _T_615; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@47438.6] wire _T_617; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47440.6] wire _T_618; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47441.6] wire _T_619; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@47446.6] wire _T_621; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47448.6] wire _T_622; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47449.6] wire _T_623; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@47454.6] wire _T_625; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47456.6] wire _T_626; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47457.6] wire _T_627; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@47462.6] wire _T_629; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47464.6] wire _T_630; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47465.6] wire _T_631; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@47470.6] wire _T_633; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47472.6] wire _T_634; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47473.6] wire _T_635; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@47478.6] wire _T_637; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47480.6] wire _T_638; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47481.6] wire _T_640; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@47488.4] reg [17:0] _T_641; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@47497.4] reg [31:0] _RAND_13; reg [3:0] _T_651; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@47507.4] reg [31:0] _RAND_14; wire [3:0] _T_653; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47509.4] wire _T_654; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47510.4] reg [3:0] _T_670; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@47529.4] reg [31:0] _RAND_15; wire [3:0] _T_672; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47531.4] wire _T_673; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47532.4] wire _T_683; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@47547.4] wire [31:0] _T_685; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@47550.6] wire [17:0] _T_686; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@47552.6] wire _T_687; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@47553.6] wire _T_688; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@47554.6] wire _T_690; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47556.6] wire _T_691; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47557.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@47549.4] wire _T_695; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@47568.4] wire _T_697; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@47570.4] wire _T_698; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@47571.4] wire [31:0] _T_699; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@47573.6] wire [17:0] _T_681; // @[:freechips.rocketchip.system.TinyConfig.fir@47543.4 :freechips.rocketchip.system.TinyConfig.fir@47545.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@47551.6] wire [17:0] _T_700; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@47575.6] wire [17:0] _T_701; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@47576.6] wire _T_702; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@47577.6] wire _T_704; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47579.6] wire _T_705; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47580.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@47572.4] wire [17:0] _T_692; // @[:freechips.rocketchip.system.TinyConfig.fir@47563.4 :freechips.rocketchip.system.TinyConfig.fir@47565.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@47574.6] wire _T_706; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@47586.4] wire _T_707; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@47587.4] wire _T_708; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@47588.4] wire _T_709; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@47589.4] wire _T_711; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47591.4] wire _T_712; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47592.4] wire [17:0] _T_713; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@47597.4] wire [17:0] _T_714; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@47598.4] wire [17:0] _T_715; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@47599.4] reg [31:0] _T_716; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@47601.4] reg [31:0] _RAND_16; wire _T_717; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@47604.4] wire _T_718; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@47605.4] wire _T_719; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@47606.4] wire _T_720; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@47607.4] wire _T_721; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@47608.4] wire _T_722; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@47609.4] wire _T_724; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47611.4] wire _T_725; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47612.4] wire [31:0] _T_727; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@47618.4] wire _T_730; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@47622.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46551.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@46623.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46706.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@46765.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@46816.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46867.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@46916.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@46964.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47042.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@47084.10] wire _GEN_139; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@47142.10] wire _GEN_153; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@47201.10] wire _GEN_161; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@47236.10] wire _GEN_169; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@47272.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@47602.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@46415.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@46416.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@46419.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@46420.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@46428.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46439.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46440.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@46441.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@46443.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@46444.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@46445.6] assign _GEN_18 = {{26'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@46446.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@46446.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@46447.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@46449.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@46450.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@46452.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@46453.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@46454.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@46455.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@46456.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46458.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46459.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46461.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46462.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@46463.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@46464.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@46465.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46466.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46467.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46468.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46469.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46470.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46471.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46472.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46473.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46474.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@46475.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@46476.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@46477.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@46480.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@46537.6] assign _T_120 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@46540.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@46541.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@46542.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@46543.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@46544.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46549.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46562.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46563.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46570.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46571.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46577.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46578.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@46583.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46585.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46586.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@46591.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@46592.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46594.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46595.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@46600.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46602.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46603.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@46609.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@46663.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46665.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46666.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@46689.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@46692.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@46700.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46703.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46704.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@46723.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46725.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46726.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@46731.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46733.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46734.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@46748.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@46799.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@46841.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@46842.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@46843.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46845.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46846.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@46852.6] assign _T_292 = 3'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@46854.8] assign _T_299 = _T_292 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@46861.8] assign _T_302 = _T_299 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46864.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46865.8] assign _T_310 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@46884.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46886.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46887.8] assign _T_318 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@46901.6] assign _T_337 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@46933.8] assign _T_339 = _T_337 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46935.8] assign _T_340 = _T_339 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46936.8] assign _T_345 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@46950.6] assign _T_371 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@47000.6] assign _T_373 = _T_371 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47002.6] assign _T_374 = _T_373 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47003.6] assign _T_375 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47008.6] assign _T_376 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47009.6] assign _T_379 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@47012.6] assign _T_380 = _T_379 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47013.6] assign _T_388 = _T_379 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47021.6] assign _T_394 = _T_375 | _T_376; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47032.6] assign _T_395 = _T_394 | _T_380; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47033.6] assign _T_396 = _T_395 | _T_388; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47034.6] assign _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@47036.6] assign _T_400 = _T_396 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47039.8] assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47040.8] assign _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@47045.8] assign _T_404 = _T_402 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47047.8] assign _T_405 = _T_404 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47048.8] assign _T_406 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@47053.8] assign _T_408 = _T_406 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47055.8] assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47056.8] assign _T_410 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@47061.8] assign _T_412 = _T_410 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47063.8] assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47064.8] assign _T_414 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@47069.8] assign _T_416 = _T_414 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47071.8] assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47072.8] assign _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@47078.6] assign _T_429 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@47102.8] assign _T_431 = _T_429 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47104.8] assign _T_432 = _T_431 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47105.8] assign _T_433 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@47110.8] assign _T_435 = _T_433 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47112.8] assign _T_436 = _T_435 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47113.8] assign _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@47136.6] assign _T_466 = _T_414 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@47177.8] assign _T_468 = _T_466 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47179.8] assign _T_469 = _T_468 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47180.8] assign _T_475 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@47195.6] assign _T_492 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@47230.6] assign _T_510 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@47266.6] assign _T_539 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@47326.4] assign _T_544 = _T_30[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@47331.4] assign _T_545 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@47332.4] assign _T_546 = _T_545 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@47333.4] assign _T_550 = _T_548 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47337.4] assign _T_551 = _T_548 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47338.4] assign _T_564 = _T_551 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@47354.4] assign _T_565 = io_in_a_valid & _T_564; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@47355.4] assign _T_566 = io_in_a_bits_opcode == _T_559; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@47357.6] assign _T_568 = _T_566 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47359.6] assign _T_569 = _T_568 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47360.6] assign _T_570 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@47365.6] assign _T_572 = _T_570 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47367.6] assign _T_573 = _T_572 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47368.6] assign _T_574 = io_in_a_bits_size == _T_561; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@47373.6] assign _T_576 = _T_574 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47375.6] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47376.6] assign _T_578 = io_in_a_bits_source == _T_562; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@47381.6] assign _T_580 = _T_578 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47383.6] assign _T_581 = _T_580 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47384.6] assign _T_582 = io_in_a_bits_address == _T_563; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@47389.6] assign _T_584 = _T_582 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47391.6] assign _T_585 = _T_584 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47392.6] assign _T_587 = _T_539 & _T_551; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@47399.4] assign _T_588 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@47407.4] assign _T_590 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@47409.4] assign _T_591 = _T_590[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@47410.4] assign _T_592 = ~ _T_591; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@47411.4] assign _T_593 = _T_592[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@47412.4] assign _T_594 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@47413.4] assign _T_598 = _T_596 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47417.4] assign _T_599 = _T_596 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47418.4] assign _T_613 = _T_599 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@47435.4] assign _T_614 = io_in_d_valid & _T_613; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@47436.4] assign _T_615 = io_in_d_bits_opcode == _T_607; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@47438.6] assign _T_617 = _T_615 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47440.6] assign _T_618 = _T_617 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47441.6] assign _T_619 = io_in_d_bits_param == _T_608; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@47446.6] assign _T_621 = _T_619 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47448.6] assign _T_622 = _T_621 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47449.6] assign _T_623 = io_in_d_bits_size == _T_609; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@47454.6] assign _T_625 = _T_623 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47456.6] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47457.6] assign _T_627 = io_in_d_bits_source == _T_610; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@47462.6] assign _T_629 = _T_627 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47464.6] assign _T_630 = _T_629 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47465.6] assign _T_631 = io_in_d_bits_sink == _T_611; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@47470.6] assign _T_633 = _T_631 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47472.6] assign _T_634 = _T_633 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47473.6] assign _T_635 = io_in_d_bits_denied == _T_612; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@47478.6] assign _T_637 = _T_635 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47480.6] assign _T_638 = _T_637 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47481.6] assign _T_640 = _T_588 & _T_599; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@47488.4] assign _T_653 = _T_651 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47509.4] assign _T_654 = _T_651 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47510.4] assign _T_672 = _T_670 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@47531.4] assign _T_673 = _T_670 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@47532.4] assign _T_683 = _T_539 & _T_654; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@47547.4] assign _T_685 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@47550.6] assign _T_686 = _T_641 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@47552.6] assign _T_687 = _T_686[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@47553.6] assign _T_688 = _T_687 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@47554.6] assign _T_690 = _T_688 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47556.6] assign _T_691 = _T_690 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47557.6] assign _GEN_15 = _T_683 ? _T_685 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@47549.4] assign _T_695 = _T_588 & _T_673; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@47568.4] assign _T_697 = _T_398 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@47570.4] assign _T_698 = _T_695 & _T_697; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@47571.4] assign _T_699 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@47573.6] assign _T_681 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@47543.4 :freechips.rocketchip.system.TinyConfig.fir@47545.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@47551.6] assign _T_700 = _T_681 | _T_641; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@47575.6] assign _T_701 = _T_700 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@47576.6] assign _T_702 = _T_701[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@47577.6] assign _T_704 = _T_702 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47579.6] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47580.6] assign _GEN_16 = _T_698 ? _T_699 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@47572.4] assign _T_692 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@47563.4 :freechips.rocketchip.system.TinyConfig.fir@47565.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@47574.6] assign _T_706 = _T_681 != _T_692; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@47586.4] assign _T_707 = _T_681 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@47587.4] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@47588.4] assign _T_709 = _T_706 | _T_708; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@47589.4] assign _T_711 = _T_709 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47591.4] assign _T_712 = _T_711 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47592.4] assign _T_713 = _T_641 | _T_681; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@47597.4] assign _T_714 = ~ _T_692; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@47598.4] assign _T_715 = _T_713 & _T_714; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@47599.4] assign _T_717 = _T_641 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@47604.4] assign _T_718 = _T_717 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@47605.4] assign _T_719 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@47606.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@47607.4] assign _T_721 = _T_716 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@47608.4] assign _T_722 = _T_720 | _T_721; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@47609.4] assign _T_724 = _T_722 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47611.4] assign _T_725 = _T_724 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47612.4] assign _T_727 = _T_716 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@47618.4] assign _T_730 = _T_539 | _T_588; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@47622.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46551.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@46623.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46706.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@46765.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@46816.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46867.10] assign _GEN_95 = io_in_a_valid & _T_318; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@46916.10] assign _GEN_105 = io_in_a_valid & _T_345; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@46964.10] assign _GEN_115 = io_in_d_valid & _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47042.10] assign _GEN_125 = io_in_d_valid & _T_418; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@47084.10] assign _GEN_139 = io_in_d_valid & _T_446; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@47142.10] assign _GEN_153 = io_in_d_valid & _T_475; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@47201.10] assign _GEN_161 = io_in_d_valid & _T_492; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@47236.10] assign _GEN_169 = io_in_d_valid & _T_510; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@47272.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_548 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_559 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_560 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_561 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_562 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_563 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_596 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_607 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_608 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_609 = _RAND_9[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_610 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_611 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_612 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_641 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_651 = _RAND_14[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_670 = _RAND_15[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_716 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_548 <= 4'h0; end else begin if (_T_539) begin if (_T_551) begin if (_T_546) begin _T_548 <= _T_544; end else begin _T_548 <= 4'h0; end end else begin _T_548 <= _T_550; end end end if (_T_587) begin _T_559 <= io_in_a_bits_opcode; end if (_T_587) begin _T_560 <= io_in_a_bits_param; end if (_T_587) begin _T_561 <= io_in_a_bits_size; end if (_T_587) begin _T_562 <= io_in_a_bits_source; end if (_T_587) begin _T_563 <= io_in_a_bits_address; end if (reset) begin _T_596 <= 4'h0; end else begin if (_T_588) begin if (_T_599) begin if (_T_594) begin _T_596 <= _T_593; end else begin _T_596 <= 4'h0; end end else begin _T_596 <= _T_598; end end end if (_T_640) begin _T_607 <= io_in_d_bits_opcode; end if (_T_640) begin _T_608 <= io_in_d_bits_param; end if (_T_640) begin _T_609 <= io_in_d_bits_size; end if (_T_640) begin _T_610 <= io_in_d_bits_source; end if (_T_640) begin _T_611 <= io_in_d_bits_sink; end if (_T_640) begin _T_612 <= io_in_d_bits_denied; end if (reset) begin _T_641 <= 18'h0; end else begin _T_641 <= _T_715; end if (reset) begin _T_651 <= 4'h0; end else begin if (_T_539) begin if (_T_654) begin if (_T_546) begin _T_651 <= _T_544; end else begin _T_651 <= 4'h0; end end else begin _T_651 <= _T_653; end end end if (reset) begin _T_670 <= 4'h0; end else begin if (_T_588) begin if (_T_673) begin if (_T_594) begin _T_670 <= _T_593; end else begin _T_670 <= 4'h0; end end else begin _T_670 <= _T_672; end end end if (reset) begin _T_716 <= 32'h0; end else begin if (_T_730) begin _T_716 <= 32'h0; end else begin _T_716 <= _T_727; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46551.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@46552.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@46558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@46559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46565.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@46566.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@46574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46580.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@46581.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46588.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@46589.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46597.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@46598.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46605.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@46606.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@46623.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@46624.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@46630.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@46631.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@46637.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@46638.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@46645.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@46646.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@46652.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@46653.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@46660.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@46661.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46668.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@46669.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@46677.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@46678.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@46685.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@46686.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46706.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@46707.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@46713.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@46714.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@46720.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@46721.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46728.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@46729.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@46737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@46744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@46745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@46765.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@46766.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@46772.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@46773.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@46779.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@46780.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@46787.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@46788.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@46795.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@46796.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@46816.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@46817.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@46823.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@46824.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@46830.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@46831.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@46838.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@46839.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46848.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@46849.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46867.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_303) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@46868.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@46874.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@46875.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@46881.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@46882.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46889.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_313) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@46890.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@46897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@46898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@46916.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_303) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@46917.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@46923.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@46924.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@46930.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@46931.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_340) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46938.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_340) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@46939.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@46946.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@46947.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@46964.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@46965.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@46971.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@46972.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@46978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@46979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@46986.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@46987.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@46994.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@46995.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_374) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47005.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_374) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@47006.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47042.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_401) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@47043.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47050.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_405) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@47051.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47058.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_409) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@47059.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47066.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_413) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@47067.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47074.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_417) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@47075.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@47084.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_401) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@47085.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@47091.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@47092.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@47099.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_405) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@47100.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_432) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47107.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_432) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@47108.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_436) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47115.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_436) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@47116.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@47123.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_413) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@47124.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@47132.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_417) begin $fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@47133.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@47142.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_401) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@47143.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@47149.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@47150.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@47157.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_405) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@47158.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_432) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@47165.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_432) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@47166.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_436) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@47173.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_436) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@47174.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_469) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_469) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@47183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@47191.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_417) begin $fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@47192.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@47201.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_401) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@47202.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@47209.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_409) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@47210.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@47217.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_413) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@47218.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@47226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_417) begin $fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@47227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@47236.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_401) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@47237.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@47244.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_409) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@47245.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_469) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@47253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_469) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@47254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@47262.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_417) begin $fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@47263.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@47272.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_401) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@47273.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@47280.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_409) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@47281.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@47288.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_413) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@47289.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@47297.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_417) begin $fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@47298.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_569) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47362.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_569) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@47363.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_573) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47370.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_573) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@47371.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47378.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_577) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@47379.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_581) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47386.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_581) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@47387.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_585) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47394.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_585) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@47395.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_618) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47443.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_618) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@47444.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_622) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47451.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_622) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@47452.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_626) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47459.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_626) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@47460.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_630) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47467.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_630) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@47468.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_634) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47475.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_634) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@47476.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_638) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47483.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_638) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@47484.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_683 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47559.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_683 & _T_691) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@47560.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_698 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47582.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_698 & _T_705) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@47583.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_712) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47594.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_712) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@47595.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_725) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:59:47)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47614.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_725) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@47615.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLWidthWidget_4( // @[:freechips.rocketchip.system.TinyConfig.fir@47627.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@47628.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@47629.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@47630.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] TLMonitor_24 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@47637.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@47689.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@47688.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@47639.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@47640.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@47685.4] endmodule module TLMonitor_25( // @[:freechips.rocketchip.system.TinyConfig.fir@47719.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@47720.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@47721.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@47722.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@48924.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47737.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47738.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@47741.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47742.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47750.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47761.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47762.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47763.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@47765.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@47766.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@47767.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@47768.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@47768.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@47769.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@47771.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@47772.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@47774.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@47775.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@47776.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@47777.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@47778.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47780.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47781.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47783.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47784.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@47785.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@47786.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@47787.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47788.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47789.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47790.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47791.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47792.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47793.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47794.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47795.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47796.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47797.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47798.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47799.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@47802.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@47859.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@47862.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@47863.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@47864.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@47865.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@47866.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47871.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47884.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47885.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47892.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47893.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47899.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47900.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@47905.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47907.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47908.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@47913.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@47914.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47916.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47917.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@47922.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47924.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47925.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@47931.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@47985.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47987.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47988.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@48011.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@48014.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@48022.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48025.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48026.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@48045.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48047.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48048.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@48053.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48055.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48056.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@48070.6] wire _T_260; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@48121.6] wire [3:0] _T_285; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@48163.8] wire [3:0] _T_286; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@48164.8] wire _T_287; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@48165.8] wire _T_289; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48167.8] wire _T_290; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48168.8] wire _T_291; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@48174.6] wire _T_292; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@48176.8] wire _T_299; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@48183.8] wire _T_302; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48186.8] wire _T_303; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48187.8] wire _T_310; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@48206.8] wire _T_312; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48208.8] wire _T_313; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48209.8] wire _T_318; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@48223.6] wire _T_337; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@48255.8] wire _T_339; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48257.8] wire _T_340; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48258.8] wire _T_345; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@48272.6] wire _T_371; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@48322.6] wire _T_373; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48324.6] wire _T_374; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48325.6] wire _T_375; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@48330.6] wire _T_376; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@48331.6] wire [1:0] _T_379; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@48334.6] wire _T_380; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@48335.6] wire _T_388; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@48343.6] wire _T_394; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48354.6] wire _T_395; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48355.6] wire _T_396; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48356.6] wire _T_398; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@48358.6] wire _T_400; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48361.8] wire _T_401; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48362.8] wire _T_402; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@48367.8] wire _T_404; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48369.8] wire _T_405; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48370.8] wire _T_406; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@48375.8] wire _T_408; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48377.8] wire _T_409; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48378.8] wire _T_410; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@48383.8] wire _T_412; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48385.8] wire _T_413; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48386.8] wire _T_414; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@48391.8] wire _T_416; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48393.8] wire _T_417; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48394.8] wire _T_418; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@48400.6] wire _T_429; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@48424.8] wire _T_431; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48426.8] wire _T_432; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48427.8] wire _T_433; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@48432.8] wire _T_435; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48434.8] wire _T_436; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48435.8] wire _T_446; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@48458.6] wire _T_466; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@48499.8] wire _T_468; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48501.8] wire _T_469; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48502.8] wire _T_475; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@48517.6] wire _T_492; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@48552.6] wire _T_510; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@48588.6] wire _T_539; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@48648.4] wire [3:0] _T_544; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@48653.4] wire _T_545; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@48654.4] wire _T_546; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@48655.4] reg [3:0] _T_548; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@48657.4] reg [31:0] _RAND_0; wire [3:0] _T_550; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48659.4] wire _T_551; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48660.4] reg [2:0] _T_559; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@48671.4] reg [31:0] _RAND_1; reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@48672.4] reg [31:0] _RAND_2; reg [2:0] _T_561; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@48673.4] reg [31:0] _RAND_3; reg [4:0] _T_562; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@48674.4] reg [31:0] _RAND_4; reg [31:0] _T_563; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@48675.4] reg [31:0] _RAND_5; wire _T_564; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@48676.4] wire _T_565; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@48677.4] wire _T_566; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@48679.6] wire _T_568; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48681.6] wire _T_569; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48682.6] wire _T_570; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@48687.6] wire _T_572; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48689.6] wire _T_573; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48690.6] wire _T_574; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@48695.6] wire _T_576; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48697.6] wire _T_577; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48698.6] wire _T_578; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@48703.6] wire _T_580; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48705.6] wire _T_581; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48706.6] wire _T_582; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@48711.6] wire _T_584; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48713.6] wire _T_585; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48714.6] wire _T_587; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@48721.4] wire _T_588; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@48729.4] wire [12:0] _T_590; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@48731.4] wire [5:0] _T_591; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@48732.4] wire [5:0] _T_592; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@48733.4] wire [3:0] _T_593; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@48734.4] wire _T_594; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@48735.4] reg [3:0] _T_596; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@48737.4] reg [31:0] _RAND_6; wire [3:0] _T_598; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48739.4] wire _T_599; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48740.4] reg [2:0] _T_607; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@48751.4] reg [31:0] _RAND_7; reg [1:0] _T_608; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@48752.4] reg [31:0] _RAND_8; reg [2:0] _T_609; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@48753.4] reg [31:0] _RAND_9; reg [4:0] _T_610; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@48754.4] reg [31:0] _RAND_10; reg _T_611; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@48755.4] reg [31:0] _RAND_11; reg _T_612; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@48756.4] reg [31:0] _RAND_12; wire _T_613; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@48757.4] wire _T_614; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@48758.4] wire _T_615; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@48760.6] wire _T_617; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48762.6] wire _T_618; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48763.6] wire _T_619; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@48768.6] wire _T_621; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48770.6] wire _T_622; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48771.6] wire _T_623; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@48776.6] wire _T_625; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48778.6] wire _T_626; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48779.6] wire _T_627; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@48784.6] wire _T_629; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48786.6] wire _T_630; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48787.6] wire _T_631; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@48792.6] wire _T_633; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48794.6] wire _T_634; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48795.6] wire _T_635; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@48800.6] wire _T_637; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48802.6] wire _T_638; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48803.6] wire _T_640; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@48810.4] reg [17:0] _T_641; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@48819.4] reg [31:0] _RAND_13; reg [3:0] _T_651; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@48829.4] reg [31:0] _RAND_14; wire [3:0] _T_653; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48831.4] wire _T_654; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48832.4] reg [3:0] _T_670; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@48851.4] reg [31:0] _RAND_15; wire [3:0] _T_672; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48853.4] wire _T_673; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48854.4] wire _T_683; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@48869.4] wire [31:0] _T_685; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@48872.6] wire [17:0] _T_686; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@48874.6] wire _T_687; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@48875.6] wire _T_688; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@48876.6] wire _T_690; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48878.6] wire _T_691; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48879.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@48871.4] wire _T_695; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@48890.4] wire _T_697; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@48892.4] wire _T_698; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@48893.4] wire [31:0] _T_699; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@48895.6] wire [17:0] _T_681; // @[:freechips.rocketchip.system.TinyConfig.fir@48865.4 :freechips.rocketchip.system.TinyConfig.fir@48867.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@48873.6] wire [17:0] _T_700; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@48897.6] wire [17:0] _T_701; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@48898.6] wire _T_702; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@48899.6] wire _T_704; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48901.6] wire _T_705; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48902.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@48894.4] wire [17:0] _T_692; // @[:freechips.rocketchip.system.TinyConfig.fir@48885.4 :freechips.rocketchip.system.TinyConfig.fir@48887.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@48896.6] wire _T_706; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@48908.4] wire _T_707; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@48909.4] wire _T_708; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@48910.4] wire _T_709; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@48911.4] wire _T_711; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48913.4] wire _T_712; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48914.4] wire [17:0] _T_713; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@48919.4] wire [17:0] _T_714; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@48920.4] wire [17:0] _T_715; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@48921.4] reg [31:0] _T_716; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@48923.4] reg [31:0] _RAND_16; wire _T_717; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@48926.4] wire _T_718; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@48927.4] wire _T_719; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@48928.4] wire _T_720; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@48929.4] wire _T_721; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@48930.4] wire _T_722; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@48931.4] wire _T_724; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48933.4] wire _T_725; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48934.4] wire [31:0] _T_727; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@48940.4] wire _T_730; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@48944.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47873.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@47945.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48028.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@48087.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@48138.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48189.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@48238.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@48286.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48364.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@48406.10] wire _GEN_139; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@48464.10] wire _GEN_153; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@48523.10] wire _GEN_161; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@48558.10] wire _GEN_169; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@48594.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@48924.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47737.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@47738.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@47741.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47742.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@47750.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47761.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47762.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@47763.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@47765.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@47766.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@47767.6] assign _GEN_18 = {{26'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@47768.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@47768.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@47769.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@47771.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@47772.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@47774.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@47775.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@47776.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@47777.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@47778.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47780.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47781.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47783.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47784.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@47785.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@47786.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@47787.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47788.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47789.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47790.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47791.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47792.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47793.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47794.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47795.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47796.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@47797.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@47798.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@47799.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@47802.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@47859.6] assign _T_120 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@47862.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@47863.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@47864.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@47865.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@47866.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47871.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47884.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47885.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47892.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47893.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47899.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47900.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@47905.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47907.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47908.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@47913.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@47914.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47916.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47917.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@47922.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47924.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47925.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@47931.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@47985.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47987.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47988.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@48011.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@48014.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@48022.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48025.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48026.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@48045.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48047.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48048.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@48053.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48055.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48056.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@48070.6] assign _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@48121.6] assign _T_285 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@48163.8] assign _T_286 = io_in_a_bits_mask & _T_285; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@48164.8] assign _T_287 = _T_286 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@48165.8] assign _T_289 = _T_287 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48167.8] assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48168.8] assign _T_291 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@48174.6] assign _T_292 = 3'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48:freechips.rocketchip.system.TinyConfig.fir@48176.8] assign _T_299 = _T_292 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@48183.8] assign _T_302 = _T_299 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48186.8] assign _T_303 = _T_302 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48187.8] assign _T_310 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@48206.8] assign _T_312 = _T_310 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48208.8] assign _T_313 = _T_312 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48209.8] assign _T_318 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@48223.6] assign _T_337 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@48255.8] assign _T_339 = _T_337 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48257.8] assign _T_340 = _T_339 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48258.8] assign _T_345 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@48272.6] assign _T_371 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@48322.6] assign _T_373 = _T_371 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48324.6] assign _T_374 = _T_373 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48325.6] assign _T_375 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@48330.6] assign _T_376 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@48331.6] assign _T_379 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@48334.6] assign _T_380 = _T_379 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@48335.6] assign _T_388 = _T_379 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@48343.6] assign _T_394 = _T_375 | _T_376; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48354.6] assign _T_395 = _T_394 | _T_380; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48355.6] assign _T_396 = _T_395 | _T_388; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@48356.6] assign _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@48358.6] assign _T_400 = _T_396 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48361.8] assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48362.8] assign _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@48367.8] assign _T_404 = _T_402 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48369.8] assign _T_405 = _T_404 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48370.8] assign _T_406 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@48375.8] assign _T_408 = _T_406 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48377.8] assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48378.8] assign _T_410 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@48383.8] assign _T_412 = _T_410 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48385.8] assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48386.8] assign _T_414 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@48391.8] assign _T_416 = _T_414 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48393.8] assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48394.8] assign _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@48400.6] assign _T_429 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@48424.8] assign _T_431 = _T_429 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48426.8] assign _T_432 = _T_431 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48427.8] assign _T_433 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@48432.8] assign _T_435 = _T_433 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48434.8] assign _T_436 = _T_435 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48435.8] assign _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@48458.6] assign _T_466 = _T_414 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@48499.8] assign _T_468 = _T_466 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48501.8] assign _T_469 = _T_468 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48502.8] assign _T_475 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@48517.6] assign _T_492 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@48552.6] assign _T_510 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@48588.6] assign _T_539 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@48648.4] assign _T_544 = _T_30[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@48653.4] assign _T_545 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@48654.4] assign _T_546 = _T_545 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@48655.4] assign _T_550 = _T_548 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48659.4] assign _T_551 = _T_548 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48660.4] assign _T_564 = _T_551 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@48676.4] assign _T_565 = io_in_a_valid & _T_564; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@48677.4] assign _T_566 = io_in_a_bits_opcode == _T_559; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@48679.6] assign _T_568 = _T_566 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48681.6] assign _T_569 = _T_568 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48682.6] assign _T_570 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@48687.6] assign _T_572 = _T_570 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48689.6] assign _T_573 = _T_572 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48690.6] assign _T_574 = io_in_a_bits_size == _T_561; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@48695.6] assign _T_576 = _T_574 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48697.6] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48698.6] assign _T_578 = io_in_a_bits_source == _T_562; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@48703.6] assign _T_580 = _T_578 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48705.6] assign _T_581 = _T_580 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48706.6] assign _T_582 = io_in_a_bits_address == _T_563; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@48711.6] assign _T_584 = _T_582 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48713.6] assign _T_585 = _T_584 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48714.6] assign _T_587 = _T_539 & _T_551; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@48721.4] assign _T_588 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@48729.4] assign _T_590 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@48731.4] assign _T_591 = _T_590[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@48732.4] assign _T_592 = ~ _T_591; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@48733.4] assign _T_593 = _T_592[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@48734.4] assign _T_594 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@48735.4] assign _T_598 = _T_596 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48739.4] assign _T_599 = _T_596 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48740.4] assign _T_613 = _T_599 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@48757.4] assign _T_614 = io_in_d_valid & _T_613; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@48758.4] assign _T_615 = io_in_d_bits_opcode == _T_607; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@48760.6] assign _T_617 = _T_615 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48762.6] assign _T_618 = _T_617 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48763.6] assign _T_619 = io_in_d_bits_param == _T_608; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@48768.6] assign _T_621 = _T_619 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48770.6] assign _T_622 = _T_621 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48771.6] assign _T_623 = io_in_d_bits_size == _T_609; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@48776.6] assign _T_625 = _T_623 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48778.6] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48779.6] assign _T_627 = io_in_d_bits_source == _T_610; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@48784.6] assign _T_629 = _T_627 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48786.6] assign _T_630 = _T_629 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48787.6] assign _T_631 = io_in_d_bits_sink == _T_611; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@48792.6] assign _T_633 = _T_631 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48794.6] assign _T_634 = _T_633 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48795.6] assign _T_635 = io_in_d_bits_denied == _T_612; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@48800.6] assign _T_637 = _T_635 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48802.6] assign _T_638 = _T_637 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48803.6] assign _T_640 = _T_588 & _T_599; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@48810.4] assign _T_653 = _T_651 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48831.4] assign _T_654 = _T_651 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48832.4] assign _T_672 = _T_670 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@48853.4] assign _T_673 = _T_670 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@48854.4] assign _T_683 = _T_539 & _T_654; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@48869.4] assign _T_685 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@48872.6] assign _T_686 = _T_641 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@48874.6] assign _T_687 = _T_686[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@48875.6] assign _T_688 = _T_687 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@48876.6] assign _T_690 = _T_688 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48878.6] assign _T_691 = _T_690 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48879.6] assign _GEN_15 = _T_683 ? _T_685 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@48871.4] assign _T_695 = _T_588 & _T_673; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@48890.4] assign _T_697 = _T_398 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@48892.4] assign _T_698 = _T_695 & _T_697; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@48893.4] assign _T_699 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@48895.6] assign _T_681 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@48865.4 :freechips.rocketchip.system.TinyConfig.fir@48867.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@48873.6] assign _T_700 = _T_681 | _T_641; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@48897.6] assign _T_701 = _T_700 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@48898.6] assign _T_702 = _T_701[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@48899.6] assign _T_704 = _T_702 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48901.6] assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48902.6] assign _GEN_16 = _T_698 ? _T_699 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@48894.4] assign _T_692 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@48885.4 :freechips.rocketchip.system.TinyConfig.fir@48887.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@48896.6] assign _T_706 = _T_681 != _T_692; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@48908.4] assign _T_707 = _T_681 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@48909.4] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@48910.4] assign _T_709 = _T_706 | _T_708; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@48911.4] assign _T_711 = _T_709 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48913.4] assign _T_712 = _T_711 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48914.4] assign _T_713 = _T_641 | _T_681; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@48919.4] assign _T_714 = ~ _T_692; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@48920.4] assign _T_715 = _T_713 & _T_714; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@48921.4] assign _T_717 = _T_641 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@48926.4] assign _T_718 = _T_717 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@48927.4] assign _T_719 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@48928.4] assign _T_720 = _T_718 | _T_719; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@48929.4] assign _T_721 = _T_716 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@48930.4] assign _T_722 = _T_720 | _T_721; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@48931.4] assign _T_724 = _T_722 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48933.4] assign _T_725 = _T_724 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48934.4] assign _T_727 = _T_716 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@48940.4] assign _T_730 = _T_539 | _T_588; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@48944.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47873.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@47945.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48028.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@48087.10] assign _GEN_75 = io_in_a_valid & _T_260; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@48138.10] assign _GEN_85 = io_in_a_valid & _T_291; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48189.10] assign _GEN_95 = io_in_a_valid & _T_318; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@48238.10] assign _GEN_105 = io_in_a_valid & _T_345; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@48286.10] assign _GEN_115 = io_in_d_valid & _T_398; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48364.10] assign _GEN_125 = io_in_d_valid & _T_418; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@48406.10] assign _GEN_139 = io_in_d_valid & _T_446; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@48464.10] assign _GEN_153 = io_in_d_valid & _T_475; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@48523.10] assign _GEN_161 = io_in_d_valid & _T_492; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@48558.10] assign _GEN_169 = io_in_d_valid & _T_510; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@48594.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_548 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_559 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_560 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_561 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_562 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_563 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_596 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_607 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_608 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_609 = _RAND_9[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_610 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_611 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_612 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_641 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_651 = _RAND_14[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_670 = _RAND_15[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_716 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_548 <= 4'h0; end else begin if (_T_539) begin if (_T_551) begin if (_T_546) begin _T_548 <= _T_544; end else begin _T_548 <= 4'h0; end end else begin _T_548 <= _T_550; end end end if (_T_587) begin _T_559 <= io_in_a_bits_opcode; end if (_T_587) begin _T_560 <= io_in_a_bits_param; end if (_T_587) begin _T_561 <= io_in_a_bits_size; end if (_T_587) begin _T_562 <= io_in_a_bits_source; end if (_T_587) begin _T_563 <= io_in_a_bits_address; end if (reset) begin _T_596 <= 4'h0; end else begin if (_T_588) begin if (_T_599) begin if (_T_594) begin _T_596 <= _T_593; end else begin _T_596 <= 4'h0; end end else begin _T_596 <= _T_598; end end end if (_T_640) begin _T_607 <= io_in_d_bits_opcode; end if (_T_640) begin _T_608 <= io_in_d_bits_param; end if (_T_640) begin _T_609 <= io_in_d_bits_size; end if (_T_640) begin _T_610 <= io_in_d_bits_source; end if (_T_640) begin _T_611 <= io_in_d_bits_sink; end if (_T_640) begin _T_612 <= io_in_d_bits_denied; end if (reset) begin _T_641 <= 18'h0; end else begin _T_641 <= _T_715; end if (reset) begin _T_651 <= 4'h0; end else begin if (_T_539) begin if (_T_654) begin if (_T_546) begin _T_651 <= _T_544; end else begin _T_651 <= 4'h0; end end else begin _T_651 <= _T_653; end end end if (reset) begin _T_670 <= 4'h0; end else begin if (_T_588) begin if (_T_673) begin if (_T_594) begin _T_670 <= _T_593; end else begin _T_670 <= 4'h0; end end else begin _T_670 <= _T_672; end end end if (reset) begin _T_716 <= 32'h0; end else begin if (_T_730) begin _T_716 <= 32'h0; end else begin _T_716 <= _T_727; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47873.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@47874.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@47880.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@47881.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47887.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@47888.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47895.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@47896.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47902.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@47903.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47910.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@47911.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47919.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@47920.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47927.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@47928.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@47945.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@47946.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@47952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@47953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@47959.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@47960.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@47967.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@47968.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@47974.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@47975.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@47982.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@47983.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47990.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@47991.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@47999.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@48000.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@48007.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@48008.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48028.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@48029.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@48035.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@48036.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@48042.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@48043.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48050.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@48051.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48058.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@48059.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@48066.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@48067.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@48087.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_212) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@48088.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@48094.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@48095.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@48101.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@48102.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@48109.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@48110.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@48117.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@48118.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@48138.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_212) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@48139.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@48145.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@48146.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@48152.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@48153.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@48160.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@48161.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_290) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48170.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_290) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@48171.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48189.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_303) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@48190.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@48196.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@48197.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@48203.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@48204.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_313) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48211.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_313) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@48212.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@48219.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@48220.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_303) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@48238.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_303) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@48239.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@48245.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@48246.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@48252.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@48253.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_340) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48260.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_340) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@48261.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@48268.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@48269.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@48286.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@48287.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@48293.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@48294.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@48300.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@48301.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@48308.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@48309.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@48316.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@48317.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_374) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48327.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_374) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@48328.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48364.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_401) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@48365.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48372.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_405) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@48373.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48380.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_409) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@48381.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_413) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@48389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48396.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_417) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@48397.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@48406.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_401) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@48407.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@48413.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_129) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@48414.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@48421.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_405) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@48422.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_432) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48429.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_432) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@48430.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_436) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48437.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_436) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@48438.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@48445.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_413) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@48446.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@48454.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_417) begin $fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@48455.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@48464.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_401) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@48465.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@48471.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_129) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@48472.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_405) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@48479.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_405) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@48480.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_432) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@48487.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_432) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@48488.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_436) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@48495.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_436) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@48496.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_469) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_469) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@48505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_139 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@48513.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_139 & _T_417) begin $fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@48514.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@48523.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_401) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@48524.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@48531.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_409) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@48532.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@48539.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_413) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@48540.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_153 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@48548.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_153 & _T_417) begin $fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@48549.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@48558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_401) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@48559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@48566.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_409) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@48567.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_469) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@48575.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_469) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@48576.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@48584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_417) begin $fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@48585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_401) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@48594.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_401) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@48595.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_409) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@48602.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_409) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@48603.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_413) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@48610.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_413) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@48611.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_169 & _T_417) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@48619.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_169 & _T_417) begin $fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@48620.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_569) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48684.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_569) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@48685.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_573) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48692.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_573) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@48693.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48700.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_577) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@48701.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_581) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48708.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_581) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@48709.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_565 & _T_585) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48716.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_565 & _T_585) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@48717.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_618) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48765.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_618) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@48766.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_622) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48773.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_622) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@48774.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_626) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48781.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_626) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@48782.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_630) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48789.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_630) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@48790.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_634) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48797.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_634) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@48798.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_614 & _T_638) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48805.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_614 & _T_638) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@48806.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_683 & _T_691) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48881.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_683 & _T_691) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@48882.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_698 & _T_705) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48904.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_698 & _T_705) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@48905.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_712) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48916.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_712) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@48917.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_725) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:59:68)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48936.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_725) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@48937.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLBuffer_8( // @[:freechips.rocketchip.system.TinyConfig.fir@48949.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@48950.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@48951.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@48952.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] TLMonitor_25 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@48959.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49011.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49010.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@48961.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@48962.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@49007.4] endmodule module SimpleLazyModule_9( // @[:freechips.rocketchip.system.TinyConfig.fir@49033.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@49034.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@49035.4] output auto_buffer_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_buffer_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [2:0] auto_buffer_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [2:0] auto_buffer_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [2:0] auto_buffer_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [4:0] auto_buffer_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [31:0] auto_buffer_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [3:0] auto_buffer_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [31:0] auto_buffer_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_buffer_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_buffer_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_buffer_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [2:0] auto_buffer_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [1:0] auto_buffer_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [2:0] auto_buffer_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [4:0] auto_buffer_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_buffer_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_buffer_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [31:0] auto_buffer_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_buffer_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_tl_slave_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_tl_slave_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [2:0] auto_tl_slave_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [2:0] auto_tl_slave_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [2:0] auto_tl_slave_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [4:0] auto_tl_slave_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [31:0] auto_tl_slave_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [3:0] auto_tl_slave_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output [31:0] auto_tl_slave_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] output auto_tl_slave_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_tl_slave_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [2:0] auto_tl_slave_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [1:0] auto_tl_slave_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [2:0] auto_tl_slave_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [4:0] auto_tl_slave_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_tl_slave_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_tl_slave_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input [31:0] auto_tl_slave_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] input auto_tl_slave_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@49036.4] ); wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [4:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [4:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [4:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [4:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] TLWidthWidget_4 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.TinyConfig.fir@49041.4] .clock(widget_clock), .reset(widget_reset), .auto_in_a_ready(widget_auto_in_a_ready), .auto_in_a_valid(widget_auto_in_a_valid), .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode), .auto_in_a_bits_param(widget_auto_in_a_bits_param), .auto_in_a_bits_size(widget_auto_in_a_bits_size), .auto_in_a_bits_source(widget_auto_in_a_bits_source), .auto_in_a_bits_address(widget_auto_in_a_bits_address), .auto_in_a_bits_mask(widget_auto_in_a_bits_mask), .auto_in_a_bits_data(widget_auto_in_a_bits_data), .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt), .auto_in_d_ready(widget_auto_in_d_ready), .auto_in_d_valid(widget_auto_in_d_valid), .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode), .auto_in_d_bits_param(widget_auto_in_d_bits_param), .auto_in_d_bits_size(widget_auto_in_d_bits_size), .auto_in_d_bits_source(widget_auto_in_d_bits_source), .auto_in_d_bits_sink(widget_auto_in_d_bits_sink), .auto_in_d_bits_denied(widget_auto_in_d_bits_denied), .auto_in_d_bits_data(widget_auto_in_d_bits_data), .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt), .auto_out_a_ready(widget_auto_out_a_ready), .auto_out_a_valid(widget_auto_out_a_valid), .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode), .auto_out_a_bits_param(widget_auto_out_a_bits_param), .auto_out_a_bits_size(widget_auto_out_a_bits_size), .auto_out_a_bits_source(widget_auto_out_a_bits_source), .auto_out_a_bits_address(widget_auto_out_a_bits_address), .auto_out_a_bits_mask(widget_auto_out_a_bits_mask), .auto_out_a_bits_data(widget_auto_out_a_bits_data), .auto_out_d_ready(widget_auto_out_d_ready), .auto_out_d_valid(widget_auto_out_d_valid), .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode), .auto_out_d_bits_param(widget_auto_out_d_bits_param), .auto_out_d_bits_size(widget_auto_out_d_bits_size), .auto_out_d_bits_source(widget_auto_out_d_bits_source), .auto_out_d_bits_sink(widget_auto_out_d_bits_sink), .auto_out_d_bits_denied(widget_auto_out_d_bits_denied), .auto_out_d_bits_data(widget_auto_out_d_bits_data), .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt) ); TLBuffer_8 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@49047.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign auto_tl_slave_xing_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign auto_tl_slave_xing_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@49060.4] assign widget_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@49045.4] assign widget_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@49046.4] assign widget_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign widget_auto_out_a_ready = auto_tl_slave_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_valid = auto_tl_slave_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_opcode = auto_tl_slave_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_param = auto_tl_slave_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_size = auto_tl_slave_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_source = auto_tl_slave_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_sink = auto_tl_slave_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_denied = auto_tl_slave_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_data = auto_tl_slave_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign widget_auto_out_d_bits_corrupt = auto_tl_slave_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49058.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@49051.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@49052.4] assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@49061.4] assign buffer_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] assign buffer_auto_out_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@49059.4] endmodule module TLMonitor_26( // @[:freechips.rocketchip.system.TinyConfig.fir@49071.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@49072.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@49073.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@49074.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@50548.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49089.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49090.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@49093.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49094.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49102.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49113.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49114.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49115.6] wire [26:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@49117.6] wire [11:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@49118.6] wire [11:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@49119.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@49120.6] wire [31:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@49120.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@49121.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@49123.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@49124.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@49126.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@49127.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@49128.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@49129.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@49130.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49132.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49133.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49135.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49136.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@49137.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@49138.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@49139.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49140.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49141.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49142.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49143.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49144.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49145.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49146.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49147.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49148.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49149.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49150.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49151.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@49154.6] wire [32:0] _T_69; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49158.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@49211.6] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49214.8] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49215.8] wire [32:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49216.8] wire [32:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49217.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49218.8] wire [31:0] _T_125; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49219.8] wire [32:0] _T_126; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49220.8] wire [32:0] _T_127; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49221.8] wire [32:0] _T_128; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49222.8] wire _T_129; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49223.8] wire [31:0] _T_130; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49224.8] wire [32:0] _T_131; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49225.8] wire [32:0] _T_132; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49226.8] wire [32:0] _T_133; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49227.8] wire _T_134; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49228.8] wire [32:0] _T_137; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49231.8] wire [32:0] _T_138; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49232.8] wire _T_139; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49233.8] wire [31:0] _T_140; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49234.8] wire [32:0] _T_141; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49235.8] wire [32:0] _T_142; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49236.8] wire [32:0] _T_143; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49237.8] wire _T_144; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49238.8] wire [31:0] _T_145; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49239.8] wire [32:0] _T_146; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49240.8] wire [32:0] _T_147; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49241.8] wire [32:0] _T_148; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49242.8] wire _T_149; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49243.8] wire _T_150; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49244.8] wire _T_151; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49245.8] wire _T_152; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49246.8] wire _T_153; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49247.8] wire _T_159; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49253.8] wire _T_164; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49266.8] wire _T_165; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49267.8] wire _T_168; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49274.8] wire _T_169; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49275.8] wire _T_171; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49281.8] wire _T_172; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49282.8] wire _T_173; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@49287.8] wire _T_175; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49289.8] wire _T_176; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49290.8] wire [3:0] _T_177; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@49295.8] wire _T_178; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@49296.8] wire _T_180; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49298.8] wire _T_181; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49299.8] wire _T_182; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@49304.8] wire _T_184; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49306.8] wire _T_185; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49307.8] wire _T_186; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@49313.6] wire _T_245; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@49397.8] wire _T_247; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49399.8] wire _T_248; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49400.8] wire _T_258; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@49423.6] wire _T_260; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49426.8] wire _T_268; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49434.8] wire _T_270; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49436.8] wire _T_298; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49464.8] wire _T_299; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49465.8] wire _T_300; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49466.8] wire _T_301; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49467.8] wire _T_302; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49468.8] wire _T_304; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@49470.8] wire _T_306; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49472.8] wire _T_307; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49473.8] wire _T_314; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@49492.8] wire _T_316; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49494.8] wire _T_317; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49495.8] wire _T_318; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@49500.8] wire _T_320; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49502.8] wire _T_321; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49503.8] wire _T_326; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@49517.6] wire _T_364; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49556.8] wire _T_373; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@49565.8] wire _T_376; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49568.8] wire _T_377; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49569.8] wire _T_392; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@49605.6] wire [3:0] _T_454; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@49684.8] wire [3:0] _T_455; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@49685.8] wire _T_456; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@49686.8] wire _T_458; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49688.8] wire _T_459; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49689.8] wire _T_460; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@49695.6] wire _T_462; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49698.8] wire _T_494; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49730.8] wire _T_505; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49741.8] wire _T_506; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49742.8] wire _T_513; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@49761.8] wire _T_515; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49763.8] wire _T_516; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49764.8] wire _T_521; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@49778.6] wire _T_574; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@49844.8] wire _T_576; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49846.8] wire _T_577; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49847.8] wire _T_582; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@49861.6] wire _T_627; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49907.8] wire _T_628; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49908.8] wire _T_643; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@49946.6] wire _T_645; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49948.6] wire _T_646; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49949.6] wire _T_647; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49954.6] wire _T_648; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49955.6] wire [1:0] _T_651; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@49958.6] wire _T_652; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49959.6] wire _T_660; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49967.6] wire _T_666; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49978.6] wire _T_667; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49979.6] wire _T_668; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49980.6] wire _T_670; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@49982.6] wire _T_672; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49985.8] wire _T_673; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49986.8] wire _T_674; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@49991.8] wire _T_676; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49993.8] wire _T_677; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49994.8] wire _T_678; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@49999.8] wire _T_680; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50001.8] wire _T_681; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50002.8] wire _T_682; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@50007.8] wire _T_684; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50009.8] wire _T_685; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50010.8] wire _T_686; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@50015.8] wire _T_688; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50017.8] wire _T_689; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50018.8] wire _T_690; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@50024.6] wire _T_701; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@50048.8] wire _T_703; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50050.8] wire _T_704; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50051.8] wire _T_705; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@50056.8] wire _T_707; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50058.8] wire _T_708; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50059.8] wire _T_718; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@50082.6] wire _T_738; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@50123.8] wire _T_740; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50125.8] wire _T_741; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50126.8] wire _T_747; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@50141.6] wire _T_764; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@50176.6] wire _T_782; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@50212.6] wire _T_811; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@50272.4] wire [9:0] _T_816; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@50277.4] wire _T_817; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@50278.4] wire _T_818; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@50279.4] reg [9:0] _T_820; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@50281.4] reg [31:0] _RAND_0; wire [9:0] _T_822; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50283.4] wire _T_823; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50284.4] reg [2:0] _T_831; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@50295.4] reg [31:0] _RAND_1; reg [2:0] _T_832; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@50296.4] reg [31:0] _RAND_2; reg [3:0] _T_833; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@50297.4] reg [31:0] _RAND_3; reg [4:0] _T_834; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@50298.4] reg [31:0] _RAND_4; reg [31:0] _T_835; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@50299.4] reg [31:0] _RAND_5; wire _T_836; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@50300.4] wire _T_837; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@50301.4] wire _T_838; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@50303.6] wire _T_840; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50305.6] wire _T_841; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50306.6] wire _T_842; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@50311.6] wire _T_844; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50313.6] wire _T_845; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50314.6] wire _T_846; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@50319.6] wire _T_848; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50321.6] wire _T_849; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50322.6] wire _T_850; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@50327.6] wire _T_852; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50329.6] wire _T_853; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50330.6] wire _T_854; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@50335.6] wire _T_856; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50337.6] wire _T_857; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50338.6] wire _T_859; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@50345.4] wire _T_860; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@50353.4] wire [26:0] _T_862; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@50355.4] wire [11:0] _T_863; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@50356.4] wire [11:0] _T_864; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@50357.4] wire [9:0] _T_865; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@50358.4] wire _T_866; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@50359.4] reg [9:0] _T_868; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@50361.4] reg [31:0] _RAND_6; wire [9:0] _T_870; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50363.4] wire _T_871; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50364.4] reg [2:0] _T_879; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@50375.4] reg [31:0] _RAND_7; reg [1:0] _T_880; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@50376.4] reg [31:0] _RAND_8; reg [3:0] _T_881; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@50377.4] reg [31:0] _RAND_9; reg [4:0] _T_882; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@50378.4] reg [31:0] _RAND_10; reg _T_883; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@50379.4] reg [31:0] _RAND_11; reg _T_884; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@50380.4] reg [31:0] _RAND_12; wire _T_885; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@50381.4] wire _T_886; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@50382.4] wire _T_887; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@50384.6] wire _T_889; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50386.6] wire _T_890; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50387.6] wire _T_891; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@50392.6] wire _T_893; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50394.6] wire _T_894; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50395.6] wire _T_895; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@50400.6] wire _T_897; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50402.6] wire _T_898; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50403.6] wire _T_899; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@50408.6] wire _T_901; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50410.6] wire _T_902; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50411.6] wire _T_903; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@50416.6] wire _T_905; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50418.6] wire _T_906; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50419.6] wire _T_907; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@50424.6] wire _T_909; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50426.6] wire _T_910; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50427.6] wire _T_912; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@50434.4] reg [17:0] _T_913; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@50443.4] reg [31:0] _RAND_13; reg [9:0] _T_923; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@50453.4] reg [31:0] _RAND_14; wire [9:0] _T_925; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50455.4] wire _T_926; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50456.4] reg [9:0] _T_942; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@50475.4] reg [31:0] _RAND_15; wire [9:0] _T_944; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50477.4] wire _T_945; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50478.4] wire _T_955; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@50493.4] wire [31:0] _T_957; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@50496.6] wire [17:0] _T_958; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@50498.6] wire _T_959; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@50499.6] wire _T_960; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@50500.6] wire _T_962; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50502.6] wire _T_963; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50503.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@50495.4] wire _T_967; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@50514.4] wire _T_969; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@50516.4] wire _T_970; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@50517.4] wire [31:0] _T_971; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@50519.6] wire [17:0] _T_953; // @[:freechips.rocketchip.system.TinyConfig.fir@50489.4 :freechips.rocketchip.system.TinyConfig.fir@50491.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@50497.6] wire [17:0] _T_972; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@50521.6] wire [17:0] _T_973; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@50522.6] wire _T_974; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@50523.6] wire _T_976; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50525.6] wire _T_977; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50526.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@50518.4] wire [17:0] _T_964; // @[:freechips.rocketchip.system.TinyConfig.fir@50509.4 :freechips.rocketchip.system.TinyConfig.fir@50511.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@50520.6] wire _T_978; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@50532.4] wire _T_979; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@50533.4] wire _T_980; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@50534.4] wire _T_981; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@50535.4] wire _T_983; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50537.4] wire _T_984; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50538.4] wire [17:0] _T_985; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@50543.4] wire [17:0] _T_986; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@50544.4] wire [17:0] _T_987; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@50545.4] reg [31:0] _T_988; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@50547.4] reg [31:0] _RAND_16; wire _T_989; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@50550.4] wire _T_990; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@50551.4] wire _T_991; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@50552.4] wire _T_992; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@50553.4] wire _T_993; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@50554.4] wire _T_994; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@50555.4] wire _T_996; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50557.4] wire _T_997; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50558.4] wire [31:0] _T_999; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@50564.4] wire _T_1002; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@50568.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49255.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@49357.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49475.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49571.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@49659.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49744.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@49827.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49910.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49988.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@50030.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@50088.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@50147.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@50182.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@50218.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@50548.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49089.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49090.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@49093.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49094.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49102.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49113.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49114.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49115.6] assign _T_28 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@49117.6] assign _T_29 = _T_28[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@49118.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@49119.6] assign _GEN_18 = {{20'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@49120.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@49120.6] assign _T_32 = _T_31 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@49121.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@49123.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@49124.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@49126.6] assign _T_38 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@49127.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@49128.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@49129.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@49130.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49132.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49133.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49135.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49136.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@49137.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@49138.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@49139.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49140.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49141.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49142.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49143.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49144.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49145.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49146.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49147.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49148.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@49149.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@49150.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@49151.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@49154.6] assign _T_69 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49158.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@49211.6] assign _T_120 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49214.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49215.8] assign _T_122 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49216.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49217.8] assign _T_124 = $signed(_T_123) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49218.8] assign _T_125 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49219.8] assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49220.8] assign _T_127 = $signed(_T_126) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49221.8] assign _T_128 = $signed(_T_127); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49222.8] assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49223.8] assign _T_130 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49224.8] assign _T_131 = {1'b0,$signed(_T_130)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49225.8] assign _T_132 = $signed(_T_131) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49226.8] assign _T_133 = $signed(_T_132); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49227.8] assign _T_134 = $signed(_T_133) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49228.8] assign _T_137 = $signed(_T_69) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49231.8] assign _T_138 = $signed(_T_137); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49232.8] assign _T_139 = $signed(_T_138) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49233.8] assign _T_140 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49234.8] assign _T_141 = {1'b0,$signed(_T_140)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49235.8] assign _T_142 = $signed(_T_141) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49236.8] assign _T_143 = $signed(_T_142); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49237.8] assign _T_144 = $signed(_T_143) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49238.8] assign _T_145 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@49239.8] assign _T_146 = {1'b0,$signed(_T_145)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@49240.8] assign _T_147 = $signed(_T_146) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49241.8] assign _T_148 = $signed(_T_147); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@49242.8] assign _T_149 = $signed(_T_148) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@49243.8] assign _T_150 = _T_124 | _T_129; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49244.8] assign _T_151 = _T_150 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49245.8] assign _T_152 = _T_151 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49246.8] assign _T_153 = _T_152 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49247.8] assign _T_159 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49253.8] assign _T_164 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49266.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49267.8] assign _T_168 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49274.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49275.8] assign _T_171 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49281.8] assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49282.8] assign _T_173 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@49287.8] assign _T_175 = _T_173 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49289.8] assign _T_176 = _T_175 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49290.8] assign _T_177 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@49295.8] assign _T_178 = _T_177 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@49296.8] assign _T_180 = _T_178 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49298.8] assign _T_181 = _T_180 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49299.8] assign _T_182 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@49304.8] assign _T_184 = _T_182 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49306.8] assign _T_185 = _T_184 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49307.8] assign _T_186 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@49313.6] assign _T_245 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@49397.8] assign _T_247 = _T_245 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49399.8] assign _T_248 = _T_247 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49400.8] assign _T_258 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@49423.6] assign _T_260 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49426.8] assign _T_268 = _T_260 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49434.8] assign _T_270 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49436.8] assign _T_298 = _T_129 | _T_134; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49464.8] assign _T_299 = _T_298 | _T_139; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49465.8] assign _T_300 = _T_299 | _T_144; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49466.8] assign _T_301 = _T_300 | _T_149; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@49467.8] assign _T_302 = _T_270 & _T_301; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49468.8] assign _T_304 = _T_268 | _T_302; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@49470.8] assign _T_306 = _T_304 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49472.8] assign _T_307 = _T_306 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49473.8] assign _T_314 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@49492.8] assign _T_316 = _T_314 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49494.8] assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49495.8] assign _T_318 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@49500.8] assign _T_320 = _T_318 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49502.8] assign _T_321 = _T_320 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49503.8] assign _T_326 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@49517.6] assign _T_364 = _T_270 & _T_300; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49556.8] assign _T_373 = _T_268 | _T_364; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@49565.8] assign _T_376 = _T_373 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49568.8] assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49569.8] assign _T_392 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@49605.6] assign _T_454 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@49684.8] assign _T_455 = io_in_a_bits_mask & _T_454; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@49685.8] assign _T_456 = _T_455 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@49686.8] assign _T_458 = _T_456 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49688.8] assign _T_459 = _T_458 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49689.8] assign _T_460 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@49695.6] assign _T_462 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@49698.8] assign _T_494 = _T_462 & _T_153; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@49730.8] assign _T_505 = _T_494 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49741.8] assign _T_506 = _T_505 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49742.8] assign _T_513 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@49761.8] assign _T_515 = _T_513 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49763.8] assign _T_516 = _T_515 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49764.8] assign _T_521 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@49778.6] assign _T_574 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@49844.8] assign _T_576 = _T_574 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49846.8] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49847.8] assign _T_582 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@49861.6] assign _T_627 = _T_268 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49907.8] assign _T_628 = _T_627 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49908.8] assign _T_643 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@49946.6] assign _T_645 = _T_643 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49948.6] assign _T_646 = _T_645 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49949.6] assign _T_647 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49954.6] assign _T_648 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@49955.6] assign _T_651 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@49958.6] assign _T_652 = _T_651 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49959.6] assign _T_660 = _T_651 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@49967.6] assign _T_666 = _T_647 | _T_648; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49978.6] assign _T_667 = _T_666 | _T_652; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49979.6] assign _T_668 = _T_667 | _T_660; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@49980.6] assign _T_670 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@49982.6] assign _T_672 = _T_668 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49985.8] assign _T_673 = _T_672 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49986.8] assign _T_674 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@49991.8] assign _T_676 = _T_674 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49993.8] assign _T_677 = _T_676 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49994.8] assign _T_678 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@49999.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50001.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50002.8] assign _T_682 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@50007.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50009.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50010.8] assign _T_686 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@50015.8] assign _T_688 = _T_686 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50017.8] assign _T_689 = _T_688 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50018.8] assign _T_690 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@50024.6] assign _T_701 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@50048.8] assign _T_703 = _T_701 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50050.8] assign _T_704 = _T_703 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50051.8] assign _T_705 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@50056.8] assign _T_707 = _T_705 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50058.8] assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50059.8] assign _T_718 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@50082.6] assign _T_738 = _T_686 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@50123.8] assign _T_740 = _T_738 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50125.8] assign _T_741 = _T_740 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50126.8] assign _T_747 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@50141.6] assign _T_764 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@50176.6] assign _T_782 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@50212.6] assign _T_811 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@50272.4] assign _T_816 = _T_30[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@50277.4] assign _T_817 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@50278.4] assign _T_818 = _T_817 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@50279.4] assign _T_822 = _T_820 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50283.4] assign _T_823 = _T_820 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50284.4] assign _T_836 = _T_823 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@50300.4] assign _T_837 = io_in_a_valid & _T_836; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@50301.4] assign _T_838 = io_in_a_bits_opcode == _T_831; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@50303.6] assign _T_840 = _T_838 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50305.6] assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50306.6] assign _T_842 = io_in_a_bits_param == _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@50311.6] assign _T_844 = _T_842 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50313.6] assign _T_845 = _T_844 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50314.6] assign _T_846 = io_in_a_bits_size == _T_833; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@50319.6] assign _T_848 = _T_846 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50321.6] assign _T_849 = _T_848 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50322.6] assign _T_850 = io_in_a_bits_source == _T_834; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@50327.6] assign _T_852 = _T_850 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50329.6] assign _T_853 = _T_852 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50330.6] assign _T_854 = io_in_a_bits_address == _T_835; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@50335.6] assign _T_856 = _T_854 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50337.6] assign _T_857 = _T_856 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50338.6] assign _T_859 = _T_811 & _T_823; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@50345.4] assign _T_860 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@50353.4] assign _T_862 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@50355.4] assign _T_863 = _T_862[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@50356.4] assign _T_864 = ~ _T_863; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@50357.4] assign _T_865 = _T_864[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@50358.4] assign _T_866 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@50359.4] assign _T_870 = _T_868 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50363.4] assign _T_871 = _T_868 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50364.4] assign _T_885 = _T_871 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@50381.4] assign _T_886 = io_in_d_valid & _T_885; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@50382.4] assign _T_887 = io_in_d_bits_opcode == _T_879; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@50384.6] assign _T_889 = _T_887 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50386.6] assign _T_890 = _T_889 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50387.6] assign _T_891 = io_in_d_bits_param == _T_880; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@50392.6] assign _T_893 = _T_891 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50394.6] assign _T_894 = _T_893 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50395.6] assign _T_895 = io_in_d_bits_size == _T_881; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@50400.6] assign _T_897 = _T_895 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50402.6] assign _T_898 = _T_897 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50403.6] assign _T_899 = io_in_d_bits_source == _T_882; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@50408.6] assign _T_901 = _T_899 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50410.6] assign _T_902 = _T_901 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50411.6] assign _T_903 = io_in_d_bits_sink == _T_883; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@50416.6] assign _T_905 = _T_903 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50418.6] assign _T_906 = _T_905 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50419.6] assign _T_907 = io_in_d_bits_denied == _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@50424.6] assign _T_909 = _T_907 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50426.6] assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50427.6] assign _T_912 = _T_860 & _T_871; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@50434.4] assign _T_925 = _T_923 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50455.4] assign _T_926 = _T_923 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50456.4] assign _T_944 = _T_942 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@50477.4] assign _T_945 = _T_942 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@50478.4] assign _T_955 = _T_811 & _T_926; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@50493.4] assign _T_957 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@50496.6] assign _T_958 = _T_913 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@50498.6] assign _T_959 = _T_958[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@50499.6] assign _T_960 = _T_959 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@50500.6] assign _T_962 = _T_960 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50502.6] assign _T_963 = _T_962 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50503.6] assign _GEN_15 = _T_955 ? _T_957 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@50495.4] assign _T_967 = _T_860 & _T_945; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@50514.4] assign _T_969 = _T_670 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@50516.4] assign _T_970 = _T_967 & _T_969; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@50517.4] assign _T_971 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@50519.6] assign _T_953 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@50489.4 :freechips.rocketchip.system.TinyConfig.fir@50491.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@50497.6] assign _T_972 = _T_953 | _T_913; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@50521.6] assign _T_973 = _T_972 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@50522.6] assign _T_974 = _T_973[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@50523.6] assign _T_976 = _T_974 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50525.6] assign _T_977 = _T_976 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50526.6] assign _GEN_16 = _T_970 ? _T_971 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@50518.4] assign _T_964 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@50509.4 :freechips.rocketchip.system.TinyConfig.fir@50511.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@50520.6] assign _T_978 = _T_953 != _T_964; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@50532.4] assign _T_979 = _T_953 != 18'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@50533.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@50534.4] assign _T_981 = _T_978 | _T_980; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@50535.4] assign _T_983 = _T_981 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50537.4] assign _T_984 = _T_983 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50538.4] assign _T_985 = _T_913 | _T_953; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@50543.4] assign _T_986 = ~ _T_964; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@50544.4] assign _T_987 = _T_985 & _T_986; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@50545.4] assign _T_989 = _T_913 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@50550.4] assign _T_990 = _T_989 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@50551.4] assign _T_991 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@50552.4] assign _T_992 = _T_990 | _T_991; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@50553.4] assign _T_993 = _T_988 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@50554.4] assign _T_994 = _T_992 | _T_993; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@50555.4] assign _T_996 = _T_994 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50557.4] assign _T_997 = _T_996 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50558.4] assign _T_999 = _T_988 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@50564.4] assign _T_1002 = _T_811 | _T_860; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@50568.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49255.10] assign _GEN_35 = io_in_a_valid & _T_186; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@49357.10] assign _GEN_53 = io_in_a_valid & _T_258; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49475.10] assign _GEN_65 = io_in_a_valid & _T_326; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49571.10] assign _GEN_75 = io_in_a_valid & _T_392; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@49659.10] assign _GEN_85 = io_in_a_valid & _T_460; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49744.10] assign _GEN_95 = io_in_a_valid & _T_521; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@49827.10] assign _GEN_105 = io_in_a_valid & _T_582; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49910.10] assign _GEN_115 = io_in_d_valid & _T_670; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49988.10] assign _GEN_125 = io_in_d_valid & _T_690; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@50030.10] assign _GEN_137 = io_in_d_valid & _T_718; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@50088.10] assign _GEN_149 = io_in_d_valid & _T_747; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@50147.10] assign _GEN_155 = io_in_d_valid & _T_764; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@50182.10] assign _GEN_161 = io_in_d_valid & _T_782; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@50218.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_820 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_831 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_832 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_833 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_834 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_835 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_868 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_879 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_880 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_881 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_882 = _RAND_10[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_883 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_884 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_913 = _RAND_13[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_923 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_942 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_988 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_820 <= 10'h0; end else begin if (_T_811) begin if (_T_823) begin if (_T_818) begin _T_820 <= _T_816; end else begin _T_820 <= 10'h0; end end else begin _T_820 <= _T_822; end end end if (_T_859) begin _T_831 <= io_in_a_bits_opcode; end if (_T_859) begin _T_832 <= io_in_a_bits_param; end if (_T_859) begin _T_833 <= io_in_a_bits_size; end if (_T_859) begin _T_834 <= io_in_a_bits_source; end if (_T_859) begin _T_835 <= io_in_a_bits_address; end if (reset) begin _T_868 <= 10'h0; end else begin if (_T_860) begin if (_T_871) begin if (_T_866) begin _T_868 <= _T_865; end else begin _T_868 <= 10'h0; end end else begin _T_868 <= _T_870; end end end if (_T_912) begin _T_879 <= io_in_d_bits_opcode; end if (_T_912) begin _T_880 <= io_in_d_bits_param; end if (_T_912) begin _T_881 <= io_in_d_bits_size; end if (_T_912) begin _T_882 <= io_in_d_bits_source; end if (_T_912) begin _T_883 <= io_in_d_bits_sink; end if (_T_912) begin _T_884 <= io_in_d_bits_denied; end if (reset) begin _T_913 <= 18'h0; end else begin _T_913 <= _T_987; end if (reset) begin _T_923 <= 10'h0; end else begin if (_T_811) begin if (_T_926) begin if (_T_818) begin _T_923 <= _T_816; end else begin _T_923 <= 10'h0; end end else begin _T_923 <= _T_925; end end end if (reset) begin _T_942 <= 10'h0; end else begin if (_T_860) begin if (_T_945) begin if (_T_866) begin _T_942 <= _T_865; end else begin _T_942 <= 10'h0; end end else begin _T_942 <= _T_944; end end end if (reset) begin _T_988 <= 32'h0; end else begin if (_T_1002) begin _T_988 <= 32'h0; end else begin _T_988 <= _T_999; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49255.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@49256.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@49262.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_159) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@49263.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49269.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_165) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@49270.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49277.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_169) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@49278.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49284.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_172) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@49285.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49292.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_176) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@49293.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49301.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_181) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@49302.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49309.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_185) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@49310.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@49357.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@49358.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@49364.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_159) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@49365.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@49371.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_165) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@49372.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@49379.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_169) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@49380.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@49386.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_172) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@49387.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_176) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@49394.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_176) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@49395.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_248) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_248) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@49403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_181) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@49411.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_181) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@49412.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@49419.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_185) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@49420.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_307) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49475.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_307) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@49476.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@49482.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@49483.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@49489.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_172) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@49490.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49497.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_317) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@49498.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49505.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_321) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@49506.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@49513.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_185) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@49514.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49571.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_377) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@49572.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@49578.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@49579.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@49585.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_172) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@49586.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@49593.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_317) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@49594.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@49601.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_321) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@49602.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_377) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@49659.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_377) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@49660.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@49666.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@49667.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@49673.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_172) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@49674.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_317) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@49681.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_317) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@49682.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_459) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49691.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_459) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@49692.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_506) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@49745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@49751.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_165) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@49752.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@49758.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_172) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@49759.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_516) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49766.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_516) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@49767.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@49774.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_321) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@49775.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_506) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@49827.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_506) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@49828.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@49834.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_165) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@49835.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@49841.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_172) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@49842.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49849.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_577) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@49850.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@49857.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_321) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@49858.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_628) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49910.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_628) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@49911.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@49917.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_165) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@49918.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_172) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@49924.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_172) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@49925.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_321) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@49932.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_321) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@49933.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_185) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@49940.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_185) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@49941.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_646) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49951.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_646) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@49952.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49988.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_673) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@49989.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49996.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_677) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@49997.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50004.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_681) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@50005.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50012.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_685) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@50013.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_689) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50020.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_689) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@50021.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@50030.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_673) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@50031.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@50037.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_159) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@50038.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@50045.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_677) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@50046.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50053.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_704) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@50054.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50061.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_708) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@50062.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@50069.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_685) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@50070.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@50088.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_673) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@50089.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_159) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@50095.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_159) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@50096.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_677) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@50103.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_677) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@50104.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_704) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@50111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_704) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@50112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_708) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@50119.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_708) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@50120.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50128.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_741) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@50129.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@50147.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_673) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@50148.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@50155.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_681) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@50156.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@50163.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_685) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@50164.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@50182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_673) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@50183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@50190.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_681) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@50191.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_741) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@50199.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_741) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@50200.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_673) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@50218.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_673) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@50219.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@50226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_681) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@50227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@50234.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_685) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@50235.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_841) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50308.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_841) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@50309.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_845) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50316.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_845) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@50317.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_849) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50324.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_849) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@50325.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_853) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50332.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_853) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@50333.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_837 & _T_857) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50340.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_837 & _T_857) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@50341.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_890) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50389.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_890) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@50390.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_894) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50397.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_894) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@50398.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_898) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50405.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_898) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@50406.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_902) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50413.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_902) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@50414.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_906) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50421.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_906) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@50422.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_886 & _T_910) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50429.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_886 & _T_910) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@50430.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_955 & _T_963) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50505.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_955 & _T_963) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@50506.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_970 & _T_977) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50528.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_970 & _T_977) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@50529.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_984) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50540.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_984) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@50541.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_997) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50560.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_997) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@50561.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLBuffer_9( // @[:freechips.rocketchip.system.TinyConfig.fir@50573.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@50574.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@50575.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@50576.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] TLMonitor_26 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@50583.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@50635.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@50634.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@50585.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@50586.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@50631.4] endmodule module TLMonitor_27( // @[:freechips.rocketchip.system.TinyConfig.fir@50689.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@50690.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@50691.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [16:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@50692.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@51875.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@50707.6] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@50708.6] wire [1:0] _T_9; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@50711.6] wire _T_10; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@50712.6] wire _T_18; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@50720.6] wire _T_24; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50731.6] wire _T_25; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50732.6] wire _T_26; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50733.6] wire [12:0] _T_28; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@50735.6] wire [5:0] _T_29; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@50736.6] wire [5:0] _T_30; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@50737.6] wire [16:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@50738.6] wire [16:0] _T_31; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@50738.6] wire _T_32; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@50739.6] wire _T_34; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@50741.6] wire [1:0] _T_35; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@50742.6] wire [1:0] _T_37; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@50744.6] wire _T_38; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@50745.6] wire _T_39; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@50746.6] wire _T_40; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@50747.6] wire _T_41; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@50748.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50750.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50751.6] wire _T_46; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50753.6] wire _T_47; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50754.6] wire _T_48; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@50755.6] wire _T_49; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@50756.6] wire _T_50; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@50757.6] wire _T_51; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50758.6] wire _T_52; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50759.6] wire _T_53; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50760.6] wire _T_54; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50761.6] wire _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50762.6] wire _T_56; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50763.6] wire _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50764.6] wire _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50765.6] wire _T_59; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50766.6] wire _T_60; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50767.6] wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50768.6] wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50769.6] wire [3:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@50772.6] wire _T_118; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@50829.6] wire [16:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@50832.8] wire [17:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@50833.8] wire [17:0] _T_122; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@50834.8] wire [17:0] _T_123; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@50835.8] wire _T_124; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@50836.8] wire _T_129; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50841.8] wire _T_134; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50854.8] wire _T_135; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50855.8] wire _T_138; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50862.8] wire _T_139; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50863.8] wire _T_141; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50869.8] wire _T_142; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50870.8] wire _T_143; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@50875.8] wire _T_145; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50877.8] wire _T_146; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50878.8] wire [3:0] _T_147; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@50883.8] wire _T_148; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@50884.8] wire _T_150; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50886.8] wire _T_151; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50887.8] wire _T_152; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@50892.8] wire _T_154; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50894.8] wire _T_155; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50895.8] wire _T_156; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@50901.6] wire _T_185; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@50955.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50957.8] wire _T_188; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50958.8] wire _T_198; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@50981.6] wire _T_200; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@50984.8] wire _T_208; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@50992.8] wire _T_211; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50995.8] wire _T_212; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50996.8] wire _T_219; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@51015.8] wire _T_221; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51017.8] wire _T_222; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51018.8] wire _T_223; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@51023.8] wire _T_225; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51025.8] wire _T_226; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51026.8] wire _T_231; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@51040.6] wire _T_257; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@51088.6] wire [3:0] _T_279; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@51127.8] wire [3:0] _T_280; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@51128.8] wire _T_281; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@51129.8] wire _T_283; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51131.8] wire _T_284; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51132.8] wire _T_285; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@51138.6] wire _T_303; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@51169.8] wire _T_305; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51171.8] wire _T_306; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51172.8] wire _T_311; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@51186.6] wire _T_329; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@51217.8] wire _T_331; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51219.8] wire _T_332; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51220.8] wire _T_337; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@51234.6] wire _T_367; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@51292.6] wire _T_368; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@51293.6] wire [1:0] _T_371; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@51296.6] wire _T_372; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@51297.6] wire _T_380; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@51305.6] wire _T_386; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51316.6] wire _T_387; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51317.6] wire _T_388; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51318.6] wire _T_392; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@51323.8] wire _T_393; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@51324.8] wire _T_531; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@51610.4] reg [3:0] _T_540; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@51619.4] reg [31:0] _RAND_0; wire [3:0] _T_542; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51621.4] wire _T_543; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51622.4] reg [2:0] _T_551; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@51633.4] reg [31:0] _RAND_1; reg [2:0] _T_552; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@51634.4] reg [31:0] _RAND_2; reg [2:0] _T_553; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@51635.4] reg [31:0] _RAND_3; reg [4:0] _T_554; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@51636.4] reg [31:0] _RAND_4; reg [16:0] _T_555; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@51637.4] reg [31:0] _RAND_5; wire _T_556; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@51638.4] wire _T_557; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@51639.4] wire _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@51641.6] wire _T_560; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51643.6] wire _T_561; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51644.6] wire _T_562; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@51649.6] wire _T_564; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51651.6] wire _T_565; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51652.6] wire _T_566; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@51657.6] wire _T_568; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51659.6] wire _T_569; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51660.6] wire _T_570; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@51665.6] wire _T_572; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51667.6] wire _T_573; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51668.6] wire _T_574; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@51673.6] wire _T_576; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51675.6] wire _T_577; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51676.6] wire _T_579; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@51683.4] wire _T_580; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@51691.4] wire [12:0] _T_582; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@51693.4] wire [5:0] _T_583; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@51694.4] wire [5:0] _T_584; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@51695.4] wire [3:0] _T_585; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@51696.4] reg [3:0] _T_588; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@51699.4] reg [31:0] _RAND_6; wire [3:0] _T_590; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51701.4] wire _T_591; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51702.4] reg [2:0] _T_601; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@51715.4] reg [31:0] _RAND_7; reg [4:0] _T_602; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@51716.4] reg [31:0] _RAND_8; wire _T_605; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@51719.4] wire _T_606; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@51720.4] wire _T_615; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@51738.6] wire _T_617; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51740.6] wire _T_618; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51741.6] wire _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@51746.6] wire _T_621; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51748.6] wire _T_622; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51749.6] wire _T_632; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@51772.4] reg [17:0] _T_633; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@51781.4] reg [31:0] _RAND_9; reg [3:0] _T_643; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@51791.4] reg [31:0] _RAND_10; wire [3:0] _T_645; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51793.4] wire _T_646; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51794.4] reg [3:0] _T_662; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@51813.4] reg [31:0] _RAND_11; wire [3:0] _T_664; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51815.4] wire _T_665; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51816.4] wire _T_675; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@51831.4] wire [31:0] _T_677; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@51834.6] wire [17:0] _T_678; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@51836.6] wire _T_679; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@51837.6] wire _T_680; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@51838.6] wire _T_682; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51840.6] wire _T_683; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51841.6] wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@51833.4] wire _T_687; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@51852.4] wire [31:0] _T_691; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@51857.6] wire [17:0] _T_673; // @[:freechips.rocketchip.system.TinyConfig.fir@51827.4 :freechips.rocketchip.system.TinyConfig.fir@51829.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@51835.6] wire [17:0] _T_692; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@51859.6] wire [17:0] _T_693; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@51860.6] wire _T_694; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@51861.6] wire _T_696; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51863.6] wire _T_697; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51864.6] wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@51856.4] wire [17:0] _T_698; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@51870.4] wire [17:0] _T_684; // @[:freechips.rocketchip.system.TinyConfig.fir@51847.4 :freechips.rocketchip.system.TinyConfig.fir@51849.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@51858.6] wire [17:0] _T_699; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@51871.4] wire [17:0] _T_700; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@51872.4] reg [31:0] _T_701; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@51874.4] reg [31:0] _RAND_12; wire _T_702; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@51877.4] wire _T_703; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@51878.4] wire _T_704; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@51879.4] wire _T_705; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@51880.4] wire _T_706; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@51881.4] wire _T_707; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@51882.4] wire _T_709; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51884.4] wire _T_710; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51885.4] wire [31:0] _T_712; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@51891.4] wire _T_715; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@51895.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50843.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@50915.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50998.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@51054.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@51102.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@51152.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@51200.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@51248.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@51875.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@50707.6] assign _T_6 = io_in_a_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@50708.6] assign _T_9 = io_in_a_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@50711.6] assign _T_10 = _T_9 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@50712.6] assign _T_18 = _T_9 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@50720.6] assign _T_24 = _T_5 | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50731.6] assign _T_25 = _T_24 | _T_10; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50732.6] assign _T_26 = _T_25 | _T_18; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@50733.6] assign _T_28 = 13'h3f << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@50735.6] assign _T_29 = _T_28[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@50736.6] assign _T_30 = ~ _T_29; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@50737.6] assign _GEN_18 = {{11'd0}, _T_30}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@50738.6] assign _T_31 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@50738.6] assign _T_32 = _T_31 == 17'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@50739.6] assign _T_34 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@50741.6] assign _T_35 = 2'h1 << _T_34; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@50742.6] assign _T_37 = _T_35 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@50744.6] assign _T_38 = io_in_a_bits_size >= 3'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@50745.6] assign _T_39 = _T_37[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@50746.6] assign _T_40 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@50747.6] assign _T_41 = _T_40 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@50748.6] assign _T_43 = _T_39 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50750.6] assign _T_44 = _T_38 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50751.6] assign _T_46 = _T_39 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50753.6] assign _T_47 = _T_38 | _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50754.6] assign _T_48 = _T_37[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@50755.6] assign _T_49 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@50756.6] assign _T_50 = _T_49 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@50757.6] assign _T_51 = _T_41 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50758.6] assign _T_52 = _T_48 & _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50759.6] assign _T_53 = _T_44 | _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50760.6] assign _T_54 = _T_41 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50761.6] assign _T_55 = _T_48 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50762.6] assign _T_56 = _T_44 | _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50763.6] assign _T_57 = _T_40 & _T_50; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50764.6] assign _T_58 = _T_48 & _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50765.6] assign _T_59 = _T_47 | _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50766.6] assign _T_60 = _T_40 & _T_49; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@50767.6] assign _T_61 = _T_48 & _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@50768.6] assign _T_62 = _T_47 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@50769.6] assign _T_65 = {_T_62,_T_59,_T_56,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@50772.6] assign _T_118 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@50829.6] assign _T_120 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@50832.8] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@50833.8] assign _T_122 = $signed(_T_121) & $signed(-18'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@50834.8] assign _T_123 = $signed(_T_122); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@50835.8] assign _T_124 = $signed(_T_123) == $signed(18'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@50836.8] assign _T_129 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50841.8] assign _T_134 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50854.8] assign _T_135 = _T_134 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50855.8] assign _T_138 = _T_38 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50862.8] assign _T_139 = _T_138 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50863.8] assign _T_141 = _T_32 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50869.8] assign _T_142 = _T_141 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50870.8] assign _T_143 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@50875.8] assign _T_145 = _T_143 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50877.8] assign _T_146 = _T_145 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50878.8] assign _T_147 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@50883.8] assign _T_148 = _T_147 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@50884.8] assign _T_150 = _T_148 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50886.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50887.8] assign _T_152 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@50892.8] assign _T_154 = _T_152 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50894.8] assign _T_155 = _T_154 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50895.8] assign _T_156 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@50901.6] assign _T_185 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@50955.8] assign _T_187 = _T_185 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50957.8] assign _T_188 = _T_187 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50958.8] assign _T_198 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@50981.6] assign _T_200 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@50984.8] assign _T_208 = _T_200 & _T_124; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@50992.8] assign _T_211 = _T_208 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50995.8] assign _T_212 = _T_211 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50996.8] assign _T_219 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@51015.8] assign _T_221 = _T_219 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51017.8] assign _T_222 = _T_221 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51018.8] assign _T_223 = io_in_a_bits_mask == _T_65; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@51023.8] assign _T_225 = _T_223 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51025.8] assign _T_226 = _T_225 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51026.8] assign _T_231 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@51040.6] assign _T_257 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@51088.6] assign _T_279 = ~ _T_65; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@51127.8] assign _T_280 = io_in_a_bits_mask & _T_279; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@51128.8] assign _T_281 = _T_280 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@51129.8] assign _T_283 = _T_281 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51131.8] assign _T_284 = _T_283 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51132.8] assign _T_285 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@51138.6] assign _T_303 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@51169.8] assign _T_305 = _T_303 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51171.8] assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51172.8] assign _T_311 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@51186.6] assign _T_329 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@51217.8] assign _T_331 = _T_329 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51219.8] assign _T_332 = _T_331 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51220.8] assign _T_337 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@51234.6] assign _T_367 = io_in_d_bits_source == 5'h11; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@51292.6] assign _T_368 = io_in_d_bits_source == 5'h10; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@51293.6] assign _T_371 = io_in_d_bits_source[4:3]; // @[Parameters.scala 54:10:freechips.rocketchip.system.TinyConfig.fir@51296.6] assign _T_372 = _T_371 == 2'h0; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@51297.6] assign _T_380 = _T_371 == 2'h1; // @[Parameters.scala 54:32:freechips.rocketchip.system.TinyConfig.fir@51305.6] assign _T_386 = _T_367 | _T_368; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51316.6] assign _T_387 = _T_386 | _T_372; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51317.6] assign _T_388 = _T_387 | _T_380; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@51318.6] assign _T_392 = _T_388 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@51323.8] assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@51324.8] assign _T_531 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@51610.4] assign _T_542 = _T_540 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51621.4] assign _T_543 = _T_540 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51622.4] assign _T_556 = _T_543 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@51638.4] assign _T_557 = io_in_a_valid & _T_556; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@51639.4] assign _T_558 = io_in_a_bits_opcode == _T_551; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@51641.6] assign _T_560 = _T_558 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51643.6] assign _T_561 = _T_560 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51644.6] assign _T_562 = io_in_a_bits_param == _T_552; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@51649.6] assign _T_564 = _T_562 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51651.6] assign _T_565 = _T_564 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51652.6] assign _T_566 = io_in_a_bits_size == _T_553; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@51657.6] assign _T_568 = _T_566 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51659.6] assign _T_569 = _T_568 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51660.6] assign _T_570 = io_in_a_bits_source == _T_554; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@51665.6] assign _T_572 = _T_570 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51667.6] assign _T_573 = _T_572 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51668.6] assign _T_574 = io_in_a_bits_address == _T_555; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@51673.6] assign _T_576 = _T_574 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51675.6] assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51676.6] assign _T_579 = _T_531 & _T_543; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@51683.4] assign _T_580 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@51691.4] assign _T_582 = 13'h3f << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@51693.4] assign _T_583 = _T_582[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@51694.4] assign _T_584 = ~ _T_583; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@51695.4] assign _T_585 = _T_584[5:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@51696.4] assign _T_590 = _T_588 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51701.4] assign _T_591 = _T_588 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51702.4] assign _T_605 = _T_591 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@51719.4] assign _T_606 = io_in_d_valid & _T_605; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@51720.4] assign _T_615 = io_in_d_bits_size == _T_601; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@51738.6] assign _T_617 = _T_615 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51740.6] assign _T_618 = _T_617 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51741.6] assign _T_619 = io_in_d_bits_source == _T_602; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@51746.6] assign _T_621 = _T_619 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51748.6] assign _T_622 = _T_621 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51749.6] assign _T_632 = _T_580 & _T_591; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@51772.4] assign _T_645 = _T_643 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51793.4] assign _T_646 = _T_643 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51794.4] assign _T_664 = _T_662 - 4'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@51815.4] assign _T_665 = _T_662 == 4'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@51816.4] assign _T_675 = _T_531 & _T_646; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@51831.4] assign _T_677 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@51834.6] assign _T_678 = _T_633 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@51836.6] assign _T_679 = _T_678[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@51837.6] assign _T_680 = _T_679 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@51838.6] assign _T_682 = _T_680 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51840.6] assign _T_683 = _T_682 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51841.6] assign _GEN_15 = _T_675 ? _T_677 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@51833.4] assign _T_687 = _T_580 & _T_665; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@51852.4] assign _T_691 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@51857.6] assign _T_673 = _GEN_15[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@51827.4 :freechips.rocketchip.system.TinyConfig.fir@51829.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@51835.6] assign _T_692 = _T_673 | _T_633; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@51859.6] assign _T_693 = _T_692 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@51860.6] assign _T_694 = _T_693[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@51861.6] assign _T_696 = _T_694 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51863.6] assign _T_697 = _T_696 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51864.6] assign _GEN_16 = _T_687 ? _T_691 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@51856.4] assign _T_698 = _T_633 | _T_673; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@51870.4] assign _T_684 = _GEN_16[17:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@51847.4 :freechips.rocketchip.system.TinyConfig.fir@51849.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@51858.6] assign _T_699 = ~ _T_684; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@51871.4] assign _T_700 = _T_698 & _T_699; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@51872.4] assign _T_702 = _T_633 != 18'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@51877.4] assign _T_703 = _T_702 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@51878.4] assign _T_704 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@51879.4] assign _T_705 = _T_703 | _T_704; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@51880.4] assign _T_706 = _T_701 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@51881.4] assign _T_707 = _T_705 | _T_706; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@51882.4] assign _T_709 = _T_707 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51884.4] assign _T_710 = _T_709 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51885.4] assign _T_712 = _T_701 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@51891.4] assign _T_715 = _T_531 | _T_580; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@51895.4] assign _GEN_19 = io_in_a_valid & _T_118; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50843.10] assign _GEN_35 = io_in_a_valid & _T_156; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@50915.10] assign _GEN_53 = io_in_a_valid & _T_198; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50998.10] assign _GEN_65 = io_in_a_valid & _T_231; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@51054.10] assign _GEN_75 = io_in_a_valid & _T_257; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@51102.10] assign _GEN_85 = io_in_a_valid & _T_285; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@51152.10] assign _GEN_95 = io_in_a_valid & _T_311; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@51200.10] assign _GEN_105 = io_in_a_valid & _T_337; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@51248.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_540 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_551 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_552 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_553 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_554 = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_555 = _RAND_5[16:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_588 = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_601 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_602 = _RAND_8[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_633 = _RAND_9[17:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_643 = _RAND_10[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_662 = _RAND_11[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_701 = _RAND_12[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_540 <= 4'h0; end else begin if (_T_531) begin if (_T_543) begin _T_540 <= 4'h0; end else begin _T_540 <= _T_542; end end end if (_T_579) begin _T_551 <= io_in_a_bits_opcode; end if (_T_579) begin _T_552 <= io_in_a_bits_param; end if (_T_579) begin _T_553 <= io_in_a_bits_size; end if (_T_579) begin _T_554 <= io_in_a_bits_source; end if (_T_579) begin _T_555 <= io_in_a_bits_address; end if (reset) begin _T_588 <= 4'h0; end else begin if (_T_580) begin if (_T_591) begin _T_588 <= _T_585; end else begin _T_588 <= _T_590; end end end if (_T_632) begin _T_601 <= io_in_d_bits_size; end if (_T_632) begin _T_602 <= io_in_d_bits_source; end if (reset) begin _T_633 <= 18'h0; end else begin _T_633 <= _T_700; end if (reset) begin _T_643 <= 4'h0; end else begin if (_T_531) begin if (_T_646) begin _T_643 <= 4'h0; end else begin _T_643 <= _T_645; end end end if (reset) begin _T_662 <= 4'h0; end else begin if (_T_580) begin if (_T_665) begin _T_662 <= _T_585; end else begin _T_662 <= _T_664; end end end if (reset) begin _T_701 <= 32'h0; end else begin if (_T_715) begin _T_701 <= 32'h0; end else begin _T_701 <= _T_712; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50843.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@50844.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:74:64)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@50850.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_129) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@50851.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50857.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_135) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@50858.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50865.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_139) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@50866.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50872.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_142) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@50873.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:74:64)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50880.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_146) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@50881.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50889.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_151) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@50890.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_155) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@50898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@50915.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@50916.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:74:64)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@50922.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_129) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@50923.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@50929.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_135) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@50930.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_139) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@50937.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_139) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@50938.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@50944.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_142) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@50945.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_146) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:74:64)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@50952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_146) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@50953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_188) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:74:64)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50960.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_188) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@50961.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@50969.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_151) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@50970.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@50977.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_155) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@50978.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_212) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50998.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_212) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@50999.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@51005.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_135) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@51006.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@51012.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_142) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@51013.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51020.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_222) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@51021.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51028.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_226) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@51029.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@51036.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_155) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@51037.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@51054.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_129) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@51055.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@51061.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_135) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@51062.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@51068.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_142) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@51069.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@51076.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_222) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@51077.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@51084.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_226) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@51085.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@51102.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_129) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@51103.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@51109.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_135) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@51110.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@51116.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_142) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@51117.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_222) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@51124.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_222) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@51125.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_284) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51134.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_284) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@51135.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@51152.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_129) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@51153.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@51159.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_135) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@51160.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@51166.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_142) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@51167.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_306) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:74:64)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51174.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_306) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@51175.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@51182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_226) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@51183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@51200.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_129) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@51201.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@51207.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_135) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@51208.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@51214.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_142) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@51215.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_332) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:74:64)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51222.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_332) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@51223.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@51230.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_226) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@51231.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_129) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@51248.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_129) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@51249.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_135) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@51255.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_135) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@51256.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_142) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@51262.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_142) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@51263.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_226) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@51270.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_226) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@51271.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_155) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@51278.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_155) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@51279.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_393) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@51520.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_393) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@51521.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_557 & _T_561) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51646.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_557 & _T_561) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@51647.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_557 & _T_565) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51654.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_557 & _T_565) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@51655.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_557 & _T_569) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51662.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_557 & _T_569) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@51663.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_557 & _T_573) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51670.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_557 & _T_573) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@51671.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_557 & _T_577) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51678.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_557 & _T_577) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@51679.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_606 & _T_618) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51743.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_606 & _T_618) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@51744.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_606 & _T_622) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51751.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_606 & _T_622) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@51752.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_675 & _T_683) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51843.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_675 & _T_683) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@51844.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_687 & _T_697) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:74:64)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51866.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_687 & _T_697) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@51867.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_710) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BootROM.scala:74:64)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51887.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_710) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@51888.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Repeater_4( // @[:freechips.rocketchip.system.TinyConfig.fir@51900.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@51901.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@51902.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output io_full, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [16:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [16:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@51903.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@51908.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_2; reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_3; reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_4; reg [16:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_5; reg [3:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_6; reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@51909.4] reg [31:0] _RAND_7; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@51912.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@51918.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@51919.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@51924.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@51925.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@51926.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@51912.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@51918.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@51919.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@51924.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@51925.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@51926.4] assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.TinyConfig.fir@51917.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@51914.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@51911.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@51916.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[16:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; saved_corrupt = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end if (_T_5) begin saved_corrupt <= io_enq_bits_corrupt; end end endmodule module TLFragmenter_3( // @[:freechips.rocketchip.system.TinyConfig.fir@51931.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@51932.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@51933.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [16:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [9:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [16:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [9:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@51934.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [16:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [16:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [3:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [16:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire [3:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] reg [3:0] _T_14; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.TinyConfig.fir@51994.4] reg [31:0] _RAND_0; reg [2:0] _T_15; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.TinyConfig.fir@51995.4] reg [31:0] _RAND_1; reg _T_16; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.TinyConfig.fir@51996.4] reg [31:0] _RAND_2; wire [3:0] _T_17; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@51997.4] wire _T_18; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@51998.4] wire [4:0] _T_24; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52004.4] wire [1:0] _T_25; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52005.4] wire [1:0] _T_26; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52006.4] wire [5:0] _T_41; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@52025.4] wire [5:0] _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@52026.4] wire [5:0] _T_42; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@52026.4] wire [6:0] _T_43; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@52027.4] wire [6:0] _T_44; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@52028.4] wire [6:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52029.4] wire [6:0] _T_46; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@52030.4] wire [6:0] _T_47; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@52031.4] wire [2:0] _T_48; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@52032.4] wire [3:0] _T_49; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@52033.4] wire _T_50; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@52034.4] wire [3:0] _GEN_8; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52035.4] wire [3:0] _T_51; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52035.4] wire [1:0] _T_52; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@52036.4] wire [1:0] _T_53; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@52037.4] wire _T_54; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@52038.4] wire [1:0] _T_55; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52039.4] wire _T_56; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@52040.4] wire [2:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52042.4] wire _T_59; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@52043.4] wire [3:0] _T_61; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@52046.6] wire _T_63; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@52051.8] wire _T_91; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@52094.4] wire [2:0] _T_92; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@52095.4] wire [12:0] _T_94; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52097.4] wire [5:0] _T_95; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52098.4] wire [5:0] _T_96; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52099.4] wire [8:0] _T_98; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52101.4] wire [1:0] _T_99; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52102.4] wire [1:0] _T_100; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52103.4] reg [3:0] _T_104; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.TinyConfig.fir@52107.4] reg [31:0] _RAND_3; wire _T_105; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@52108.4] wire [3:0] _T_106; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@52109.4] wire [3:0] _T_108; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@52111.4] wire [3:0] _T_109; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@52112.4] wire [3:0] _T_110; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@52113.4] wire [3:0] _T_113; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@52116.4] reg _T_120; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@52123.4] reg [31:0] _RAND_4; wire _GEN_5; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@52124.4] wire _T_122; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@52128.4] wire _T_13_a_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@51990.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@52137.4] wire _T_123; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@52129.4] wire [5:0] _T_127; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@52138.4] wire [5:0] _T_128; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@52139.4] wire [5:0] _T_129; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@52140.4] wire [5:0] _GEN_9; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@52141.4] wire [5:0] _T_130; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@52141.4] wire [5:0] _T_131; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@52142.4] wire [5:0] _T_132; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@52143.4] wire [16:0] _GEN_10; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@52144.4] wire [5:0] _T_134; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52146.4] wire _T_136; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@52150.4] wire _T_143; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@52162.4] wire _T_144; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@52163.4] wire _T_146; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52165.4] wire _T_147; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52166.4] TLMonitor_27 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@51941.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); Repeater_4 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@52069.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_full(Repeater_io_full), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask), .io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt) ); assign _T_17 = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@51997.4] assign _T_18 = _T_14 == 4'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@51998.4] assign _T_24 = 5'h3 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52004.4] assign _T_25 = _T_24[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52005.4] assign _T_26 = ~ _T_25; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52006.4] assign _T_41 = {_T_17, 2'h0}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@52025.4] assign _GEN_7 = {{4'd0}, _T_26}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@52026.4] assign _T_42 = _T_41 | _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@52026.4] assign _T_43 = {_T_42, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@52027.4] assign _T_44 = _T_43 | 7'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@52028.4] assign _T_45 = {1'h0,_T_42}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52029.4] assign _T_46 = ~ _T_45; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@52030.4] assign _T_47 = _T_44 & _T_46; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@52031.4] assign _T_48 = _T_47[6:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@52032.4] assign _T_49 = _T_47[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@52033.4] assign _T_50 = _T_48 != 3'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@52034.4] assign _GEN_8 = {{1'd0}, _T_48}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52035.4] assign _T_51 = _GEN_8 | _T_49; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52035.4] assign _T_52 = _T_51[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@52036.4] assign _T_53 = _T_51[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@52037.4] assign _T_54 = _T_52 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@52038.4] assign _T_55 = _T_52 | _T_53; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@52039.4] assign _T_56 = _T_55[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@52040.4] assign _T_58 = {_T_50,_T_54,_T_56}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52042.4] assign _T_59 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@52043.4] assign _T_61 = _T_14 - 4'h1; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@52046.6] assign _T_63 = auto_out_d_bits_source[4]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@52051.8] assign _T_91 = Repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@52094.4] assign _T_92 = _T_91 ? 3'h2 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@52095.4] assign _T_94 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52097.4] assign _T_95 = _T_94[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52098.4] assign _T_96 = ~ _T_95; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52099.4] assign _T_98 = 9'h3 << _T_92; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52101.4] assign _T_99 = _T_98[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52102.4] assign _T_100 = ~ _T_99; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52103.4] assign _T_105 = _T_104 == 4'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@52108.4] assign _T_106 = _T_96[5:2]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@52109.4] assign _T_108 = _T_104 - 4'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@52111.4] assign _T_109 = _T_105 ? _T_106 : _T_108; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@52112.4] assign _T_110 = ~ _T_109; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@52113.4] assign _T_113 = ~ _T_110; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@52116.4] assign _GEN_5 = _T_105 ? _T_16 : _T_120; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@52124.4] assign _T_122 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@52128.4] assign _T_13_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@51990.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@52137.4] assign _T_123 = auto_out_a_ready & _T_13_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@52129.4] assign _T_127 = {_T_109, 2'h0}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@52138.4] assign _T_128 = ~ _T_96; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@52139.4] assign _T_129 = _T_127 | _T_128; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@52140.4] assign _GEN_9 = {{4'd0}, _T_100}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@52141.4] assign _T_130 = _T_129 | _GEN_9; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@52141.4] assign _T_131 = _T_130 | 6'h3; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@52142.4] assign _T_132 = ~ _T_131; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@52143.4] assign _GEN_10 = {{11'd0}, _T_132}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@52144.4] assign _T_134 = {Repeater_io_deq_bits_source,_T_122}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52146.4] assign _T_136 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@52150.4] assign _T_143 = Repeater_io_deq_bits_mask == 4'hf; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@52162.4] assign _T_144 = _T_136 | _T_143; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@52163.4] assign _T_146 = _T_144 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52165.4] assign _T_147 = _T_146 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52166.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@51993.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@51993.4] assign auto_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@51993.4] assign auto_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@51993.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@51993.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_size = _T_92[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_source = {_T_134,_T_113}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_10; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_mask = Repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@51992.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@51943.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@51944.4] assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_d_bits_size = _T_18 ? _T_58 : _T_15; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[9:5]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@51989.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52071.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52072.4] assign Repeater_io_repeat = _T_113 != 4'h0; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.TinyConfig.fir@52136.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@52073.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@52137.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_14 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_15 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_16 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_104 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_120 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_14 <= 4'h0; end else begin if (_T_59) begin if (_T_18) begin _T_14 <= _T_17; end else begin _T_14 <= _T_61; end end end if (_T_59) begin if (_T_18) begin _T_15 <= _T_58; end end if (reset) begin _T_16 <= 1'h0; end else begin if (_T_59) begin if (_T_18) begin _T_16 <= _T_63; end end end if (reset) begin _T_104 <= 4'h0; end else begin if (_T_123) begin _T_104 <= _T_113; end end if (_T_105) begin _T_120 <= _T_16; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_147) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52168.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_147) begin $fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@52169.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SimpleLazyModule_11( // @[:freechips.rocketchip.system.TinyConfig.fir@52192.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@52193.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@52194.4] output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [16:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [3:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [31:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [9:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [16:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output [3:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [9:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] input [31:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@52195.4] ); wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [16:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [16:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] TLFragmenter_3 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@52200.4] .clock(fragmenter_clock), .reset(fragmenter_reset), .auto_in_a_ready(fragmenter_auto_in_a_ready), .auto_in_a_valid(fragmenter_auto_in_a_valid), .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode), .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param), .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size), .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source), .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address), .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask), .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt), .auto_in_d_ready(fragmenter_auto_in_d_ready), .auto_in_d_valid(fragmenter_auto_in_d_valid), .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size), .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source), .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data), .auto_out_a_ready(fragmenter_auto_out_a_ready), .auto_out_a_valid(fragmenter_auto_out_a_valid), .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode), .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param), .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size), .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source), .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address), .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask), .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt), .auto_out_d_ready(fragmenter_auto_out_d_ready), .auto_out_d_valid(fragmenter_auto_out_d_valid), .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size), .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source), .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data) ); assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52204.4] assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52205.4] assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52207.4] assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52206.4] endmodule module PeripheryBus_1( // @[:freechips.rocketchip.system.TinyConfig.fir@52209.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@52210.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@52211.4] input auto_coupler_to_bootrom_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_bootrom_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [1:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [9:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [16:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_bootrom_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_bootrom_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [1:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [9:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [4:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [1:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [4:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_debug_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_debug_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [1:0] auto_coupler_to_debug_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [9:0] auto_coupler_to_debug_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [11:0] auto_coupler_to_debug_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_coupler_to_debug_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_coupler_to_debug_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_debug_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_debug_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_debug_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_coupler_to_debug_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [1:0] auto_coupler_to_debug_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [9:0] auto_coupler_to_debug_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_coupler_to_debug_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_clint_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_clint_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [1:0] auto_coupler_to_clint_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [9:0] auto_coupler_to_clint_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [25:0] auto_coupler_to_clint_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_coupler_to_clint_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_coupler_to_clint_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_clint_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_clint_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_clint_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_coupler_to_clint_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [1:0] auto_coupler_to_clint_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [9:0] auto_coupler_to_clint_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_coupler_to_clint_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_plic_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_plic_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [1:0] auto_coupler_to_plic_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [9:0] auto_coupler_to_plic_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [27:0] auto_coupler_to_plic_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_coupler_to_plic_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_coupler_to_plic_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_plic_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_coupler_to_plic_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_coupler_to_plic_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_coupler_to_plic_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [1:0] auto_coupler_to_plic_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [9:0] auto_coupler_to_plic_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_coupler_to_plic_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [2:0] auto_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [3:0] auto_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [4:0] auto_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [3:0] auto_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input [31:0] auto_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] input auto_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [1:0] auto_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [3:0] auto_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [4:0] auto_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output [31:0] auto_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] output auto_bus_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@52212.4] ); wire fixer_clock; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_reset; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_a_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_a_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [4:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_d_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_d_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [1:0] fixer_auto_in_d_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [4:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_d_bits_sink; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_d_bits_denied; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_a_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_a_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [4:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_d_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_d_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [1:0] fixer_auto_out_d_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [3:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [4:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_d_bits_sink; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_d_bits_denied; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire [31:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire fixer_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] wire in_xbar_clock; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_reset; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_a_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_a_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [4:0] in_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_d_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_d_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [1:0] in_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [4:0] in_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [4:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [3:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [4:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire [31:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] wire out_xbar_clock; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_reset; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [1:0] out_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_5_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_5_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_5_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_5_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_5_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_5_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [16:0] out_xbar_auto_out_5_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_5_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_5_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_5_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_5_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_5_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_5_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_5_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_4_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_4_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [1:0] out_xbar_auto_out_4_d_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_d_bits_sink; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_d_bits_denied; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_4_d_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [11:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [25:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [27:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [13:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [1:0] out_xbar_auto_out_0_d_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [3:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [4:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_d_bits_sink; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_d_bits_denied; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire [31:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire out_xbar_auto_out_0_d_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] wire atomics_clock; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_reset; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_a_ready; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_a_valid; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [4:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_d_ready; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_d_valid; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [4:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_a_ready; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_a_valid; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [4:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_d_ready; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_d_valid; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [3:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [4:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire [31:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] wire wrapped_error_device_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [4:0] wrapped_error_device_auto_buffer_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [13:0] wrapped_error_device_auto_buffer_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [2:0] wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [1:0] wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [3:0] wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [4:0] wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire [31:0] wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] wire coupler_to_plic_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [4:0] coupler_to_plic_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [27:0] coupler_to_plic_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [3:0] coupler_to_plic_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [31:0] coupler_to_plic_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [4:0] coupler_to_plic_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [31:0] coupler_to_plic_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [1:0] coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [9:0] coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [27:0] coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [3:0] coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [31:0] coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_plic_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [2:0] coupler_to_plic_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [1:0] coupler_to_plic_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [9:0] coupler_to_plic_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire [31:0] coupler_to_plic_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] wire coupler_to_clint_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [4:0] coupler_to_clint_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [25:0] coupler_to_clint_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [3:0] coupler_to_clint_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [31:0] coupler_to_clint_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [4:0] coupler_to_clint_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [31:0] coupler_to_clint_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [1:0] coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [9:0] coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [25:0] coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [3:0] coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [31:0] coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_clint_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [2:0] coupler_to_clint_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [1:0] coupler_to_clint_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [9:0] coupler_to_clint_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire [31:0] coupler_to_clint_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] wire coupler_to_debug_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [4:0] coupler_to_debug_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [11:0] coupler_to_debug_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [3:0] coupler_to_debug_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [31:0] coupler_to_debug_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [4:0] coupler_to_debug_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [31:0] coupler_to_debug_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [1:0] coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [9:0] coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [11:0] coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [3:0] coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [31:0] coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_debug_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [2:0] coupler_to_debug_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [1:0] coupler_to_debug_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [9:0] coupler_to_debug_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire [31:0] coupler_to_debug_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] wire coupler_to_tile_named_tile_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [4:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [3:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_buffer_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [1:0] coupler_to_tile_named_tile_auto_buffer_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_buffer_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [4:0] coupler_to_tile_named_tile_auto_buffer_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_buffer_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [4:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [3:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [1:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [2:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [4:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire [31:0] coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] wire buffer_1_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [4:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [4:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [4:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [4:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire [31:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] wire coupler_to_bootrom_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [4:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [16:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [3:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [4:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [31:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [1:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [9:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [16:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [3:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire coupler_to_bootrom_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [1:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [9:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] wire [31:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] TLFIFOFixer_3 fixer ( // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.TinyConfig.fir@52217.4] .clock(fixer_clock), .reset(fixer_reset), .auto_in_a_ready(fixer_auto_in_a_ready), .auto_in_a_valid(fixer_auto_in_a_valid), .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode), .auto_in_a_bits_param(fixer_auto_in_a_bits_param), .auto_in_a_bits_size(fixer_auto_in_a_bits_size), .auto_in_a_bits_source(fixer_auto_in_a_bits_source), .auto_in_a_bits_address(fixer_auto_in_a_bits_address), .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask), .auto_in_a_bits_data(fixer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt), .auto_in_d_ready(fixer_auto_in_d_ready), .auto_in_d_valid(fixer_auto_in_d_valid), .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode), .auto_in_d_bits_param(fixer_auto_in_d_bits_param), .auto_in_d_bits_size(fixer_auto_in_d_bits_size), .auto_in_d_bits_source(fixer_auto_in_d_bits_source), .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink), .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied), .auto_in_d_bits_data(fixer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt), .auto_out_a_ready(fixer_auto_out_a_ready), .auto_out_a_valid(fixer_auto_out_a_valid), .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode), .auto_out_a_bits_param(fixer_auto_out_a_bits_param), .auto_out_a_bits_size(fixer_auto_out_a_bits_size), .auto_out_a_bits_source(fixer_auto_out_a_bits_source), .auto_out_a_bits_address(fixer_auto_out_a_bits_address), .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask), .auto_out_a_bits_data(fixer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt), .auto_out_d_ready(fixer_auto_out_d_ready), .auto_out_d_valid(fixer_auto_out_d_valid), .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode), .auto_out_d_bits_param(fixer_auto_out_d_bits_param), .auto_out_d_bits_size(fixer_auto_out_d_bits_size), .auto_out_d_bits_source(fixer_auto_out_d_bits_source), .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink), .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied), .auto_out_d_bits_data(fixer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt) ); TLXbar_5 in_xbar ( // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.TinyConfig.fir@52223.4] .clock(in_xbar_clock), .reset(in_xbar_reset), .auto_in_a_ready(in_xbar_auto_in_a_ready), .auto_in_a_valid(in_xbar_auto_in_a_valid), .auto_in_a_bits_opcode(in_xbar_auto_in_a_bits_opcode), .auto_in_a_bits_param(in_xbar_auto_in_a_bits_param), .auto_in_a_bits_size(in_xbar_auto_in_a_bits_size), .auto_in_a_bits_source(in_xbar_auto_in_a_bits_source), .auto_in_a_bits_address(in_xbar_auto_in_a_bits_address), .auto_in_a_bits_mask(in_xbar_auto_in_a_bits_mask), .auto_in_a_bits_data(in_xbar_auto_in_a_bits_data), .auto_in_a_bits_corrupt(in_xbar_auto_in_a_bits_corrupt), .auto_in_d_ready(in_xbar_auto_in_d_ready), .auto_in_d_valid(in_xbar_auto_in_d_valid), .auto_in_d_bits_opcode(in_xbar_auto_in_d_bits_opcode), .auto_in_d_bits_param(in_xbar_auto_in_d_bits_param), .auto_in_d_bits_size(in_xbar_auto_in_d_bits_size), .auto_in_d_bits_source(in_xbar_auto_in_d_bits_source), .auto_in_d_bits_sink(in_xbar_auto_in_d_bits_sink), .auto_in_d_bits_denied(in_xbar_auto_in_d_bits_denied), .auto_in_d_bits_data(in_xbar_auto_in_d_bits_data), .auto_in_d_bits_corrupt(in_xbar_auto_in_d_bits_corrupt), .auto_out_a_ready(in_xbar_auto_out_a_ready), .auto_out_a_valid(in_xbar_auto_out_a_valid), .auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode), .auto_out_a_bits_param(in_xbar_auto_out_a_bits_param), .auto_out_a_bits_size(in_xbar_auto_out_a_bits_size), .auto_out_a_bits_source(in_xbar_auto_out_a_bits_source), .auto_out_a_bits_address(in_xbar_auto_out_a_bits_address), .auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask), .auto_out_a_bits_data(in_xbar_auto_out_a_bits_data), .auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt), .auto_out_d_ready(in_xbar_auto_out_d_ready), .auto_out_d_valid(in_xbar_auto_out_d_valid), .auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode), .auto_out_d_bits_param(in_xbar_auto_out_d_bits_param), .auto_out_d_bits_size(in_xbar_auto_out_d_bits_size), .auto_out_d_bits_source(in_xbar_auto_out_d_bits_source), .auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink), .auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied), .auto_out_d_bits_data(in_xbar_auto_out_d_bits_data), .auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt) ); TLXbar_6 out_xbar ( // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@52229.4] .clock(out_xbar_clock), .reset(out_xbar_reset), .auto_in_a_ready(out_xbar_auto_in_a_ready), .auto_in_a_valid(out_xbar_auto_in_a_valid), .auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode), .auto_in_a_bits_param(out_xbar_auto_in_a_bits_param), .auto_in_a_bits_size(out_xbar_auto_in_a_bits_size), .auto_in_a_bits_source(out_xbar_auto_in_a_bits_source), .auto_in_a_bits_address(out_xbar_auto_in_a_bits_address), .auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask), .auto_in_a_bits_data(out_xbar_auto_in_a_bits_data), .auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt), .auto_in_d_ready(out_xbar_auto_in_d_ready), .auto_in_d_valid(out_xbar_auto_in_d_valid), .auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode), .auto_in_d_bits_param(out_xbar_auto_in_d_bits_param), .auto_in_d_bits_size(out_xbar_auto_in_d_bits_size), .auto_in_d_bits_source(out_xbar_auto_in_d_bits_source), .auto_in_d_bits_sink(out_xbar_auto_in_d_bits_sink), .auto_in_d_bits_denied(out_xbar_auto_in_d_bits_denied), .auto_in_d_bits_data(out_xbar_auto_in_d_bits_data), .auto_in_d_bits_corrupt(out_xbar_auto_in_d_bits_corrupt), .auto_out_5_a_ready(out_xbar_auto_out_5_a_ready), .auto_out_5_a_valid(out_xbar_auto_out_5_a_valid), .auto_out_5_a_bits_opcode(out_xbar_auto_out_5_a_bits_opcode), .auto_out_5_a_bits_param(out_xbar_auto_out_5_a_bits_param), .auto_out_5_a_bits_size(out_xbar_auto_out_5_a_bits_size), .auto_out_5_a_bits_source(out_xbar_auto_out_5_a_bits_source), .auto_out_5_a_bits_address(out_xbar_auto_out_5_a_bits_address), .auto_out_5_a_bits_mask(out_xbar_auto_out_5_a_bits_mask), .auto_out_5_a_bits_corrupt(out_xbar_auto_out_5_a_bits_corrupt), .auto_out_5_d_ready(out_xbar_auto_out_5_d_ready), .auto_out_5_d_valid(out_xbar_auto_out_5_d_valid), .auto_out_5_d_bits_size(out_xbar_auto_out_5_d_bits_size), .auto_out_5_d_bits_source(out_xbar_auto_out_5_d_bits_source), .auto_out_5_d_bits_data(out_xbar_auto_out_5_d_bits_data), .auto_out_4_a_ready(out_xbar_auto_out_4_a_ready), .auto_out_4_a_valid(out_xbar_auto_out_4_a_valid), .auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode), .auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param), .auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size), .auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source), .auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address), .auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask), .auto_out_4_a_bits_data(out_xbar_auto_out_4_a_bits_data), .auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt), .auto_out_4_d_ready(out_xbar_auto_out_4_d_ready), .auto_out_4_d_valid(out_xbar_auto_out_4_d_valid), .auto_out_4_d_bits_opcode(out_xbar_auto_out_4_d_bits_opcode), .auto_out_4_d_bits_param(out_xbar_auto_out_4_d_bits_param), .auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size), .auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source), .auto_out_4_d_bits_sink(out_xbar_auto_out_4_d_bits_sink), .auto_out_4_d_bits_denied(out_xbar_auto_out_4_d_bits_denied), .auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data), .auto_out_4_d_bits_corrupt(out_xbar_auto_out_4_d_bits_corrupt), .auto_out_3_a_ready(out_xbar_auto_out_3_a_ready), .auto_out_3_a_valid(out_xbar_auto_out_3_a_valid), .auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param), .auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size), .auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source), .auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt), .auto_out_3_d_ready(out_xbar_auto_out_3_d_ready), .auto_out_3_d_valid(out_xbar_auto_out_3_d_valid), .auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode), .auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size), .auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source), .auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data), .auto_out_2_a_ready(out_xbar_auto_out_2_a_ready), .auto_out_2_a_valid(out_xbar_auto_out_2_a_valid), .auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param), .auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size), .auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source), .auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt), .auto_out_2_d_ready(out_xbar_auto_out_2_d_ready), .auto_out_2_d_valid(out_xbar_auto_out_2_d_valid), .auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode), .auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size), .auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source), .auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data), .auto_out_1_a_ready(out_xbar_auto_out_1_a_ready), .auto_out_1_a_valid(out_xbar_auto_out_1_a_valid), .auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param), .auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size), .auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source), .auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready(out_xbar_auto_out_1_d_ready), .auto_out_1_d_valid(out_xbar_auto_out_1_d_valid), .auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode), .auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size), .auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source), .auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data), .auto_out_0_a_ready(out_xbar_auto_out_0_a_ready), .auto_out_0_a_valid(out_xbar_auto_out_0_a_valid), .auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param), .auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size), .auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source), .auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask), .auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready(out_xbar_auto_out_0_d_ready), .auto_out_0_d_valid(out_xbar_auto_out_0_d_valid), .auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode), .auto_out_0_d_bits_param(out_xbar_auto_out_0_d_bits_param), .auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size), .auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source), .auto_out_0_d_bits_sink(out_xbar_auto_out_0_d_bits_sink), .auto_out_0_d_bits_denied(out_xbar_auto_out_0_d_bits_denied), .auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data), .auto_out_0_d_bits_corrupt(out_xbar_auto_out_0_d_bits_corrupt) ); TLBuffer_6 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52235.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); TLAtomicAutomata_1 atomics ( // @[AtomicAutomata.scala 282:29:freechips.rocketchip.system.TinyConfig.fir@52241.4] .clock(atomics_clock), .reset(atomics_reset), .auto_in_a_ready(atomics_auto_in_a_ready), .auto_in_a_valid(atomics_auto_in_a_valid), .auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode), .auto_in_a_bits_param(atomics_auto_in_a_bits_param), .auto_in_a_bits_size(atomics_auto_in_a_bits_size), .auto_in_a_bits_source(atomics_auto_in_a_bits_source), .auto_in_a_bits_address(atomics_auto_in_a_bits_address), .auto_in_a_bits_mask(atomics_auto_in_a_bits_mask), .auto_in_a_bits_data(atomics_auto_in_a_bits_data), .auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt), .auto_in_d_ready(atomics_auto_in_d_ready), .auto_in_d_valid(atomics_auto_in_d_valid), .auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode), .auto_in_d_bits_param(atomics_auto_in_d_bits_param), .auto_in_d_bits_size(atomics_auto_in_d_bits_size), .auto_in_d_bits_source(atomics_auto_in_d_bits_source), .auto_in_d_bits_sink(atomics_auto_in_d_bits_sink), .auto_in_d_bits_denied(atomics_auto_in_d_bits_denied), .auto_in_d_bits_data(atomics_auto_in_d_bits_data), .auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt), .auto_out_a_ready(atomics_auto_out_a_ready), .auto_out_a_valid(atomics_auto_out_a_valid), .auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param(atomics_auto_out_a_bits_param), .auto_out_a_bits_size(atomics_auto_out_a_bits_size), .auto_out_a_bits_source(atomics_auto_out_a_bits_source), .auto_out_a_bits_address(atomics_auto_out_a_bits_address), .auto_out_a_bits_mask(atomics_auto_out_a_bits_mask), .auto_out_a_bits_data(atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt), .auto_out_d_ready(atomics_auto_out_d_ready), .auto_out_d_valid(atomics_auto_out_d_valid), .auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode), .auto_out_d_bits_param(atomics_auto_out_d_bits_param), .auto_out_d_bits_size(atomics_auto_out_d_bits_size), .auto_out_d_bits_source(atomics_auto_out_d_bits_source), .auto_out_d_bits_sink(atomics_auto_out_d_bits_sink), .auto_out_d_bits_denied(atomics_auto_out_d_bits_denied), .auto_out_d_bits_data(atomics_auto_out_d_bits_data), .auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt) ); SimpleLazyModule_5 wrapped_error_device ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52247.4] .clock(wrapped_error_device_clock), .reset(wrapped_error_device_reset), .auto_buffer_in_a_ready(wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid(wrapped_error_device_auto_buffer_in_a_valid), .auto_buffer_in_a_bits_opcode(wrapped_error_device_auto_buffer_in_a_bits_opcode), .auto_buffer_in_a_bits_param(wrapped_error_device_auto_buffer_in_a_bits_param), .auto_buffer_in_a_bits_size(wrapped_error_device_auto_buffer_in_a_bits_size), .auto_buffer_in_a_bits_source(wrapped_error_device_auto_buffer_in_a_bits_source), .auto_buffer_in_a_bits_address(wrapped_error_device_auto_buffer_in_a_bits_address), .auto_buffer_in_a_bits_mask(wrapped_error_device_auto_buffer_in_a_bits_mask), .auto_buffer_in_a_bits_corrupt(wrapped_error_device_auto_buffer_in_a_bits_corrupt), .auto_buffer_in_d_ready(wrapped_error_device_auto_buffer_in_d_ready), .auto_buffer_in_d_valid(wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode(wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param(wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size(wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source(wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink(wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied(wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data(wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt(wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); SimpleLazyModule_6 coupler_to_plic ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52253.4] .clock(coupler_to_plic_clock), .reset(coupler_to_plic_reset), .auto_fragmenter_in_a_ready(coupler_to_plic_auto_fragmenter_in_a_ready), .auto_fragmenter_in_a_valid(coupler_to_plic_auto_fragmenter_in_a_valid), .auto_fragmenter_in_a_bits_opcode(coupler_to_plic_auto_fragmenter_in_a_bits_opcode), .auto_fragmenter_in_a_bits_param(coupler_to_plic_auto_fragmenter_in_a_bits_param), .auto_fragmenter_in_a_bits_size(coupler_to_plic_auto_fragmenter_in_a_bits_size), .auto_fragmenter_in_a_bits_source(coupler_to_plic_auto_fragmenter_in_a_bits_source), .auto_fragmenter_in_a_bits_address(coupler_to_plic_auto_fragmenter_in_a_bits_address), .auto_fragmenter_in_a_bits_mask(coupler_to_plic_auto_fragmenter_in_a_bits_mask), .auto_fragmenter_in_a_bits_data(coupler_to_plic_auto_fragmenter_in_a_bits_data), .auto_fragmenter_in_a_bits_corrupt(coupler_to_plic_auto_fragmenter_in_a_bits_corrupt), .auto_fragmenter_in_d_ready(coupler_to_plic_auto_fragmenter_in_d_ready), .auto_fragmenter_in_d_valid(coupler_to_plic_auto_fragmenter_in_d_valid), .auto_fragmenter_in_d_bits_opcode(coupler_to_plic_auto_fragmenter_in_d_bits_opcode), .auto_fragmenter_in_d_bits_size(coupler_to_plic_auto_fragmenter_in_d_bits_size), .auto_fragmenter_in_d_bits_source(coupler_to_plic_auto_fragmenter_in_d_bits_source), .auto_fragmenter_in_d_bits_data(coupler_to_plic_auto_fragmenter_in_d_bits_data), .auto_fragmenter_out_a_ready(coupler_to_plic_auto_fragmenter_out_a_ready), .auto_fragmenter_out_a_valid(coupler_to_plic_auto_fragmenter_out_a_valid), .auto_fragmenter_out_a_bits_opcode(coupler_to_plic_auto_fragmenter_out_a_bits_opcode), .auto_fragmenter_out_a_bits_param(coupler_to_plic_auto_fragmenter_out_a_bits_param), .auto_fragmenter_out_a_bits_size(coupler_to_plic_auto_fragmenter_out_a_bits_size), .auto_fragmenter_out_a_bits_source(coupler_to_plic_auto_fragmenter_out_a_bits_source), .auto_fragmenter_out_a_bits_address(coupler_to_plic_auto_fragmenter_out_a_bits_address), .auto_fragmenter_out_a_bits_mask(coupler_to_plic_auto_fragmenter_out_a_bits_mask), .auto_fragmenter_out_a_bits_data(coupler_to_plic_auto_fragmenter_out_a_bits_data), .auto_fragmenter_out_a_bits_corrupt(coupler_to_plic_auto_fragmenter_out_a_bits_corrupt), .auto_fragmenter_out_d_ready(coupler_to_plic_auto_fragmenter_out_d_ready), .auto_fragmenter_out_d_valid(coupler_to_plic_auto_fragmenter_out_d_valid), .auto_fragmenter_out_d_bits_opcode(coupler_to_plic_auto_fragmenter_out_d_bits_opcode), .auto_fragmenter_out_d_bits_size(coupler_to_plic_auto_fragmenter_out_d_bits_size), .auto_fragmenter_out_d_bits_source(coupler_to_plic_auto_fragmenter_out_d_bits_source), .auto_fragmenter_out_d_bits_data(coupler_to_plic_auto_fragmenter_out_d_bits_data) ); SimpleLazyModule_7 coupler_to_clint ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52259.4] .clock(coupler_to_clint_clock), .reset(coupler_to_clint_reset), .auto_fragmenter_in_a_ready(coupler_to_clint_auto_fragmenter_in_a_ready), .auto_fragmenter_in_a_valid(coupler_to_clint_auto_fragmenter_in_a_valid), .auto_fragmenter_in_a_bits_opcode(coupler_to_clint_auto_fragmenter_in_a_bits_opcode), .auto_fragmenter_in_a_bits_param(coupler_to_clint_auto_fragmenter_in_a_bits_param), .auto_fragmenter_in_a_bits_size(coupler_to_clint_auto_fragmenter_in_a_bits_size), .auto_fragmenter_in_a_bits_source(coupler_to_clint_auto_fragmenter_in_a_bits_source), .auto_fragmenter_in_a_bits_address(coupler_to_clint_auto_fragmenter_in_a_bits_address), .auto_fragmenter_in_a_bits_mask(coupler_to_clint_auto_fragmenter_in_a_bits_mask), .auto_fragmenter_in_a_bits_data(coupler_to_clint_auto_fragmenter_in_a_bits_data), .auto_fragmenter_in_a_bits_corrupt(coupler_to_clint_auto_fragmenter_in_a_bits_corrupt), .auto_fragmenter_in_d_ready(coupler_to_clint_auto_fragmenter_in_d_ready), .auto_fragmenter_in_d_valid(coupler_to_clint_auto_fragmenter_in_d_valid), .auto_fragmenter_in_d_bits_opcode(coupler_to_clint_auto_fragmenter_in_d_bits_opcode), .auto_fragmenter_in_d_bits_size(coupler_to_clint_auto_fragmenter_in_d_bits_size), .auto_fragmenter_in_d_bits_source(coupler_to_clint_auto_fragmenter_in_d_bits_source), .auto_fragmenter_in_d_bits_data(coupler_to_clint_auto_fragmenter_in_d_bits_data), .auto_fragmenter_out_a_ready(coupler_to_clint_auto_fragmenter_out_a_ready), .auto_fragmenter_out_a_valid(coupler_to_clint_auto_fragmenter_out_a_valid), .auto_fragmenter_out_a_bits_opcode(coupler_to_clint_auto_fragmenter_out_a_bits_opcode), .auto_fragmenter_out_a_bits_param(coupler_to_clint_auto_fragmenter_out_a_bits_param), .auto_fragmenter_out_a_bits_size(coupler_to_clint_auto_fragmenter_out_a_bits_size), .auto_fragmenter_out_a_bits_source(coupler_to_clint_auto_fragmenter_out_a_bits_source), .auto_fragmenter_out_a_bits_address(coupler_to_clint_auto_fragmenter_out_a_bits_address), .auto_fragmenter_out_a_bits_mask(coupler_to_clint_auto_fragmenter_out_a_bits_mask), .auto_fragmenter_out_a_bits_data(coupler_to_clint_auto_fragmenter_out_a_bits_data), .auto_fragmenter_out_a_bits_corrupt(coupler_to_clint_auto_fragmenter_out_a_bits_corrupt), .auto_fragmenter_out_d_ready(coupler_to_clint_auto_fragmenter_out_d_ready), .auto_fragmenter_out_d_valid(coupler_to_clint_auto_fragmenter_out_d_valid), .auto_fragmenter_out_d_bits_opcode(coupler_to_clint_auto_fragmenter_out_d_bits_opcode), .auto_fragmenter_out_d_bits_size(coupler_to_clint_auto_fragmenter_out_d_bits_size), .auto_fragmenter_out_d_bits_source(coupler_to_clint_auto_fragmenter_out_d_bits_source), .auto_fragmenter_out_d_bits_data(coupler_to_clint_auto_fragmenter_out_d_bits_data) ); SimpleLazyModule_8 coupler_to_debug ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52265.4] .clock(coupler_to_debug_clock), .reset(coupler_to_debug_reset), .auto_fragmenter_in_a_ready(coupler_to_debug_auto_fragmenter_in_a_ready), .auto_fragmenter_in_a_valid(coupler_to_debug_auto_fragmenter_in_a_valid), .auto_fragmenter_in_a_bits_opcode(coupler_to_debug_auto_fragmenter_in_a_bits_opcode), .auto_fragmenter_in_a_bits_param(coupler_to_debug_auto_fragmenter_in_a_bits_param), .auto_fragmenter_in_a_bits_size(coupler_to_debug_auto_fragmenter_in_a_bits_size), .auto_fragmenter_in_a_bits_source(coupler_to_debug_auto_fragmenter_in_a_bits_source), .auto_fragmenter_in_a_bits_address(coupler_to_debug_auto_fragmenter_in_a_bits_address), .auto_fragmenter_in_a_bits_mask(coupler_to_debug_auto_fragmenter_in_a_bits_mask), .auto_fragmenter_in_a_bits_data(coupler_to_debug_auto_fragmenter_in_a_bits_data), .auto_fragmenter_in_a_bits_corrupt(coupler_to_debug_auto_fragmenter_in_a_bits_corrupt), .auto_fragmenter_in_d_ready(coupler_to_debug_auto_fragmenter_in_d_ready), .auto_fragmenter_in_d_valid(coupler_to_debug_auto_fragmenter_in_d_valid), .auto_fragmenter_in_d_bits_opcode(coupler_to_debug_auto_fragmenter_in_d_bits_opcode), .auto_fragmenter_in_d_bits_size(coupler_to_debug_auto_fragmenter_in_d_bits_size), .auto_fragmenter_in_d_bits_source(coupler_to_debug_auto_fragmenter_in_d_bits_source), .auto_fragmenter_in_d_bits_data(coupler_to_debug_auto_fragmenter_in_d_bits_data), .auto_fragmenter_out_a_ready(coupler_to_debug_auto_fragmenter_out_a_ready), .auto_fragmenter_out_a_valid(coupler_to_debug_auto_fragmenter_out_a_valid), .auto_fragmenter_out_a_bits_opcode(coupler_to_debug_auto_fragmenter_out_a_bits_opcode), .auto_fragmenter_out_a_bits_param(coupler_to_debug_auto_fragmenter_out_a_bits_param), .auto_fragmenter_out_a_bits_size(coupler_to_debug_auto_fragmenter_out_a_bits_size), .auto_fragmenter_out_a_bits_source(coupler_to_debug_auto_fragmenter_out_a_bits_source), .auto_fragmenter_out_a_bits_address(coupler_to_debug_auto_fragmenter_out_a_bits_address), .auto_fragmenter_out_a_bits_mask(coupler_to_debug_auto_fragmenter_out_a_bits_mask), .auto_fragmenter_out_a_bits_data(coupler_to_debug_auto_fragmenter_out_a_bits_data), .auto_fragmenter_out_a_bits_corrupt(coupler_to_debug_auto_fragmenter_out_a_bits_corrupt), .auto_fragmenter_out_d_ready(coupler_to_debug_auto_fragmenter_out_d_ready), .auto_fragmenter_out_d_valid(coupler_to_debug_auto_fragmenter_out_d_valid), .auto_fragmenter_out_d_bits_opcode(coupler_to_debug_auto_fragmenter_out_d_bits_opcode), .auto_fragmenter_out_d_bits_size(coupler_to_debug_auto_fragmenter_out_d_bits_size), .auto_fragmenter_out_d_bits_source(coupler_to_debug_auto_fragmenter_out_d_bits_source), .auto_fragmenter_out_d_bits_data(coupler_to_debug_auto_fragmenter_out_d_bits_data) ); SimpleLazyModule_9 coupler_to_tile_named_tile ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52271.4] .clock(coupler_to_tile_named_tile_clock), .reset(coupler_to_tile_named_tile_reset), .auto_buffer_in_a_ready(coupler_to_tile_named_tile_auto_buffer_in_a_ready), .auto_buffer_in_a_valid(coupler_to_tile_named_tile_auto_buffer_in_a_valid), .auto_buffer_in_a_bits_opcode(coupler_to_tile_named_tile_auto_buffer_in_a_bits_opcode), .auto_buffer_in_a_bits_param(coupler_to_tile_named_tile_auto_buffer_in_a_bits_param), .auto_buffer_in_a_bits_size(coupler_to_tile_named_tile_auto_buffer_in_a_bits_size), .auto_buffer_in_a_bits_source(coupler_to_tile_named_tile_auto_buffer_in_a_bits_source), .auto_buffer_in_a_bits_address(coupler_to_tile_named_tile_auto_buffer_in_a_bits_address), .auto_buffer_in_a_bits_mask(coupler_to_tile_named_tile_auto_buffer_in_a_bits_mask), .auto_buffer_in_a_bits_data(coupler_to_tile_named_tile_auto_buffer_in_a_bits_data), .auto_buffer_in_a_bits_corrupt(coupler_to_tile_named_tile_auto_buffer_in_a_bits_corrupt), .auto_buffer_in_d_ready(coupler_to_tile_named_tile_auto_buffer_in_d_ready), .auto_buffer_in_d_valid(coupler_to_tile_named_tile_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode(coupler_to_tile_named_tile_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param(coupler_to_tile_named_tile_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size(coupler_to_tile_named_tile_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source(coupler_to_tile_named_tile_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink(coupler_to_tile_named_tile_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied(coupler_to_tile_named_tile_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data(coupler_to_tile_named_tile_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt(coupler_to_tile_named_tile_auto_buffer_in_d_bits_corrupt), .auto_tl_slave_xing_out_a_ready(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_ready), .auto_tl_slave_xing_out_a_valid(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_valid), .auto_tl_slave_xing_out_a_bits_opcode(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_opcode), .auto_tl_slave_xing_out_a_bits_param(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_param), .auto_tl_slave_xing_out_a_bits_size(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_size), .auto_tl_slave_xing_out_a_bits_source(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_source), .auto_tl_slave_xing_out_a_bits_address(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_address), .auto_tl_slave_xing_out_a_bits_mask(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_mask), .auto_tl_slave_xing_out_a_bits_data(coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_data), .auto_tl_slave_xing_out_d_ready(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_ready), .auto_tl_slave_xing_out_d_valid(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_valid), .auto_tl_slave_xing_out_d_bits_opcode(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_opcode), .auto_tl_slave_xing_out_d_bits_param(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_param), .auto_tl_slave_xing_out_d_bits_size(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_size), .auto_tl_slave_xing_out_d_bits_source(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_source), .auto_tl_slave_xing_out_d_bits_sink(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_sink), .auto_tl_slave_xing_out_d_bits_denied(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_denied), .auto_tl_slave_xing_out_d_bits_data(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_data), .auto_tl_slave_xing_out_d_bits_corrupt(coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_corrupt) ); TLBuffer_9 buffer_1 ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@52277.4] .clock(buffer_1_clock), .reset(buffer_1_reset), .auto_in_a_ready(buffer_1_auto_in_a_ready), .auto_in_a_valid(buffer_1_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_1_auto_in_d_ready), .auto_in_d_valid(buffer_1_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_1_auto_out_a_ready), .auto_out_a_valid(buffer_1_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_1_auto_out_d_ready), .auto_out_d_valid(buffer_1_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt) ); SimpleLazyModule_11 coupler_to_bootrom ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.TinyConfig.fir@52289.4] .clock(coupler_to_bootrom_clock), .reset(coupler_to_bootrom_reset), .auto_fragmenter_in_a_ready(coupler_to_bootrom_auto_fragmenter_in_a_ready), .auto_fragmenter_in_a_valid(coupler_to_bootrom_auto_fragmenter_in_a_valid), .auto_fragmenter_in_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode), .auto_fragmenter_in_a_bits_param(coupler_to_bootrom_auto_fragmenter_in_a_bits_param), .auto_fragmenter_in_a_bits_size(coupler_to_bootrom_auto_fragmenter_in_a_bits_size), .auto_fragmenter_in_a_bits_source(coupler_to_bootrom_auto_fragmenter_in_a_bits_source), .auto_fragmenter_in_a_bits_address(coupler_to_bootrom_auto_fragmenter_in_a_bits_address), .auto_fragmenter_in_a_bits_mask(coupler_to_bootrom_auto_fragmenter_in_a_bits_mask), .auto_fragmenter_in_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt), .auto_fragmenter_in_d_ready(coupler_to_bootrom_auto_fragmenter_in_d_ready), .auto_fragmenter_in_d_valid(coupler_to_bootrom_auto_fragmenter_in_d_valid), .auto_fragmenter_in_d_bits_size(coupler_to_bootrom_auto_fragmenter_in_d_bits_size), .auto_fragmenter_in_d_bits_source(coupler_to_bootrom_auto_fragmenter_in_d_bits_source), .auto_fragmenter_in_d_bits_data(coupler_to_bootrom_auto_fragmenter_in_d_bits_data), .auto_fragmenter_out_a_ready(coupler_to_bootrom_auto_fragmenter_out_a_ready), .auto_fragmenter_out_a_valid(coupler_to_bootrom_auto_fragmenter_out_a_valid), .auto_fragmenter_out_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode), .auto_fragmenter_out_a_bits_param(coupler_to_bootrom_auto_fragmenter_out_a_bits_param), .auto_fragmenter_out_a_bits_size(coupler_to_bootrom_auto_fragmenter_out_a_bits_size), .auto_fragmenter_out_a_bits_source(coupler_to_bootrom_auto_fragmenter_out_a_bits_source), .auto_fragmenter_out_a_bits_address(coupler_to_bootrom_auto_fragmenter_out_a_bits_address), .auto_fragmenter_out_a_bits_mask(coupler_to_bootrom_auto_fragmenter_out_a_bits_mask), .auto_fragmenter_out_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt), .auto_fragmenter_out_d_ready(coupler_to_bootrom_auto_fragmenter_out_d_ready), .auto_fragmenter_out_d_valid(coupler_to_bootrom_auto_fragmenter_out_d_valid), .auto_fragmenter_out_d_bits_size(coupler_to_bootrom_auto_fragmenter_out_d_bits_size), .auto_fragmenter_out_d_bits_source(coupler_to_bootrom_auto_fragmenter_out_d_bits_source), .auto_fragmenter_out_d_bits_data(coupler_to_bootrom_auto_fragmenter_out_d_bits_data) ); assign auto_coupler_to_bootrom_fragmenter_out_a_valid = coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode = coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_param = coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_size = coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_source = coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_address = coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_mask = coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt = coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_bootrom_fragmenter_out_d_ready = coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data = coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready = coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign auto_coupler_to_debug_fragmenter_out_a_valid = coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_opcode = coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_param = coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_size = coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_source = coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_address = coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_mask = coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_data = coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_a_bits_corrupt = coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_debug_fragmenter_out_d_ready = coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign auto_coupler_to_clint_fragmenter_out_a_valid = coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_opcode = coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_param = coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_size = coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_source = coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_address = coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_mask = coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_data = coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_a_bits_corrupt = coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_clint_fragmenter_out_d_ready = coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign auto_coupler_to_plic_fragmenter_out_a_valid = coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_opcode = coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_param = coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_size = coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_source = coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_address = coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_mask = coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_data = coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_a_bits_corrupt = coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_coupler_to_plic_fragmenter_out_d_ready = coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@52312.4] assign fixer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52221.4] assign fixer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52222.4] assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_param = out_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_sink = out_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_denied = out_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign fixer_auto_out_d_bits_corrupt = out_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign in_xbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52227.4] assign in_xbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52228.4] assign in_xbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign out_xbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52233.4] assign out_xbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52234.4] assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52300.4] assign out_xbar_auto_out_5_a_ready = coupler_to_bootrom_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign out_xbar_auto_out_5_d_valid = coupler_to_bootrom_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign out_xbar_auto_out_5_d_bits_size = coupler_to_bootrom_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign out_xbar_auto_out_5_d_bits_source = coupler_to_bootrom_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign out_xbar_auto_out_5_d_bits_data = coupler_to_bootrom_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign out_xbar_auto_out_4_a_ready = coupler_to_tile_named_tile_auto_buffer_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_valid = coupler_to_tile_named_tile_auto_buffer_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_opcode = coupler_to_tile_named_tile_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_param = coupler_to_tile_named_tile_auto_buffer_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_size = coupler_to_tile_named_tile_auto_buffer_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_source = coupler_to_tile_named_tile_auto_buffer_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_sink = coupler_to_tile_named_tile_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_denied = coupler_to_tile_named_tile_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_data = coupler_to_tile_named_tile_auto_buffer_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_4_d_bits_corrupt = coupler_to_tile_named_tile_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign out_xbar_auto_out_3_a_ready = coupler_to_debug_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_3_d_valid = coupler_to_debug_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_debug_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_3_d_bits_size = coupler_to_debug_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_3_d_bits_source = coupler_to_debug_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_3_d_bits_data = coupler_to_debug_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign out_xbar_auto_out_2_a_ready = coupler_to_clint_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_2_d_valid = coupler_to_clint_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_clint_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_2_d_bits_size = coupler_to_clint_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_2_d_bits_source = coupler_to_clint_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_2_d_bits_data = coupler_to_clint_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign out_xbar_auto_out_1_a_ready = coupler_to_plic_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_1_d_valid = coupler_to_plic_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_plic_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_1_d_bits_size = coupler_to_plic_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_1_d_bits_source = coupler_to_plic_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_1_d_bits_data = coupler_to_plic_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign out_xbar_auto_out_0_a_ready = wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_valid = wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_opcode = wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_param = wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_size = wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_source = wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_sink = wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_denied = wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_data = wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign out_xbar_auto_out_0_d_bits_corrupt = wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52239.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52240.4] assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign buffer_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52308.4] assign atomics_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52245.4] assign atomics_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52246.4] assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52301.4] assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52309.4] assign wrapped_error_device_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52251.4] assign wrapped_error_device_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52252.4] assign wrapped_error_device_auto_buffer_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign wrapped_error_device_auto_buffer_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52302.4] assign coupler_to_plic_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52257.4] assign coupler_to_plic_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52258.4] assign coupler_to_plic_auto_fragmenter_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52303.4] assign coupler_to_plic_auto_fragmenter_out_a_ready = auto_coupler_to_plic_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_plic_auto_fragmenter_out_d_valid = auto_coupler_to_plic_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_plic_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_plic_auto_fragmenter_out_d_bits_size = auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_plic_auto_fragmenter_out_d_bits_source = auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_plic_auto_fragmenter_out_d_bits_data = auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52313.4] assign coupler_to_clint_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52263.4] assign coupler_to_clint_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52264.4] assign coupler_to_clint_auto_fragmenter_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52304.4] assign coupler_to_clint_auto_fragmenter_out_a_ready = auto_coupler_to_clint_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_clint_auto_fragmenter_out_d_valid = auto_coupler_to_clint_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_clint_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_clint_auto_fragmenter_out_d_bits_size = auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_clint_auto_fragmenter_out_d_bits_source = auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_clint_auto_fragmenter_out_d_bits_data = auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52314.4] assign coupler_to_debug_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52269.4] assign coupler_to_debug_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52270.4] assign coupler_to_debug_auto_fragmenter_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52305.4] assign coupler_to_debug_auto_fragmenter_out_a_ready = auto_coupler_to_debug_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_debug_auto_fragmenter_out_d_valid = auto_coupler_to_debug_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_debug_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_debug_auto_fragmenter_out_d_bits_size = auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_debug_auto_fragmenter_out_d_bits_source = auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_debug_auto_fragmenter_out_d_bits_data = auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52315.4] assign coupler_to_tile_named_tile_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52275.4] assign coupler_to_tile_named_tile_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52276.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_data = out_xbar_auto_out_4_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_buffer_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52306.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_a_ready = auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_valid = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_opcode = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_param = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_size = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_source = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_sink = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_denied = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_data = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign coupler_to_tile_named_tile_auto_tl_slave_xing_out_d_bits_corrupt = auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52316.4] assign buffer_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52281.4] assign buffer_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52282.4] assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52311.4] assign buffer_1_auto_out_a_ready = in_xbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_valid = in_xbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@52310.4] assign coupler_to_bootrom_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@52293.4] assign coupler_to_bootrom_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@52294.4] assign coupler_to_bootrom_auto_fragmenter_in_a_valid = out_xbar_auto_out_5_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_5_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_5_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_5_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_5_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_5_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_5_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_5_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_in_d_ready = out_xbar_auto_out_5_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@52307.4] assign coupler_to_bootrom_auto_fragmenter_out_a_ready = auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign coupler_to_bootrom_auto_fragmenter_out_d_valid = auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign coupler_to_bootrom_auto_fragmenter_out_d_bits_size = auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign coupler_to_bootrom_auto_fragmenter_out_d_bits_source = auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] assign coupler_to_bootrom_auto_fragmenter_out_d_bits_data = auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@52317.4] endmodule module TLMonitor_28( // @[:freechips.rocketchip.system.TinyConfig.fir@52375.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@52376.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@52377.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [9:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] input [9:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@52378.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@53512.4] wire _T_11; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@52399.6] wire [4:0] _T_15; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52405.6] wire [1:0] _T_16; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52406.6] wire [1:0] _T_17; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52407.6] wire [27:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@52408.6] wire [27:0] _T_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@52408.6] wire _T_19; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@52409.6] wire _T_21; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@52411.6] wire [1:0] _T_22; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@52412.6] wire [1:0] _T_24; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@52414.6] wire _T_25; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@52415.6] wire _T_26; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@52416.6] wire _T_27; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@52417.6] wire _T_28; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@52418.6] wire _T_30; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52420.6] wire _T_31; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52421.6] wire _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52423.6] wire _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52424.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@52425.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@52426.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@52427.6] wire _T_38; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52428.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52429.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52430.6] wire _T_41; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52431.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52432.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52433.6] wire _T_44; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52434.6] wire _T_45; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52435.6] wire _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52436.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52437.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52438.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52439.6] wire [3:0] _T_52; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52442.6] wire _T_71; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@52465.6] wire [27:0] _T_73; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@52468.8] wire [28:0] _T_74; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@52469.8] wire [28:0] _T_75; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@52470.8] wire [28:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@52471.8] wire _T_77; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@52472.8] wire _T_82; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52477.8] wire _T_87; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52490.8] wire _T_88; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52491.8] wire _T_91; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52498.8] wire _T_92; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52499.8] wire _T_94; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52505.8] wire _T_95; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52506.8] wire _T_96; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@52511.8] wire _T_98; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52513.8] wire _T_99; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52514.8] wire [3:0] _T_100; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@52519.8] wire _T_101; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@52520.8] wire _T_103; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52522.8] wire _T_104; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52523.8] wire _T_105; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@52528.8] wire _T_107; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52530.8] wire _T_108; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52531.8] wire _T_109; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@52537.6] wire _T_138; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@52591.8] wire _T_140; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52593.8] wire _T_141; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52594.8] wire _T_151; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@52617.6] wire _T_153; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@52620.8] wire _T_161; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@52628.8] wire _T_164; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52631.8] wire _T_165; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52632.8] wire _T_172; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@52651.8] wire _T_174; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52653.8] wire _T_175; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52654.8] wire _T_176; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@52659.8] wire _T_178; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52661.8] wire _T_179; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52662.8] wire _T_184; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@52676.6] wire _T_213; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@52727.6] wire [3:0] _T_238; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@52769.8] wire [3:0] _T_239; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@52770.8] wire _T_240; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@52771.8] wire _T_242; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52773.8] wire _T_243; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52774.8] wire _T_244; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@52780.6] wire _T_262; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@52811.8] wire _T_264; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52813.8] wire _T_265; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52814.8] wire _T_270; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@52828.6] wire _T_288; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@52859.8] wire _T_290; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52861.8] wire _T_291; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52862.8] wire _T_296; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@52876.6] wire _T_322; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@52926.6] wire _T_324; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52928.6] wire _T_325; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52929.6] wire _T_332; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@52940.6] wire _T_336; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@52946.6] wire _T_338; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52949.8] wire _T_339; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52950.8] wire _T_340; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@52955.8] wire _T_342; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52957.8] wire _T_343; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52958.8] wire _T_356; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@52988.6] wire _T_384; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@53046.6] wire _T_413; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@53105.6] wire _T_430; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@53140.6] wire _T_448; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@53176.6] wire _T_477; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@53236.4] reg _T_486; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@53245.4] reg [31:0] _RAND_0; wire _T_488; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53247.4] wire _T_489; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53248.4] reg [2:0] _T_497; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@53259.4] reg [31:0] _RAND_1; reg [2:0] _T_498; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@53260.4] reg [31:0] _RAND_2; reg [1:0] _T_499; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@53261.4] reg [31:0] _RAND_3; reg [9:0] _T_500; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@53262.4] reg [31:0] _RAND_4; reg [27:0] _T_501; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@53263.4] reg [31:0] _RAND_5; wire _T_502; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@53264.4] wire _T_503; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@53265.4] wire _T_504; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@53267.6] wire _T_506; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53269.6] wire _T_507; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53270.6] wire _T_508; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@53275.6] wire _T_510; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53277.6] wire _T_511; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53278.6] wire _T_512; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@53283.6] wire _T_514; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53285.6] wire _T_515; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53286.6] wire _T_516; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@53291.6] wire _T_518; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53293.6] wire _T_519; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53294.6] wire _T_520; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@53299.6] wire _T_522; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53301.6] wire _T_523; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53302.6] wire _T_525; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@53309.4] wire _T_526; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@53317.4] reg _T_534; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@53325.4] reg [31:0] _RAND_6; wire _T_536; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53327.4] wire _T_537; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53328.4] reg [2:0] _T_545; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@53339.4] reg [31:0] _RAND_7; reg [1:0] _T_547; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@53341.4] reg [31:0] _RAND_8; reg [9:0] _T_548; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@53342.4] reg [31:0] _RAND_9; wire _T_551; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@53345.4] wire _T_552; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@53346.4] wire _T_553; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@53348.6] wire _T_555; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53350.6] wire _T_556; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53351.6] wire _T_561; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@53364.6] wire _T_563; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53366.6] wire _T_564; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53367.6] wire _T_565; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@53372.6] wire _T_567; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53374.6] wire _T_568; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53375.6] wire _T_578; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@53398.4] reg [575:0] _T_579; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@53407.4] reg [575:0] _RAND_10; reg _T_589; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@53417.4] reg [31:0] _RAND_11; wire _T_591; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53419.4] wire _T_592; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53420.4] reg _T_608; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@53439.4] reg [31:0] _RAND_12; wire _T_610; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53441.4] wire _T_611; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53442.4] wire _T_621; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@53457.4] wire [1023:0] _T_623; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@53460.6] wire [575:0] _T_624; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@53462.6] wire _T_625; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@53463.6] wire _T_626; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@53464.6] wire _T_628; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53466.6] wire _T_629; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53467.6] wire [1023:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@53459.4] wire _T_633; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@53478.4] wire _T_635; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@53480.4] wire _T_636; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@53481.4] wire [1023:0] _T_637; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@53483.6] wire [575:0] _T_619; // @[:freechips.rocketchip.system.TinyConfig.fir@53453.4 :freechips.rocketchip.system.TinyConfig.fir@53455.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@53461.6] wire [575:0] _T_638; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@53485.6] wire [575:0] _T_639; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@53486.6] wire _T_640; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@53487.6] wire _T_642; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53489.6] wire _T_643; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53490.6] wire [1023:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@53482.4] wire [575:0] _T_630; // @[:freechips.rocketchip.system.TinyConfig.fir@53473.4 :freechips.rocketchip.system.TinyConfig.fir@53475.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@53484.6] wire _T_644; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@53496.4] wire _T_645; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@53497.4] wire _T_646; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@53498.4] wire _T_647; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@53499.4] wire _T_649; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53501.4] wire _T_650; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53502.4] wire [575:0] _T_651; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@53507.4] wire [575:0] _T_652; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@53508.4] wire [575:0] _T_653; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@53509.4] reg [31:0] _T_654; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@53511.4] reg [31:0] _RAND_13; wire _T_655; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@53514.4] wire _T_656; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@53515.4] wire _T_657; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@53516.4] wire _T_658; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@53517.4] wire _T_659; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@53518.4] wire _T_660; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@53519.4] wire _T_662; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53521.4] wire _T_663; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53522.4] wire [31:0] _T_665; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@53528.4] wire _T_668; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@53532.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52479.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@52551.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52634.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@52693.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@52744.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@52794.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@52842.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@52890.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52952.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@52994.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@53052.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@53111.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@53146.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@53182.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@53512.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@52399.6] assign _T_15 = 5'h3 << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@52405.6] assign _T_16 = _T_15[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@52406.6] assign _T_17 = ~ _T_16; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@52407.6] assign _GEN_18 = {{26'd0}, _T_17}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@52408.6] assign _T_18 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@52408.6] assign _T_19 = _T_18 == 28'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@52409.6] assign _T_21 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@52411.6] assign _T_22 = 2'h1 << _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@52412.6] assign _T_24 = _T_22 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@52414.6] assign _T_25 = io_in_a_bits_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@52415.6] assign _T_26 = _T_24[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@52416.6] assign _T_27 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@52417.6] assign _T_28 = _T_27 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@52418.6] assign _T_30 = _T_26 & _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52420.6] assign _T_31 = _T_25 | _T_30; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52421.6] assign _T_33 = _T_26 & _T_27; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52423.6] assign _T_34 = _T_25 | _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52424.6] assign _T_35 = _T_24[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@52425.6] assign _T_36 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@52426.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@52427.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52428.6] assign _T_39 = _T_35 & _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52429.6] assign _T_40 = _T_31 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52430.6] assign _T_41 = _T_28 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52431.6] assign _T_42 = _T_35 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52432.6] assign _T_43 = _T_31 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52433.6] assign _T_44 = _T_27 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52434.6] assign _T_45 = _T_35 & _T_44; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52435.6] assign _T_46 = _T_34 | _T_45; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52436.6] assign _T_47 = _T_27 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@52437.6] assign _T_48 = _T_35 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@52438.6] assign _T_49 = _T_34 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@52439.6] assign _T_52 = {_T_49,_T_46,_T_43,_T_40}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@52442.6] assign _T_71 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@52465.6] assign _T_73 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@52468.8] assign _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@52469.8] assign _T_75 = $signed(_T_74) & $signed(-29'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@52470.8] assign _T_76 = $signed(_T_75); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@52471.8] assign _T_77 = $signed(_T_76) == $signed(29'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@52472.8] assign _T_82 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52477.8] assign _T_87 = _T_11 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52490.8] assign _T_88 = _T_87 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52491.8] assign _T_91 = _T_25 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52498.8] assign _T_92 = _T_91 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52499.8] assign _T_94 = _T_19 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52505.8] assign _T_95 = _T_94 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52506.8] assign _T_96 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@52511.8] assign _T_98 = _T_96 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52513.8] assign _T_99 = _T_98 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52514.8] assign _T_100 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@52519.8] assign _T_101 = _T_100 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@52520.8] assign _T_103 = _T_101 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52522.8] assign _T_104 = _T_103 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52523.8] assign _T_105 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@52528.8] assign _T_107 = _T_105 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52530.8] assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52531.8] assign _T_109 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@52537.6] assign _T_138 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@52591.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52593.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52594.8] assign _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@52617.6] assign _T_153 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@52620.8] assign _T_161 = _T_153 & _T_77; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@52628.8] assign _T_164 = _T_161 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52631.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52632.8] assign _T_172 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@52651.8] assign _T_174 = _T_172 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52653.8] assign _T_175 = _T_174 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52654.8] assign _T_176 = io_in_a_bits_mask == _T_52; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@52659.8] assign _T_178 = _T_176 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52661.8] assign _T_179 = _T_178 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52662.8] assign _T_184 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@52676.6] assign _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@52727.6] assign _T_238 = ~ _T_52; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@52769.8] assign _T_239 = io_in_a_bits_mask & _T_238; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@52770.8] assign _T_240 = _T_239 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@52771.8] assign _T_242 = _T_240 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52773.8] assign _T_243 = _T_242 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52774.8] assign _T_244 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@52780.6] assign _T_262 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@52811.8] assign _T_264 = _T_262 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52813.8] assign _T_265 = _T_264 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52814.8] assign _T_270 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@52828.6] assign _T_288 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@52859.8] assign _T_290 = _T_288 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52861.8] assign _T_291 = _T_290 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52862.8] assign _T_296 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@52876.6] assign _T_322 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@52926.6] assign _T_324 = _T_322 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52928.6] assign _T_325 = _T_324 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52929.6] assign _T_332 = io_in_d_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@52940.6] assign _T_336 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@52946.6] assign _T_338 = _T_332 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52949.8] assign _T_339 = _T_338 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52950.8] assign _T_340 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@52955.8] assign _T_342 = _T_340 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52957.8] assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52958.8] assign _T_356 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@52988.6] assign _T_384 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@53046.6] assign _T_413 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@53105.6] assign _T_430 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@53140.6] assign _T_448 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@53176.6] assign _T_477 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@53236.4] assign _T_488 = _T_486 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53247.4] assign _T_489 = _T_486 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53248.4] assign _T_502 = _T_489 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@53264.4] assign _T_503 = io_in_a_valid & _T_502; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@53265.4] assign _T_504 = io_in_a_bits_opcode == _T_497; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@53267.6] assign _T_506 = _T_504 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53269.6] assign _T_507 = _T_506 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53270.6] assign _T_508 = io_in_a_bits_param == _T_498; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@53275.6] assign _T_510 = _T_508 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53277.6] assign _T_511 = _T_510 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53278.6] assign _T_512 = io_in_a_bits_size == _T_499; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@53283.6] assign _T_514 = _T_512 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53285.6] assign _T_515 = _T_514 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53286.6] assign _T_516 = io_in_a_bits_source == _T_500; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@53291.6] assign _T_518 = _T_516 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53293.6] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53294.6] assign _T_520 = io_in_a_bits_address == _T_501; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@53299.6] assign _T_522 = _T_520 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53301.6] assign _T_523 = _T_522 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53302.6] assign _T_525 = _T_477 & _T_489; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@53309.4] assign _T_526 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@53317.4] assign _T_536 = _T_534 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53327.4] assign _T_537 = _T_534 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53328.4] assign _T_551 = _T_537 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@53345.4] assign _T_552 = io_in_d_valid & _T_551; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@53346.4] assign _T_553 = io_in_d_bits_opcode == _T_545; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@53348.6] assign _T_555 = _T_553 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53350.6] assign _T_556 = _T_555 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53351.6] assign _T_561 = io_in_d_bits_size == _T_547; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@53364.6] assign _T_563 = _T_561 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53366.6] assign _T_564 = _T_563 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53367.6] assign _T_565 = io_in_d_bits_source == _T_548; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@53372.6] assign _T_567 = _T_565 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53374.6] assign _T_568 = _T_567 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53375.6] assign _T_578 = _T_526 & _T_537; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@53398.4] assign _T_591 = _T_589 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53419.4] assign _T_592 = _T_589 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53420.4] assign _T_610 = _T_608 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@53441.4] assign _T_611 = _T_608 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@53442.4] assign _T_621 = _T_477 & _T_592; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@53457.4] assign _T_623 = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@53460.6] assign _T_624 = _T_579 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@53462.6] assign _T_625 = _T_624[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@53463.6] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@53464.6] assign _T_628 = _T_626 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53466.6] assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53467.6] assign _GEN_15 = _T_621 ? _T_623 : 1024'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@53459.4] assign _T_633 = _T_526 & _T_611; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@53478.4] assign _T_635 = _T_336 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@53480.4] assign _T_636 = _T_633 & _T_635; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@53481.4] assign _T_637 = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@53483.6] assign _T_619 = _GEN_15[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@53453.4 :freechips.rocketchip.system.TinyConfig.fir@53455.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@53461.6] assign _T_638 = _T_619 | _T_579; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@53485.6] assign _T_639 = _T_638 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@53486.6] assign _T_640 = _T_639[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@53487.6] assign _T_642 = _T_640 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53489.6] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53490.6] assign _GEN_16 = _T_636 ? _T_637 : 1024'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@53482.4] assign _T_630 = _GEN_16[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@53473.4 :freechips.rocketchip.system.TinyConfig.fir@53475.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@53484.6] assign _T_644 = _T_619 != _T_630; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@53496.4] assign _T_645 = _T_619 != 576'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@53497.4] assign _T_646 = _T_645 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@53498.4] assign _T_647 = _T_644 | _T_646; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@53499.4] assign _T_649 = _T_647 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53501.4] assign _T_650 = _T_649 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53502.4] assign _T_651 = _T_579 | _T_619; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@53507.4] assign _T_652 = ~ _T_630; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@53508.4] assign _T_653 = _T_651 & _T_652; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@53509.4] assign _T_655 = _T_579 != 576'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@53514.4] assign _T_656 = _T_655 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@53515.4] assign _T_657 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@53516.4] assign _T_658 = _T_656 | _T_657; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@53517.4] assign _T_659 = _T_654 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@53518.4] assign _T_660 = _T_658 | _T_659; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@53519.4] assign _T_662 = _T_660 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53521.4] assign _T_663 = _T_662 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53522.4] assign _T_665 = _T_654 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@53528.4] assign _T_668 = _T_477 | _T_526; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@53532.4] assign _GEN_19 = io_in_a_valid & _T_71; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52479.10] assign _GEN_35 = io_in_a_valid & _T_109; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@52551.10] assign _GEN_53 = io_in_a_valid & _T_151; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52634.10] assign _GEN_65 = io_in_a_valid & _T_184; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@52693.10] assign _GEN_75 = io_in_a_valid & _T_213; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@52744.10] assign _GEN_85 = io_in_a_valid & _T_244; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@52794.10] assign _GEN_95 = io_in_a_valid & _T_270; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@52842.10] assign _GEN_105 = io_in_a_valid & _T_296; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@52890.10] assign _GEN_115 = io_in_d_valid & _T_336; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52952.10] assign _GEN_119 = io_in_d_valid & _T_356; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@52994.10] assign _GEN_125 = io_in_d_valid & _T_384; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@53052.10] assign _GEN_131 = io_in_d_valid & _T_413; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@53111.10] assign _GEN_133 = io_in_d_valid & _T_430; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@53146.10] assign _GEN_135 = io_in_d_valid & _T_448; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@53182.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_486 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_497 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_498 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_499 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_500 = _RAND_4[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_501 = _RAND_5[27:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_534 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_545 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_547 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_548 = _RAND_9[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {18{`RANDOM}}; _T_579 = _RAND_10[575:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_589 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_608 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_654 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_486 <= 1'h0; end else begin if (_T_477) begin if (_T_489) begin _T_486 <= 1'h0; end else begin _T_486 <= _T_488; end end end if (_T_525) begin _T_497 <= io_in_a_bits_opcode; end if (_T_525) begin _T_498 <= io_in_a_bits_param; end if (_T_525) begin _T_499 <= io_in_a_bits_size; end if (_T_525) begin _T_500 <= io_in_a_bits_source; end if (_T_525) begin _T_501 <= io_in_a_bits_address; end if (reset) begin _T_534 <= 1'h0; end else begin if (_T_526) begin if (_T_537) begin _T_534 <= 1'h0; end else begin _T_534 <= _T_536; end end end if (_T_578) begin _T_545 <= io_in_d_bits_opcode; end if (_T_578) begin _T_547 <= io_in_d_bits_size; end if (_T_578) begin _T_548 <= io_in_d_bits_source; end if (reset) begin _T_579 <= 576'h0; end else begin _T_579 <= _T_653; end if (reset) begin _T_589 <= 1'h0; end else begin if (_T_477) begin if (_T_592) begin _T_589 <= 1'h0; end else begin _T_589 <= _T_591; end end end if (reset) begin _T_608 <= 1'h0; end else begin if (_T_526) begin if (_T_611) begin _T_608 <= 1'h0; end else begin _T_608 <= _T_610; end end end if (reset) begin _T_654 <= 32'h0; end else begin if (_T_668) begin _T_654 <= 32'h0; end else begin _T_654 <= _T_665; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52479.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@52480.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:341:15)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@52486.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@52487.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_88) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@52494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:341:15)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52501.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_92) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@52502.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52508.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_95) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@52509.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:341:15)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52516.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_99) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@52517.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52525.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@52526.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:341:15)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52533.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_108) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@52534.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@52551.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@52552.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:341:15)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@52558.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@52559.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@52565.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_88) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@52566.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:341:15)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@52573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_92) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@52574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@52580.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_95) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@52581.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:341:15)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@52588.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_99) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@52589.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:341:15)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52596.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@52597.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@52605.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_104) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@52606.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:341:15)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@52613.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_108) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@52614.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52634.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@52635.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@52641.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_88) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@52642.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@52648.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_95) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@52649.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:341:15)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52656.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_175) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@52657.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52664.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_179) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@52665.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:341:15)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@52672.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_108) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@52673.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@52693.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@52694.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@52700.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_88) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@52701.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@52707.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_95) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@52708.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:341:15)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@52715.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_175) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@52716.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@52723.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_179) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@52724.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@52744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@52745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@52751.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_88) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@52752.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@52758.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_95) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@52759.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:341:15)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@52766.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_175) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@52767.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_243) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_243) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@52777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@52794.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_82) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@52795.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@52801.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_88) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@52802.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@52808.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_95) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@52809.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_265) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:341:15)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52816.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_265) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@52817.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@52824.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_179) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@52825.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@52842.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_82) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@52843.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@52849.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_88) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@52850.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@52856.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_95) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@52857.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_291) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:341:15)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52864.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_291) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@52865.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@52872.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_179) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@52873.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Plic.scala:341:15)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@52890.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_82) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@52891.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@52897.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_88) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@52898.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:341:15)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@52904.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_95) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@52905.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:341:15)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@52912.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_179) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@52913.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:341:15)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@52920.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_108) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@52921.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_325) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:341:15)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52931.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_325) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@52932.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52952.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_339) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@52953.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:341:15)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52960.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_343) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@52961.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@52994.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_339) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@52995.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:341:15)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@53001.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_82) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@53002.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:341:15)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@53009.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_343) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@53010.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@53052.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_339) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@53053.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:341:15)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@53059.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_82) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@53060.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:341:15)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@53067.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_343) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@53068.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@53111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_339) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@53112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@53146.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_339) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@53147.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:341:15)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@53182.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_339) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@53183.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_507) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53272.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_507) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@53273.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_511) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53280.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_511) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@53281.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_515) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53288.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_515) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@53289.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53296.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_519) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@53297.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_523) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53304.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_523) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@53305.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_556) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53353.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_556) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@53354.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_564) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53369.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_564) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@53370.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_568) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:341:15)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53377.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_568) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@53378.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_629) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:341:15)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53469.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_629) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@53470.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_636 & _T_643) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:341:15)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53492.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_636 & _T_643) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@53493.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_650) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:341:15)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53504.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_650) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@53505.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_663) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Plic.scala:341:15)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53524.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_663) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@53525.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module LevelGateway( // @[:freechips.rocketchip.system.TinyConfig.fir@53537.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@53538.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@53539.4] input io_interrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@53540.4] output io_plic_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@53540.4] input io_plic_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@53540.4] input io_plic_complete // @[:freechips.rocketchip.system.TinyConfig.fir@53540.4] ); reg inFlight; // @[Plic.scala 32:21:freechips.rocketchip.system.TinyConfig.fir@53545.4] reg [31:0] _RAND_0; wire _T; // @[Plic.scala 33:22:freechips.rocketchip.system.TinyConfig.fir@53546.4] wire _T_1; // @[Plic.scala 35:36:freechips.rocketchip.system.TinyConfig.fir@53553.4] assign _T = io_interrupt & io_plic_ready; // @[Plic.scala 33:22:freechips.rocketchip.system.TinyConfig.fir@53546.4] assign _T_1 = inFlight == 1'h0; // @[Plic.scala 35:36:freechips.rocketchip.system.TinyConfig.fir@53553.4] assign io_plic_valid = io_interrupt & _T_1; // @[Plic.scala 35:17:freechips.rocketchip.system.TinyConfig.fir@53555.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; inFlight = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin inFlight <= 1'h0; end else begin if (io_plic_complete) begin inFlight <= 1'h0; end else begin if (_T) begin inFlight <= 1'h1; end end end end endmodule module PLICFanIn( // @[:freechips.rocketchip.system.TinyConfig.fir@53577.2] input [1:0] io_prio_0, // @[:freechips.rocketchip.system.TinyConfig.fir@53580.4] input [1:0] io_prio_1, // @[:freechips.rocketchip.system.TinyConfig.fir@53580.4] input [1:0] io_ip, // @[:freechips.rocketchip.system.TinyConfig.fir@53580.4] output [1:0] io_dev, // @[:freechips.rocketchip.system.TinyConfig.fir@53580.4] output [1:0] io_max // @[:freechips.rocketchip.system.TinyConfig.fir@53580.4] ); wire _T; // @[Plic.scala 331:59:freechips.rocketchip.system.TinyConfig.fir@53586.4] wire _T_1; // @[Plic.scala 331:59:freechips.rocketchip.system.TinyConfig.fir@53587.4] wire [2:0] effectivePriority_1; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53588.4] wire [2:0] effectivePriority_2; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53589.4] wire _T_2; // @[Plic.scala 327:20:freechips.rocketchip.system.TinyConfig.fir@53590.4] wire [2:0] _T_4; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@53592.4] wire _T_5; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@53593.4] wire _T_6; // @[Plic.scala 327:20:freechips.rocketchip.system.TinyConfig.fir@53594.4] wire [2:0] maxPri; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@53596.4] assign _T = io_ip[0]; // @[Plic.scala 331:59:freechips.rocketchip.system.TinyConfig.fir@53586.4] assign _T_1 = io_ip[1]; // @[Plic.scala 331:59:freechips.rocketchip.system.TinyConfig.fir@53587.4] assign effectivePriority_1 = {_T,io_prio_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53588.4] assign effectivePriority_2 = {_T_1,io_prio_1}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53589.4] assign _T_2 = 3'h4 >= effectivePriority_1; // @[Plic.scala 327:20:freechips.rocketchip.system.TinyConfig.fir@53590.4] assign _T_4 = _T_2 ? 3'h4 : effectivePriority_1; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@53592.4] assign _T_5 = _T_2 ? 1'h0 : 1'h1; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@53593.4] assign _T_6 = _T_4 >= effectivePriority_2; // @[Plic.scala 327:20:freechips.rocketchip.system.TinyConfig.fir@53594.4] assign maxPri = _T_6 ? _T_4 : effectivePriority_2; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@53596.4] assign io_dev = _T_6 ? {{1'd0}, _T_5} : 2'h2; // @[Plic.scala 334:10:freechips.rocketchip.system.TinyConfig.fir@53599.4] assign io_max = maxPri[1:0]; // @[Plic.scala 333:10:freechips.rocketchip.system.TinyConfig.fir@53598.4] endmodule module Queue_37( // @[:freechips.rocketchip.system.TinyConfig.fir@53601.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@53602.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@53603.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input io_enq_bits_read, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input [23:0] io_enq_bits_index, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input [11:0] io_enq_bits_extra, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output io_deq_bits_read, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output [23:0] io_deq_bits_index, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] output [11:0] io_deq_bits_extra // @[:freechips.rocketchip.system.TinyConfig.fir@53604.4] ); reg _T_read [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _RAND_0; wire _T_read__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_read__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_read__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_read__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_read__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_read__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [23:0] _T_index [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _RAND_1; wire [23:0] _T_index__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_index__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire [23:0] _T_index__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_index__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_index__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_index__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _T_data [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _RAND_2; wire [31:0] _T_data__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_data__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [3:0] _T_mask [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _RAND_3; wire [3:0] _T_mask__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_mask__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [11:0] _T_extra [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg [31:0] _RAND_4; wire [11:0] _T_extra__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_extra__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire [11:0] _T_extra__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_extra__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_extra__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] wire _T_extra__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@53607.4] reg [31:0] _RAND_5; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@53609.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@53612.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@53615.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@53628.4] assign _T_read__T_14_addr = 1'h0; assign _T_read__T_14_data = _T_read[_T_read__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] assign _T_read__T_10_data = io_enq_bits_read; assign _T_read__T_10_addr = 1'h0; assign _T_read__T_10_mask = 1'h1; assign _T_read__T_10_en = io_enq_ready & io_enq_valid; assign _T_index__T_14_addr = 1'h0; assign _T_index__T_14_data = _T_index[_T_index__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] assign _T_index__T_10_data = io_enq_bits_index; assign _T_index__T_10_addr = 1'h0; assign _T_index__T_10_mask = 1'h1; assign _T_index__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_14_addr = 1'h0; assign _T_data__T_14_data = _T_data[_T_data__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = 1'h0; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_14_addr = 1'h0; assign _T_mask__T_14_data = _T_mask[_T_mask__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = 1'h0; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_extra__T_14_addr = 1'h0; assign _T_extra__T_14_data = _T_extra[_T_extra__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] assign _T_extra__T_10_data = io_enq_bits_extra; assign _T_extra__T_10_addr = 1'h0; assign _T_extra__T_10_mask = 1'h1; assign _T_extra__T_10_en = io_enq_ready & io_enq_valid; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@53609.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@53612.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@53615.4] assign _T_11 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@53628.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@53635.4] assign io_deq_valid = _T_3 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@53633.4] assign io_deq_bits_read = _T_read__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@53641.4] assign io_deq_bits_index = _T_index__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@53640.4] assign io_deq_bits_data = _T_data__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@53639.4] assign io_deq_bits_mask = _T_mask__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@53638.4] assign io_deq_bits_extra = _T_extra__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@53637.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_read[initvar] = _RAND_0[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_index[initvar] = _RAND_1[23:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_data[initvar] = _RAND_2[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_mask[initvar] = _RAND_3[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_extra[initvar] = _RAND_4[11:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_read__T_10_en & _T_read__T_10_mask) begin _T_read[_T_read__T_10_addr] <= _T_read__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] end if(_T_index__T_10_en & _T_index__T_10_mask) begin _T_index[_T_index__T_10_addr] <= _T_index__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] end if(_T_extra__T_10_en & _T_extra__T_10_mask) begin _T_extra[_T_extra__T_10_addr] <= _T_extra__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@53606.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin _T_1 <= _T_6; end end end endmodule module TLPLIC( // @[:freechips.rocketchip.system.TinyConfig.fir@53649.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@53650.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@53651.4] input auto_int_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input auto_int_in_1, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [9:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output [9:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] output [31:0] auto_in_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@53652.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [9:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire [9:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] wire LevelGateway_clock; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_reset; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_io_interrupt; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_io_plic_valid; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_io_plic_ready; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_io_plic_complete; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] wire LevelGateway_1_clock; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire LevelGateway_1_reset; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire LevelGateway_1_io_interrupt; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire LevelGateway_1_io_plic_valid; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire LevelGateway_1_io_plic_ready; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire LevelGateway_1_io_plic_complete; // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] wire [1:0] PLICFanIn_io_prio_0; // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] wire [1:0] PLICFanIn_io_prio_1; // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] wire [1:0] PLICFanIn_io_ip; // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] wire [1:0] PLICFanIn_io_dev; // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] wire [1:0] PLICFanIn_io_max; // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_enq_bits_read; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [23:0] Queue_io_enq_bits_index; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [11:0] Queue_io_enq_bits_extra; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire Queue_io_deq_bits_read; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [23:0] Queue_io_deq_bits_index; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] wire [11:0] Queue_io_deq_bits_extra; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] reg [1:0] priority_0; // @[Plic.scala 151:31:freechips.rocketchip.system.TinyConfig.fir@53725.4] reg [31:0] _RAND_0; reg [1:0] priority_1; // @[Plic.scala 151:31:freechips.rocketchip.system.TinyConfig.fir@53725.4] reg [31:0] _RAND_1; reg [1:0] threshold_0; // @[Plic.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@53726.4] reg [31:0] _RAND_2; reg pending_0; // @[Plic.scala 156:22:freechips.rocketchip.system.TinyConfig.fir@53731.4] reg [31:0] _RAND_3; reg pending_1; // @[Plic.scala 156:22:freechips.rocketchip.system.TinyConfig.fir@53731.4] reg [31:0] _RAND_4; reg [1:0] enables_0_0; // @[Plic.scala 162:26:freechips.rocketchip.system.TinyConfig.fir@53732.4] reg [31:0] _RAND_5; wire [2:0] enableVec0_0; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53736.4] reg [1:0] maxDevs_0; // @[Plic.scala 169:22:freechips.rocketchip.system.TinyConfig.fir@53740.4] reg [31:0] _RAND_6; wire [1:0] pendingUInt; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53741.4] reg [1:0] _T_16; // @[Plic.scala 176:41:freechips.rocketchip.system.TinyConfig.fir@53750.4] reg [31:0] _RAND_7; wire _T_611; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54538.4] wire _T_612; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54539.4] wire _T_398; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54207.4] wire _T_390; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54199.4] wire _T_389; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54198.4] wire _T_379; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54188.4] wire [3:0] _T_405; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@54214.4] wire [15:0] _T_423; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@54232.4] wire _T_433; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54242.4] wire _T_659; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54614.4] wire [23:0] _T_58; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53844.4] wire _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53848.4] wire _T_660; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54615.4] wire _T_93; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53883.4] wire [7:0] _T_101; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53891.4] wire _T_92; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53882.4] wire [7:0] _T_99; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53889.4] wire _T_91; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53881.4] wire [7:0] _T_97; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53887.4] wire _T_90; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53880.4] wire [7:0] _T_95; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53885.4] wire [31:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53894.4] wire _T_183; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53973.4] wire claimer_0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53977.4] wire _T_19; // @[Plic.scala 227:46:freechips.rocketchip.system.TinyConfig.fir@53757.4] wire _T_20; // @[Plic.scala 227:28:freechips.rocketchip.system.TinyConfig.fir@53758.4] wire _T_21; // @[Plic.scala 227:58:freechips.rocketchip.system.TinyConfig.fir@53759.4] wire _T_23; // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53761.4] wire _T_24; // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53762.4] wire [1:0] claiming; // @[Plic.scala 228:49:freechips.rocketchip.system.TinyConfig.fir@53767.4] wire [3:0] _T_26; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@53769.4] wire [2:0] _T_27; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@53770.4] wire claimedDevs_1; // @[Plic.scala 229:58:freechips.rocketchip.system.TinyConfig.fir@53772.4] wire claimedDevs_2; // @[Plic.scala 229:58:freechips.rocketchip.system.TinyConfig.fir@53773.4] wire _T_32; // @[Plic.scala 233:15:freechips.rocketchip.system.TinyConfig.fir@53781.4] wire _T_33; // @[Plic.scala 233:34:freechips.rocketchip.system.TinyConfig.fir@53783.6] wire _T_35; // @[Plic.scala 233:15:freechips.rocketchip.system.TinyConfig.fir@53788.4] wire _T_36; // @[Plic.scala 233:34:freechips.rocketchip.system.TinyConfig.fir@53790.6] wire _T_697; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54683.4] wire _T_698; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54684.4] wire _T_745; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54759.4] wire _T_746; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54760.4] wire _T_185; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53975.4] wire _T_189; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53979.4] wire [31:0] _T_190; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53981.4] wire [1:0] completerDev; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@53991.4] wire [2:0] _T_197; // @[Plic.scala 277:51:freechips.rocketchip.system.TinyConfig.fir@53993.4] wire _T_198; // @[Plic.scala 277:51:freechips.rocketchip.system.TinyConfig.fir@53994.4] wire completer_0; // @[Plic.scala 277:35:freechips.rocketchip.system.TinyConfig.fir@53995.4] wire _T_38; // @[Plic.scala 244:50:freechips.rocketchip.system.TinyConfig.fir@53796.4] wire _T_39; // @[Plic.scala 244:30:freechips.rocketchip.system.TinyConfig.fir@53797.4] wire _T_40; // @[Plic.scala 244:62:freechips.rocketchip.system.TinyConfig.fir@53798.4] wire _T_42; // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53800.4] wire _T_43; // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53801.4] wire [3:0] _T_45; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@53809.4] wire [2:0] _T_46; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@53810.4] wire [2:0] completedDevs; // @[Plic.scala 246:28:freechips.rocketchip.system.TinyConfig.fir@53811.4] wire [25:0] _T_52; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@53821.4] wire _T_66; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53852.4] wire [2:0] _T_175; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53965.4] wire _T_192; // @[Plic.scala 274:33:freechips.rocketchip.system.TinyConfig.fir@53983.4] wire _T_194; // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53985.4] wire _T_195; // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53986.4] wire [31:0] _T_208; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54005.4] wire [1:0] _T_214; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54011.4] wire _T_217; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54014.4] wire _T_425; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54234.4] wire _T_705; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54695.4] wire _T_706; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54696.4] wire _T_221; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54018.4] wire [1:0] _T_222; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54019.4] wire _T_424; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54233.4] wire _T_700; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54687.4] wire _T_701; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54688.4] wire _T_244; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54044.4] wire _T_432; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54241.4] wire _T_740; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54750.4] wire _T_741; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54751.4] wire _T_267; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54070.4] wire [2:0] _T_301; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@54107.4] wire [31:0] _T_302; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54108.4] wire _T_428; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54237.4] wire _T_720; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54720.4] wire _T_721; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54721.4] wire [1:0] _T_331; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54137.4] wire _T_334; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54140.4] wire _T_338; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54144.4] wire [1:0] _T_339; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54145.4] wire _T_789; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54841.4] wire _T_790; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54846.6] wire _T_791; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54851.8] wire _T_792; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54856.10] wire _T_793; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54861.12] wire _T_794; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54866.14] wire _GEN_70; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54867.14] wire _GEN_71; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54862.12] wire _GEN_72; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54857.10] wire _GEN_73; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54852.8] wire _GEN_74; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54847.6] wire _GEN_75; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@54842.4] wire [31:0] _GEN_76; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54899.14] wire [31:0] _GEN_77; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54894.12] wire [31:0] _GEN_78; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54889.10] wire [31:0] _GEN_79; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54884.8] wire [31:0] _GEN_80; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54879.6] wire [31:0] _GEN_81; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@54874.4] wire [11:0] _T_54_bits_extra; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53827.4 RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54904.4] wire _T_54_bits_read; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53827.4 RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54837.4] TLMonitor_28 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@53659.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); LevelGateway LevelGateway ( // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53715.4] .clock(LevelGateway_clock), .reset(LevelGateway_reset), .io_interrupt(LevelGateway_io_interrupt), .io_plic_valid(LevelGateway_io_plic_valid), .io_plic_ready(LevelGateway_io_plic_ready), .io_plic_complete(LevelGateway_io_plic_complete) ); LevelGateway LevelGateway_1 ( // @[Plic.scala 144:27:freechips.rocketchip.system.TinyConfig.fir@53720.4] .clock(LevelGateway_1_clock), .reset(LevelGateway_1_reset), .io_interrupt(LevelGateway_1_io_interrupt), .io_plic_valid(LevelGateway_1_io_plic_valid), .io_plic_ready(LevelGateway_1_io_plic_ready), .io_plic_complete(LevelGateway_1_io_plic_complete) ); PLICFanIn PLICFanIn ( // @[Plic.scala 172:25:freechips.rocketchip.system.TinyConfig.fir@53742.4] .io_prio_0(PLICFanIn_io_prio_0), .io_prio_1(PLICFanIn_io_prio_1), .io_ip(PLICFanIn_io_ip), .io_dev(PLICFanIn_io_dev), .io_max(PLICFanIn_io_max) ); Queue_37 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@53832.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_read(Queue_io_enq_bits_read), .io_enq_bits_index(Queue_io_enq_bits_index), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_extra(Queue_io_enq_bits_extra), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_read(Queue_io_deq_bits_read), .io_deq_bits_index(Queue_io_deq_bits_index), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_extra(Queue_io_deq_bits_extra) ); assign enableVec0_0 = {enables_0_0,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53736.4] assign pendingUInt = {pending_1,pending_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53741.4] assign _T_611 = Queue_io_deq_valid & auto_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54538.4] assign _T_612 = _T_611 & Queue_io_deq_bits_read; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54539.4] assign _T_398 = Queue_io_deq_bits_index[19]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54207.4] assign _T_390 = Queue_io_deq_bits_index[11]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54199.4] assign _T_389 = Queue_io_deq_bits_index[10]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54198.4] assign _T_379 = Queue_io_deq_bits_index[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54188.4] assign _T_405 = {_T_398,_T_390,_T_389,_T_379}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@54214.4] assign _T_423 = 16'h1 << _T_405; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@54232.4] assign _T_433 = _T_423[9]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54242.4] assign _T_659 = _T_612 & _T_433; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54614.4] assign _T_58 = Queue_io_deq_bits_index & 24'hf7f3fe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53844.4] assign _T_62 = _T_58 == 24'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53848.4] assign _T_660 = _T_659 & _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54615.4] assign _T_93 = Queue_io_deq_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53883.4] assign _T_101 = _T_93 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53891.4] assign _T_92 = Queue_io_deq_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53882.4] assign _T_99 = _T_92 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53889.4] assign _T_91 = Queue_io_deq_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53881.4] assign _T_97 = _T_91 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53887.4] assign _T_90 = Queue_io_deq_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@53880.4] assign _T_95 = _T_90 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@53885.4] assign _T_104 = {_T_101,_T_99,_T_97,_T_95}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53894.4] assign _T_183 = _T_104 != 32'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53973.4] assign claimer_0 = _T_660 & _T_183; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53977.4] assign _T_19 = claimer_0 - 1'h1; // @[Plic.scala 227:46:freechips.rocketchip.system.TinyConfig.fir@53757.4] assign _T_20 = claimer_0 & _T_19; // @[Plic.scala 227:28:freechips.rocketchip.system.TinyConfig.fir@53758.4] assign _T_21 = _T_20 == 1'h0; // @[Plic.scala 227:58:freechips.rocketchip.system.TinyConfig.fir@53759.4] assign _T_23 = _T_21 | reset; // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53761.4] assign _T_24 = _T_23 == 1'h0; // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53762.4] assign claiming = claimer_0 ? maxDevs_0 : 2'h0; // @[Plic.scala 228:49:freechips.rocketchip.system.TinyConfig.fir@53767.4] assign _T_26 = 4'h1 << claiming; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@53769.4] assign _T_27 = _T_26[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@53770.4] assign claimedDevs_1 = _T_27[1]; // @[Plic.scala 229:58:freechips.rocketchip.system.TinyConfig.fir@53772.4] assign claimedDevs_2 = _T_27[2]; // @[Plic.scala 229:58:freechips.rocketchip.system.TinyConfig.fir@53773.4] assign _T_32 = claimedDevs_1 | LevelGateway_io_plic_valid; // @[Plic.scala 233:15:freechips.rocketchip.system.TinyConfig.fir@53781.4] assign _T_33 = claimedDevs_1 == 1'h0; // @[Plic.scala 233:34:freechips.rocketchip.system.TinyConfig.fir@53783.6] assign _T_35 = claimedDevs_2 | LevelGateway_1_io_plic_valid; // @[Plic.scala 233:15:freechips.rocketchip.system.TinyConfig.fir@53788.4] assign _T_36 = claimedDevs_2 == 1'h0; // @[Plic.scala 233:34:freechips.rocketchip.system.TinyConfig.fir@53790.6] assign _T_697 = Queue_io_deq_bits_read == 1'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54683.4] assign _T_698 = _T_611 & _T_697; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54684.4] assign _T_745 = _T_698 & _T_433; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54759.4] assign _T_746 = _T_745 & _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54760.4] assign _T_185 = _T_104 == 32'hffffffff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53975.4] assign _T_189 = _T_746 & _T_185; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53979.4] assign _T_190 = Queue_io_deq_bits_data; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53981.4] assign completerDev = _T_190[1:0]; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@53991.4] assign _T_197 = enableVec0_0 >> completerDev; // @[Plic.scala 277:51:freechips.rocketchip.system.TinyConfig.fir@53993.4] assign _T_198 = _T_197[0]; // @[Plic.scala 277:51:freechips.rocketchip.system.TinyConfig.fir@53994.4] assign completer_0 = _T_189 & _T_198; // @[Plic.scala 277:35:freechips.rocketchip.system.TinyConfig.fir@53995.4] assign _T_38 = completer_0 - 1'h1; // @[Plic.scala 244:50:freechips.rocketchip.system.TinyConfig.fir@53796.4] assign _T_39 = completer_0 & _T_38; // @[Plic.scala 244:30:freechips.rocketchip.system.TinyConfig.fir@53797.4] assign _T_40 = _T_39 == 1'h0; // @[Plic.scala 244:62:freechips.rocketchip.system.TinyConfig.fir@53798.4] assign _T_42 = _T_40 | reset; // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53800.4] assign _T_43 = _T_42 == 1'h0; // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53801.4] assign _T_45 = 4'h1 << completerDev; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@53809.4] assign _T_46 = _T_45[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@53810.4] assign completedDevs = completer_0 ? _T_46 : 3'h0; // @[Plic.scala 246:28:freechips.rocketchip.system.TinyConfig.fir@53811.4] assign _T_52 = auto_in_a_bits_address[27:2]; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@53821.4] assign _T_66 = _T_58 == 24'h2; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53852.4] assign _T_175 = {pending_1,pending_0,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@53965.4] assign _T_192 = completerDev == completerDev; // @[Plic.scala 274:33:freechips.rocketchip.system.TinyConfig.fir@53983.4] assign _T_194 = _T_192 | reset; // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53985.4] assign _T_195 = _T_194 == 1'h0; // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53986.4] assign _T_208 = {{30'd0}, maxDevs_0}; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54005.4] assign _T_214 = _T_104[1:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54011.4] assign _T_217 = _T_214 == 2'h3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54014.4] assign _T_425 = _T_423[1]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54234.4] assign _T_705 = _T_698 & _T_425; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54695.4] assign _T_706 = _T_705 & _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54696.4] assign _T_221 = _T_706 & _T_217; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54018.4] assign _T_222 = Queue_io_deq_bits_data[1:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54019.4] assign _T_424 = _T_423[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54233.4] assign _T_700 = _T_698 & _T_424; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54687.4] assign _T_701 = _T_700 & _T_66; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54688.4] assign _T_244 = _T_701 & _T_217; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54044.4] assign _T_432 = _T_423[8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54241.4] assign _T_740 = _T_698 & _T_432; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54750.4] assign _T_741 = _T_740 & _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54751.4] assign _T_267 = _T_741 & _T_217; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54070.4] assign _T_301 = {1'h0,threshold_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@54107.4] assign _T_302 = {{29'd0}, _T_301}; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54108.4] assign _T_428 = _T_423[4]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54237.4] assign _T_720 = _T_698 & _T_428; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54720.4] assign _T_721 = _T_720 & _T_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54721.4] assign _T_331 = _T_104[2:1]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54137.4] assign _T_334 = _T_331 == 2'h3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54140.4] assign _T_338 = _T_721 & _T_334; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54144.4] assign _T_339 = Queue_io_deq_bits_data[2:1]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54145.4] assign _T_789 = 4'h0 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54841.4] assign _T_790 = 4'h1 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54846.6] assign _T_791 = 4'h2 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54851.8] assign _T_792 = 4'h4 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54856.10] assign _T_793 = 4'h8 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54861.12] assign _T_794 = 4'h9 == _T_405; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@54866.14] assign _GEN_70 = _T_794 ? _T_62 : 1'h1; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54867.14] assign _GEN_71 = _T_793 ? _T_62 : _GEN_70; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54862.12] assign _GEN_72 = _T_792 ? _T_62 : _GEN_71; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54857.10] assign _GEN_73 = _T_791 ? _T_62 : _GEN_72; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54852.8] assign _GEN_74 = _T_790 ? _T_62 : _GEN_73; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54847.6] assign _GEN_75 = _T_789 ? _T_66 : _GEN_74; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@54842.4] assign _GEN_76 = _T_794 ? _T_208 : 32'h0; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54899.14] assign _GEN_77 = _T_793 ? _T_302 : _GEN_76; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54894.12] assign _GEN_78 = _T_792 ? {{29'd0}, enableVec0_0} : _GEN_77; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54889.10] assign _GEN_79 = _T_791 ? {{29'd0}, _T_175} : _GEN_78; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54884.8] assign _GEN_80 = _T_790 ? {{30'd0}, priority_0} : _GEN_79; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@54879.6] assign _GEN_81 = _T_789 ? {{30'd0}, priority_1} : _GEN_80; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@54874.4] assign _T_54_bits_extra = Queue_io_deq_bits_extra; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53827.4 RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54904.4] assign _T_54_bits_read = Queue_io_deq_bits_read; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@53827.4 RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54837.4] assign auto_int_out_0 = _T_16 > threshold_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@53713.4] assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign auto_in_d_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign auto_in_d_bits_opcode = {{2'd0}, _T_54_bits_read}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign auto_in_d_bits_size = _T_54_bits_extra[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign auto_in_d_bits_source = _T_54_bits_extra[11:2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign auto_in_d_bits_data = _GEN_75 ? _GEN_81 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@53712.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@53661.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@53662.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_d_valid = Queue_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_54_bits_read}; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_d_bits_size = _T_54_bits_extra[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign TLMonitor_io_in_d_bits_source = _T_54_bits_extra[11:2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@53707.4] assign LevelGateway_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@53717.4] assign LevelGateway_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@53718.4] assign LevelGateway_io_interrupt = auto_int_in_0; // @[Plic.scala 145:28:freechips.rocketchip.system.TinyConfig.fir@53719.4] assign LevelGateway_io_plic_ready = pending_0 == 1'h0; // @[Plic.scala 232:15:freechips.rocketchip.system.TinyConfig.fir@53780.4] assign LevelGateway_io_plic_complete = completedDevs[1]; // @[Plic.scala 248:19:freechips.rocketchip.system.TinyConfig.fir@53815.4] assign LevelGateway_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@53722.4] assign LevelGateway_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@53723.4] assign LevelGateway_1_io_interrupt = auto_int_in_1; // @[Plic.scala 145:28:freechips.rocketchip.system.TinyConfig.fir@53724.4] assign LevelGateway_1_io_plic_ready = pending_1 == 1'h0; // @[Plic.scala 232:15:freechips.rocketchip.system.TinyConfig.fir@53787.4] assign LevelGateway_1_io_plic_complete = completedDevs[2]; // @[Plic.scala 248:19:freechips.rocketchip.system.TinyConfig.fir@53816.4] assign PLICFanIn_io_prio_0 = priority_0; // @[Plic.scala 173:21:freechips.rocketchip.system.TinyConfig.fir@53746.4] assign PLICFanIn_io_prio_1 = priority_1; // @[Plic.scala 173:21:freechips.rocketchip.system.TinyConfig.fir@53746.4] assign PLICFanIn_io_ip = enables_0_0 & pendingUInt; // @[Plic.scala 174:21:freechips.rocketchip.system.TinyConfig.fir@53748.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@53833.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@53834.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@53835.4] assign Queue_io_enq_bits_read = auto_in_a_bits_opcode == 3'h4; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@53840.4] assign Queue_io_enq_bits_index = _T_52[23:0]; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@53839.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@53838.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@53837.4] assign Queue_io_enq_bits_extra = {auto_in_a_bits_source,auto_in_a_bits_size}; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@53836.4] assign Queue_io_deq_ready = auto_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@54834.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; priority_0 = _RAND_0[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; priority_1 = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; threshold_0 = _RAND_2[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; pending_0 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; pending_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; enables_0_0 = _RAND_5[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; maxDevs_0 = _RAND_6[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_16 = _RAND_7[1:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (_T_221) begin priority_0 <= _T_222; end if (_T_244) begin priority_1 <= _T_222; end if (_T_267) begin threshold_0 <= _T_222; end if (reset) begin pending_0 <= 1'h0; end else begin if (_T_32) begin pending_0 <= _T_33; end end if (reset) begin pending_1 <= 1'h0; end else begin if (_T_35) begin pending_1 <= _T_36; end end if (_T_338) begin enables_0_0 <= _T_339; end maxDevs_0 <= PLICFanIn_io_dev; _T_16 <= PLICFanIn_io_max; `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_24) begin $fwrite(32'h80000002,"Assertion failed\n at Plic.scala:227 assert((claimer.asUInt & (claimer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"); // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53764.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_24) begin $fatal; // @[Plic.scala 227:11:freechips.rocketchip.system.TinyConfig.fir@53765.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_43) begin $fwrite(32'h80000002,"Assertion failed\n at Plic.scala:244 assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"); // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53803.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_43) begin $fatal; // @[Plic.scala 244:11:freechips.rocketchip.system.TinyConfig.fir@53804.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_195) begin $fwrite(32'h80000002,"Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:274 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"); // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53988.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_195) begin $fatal; // @[Plic.scala 274:19:freechips.rocketchip.system.TinyConfig.fir@53989.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_29( // @[:freechips.rocketchip.system.TinyConfig.fir@54972.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@54973.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@54974.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [9:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [25:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] input [9:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@54975.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@56098.4] wire _T_11; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@54996.6] wire [4:0] _T_15; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@55002.6] wire [1:0] _T_16; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@55003.6] wire [1:0] _T_17; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@55004.6] wire [25:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@55005.6] wire [25:0] _T_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@55005.6] wire _T_19; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@55006.6] wire _T_21; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@55008.6] wire [1:0] _T_22; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@55009.6] wire [1:0] _T_24; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@55011.6] wire _T_25; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@55012.6] wire _T_26; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@55013.6] wire _T_27; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@55014.6] wire _T_28; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@55015.6] wire _T_30; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55017.6] wire _T_31; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55018.6] wire _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55020.6] wire _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55021.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@55022.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@55023.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@55024.6] wire _T_38; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55025.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55026.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55027.6] wire _T_41; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55028.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55029.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55030.6] wire _T_44; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55031.6] wire _T_45; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55032.6] wire _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55033.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55034.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55035.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55036.6] wire [3:0] _T_52; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@55039.6] wire _T_71; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@55062.6] wire [25:0] _T_73; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@55065.8] wire [26:0] _T_74; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@55066.8] wire [26:0] _T_75; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@55067.8] wire [26:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@55068.8] wire _T_77; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@55069.8] wire _T_82; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55074.8] wire _T_87; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55087.8] wire _T_88; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55088.8] wire _T_91; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55095.8] wire _T_92; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55096.8] wire _T_94; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55102.8] wire _T_95; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55103.8] wire _T_96; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@55108.8] wire _T_98; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55110.8] wire _T_99; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55111.8] wire [3:0] _T_100; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@55116.8] wire _T_101; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@55117.8] wire _T_103; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55119.8] wire _T_104; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55120.8] wire _T_105; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@55125.8] wire _T_107; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55127.8] wire _T_108; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55128.8] wire _T_109; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@55134.6] wire _T_138; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@55188.8] wire _T_140; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55190.8] wire _T_141; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55191.8] wire _T_151; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@55214.6] wire _T_153; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@55217.8] wire _T_161; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@55225.8] wire _T_164; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55228.8] wire _T_165; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55229.8] wire _T_172; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@55248.8] wire _T_174; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55250.8] wire _T_175; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55251.8] wire _T_176; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@55256.8] wire _T_178; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55258.8] wire _T_179; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55259.8] wire _T_184; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@55273.6] wire _T_213; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@55324.6] wire [3:0] _T_238; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@55366.8] wire [3:0] _T_239; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@55367.8] wire _T_240; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@55368.8] wire _T_242; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55370.8] wire _T_243; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55371.8] wire _T_244; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@55377.6] wire _T_262; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@55408.8] wire _T_264; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55410.8] wire _T_265; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55411.8] wire _T_270; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@55425.6] wire _T_288; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@55456.8] wire _T_290; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55458.8] wire _T_291; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55459.8] wire _T_296; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@55473.6] wire _T_322; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@55523.6] wire _T_324; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55525.6] wire _T_325; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55526.6] wire _T_332; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@55537.6] wire _T_336; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@55543.6] wire _T_338; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55546.8] wire _T_339; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55547.8] wire _T_340; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@55552.8] wire _T_342; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55554.8] wire _T_343; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55555.8] wire _T_356; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@55585.6] wire _T_384; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@55643.6] wire _T_413; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@55702.6] wire _T_430; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@55737.6] wire _T_448; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@55773.6] wire _T_477; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@55833.4] reg _T_486; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@55842.4] reg [31:0] _RAND_0; wire _T_488; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@55844.4] wire _T_489; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@55845.4] reg [2:0] _T_497; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@55856.4] reg [31:0] _RAND_1; reg [2:0] _T_498; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@55857.4] reg [31:0] _RAND_2; reg [1:0] _T_499; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@55858.4] reg [31:0] _RAND_3; reg [9:0] _T_500; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@55859.4] reg [31:0] _RAND_4; reg [25:0] _T_501; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@55860.4] reg [31:0] _RAND_5; wire _T_502; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@55861.4] wire _T_503; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@55862.4] wire _T_504; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@55864.6] wire _T_506; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55866.6] wire _T_507; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55867.6] wire _T_508; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@55872.6] wire _T_510; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55874.6] wire _T_511; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55875.6] wire _T_512; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@55880.6] wire _T_514; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55882.6] wire _T_515; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55883.6] wire _T_516; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@55888.6] wire _T_518; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55890.6] wire _T_519; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55891.6] wire _T_520; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@55896.6] wire _T_522; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55898.6] wire _T_523; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55899.6] wire _T_525; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@55906.4] wire _T_526; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@55914.4] reg _T_534; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@55922.4] reg [31:0] _RAND_6; wire _T_536; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@55924.4] wire _T_537; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@55925.4] reg [2:0] _T_545; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@55936.4] reg [31:0] _RAND_7; reg [1:0] _T_547; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@55938.4] reg [31:0] _RAND_8; reg [9:0] _T_548; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@55939.4] reg [31:0] _RAND_9; wire _T_551; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@55942.4] wire _T_552; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@55943.4] wire _T_553; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@55945.6] wire _T_555; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55947.6] wire _T_556; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55948.6] wire _T_561; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@55961.6] wire _T_563; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55963.6] wire _T_564; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55964.6] wire _T_565; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@55969.6] wire _T_567; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55971.6] wire _T_568; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55972.6] wire _T_578; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@55995.4] reg [575:0] _T_579; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@56004.4] reg [575:0] _RAND_10; reg _T_589; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@56014.4] reg [31:0] _RAND_11; wire _T_591; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@56016.4] wire _T_592; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@56017.4] reg _T_608; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@56036.4] reg [31:0] _RAND_12; wire _T_610; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@56038.4] wire _T_611; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@56039.4] wire _T_621; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@56054.4] wire [1023:0] _T_623; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56057.6] wire [575:0] _T_624; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@56059.6] wire _T_625; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@56060.6] wire _T_626; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@56061.6] wire _T_628; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56063.6] wire _T_629; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56064.6] wire [1023:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@56056.4] wire _T_633; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@56075.4] wire _T_635; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@56077.4] wire _T_636; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@56078.4] wire [1023:0] _T_637; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56080.6] wire [575:0] _T_619; // @[:freechips.rocketchip.system.TinyConfig.fir@56050.4 :freechips.rocketchip.system.TinyConfig.fir@56052.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@56058.6] wire [575:0] _T_638; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@56082.6] wire [575:0] _T_639; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@56083.6] wire _T_640; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@56084.6] wire _T_642; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56086.6] wire _T_643; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56087.6] wire [1023:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@56079.4] wire [575:0] _T_644; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@56093.4] wire [575:0] _T_630; // @[:freechips.rocketchip.system.TinyConfig.fir@56070.4 :freechips.rocketchip.system.TinyConfig.fir@56072.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@56081.6] wire [575:0] _T_645; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@56094.4] wire [575:0] _T_646; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@56095.4] reg [31:0] _T_647; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@56097.4] reg [31:0] _RAND_13; wire _T_648; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@56100.4] wire _T_649; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@56101.4] wire _T_650; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@56102.4] wire _T_651; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@56103.4] wire _T_652; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@56104.4] wire _T_653; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@56105.4] wire _T_655; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56107.4] wire _T_656; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56108.4] wire [31:0] _T_658; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@56114.4] wire _T_661; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@56118.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55076.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@55148.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55231.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@55290.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@55341.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@55391.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@55439.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@55487.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55549.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@55591.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@55649.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@55708.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@55743.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@55779.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@56098.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@54996.6] assign _T_15 = 5'h3 << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@55002.6] assign _T_16 = _T_15[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@55003.6] assign _T_17 = ~ _T_16; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@55004.6] assign _GEN_18 = {{24'd0}, _T_17}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@55005.6] assign _T_18 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@55005.6] assign _T_19 = _T_18 == 26'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@55006.6] assign _T_21 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@55008.6] assign _T_22 = 2'h1 << _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@55009.6] assign _T_24 = _T_22 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@55011.6] assign _T_25 = io_in_a_bits_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@55012.6] assign _T_26 = _T_24[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@55013.6] assign _T_27 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@55014.6] assign _T_28 = _T_27 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@55015.6] assign _T_30 = _T_26 & _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55017.6] assign _T_31 = _T_25 | _T_30; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55018.6] assign _T_33 = _T_26 & _T_27; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55020.6] assign _T_34 = _T_25 | _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55021.6] assign _T_35 = _T_24[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@55022.6] assign _T_36 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@55023.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@55024.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55025.6] assign _T_39 = _T_35 & _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55026.6] assign _T_40 = _T_31 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55027.6] assign _T_41 = _T_28 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55028.6] assign _T_42 = _T_35 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55029.6] assign _T_43 = _T_31 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55030.6] assign _T_44 = _T_27 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55031.6] assign _T_45 = _T_35 & _T_44; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55032.6] assign _T_46 = _T_34 | _T_45; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55033.6] assign _T_47 = _T_27 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@55034.6] assign _T_48 = _T_35 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@55035.6] assign _T_49 = _T_34 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@55036.6] assign _T_52 = {_T_49,_T_46,_T_43,_T_40}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@55039.6] assign _T_71 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@55062.6] assign _T_73 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@55065.8] assign _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@55066.8] assign _T_75 = $signed(_T_74) & $signed(-27'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@55067.8] assign _T_76 = $signed(_T_75); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@55068.8] assign _T_77 = $signed(_T_76) == $signed(27'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@55069.8] assign _T_82 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55074.8] assign _T_87 = _T_11 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55087.8] assign _T_88 = _T_87 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55088.8] assign _T_91 = _T_25 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55095.8] assign _T_92 = _T_91 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55096.8] assign _T_94 = _T_19 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55102.8] assign _T_95 = _T_94 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55103.8] assign _T_96 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@55108.8] assign _T_98 = _T_96 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55110.8] assign _T_99 = _T_98 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55111.8] assign _T_100 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@55116.8] assign _T_101 = _T_100 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@55117.8] assign _T_103 = _T_101 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55119.8] assign _T_104 = _T_103 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55120.8] assign _T_105 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@55125.8] assign _T_107 = _T_105 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55127.8] assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55128.8] assign _T_109 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@55134.6] assign _T_138 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@55188.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55190.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55191.8] assign _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@55214.6] assign _T_153 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@55217.8] assign _T_161 = _T_153 & _T_77; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@55225.8] assign _T_164 = _T_161 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55228.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55229.8] assign _T_172 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@55248.8] assign _T_174 = _T_172 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55250.8] assign _T_175 = _T_174 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55251.8] assign _T_176 = io_in_a_bits_mask == _T_52; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@55256.8] assign _T_178 = _T_176 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55258.8] assign _T_179 = _T_178 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55259.8] assign _T_184 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@55273.6] assign _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@55324.6] assign _T_238 = ~ _T_52; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@55366.8] assign _T_239 = io_in_a_bits_mask & _T_238; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@55367.8] assign _T_240 = _T_239 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@55368.8] assign _T_242 = _T_240 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55370.8] assign _T_243 = _T_242 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55371.8] assign _T_244 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@55377.6] assign _T_262 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@55408.8] assign _T_264 = _T_262 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55410.8] assign _T_265 = _T_264 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55411.8] assign _T_270 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@55425.6] assign _T_288 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@55456.8] assign _T_290 = _T_288 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55458.8] assign _T_291 = _T_290 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55459.8] assign _T_296 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@55473.6] assign _T_322 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@55523.6] assign _T_324 = _T_322 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55525.6] assign _T_325 = _T_324 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55526.6] assign _T_332 = io_in_d_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@55537.6] assign _T_336 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@55543.6] assign _T_338 = _T_332 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55546.8] assign _T_339 = _T_338 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55547.8] assign _T_340 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@55552.8] assign _T_342 = _T_340 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55554.8] assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55555.8] assign _T_356 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@55585.6] assign _T_384 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@55643.6] assign _T_413 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@55702.6] assign _T_430 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@55737.6] assign _T_448 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@55773.6] assign _T_477 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@55833.4] assign _T_488 = _T_486 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@55844.4] assign _T_489 = _T_486 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@55845.4] assign _T_502 = _T_489 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@55861.4] assign _T_503 = io_in_a_valid & _T_502; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@55862.4] assign _T_504 = io_in_a_bits_opcode == _T_497; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@55864.6] assign _T_506 = _T_504 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55866.6] assign _T_507 = _T_506 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55867.6] assign _T_508 = io_in_a_bits_param == _T_498; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@55872.6] assign _T_510 = _T_508 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55874.6] assign _T_511 = _T_510 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55875.6] assign _T_512 = io_in_a_bits_size == _T_499; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@55880.6] assign _T_514 = _T_512 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55882.6] assign _T_515 = _T_514 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55883.6] assign _T_516 = io_in_a_bits_source == _T_500; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@55888.6] assign _T_518 = _T_516 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55890.6] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55891.6] assign _T_520 = io_in_a_bits_address == _T_501; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@55896.6] assign _T_522 = _T_520 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55898.6] assign _T_523 = _T_522 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55899.6] assign _T_525 = _T_477 & _T_489; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@55906.4] assign _T_526 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@55914.4] assign _T_536 = _T_534 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@55924.4] assign _T_537 = _T_534 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@55925.4] assign _T_551 = _T_537 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@55942.4] assign _T_552 = io_in_d_valid & _T_551; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@55943.4] assign _T_553 = io_in_d_bits_opcode == _T_545; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@55945.6] assign _T_555 = _T_553 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55947.6] assign _T_556 = _T_555 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55948.6] assign _T_561 = io_in_d_bits_size == _T_547; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@55961.6] assign _T_563 = _T_561 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55963.6] assign _T_564 = _T_563 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55964.6] assign _T_565 = io_in_d_bits_source == _T_548; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@55969.6] assign _T_567 = _T_565 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55971.6] assign _T_568 = _T_567 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55972.6] assign _T_578 = _T_526 & _T_537; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@55995.4] assign _T_591 = _T_589 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@56016.4] assign _T_592 = _T_589 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@56017.4] assign _T_610 = _T_608 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@56038.4] assign _T_611 = _T_608 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@56039.4] assign _T_621 = _T_477 & _T_592; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@56054.4] assign _T_623 = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56057.6] assign _T_624 = _T_579 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@56059.6] assign _T_625 = _T_624[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@56060.6] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@56061.6] assign _T_628 = _T_626 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56063.6] assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56064.6] assign _GEN_15 = _T_621 ? _T_623 : 1024'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@56056.4] assign _T_633 = _T_526 & _T_611; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@56075.4] assign _T_635 = _T_336 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@56077.4] assign _T_636 = _T_633 & _T_635; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@56078.4] assign _T_637 = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56080.6] assign _T_619 = _GEN_15[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@56050.4 :freechips.rocketchip.system.TinyConfig.fir@56052.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@56058.6] assign _T_638 = _T_619 | _T_579; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@56082.6] assign _T_639 = _T_638 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@56083.6] assign _T_640 = _T_639[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@56084.6] assign _T_642 = _T_640 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56086.6] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56087.6] assign _GEN_16 = _T_636 ? _T_637 : 1024'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@56079.4] assign _T_644 = _T_579 | _T_619; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@56093.4] assign _T_630 = _GEN_16[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@56070.4 :freechips.rocketchip.system.TinyConfig.fir@56072.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@56081.6] assign _T_645 = ~ _T_630; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@56094.4] assign _T_646 = _T_644 & _T_645; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@56095.4] assign _T_648 = _T_579 != 576'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@56100.4] assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@56101.4] assign _T_650 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@56102.4] assign _T_651 = _T_649 | _T_650; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@56103.4] assign _T_652 = _T_647 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@56104.4] assign _T_653 = _T_651 | _T_652; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@56105.4] assign _T_655 = _T_653 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56107.4] assign _T_656 = _T_655 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56108.4] assign _T_658 = _T_647 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@56114.4] assign _T_661 = _T_477 | _T_526; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@56118.4] assign _GEN_19 = io_in_a_valid & _T_71; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55076.10] assign _GEN_35 = io_in_a_valid & _T_109; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@55148.10] assign _GEN_53 = io_in_a_valid & _T_151; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55231.10] assign _GEN_65 = io_in_a_valid & _T_184; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@55290.10] assign _GEN_75 = io_in_a_valid & _T_213; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@55341.10] assign _GEN_85 = io_in_a_valid & _T_244; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@55391.10] assign _GEN_95 = io_in_a_valid & _T_270; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@55439.10] assign _GEN_105 = io_in_a_valid & _T_296; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@55487.10] assign _GEN_115 = io_in_d_valid & _T_336; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55549.10] assign _GEN_119 = io_in_d_valid & _T_356; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@55591.10] assign _GEN_125 = io_in_d_valid & _T_384; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@55649.10] assign _GEN_131 = io_in_d_valid & _T_413; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@55708.10] assign _GEN_133 = io_in_d_valid & _T_430; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@55743.10] assign _GEN_135 = io_in_d_valid & _T_448; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@55779.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_486 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_497 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_498 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_499 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_500 = _RAND_4[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_501 = _RAND_5[25:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_534 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_545 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_547 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_548 = _RAND_9[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {18{`RANDOM}}; _T_579 = _RAND_10[575:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_589 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_608 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_647 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_486 <= 1'h0; end else begin if (_T_477) begin if (_T_489) begin _T_486 <= 1'h0; end else begin _T_486 <= _T_488; end end end if (_T_525) begin _T_497 <= io_in_a_bits_opcode; end if (_T_525) begin _T_498 <= io_in_a_bits_param; end if (_T_525) begin _T_499 <= io_in_a_bits_size; end if (_T_525) begin _T_500 <= io_in_a_bits_source; end if (_T_525) begin _T_501 <= io_in_a_bits_address; end if (reset) begin _T_534 <= 1'h0; end else begin if (_T_526) begin if (_T_537) begin _T_534 <= 1'h0; end else begin _T_534 <= _T_536; end end end if (_T_578) begin _T_545 <= io_in_d_bits_opcode; end if (_T_578) begin _T_547 <= io_in_d_bits_size; end if (_T_578) begin _T_548 <= io_in_d_bits_source; end if (reset) begin _T_579 <= 576'h0; end else begin _T_579 <= _T_646; end if (reset) begin _T_589 <= 1'h0; end else begin if (_T_477) begin if (_T_592) begin _T_589 <= 1'h0; end else begin _T_589 <= _T_591; end end end if (reset) begin _T_608 <= 1'h0; end else begin if (_T_526) begin if (_T_611) begin _T_608 <= 1'h0; end else begin _T_608 <= _T_610; end end end if (reset) begin _T_647 <= 32'h0; end else begin if (_T_661) begin _T_647 <= 32'h0; end else begin _T_647 <= _T_658; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55076.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@55077.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:106:16)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@55083.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@55084.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55090.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_88) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@55091.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:106:16)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55098.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_92) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@55099.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55105.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_95) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@55106.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:106:16)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55113.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_99) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@55114.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55122.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@55123.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:106:16)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55130.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_108) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@55131.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@55148.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@55149.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:106:16)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@55155.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@55156.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@55162.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_88) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@55163.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:106:16)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@55170.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_92) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@55171.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@55177.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_95) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@55178.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:106:16)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@55185.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_99) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@55186.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:106:16)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55193.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@55194.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@55202.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_104) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@55203.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:106:16)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@55210.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_108) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@55211.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@55232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@55238.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_88) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@55239.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@55245.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_95) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@55246.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:106:16)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55253.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_175) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@55254.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55261.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_179) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@55262.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:106:16)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@55269.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_108) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@55270.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@55290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@55291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@55297.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_88) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@55298.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@55304.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_95) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@55305.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:106:16)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@55312.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_175) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@55313.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@55320.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_179) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@55321.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@55341.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@55342.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@55348.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_88) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@55349.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@55355.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_95) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@55356.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:106:16)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@55363.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_175) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@55364.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_243) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55373.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_243) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@55374.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@55391.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_82) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@55392.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@55398.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_88) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@55399.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@55405.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_95) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@55406.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_265) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:106:16)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55413.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_265) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@55414.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@55421.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_179) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@55422.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@55439.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_82) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@55440.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@55446.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_88) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@55447.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@55453.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_95) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@55454.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_291) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:106:16)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55461.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_291) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@55462.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@55469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_179) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@55470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CLINT.scala:106:16)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@55487.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_82) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@55488.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@55494.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_88) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@55495.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:106:16)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@55501.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_95) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@55502.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:106:16)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@55509.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_179) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@55510.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:106:16)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@55517.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_108) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@55518.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_325) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:106:16)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55528.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_325) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@55529.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55549.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_339) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@55550.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:106:16)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55557.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_343) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@55558.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@55591.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_339) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@55592.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:106:16)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@55598.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_82) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@55599.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:106:16)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@55606.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_343) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@55607.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@55649.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_339) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@55650.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:106:16)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@55656.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_82) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@55657.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:106:16)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@55664.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_343) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@55665.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@55708.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_339) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@55709.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@55743.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_339) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@55744.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@55779.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_339) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@55780.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_507) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55869.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_507) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@55870.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_511) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55877.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_511) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@55878.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_515) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55885.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_515) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@55886.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55893.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_519) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@55894.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_523) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55901.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_523) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@55902.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_556) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55950.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_556) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@55951.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_564) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55966.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_564) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@55967.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_568) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:106:16)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55974.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_568) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@55975.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_629) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:106:16)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56066.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_629) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@56067.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_636 & _T_643) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:106:16)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56089.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_636 & _T_643) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@56090.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_656) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CLINT.scala:106:16)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56110.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_656) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@56111.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module CLINT( // @[:freechips.rocketchip.system.TinyConfig.fir@56123.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@56124.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@56125.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output auto_int_out_1, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [9:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [25:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output [9:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@56126.4] input io_rtcTick // @[:freechips.rocketchip.system.TinyConfig.fir@56127.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [9:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [25:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] wire [9:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] reg [63:0] time_; // @[CLINT.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@56188.4] reg [63:0] _RAND_0; wire [63:0] _T_14; // @[CLINT.scala 64:38:freechips.rocketchip.system.TinyConfig.fir@56191.6] reg [63:0] timecmp_0; // @[CLINT.scala 67:41:freechips.rocketchip.system.TinyConfig.fir@56194.4] reg [63:0] _RAND_1; reg ipi_0; // @[CLINT.scala 68:41:freechips.rocketchip.system.TinyConfig.fir@56195.4] reg [31:0] _RAND_2; wire [7:0] _T_18; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56201.4] wire [7:0] _T_19; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56202.4] wire [7:0] _T_20; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56203.4] wire [7:0] _T_21; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56204.4] wire [7:0] _T_22; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56205.4] wire [7:0] _T_23; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56206.4] wire [7:0] _T_24; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56207.4] wire [7:0] _T_25; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56208.4] wire _T_72; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@56306.4] wire [23:0] _T_73; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@56308.4] wire [13:0] _T_71_bits_index; // @[RegisterRouter.scala 58:18:freechips.rocketchip.system.TinyConfig.fir@56304.4 RegisterRouter.scala 60:19:freechips.rocketchip.system.TinyConfig.fir@56309.4] wire _T_577; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56890.4] wire _T_576; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56889.4] wire _T_564; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56877.4] wire [2:0] _T_579; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56892.4] wire [13:0] _T_78; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56320.4] wire _T_86; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56328.4] wire _T_82; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56324.4] wire _T_750; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57192.4] wire _T_751; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57193.4] wire _T_752; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57194.4] wire [7:0] _T_605; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56918.4] wire _T_608; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56921.4] wire _T_764; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57213.4] wire _T_765; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57214.4] wire _T_112; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56358.4] wire [7:0] _T_120; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56366.4] wire _T_111; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56357.4] wire [7:0] _T_118; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56364.4] wire _T_110; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56356.4] wire [7:0] _T_116; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56362.4] wire _T_109; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56355.4] wire [7:0] _T_114; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56360.4] wire [31:0] _T_123; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56369.4] wire [7:0] _T_472; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56769.4] wire _T_473; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56770.4] wire _T_477; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56774.4] wire [7:0] _T_495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56796.4] wire _T_496; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56797.4] wire _T_500; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56801.4] wire _T_30; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56235.4] wire [7:0] _T_520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56825.4] wire _T_521; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56826.4] wire _T_525; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56830.4] wire _T_31; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56236.4] wire [7:0] _T_545; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56854.4] wire _T_546; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56855.4] wire _T_550; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56859.4] wire _T_32; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56237.4] wire _T_609; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56922.4] wire _T_769; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57224.4] wire _T_770; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57225.4] wire _T_183; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56432.4] wire _T_33; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56238.4] wire _T_206; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56459.4] wire _T_34; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56239.4] wire _T_231; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56488.4] wire _T_35; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56240.4] wire _T_256; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56517.4] wire _T_36; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56241.4] wire [7:0] _T_501; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56802.4] wire [7:0] _GEN_17; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56804.4] wire [7:0] _T_478; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56775.4] wire [7:0] _GEN_16; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56777.4] wire [7:0] _T_551; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56860.4] wire [7:0] _GEN_19; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56862.4] wire [7:0] _T_526; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56831.4] wire [7:0] _GEN_18; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56833.4] wire [7:0] _GEN_5; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56462.4] wire [7:0] _GEN_4; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56435.4] wire [7:0] _GEN_7; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56520.4] wire [7:0] _GEN_6; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56491.4] wire [63:0] _T_43; // @[RegField.scala 214:52:freechips.rocketchip.system.TinyConfig.fir@56249.6] wire [7:0] _T_45; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56253.4] wire [7:0] _T_46; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56254.4] wire [7:0] _T_47; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56255.4] wire [7:0] _T_48; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56256.4] wire [7:0] _T_49; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56257.4] wire [7:0] _T_50; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56258.4] wire [7:0] _T_51; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56259.4] wire [7:0] _T_52; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56260.4] wire _T_610; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56923.4] wire _T_774; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57235.4] wire _T_775; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57236.4] wire _T_281; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56546.4] wire _T_304; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56573.4] wire _T_57; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56287.4] wire _T_329; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56602.4] wire _T_58; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56288.4] wire _T_354; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56631.4] wire _T_59; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56289.4] wire _T_611; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56924.4] wire _T_779; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57246.4] wire _T_780; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57247.4] wire _T_379; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56660.4] wire _T_60; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56290.4] wire _T_402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56687.4] wire _T_61; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56291.4] wire _T_427; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56716.4] wire _T_62; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56292.4] wire _T_452; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56745.4] wire _T_63; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56293.4] wire [7:0] _GEN_9; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56576.4] wire [7:0] _GEN_8; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56549.4] wire [7:0] _GEN_11; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56634.4] wire [7:0] _GEN_10; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56605.4] wire [7:0] _GEN_13; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56690.4] wire [7:0] _GEN_12; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56663.4] wire [7:0] _GEN_15; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56748.4] wire [7:0] _GEN_14; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56719.4] wire [63:0] _T_70; // @[RegField.scala 214:52:freechips.rocketchip.system.TinyConfig.fir@56301.6] wire [11:0] _T_74; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56312.4] wire _T_124; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56370.4] wire _T_597; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56910.4] wire _T_663; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57020.4] wire _T_664; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57021.4] wire _T_134; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56380.4] wire _T_136; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56382.4] wire [1:0] _T_169; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56418.4] wire [31:0] _T_170; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56419.4] wire [31:0] _T_267; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56532.4] wire [31:0] _T_365; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56646.4] wire [31:0] _T_463; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56760.4] wire [31:0] _T_561; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56874.4] wire _GEN_53; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_54; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_55; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_56; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_57; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_58; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire _GEN_59; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] wire [31:0] _GEN_61; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_62; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_63; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_64; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_65; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_66; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] wire [31:0] _GEN_67; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] TLMonitor_29 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@56135.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); assign _T_14 = time_ + 64'h1; // @[CLINT.scala 64:38:freechips.rocketchip.system.TinyConfig.fir@56191.6] assign _T_18 = timecmp_0[7:0]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56201.4] assign _T_19 = timecmp_0[15:8]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56202.4] assign _T_20 = timecmp_0[23:16]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56203.4] assign _T_21 = timecmp_0[31:24]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56204.4] assign _T_22 = timecmp_0[39:32]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56205.4] assign _T_23 = timecmp_0[47:40]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56206.4] assign _T_24 = timecmp_0[55:48]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56207.4] assign _T_25 = timecmp_0[63:56]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56208.4] assign _T_72 = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@56306.4] assign _T_73 = auto_in_a_bits_address[25:2]; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@56308.4] assign _T_71_bits_index = _T_73[13:0]; // @[RegisterRouter.scala 58:18:freechips.rocketchip.system.TinyConfig.fir@56304.4 RegisterRouter.scala 60:19:freechips.rocketchip.system.TinyConfig.fir@56309.4] assign _T_577 = _T_71_bits_index[13]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56890.4] assign _T_576 = _T_71_bits_index[12]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56889.4] assign _T_564 = _T_71_bits_index[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56877.4] assign _T_579 = {_T_577,_T_576,_T_564}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56892.4] assign _T_78 = _T_71_bits_index & 14'hffe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56320.4] assign _T_86 = _T_78 == 14'hffe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56328.4] assign _T_82 = _T_78 == 14'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56324.4] assign _T_750 = auto_in_a_valid & auto_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57192.4] assign _T_751 = _T_72 == 1'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57193.4] assign _T_752 = _T_750 & _T_751; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57194.4] assign _T_605 = 8'h1 << _T_579; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@56918.4] assign _T_608 = _T_605[2]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56921.4] assign _T_764 = _T_752 & _T_608; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57213.4] assign _T_765 = _T_764 & _T_82; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57214.4] assign _T_112 = auto_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56358.4] assign _T_120 = _T_112 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56366.4] assign _T_111 = auto_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56357.4] assign _T_118 = _T_111 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56364.4] assign _T_110 = auto_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56356.4] assign _T_116 = _T_110 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56362.4] assign _T_109 = auto_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@56355.4] assign _T_114 = _T_109 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@56360.4] assign _T_123 = {_T_120,_T_118,_T_116,_T_114}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56369.4] assign _T_472 = _T_123[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56769.4] assign _T_473 = _T_472 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56770.4] assign _T_477 = _T_765 & _T_473; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56774.4] assign _T_495 = _T_123[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56796.4] assign _T_496 = _T_495 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56797.4] assign _T_500 = _T_765 & _T_496; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56801.4] assign _T_30 = _T_477 | _T_500; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56235.4] assign _T_520 = _T_123[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56825.4] assign _T_521 = _T_520 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56826.4] assign _T_525 = _T_765 & _T_521; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56830.4] assign _T_31 = _T_30 | _T_525; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56236.4] assign _T_545 = _T_123[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56854.4] assign _T_546 = _T_545 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56855.4] assign _T_550 = _T_765 & _T_546; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56859.4] assign _T_32 = _T_31 | _T_550; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56237.4] assign _T_609 = _T_605[3]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56922.4] assign _T_769 = _T_752 & _T_609; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57224.4] assign _T_770 = _T_769 & _T_82; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57225.4] assign _T_183 = _T_770 & _T_473; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56432.4] assign _T_33 = _T_32 | _T_183; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56238.4] assign _T_206 = _T_770 & _T_496; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56459.4] assign _T_34 = _T_33 | _T_206; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56239.4] assign _T_231 = _T_770 & _T_521; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56488.4] assign _T_35 = _T_34 | _T_231; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56240.4] assign _T_256 = _T_770 & _T_546; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56517.4] assign _T_36 = _T_35 | _T_256; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56241.4] assign _T_501 = auto_in_a_bits_data[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56802.4] assign _GEN_17 = _T_500 ? _T_501 : _T_19; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56804.4] assign _T_478 = auto_in_a_bits_data[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56775.4] assign _GEN_16 = _T_477 ? _T_478 : _T_18; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56777.4] assign _T_551 = auto_in_a_bits_data[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56860.4] assign _GEN_19 = _T_550 ? _T_551 : _T_21; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56862.4] assign _T_526 = auto_in_a_bits_data[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56831.4] assign _GEN_18 = _T_525 ? _T_526 : _T_20; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56833.4] assign _GEN_5 = _T_206 ? _T_501 : _T_23; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56462.4] assign _GEN_4 = _T_183 ? _T_478 : _T_22; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56435.4] assign _GEN_7 = _T_256 ? _T_551 : _T_25; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56520.4] assign _GEN_6 = _T_231 ? _T_526 : _T_24; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56491.4] assign _T_43 = {_GEN_7,_GEN_6,_GEN_5,_GEN_4,_GEN_19,_GEN_18,_GEN_17,_GEN_16}; // @[RegField.scala 214:52:freechips.rocketchip.system.TinyConfig.fir@56249.6] assign _T_45 = time_[7:0]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56253.4] assign _T_46 = time_[15:8]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56254.4] assign _T_47 = time_[23:16]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56255.4] assign _T_48 = time_[31:24]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56256.4] assign _T_49 = time_[39:32]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56257.4] assign _T_50 = time_[47:40]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56258.4] assign _T_51 = time_[55:48]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56259.4] assign _T_52 = time_[63:56]; // @[RegField.scala 211:53:freechips.rocketchip.system.TinyConfig.fir@56260.4] assign _T_610 = _T_605[4]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56923.4] assign _T_774 = _T_752 & _T_610; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57235.4] assign _T_775 = _T_774 & _T_86; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57236.4] assign _T_281 = _T_775 & _T_473; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56546.4] assign _T_304 = _T_775 & _T_496; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56573.4] assign _T_57 = _T_281 | _T_304; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56287.4] assign _T_329 = _T_775 & _T_521; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56602.4] assign _T_58 = _T_57 | _T_329; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56288.4] assign _T_354 = _T_775 & _T_546; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56631.4] assign _T_59 = _T_58 | _T_354; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56289.4] assign _T_611 = _T_605[5]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56924.4] assign _T_779 = _T_752 & _T_611; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57246.4] assign _T_780 = _T_779 & _T_86; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57247.4] assign _T_379 = _T_780 & _T_473; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56660.4] assign _T_60 = _T_59 | _T_379; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56290.4] assign _T_402 = _T_780 & _T_496; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56687.4] assign _T_61 = _T_60 | _T_402; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56291.4] assign _T_427 = _T_780 & _T_521; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56716.4] assign _T_62 = _T_61 | _T_427; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56292.4] assign _T_452 = _T_780 & _T_546; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56745.4] assign _T_63 = _T_62 | _T_452; // @[RegField.scala 214:27:freechips.rocketchip.system.TinyConfig.fir@56293.4] assign _GEN_9 = _T_304 ? _T_501 : _T_46; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56576.4] assign _GEN_8 = _T_281 ? _T_478 : _T_45; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56549.4] assign _GEN_11 = _T_354 ? _T_551 : _T_48; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56634.4] assign _GEN_10 = _T_329 ? _T_526 : _T_47; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56605.4] assign _GEN_13 = _T_402 ? _T_501 : _T_50; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56690.4] assign _GEN_12 = _T_379 ? _T_478 : _T_49; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56663.4] assign _GEN_15 = _T_452 ? _T_551 : _T_52; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56748.4] assign _GEN_14 = _T_427 ? _T_526 : _T_51; // @[RegField.scala 218:20:freechips.rocketchip.system.TinyConfig.fir@56719.4] assign _T_70 = {_GEN_15,_GEN_14,_GEN_13,_GEN_12,_GEN_11,_GEN_10,_GEN_9,_GEN_8}; // @[RegField.scala 214:52:freechips.rocketchip.system.TinyConfig.fir@56301.6] assign _T_74 = {auto_in_a_bits_source,auto_in_a_bits_size}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56312.4] assign _T_124 = _T_123[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56370.4] assign _T_597 = _T_605[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56910.4] assign _T_663 = _T_752 & _T_597; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57020.4] assign _T_664 = _T_663 & _T_82; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@57021.4] assign _T_134 = _T_664 & _T_124; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56380.4] assign _T_136 = auto_in_a_bits_data[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56382.4] assign _T_169 = {1'h0,ipi_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56418.4] assign _T_170 = {{30'd0}, _T_169}; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@56419.4] assign _T_267 = {_T_25,_T_24,_T_23,_T_22}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56532.4] assign _T_365 = {_T_48,_T_47,_T_46,_T_45}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56646.4] assign _T_463 = {_T_52,_T_51,_T_50,_T_49}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56760.4] assign _T_561 = {_T_21,_T_20,_T_19,_T_18}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@56874.4] assign _GEN_53 = 3'h1 == _T_579 ? 1'h1 : _T_82; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_54 = 3'h2 == _T_579 ? _T_82 : _GEN_53; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_55 = 3'h3 == _T_579 ? _T_82 : _GEN_54; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_56 = 3'h4 == _T_579 ? _T_86 : _GEN_55; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_57 = 3'h5 == _T_579 ? _T_86 : _GEN_56; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_58 = 3'h6 == _T_579 ? 1'h1 : _GEN_57; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_59 = 3'h7 == _T_579 ? 1'h1 : _GEN_58; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57303.4] assign _GEN_61 = 3'h1 == _T_579 ? 32'h0 : _T_170; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_62 = 3'h2 == _T_579 ? _T_561 : _GEN_61; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_63 = 3'h3 == _T_579 ? _T_267 : _GEN_62; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_64 = 3'h4 == _T_579 ? _T_365 : _GEN_63; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_65 = 3'h5 == _T_579 ? _T_463 : _GEN_64; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_66 = 3'h6 == _T_579 ? 32'h0 : _GEN_65; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign _GEN_67 = 3'h7 == _T_579 ? 32'h0 : _GEN_66; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@57315.4] assign auto_int_out_0 = ipi_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@56187.4] assign auto_int_out_1 = time_ >= timecmp_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@56187.4] assign auto_in_a_ready = auto_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign auto_in_d_valid = auto_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign auto_in_d_bits_opcode = {{2'd0}, _T_72}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign auto_in_d_bits_size = _T_74[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign auto_in_d_bits_source = _T_74[11:2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign auto_in_d_bits_data = _GEN_59 ? _GEN_67 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@56186.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@56137.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@56138.4] assign TLMonitor_io_in_a_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_d_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_72}; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_d_bits_size = _T_74[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] assign TLMonitor_io_in_d_bits_source = _T_74[11:2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@56183.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {2{`RANDOM}}; time_ = _RAND_0[63:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {2{`RANDOM}}; timecmp_0 = _RAND_1[63:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; ipi_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin time_ <= 64'h0; end else begin if (_T_63) begin time_ <= _T_70; end else begin if (io_rtcTick) begin time_ <= _T_14; end end end if (_T_36) begin timecmp_0 <= _T_43; end if (reset) begin ipi_0 <= 1'h0; end else begin if (_T_134) begin ipi_0 <= _T_136; end end end endmodule module TLMonitor_30( // @[:freechips.rocketchip.system.TinyConfig.fir@57357.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@57358.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@57359.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [8:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@57360.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@58462.4] wire [8:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57383.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@57384.6] wire [9:0] _T_49; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@57421.6] wire _T_57; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@57433.6] wire [9:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@57438.8] wire [9:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@57439.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@57440.8] wire _T_68; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57445.8] wire _T_80; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57473.8] wire _T_81; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57474.8] wire [3:0] _T_86; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@57487.8] wire _T_87; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@57488.8] wire _T_89; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57490.8] wire _T_90; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57491.8] wire _T_95; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@57505.6] wire _T_137; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@57585.6] wire _T_150; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57599.8] wire _T_151; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57600.8] wire _T_162; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@57627.8] wire _T_164; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57629.8] wire _T_165; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57630.8] wire _T_170; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@57644.6] wire _T_199; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@57695.6] wire _T_230; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@57748.6] wire _T_256; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@57796.6] wire _T_282; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@57844.6] wire _T_308; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@57894.6] wire _T_310; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57896.6] wire _T_311; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57897.6] wire _T_315; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@57907.6] wire _T_319; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@57916.8] wire _T_321; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57918.8] wire _T_322; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57919.8] wire _T_323; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@57924.8] wire _T_325; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57926.8] wire _T_326; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57927.8] wire _T_327; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@57932.8] wire _T_329; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57934.8] wire _T_330; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57935.8] wire _T_331; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@57940.8] wire _T_333; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57942.8] wire _T_334; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57943.8] wire _T_335; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@57949.6] wire _T_346; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@57973.8] wire _T_348; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57975.8] wire _T_349; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57976.8] wire _T_350; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@57981.8] wire _T_352; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57983.8] wire _T_353; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57984.8] wire _T_363; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@58007.6] wire _T_383; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@58048.8] wire _T_385; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58050.8] wire _T_386; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58051.8] wire _T_392; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@58066.6] wire _T_409; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@58101.6] wire _T_427; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@58137.6] wire _T_456; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@58197.4] reg _T_465; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@58206.4] reg [31:0] _RAND_0; wire _T_467; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58208.4] wire _T_468; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58209.4] reg [2:0] _T_476; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@58220.4] reg [31:0] _RAND_1; reg [8:0] _T_480; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@58224.4] reg [31:0] _RAND_2; wire _T_481; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@58225.4] wire _T_482; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@58226.4] wire _T_483; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@58228.6] wire _T_485; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58230.6] wire _T_486; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58231.6] wire _T_499; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@58260.6] wire _T_501; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58262.6] wire _T_502; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58263.6] wire _T_504; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@58270.4] wire _T_505; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@58278.4] reg _T_513; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@58286.4] reg [31:0] _RAND_3; wire _T_515; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58288.4] wire _T_516; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58289.4] reg [2:0] _T_524; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@58300.4] reg [31:0] _RAND_4; reg [1:0] _T_525; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@58301.4] reg [31:0] _RAND_5; reg [1:0] _T_526; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@58302.4] reg [31:0] _RAND_6; reg _T_528; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@58304.4] reg [31:0] _RAND_7; reg _T_529; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@58305.4] reg [31:0] _RAND_8; wire _T_530; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@58306.4] wire _T_531; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@58307.4] wire _T_532; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@58309.6] wire _T_534; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58311.6] wire _T_535; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58312.6] wire _T_536; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@58317.6] wire _T_538; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58319.6] wire _T_539; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58320.6] wire _T_540; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@58325.6] wire _T_542; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58327.6] wire _T_543; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58328.6] wire _T_548; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@58341.6] wire _T_550; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58343.6] wire _T_551; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58344.6] wire _T_552; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@58349.6] wire _T_554; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58351.6] wire _T_555; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58352.6] wire _T_557; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@58359.4] reg _T_558; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@58368.4] reg [31:0] _RAND_9; reg _T_568; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@58378.4] reg [31:0] _RAND_10; wire _T_570; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58380.4] wire _T_571; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58381.4] reg _T_587; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@58400.4] reg [31:0] _RAND_11; wire _T_589; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58402.4] wire _T_590; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58403.4] wire _T_600; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@58418.4] wire _T_605; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@58425.6] wire _T_607; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58427.6] wire _T_608; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58428.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@58420.4] wire _T_612; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@58439.4] wire _T_614; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@58441.4] wire _T_615; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@58442.4] wire _T_598; // @[:freechips.rocketchip.system.TinyConfig.fir@58414.4 :freechips.rocketchip.system.TinyConfig.fir@58416.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@58422.6] wire _T_617; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@58446.6] wire _T_621; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58450.6] wire _T_622; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58451.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@58443.4] wire _T_623; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@58457.4] wire _T_609; // @[:freechips.rocketchip.system.TinyConfig.fir@58434.4 :freechips.rocketchip.system.TinyConfig.fir@58436.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@58445.6] wire _T_624; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@58458.4] wire _T_625; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@58459.4] reg [31:0] _T_626; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@58461.4] reg [31:0] _RAND_12; wire _T_629; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@58466.4] wire _T_630; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@58467.4] wire _T_631; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@58468.4] wire _T_632; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@58469.4] wire _T_634; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58471.4] wire _T_635; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58472.4] wire [31:0] _T_637; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@58478.4] wire _T_640; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@58482.4] wire _GEN_18; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57447.10] wire _GEN_26; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@57519.10] wire _GEN_36; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57602.10] wire _GEN_42; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@57661.10] wire _GEN_48; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@57712.10] wire _GEN_52; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@57762.10] wire _GEN_58; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@57810.10] wire _GEN_64; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@57858.10] wire _GEN_70; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57921.10] wire _GEN_78; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@57962.10] wire _GEN_90; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@58020.10] wire _GEN_102; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@58080.10] wire _GEN_108; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@58115.10] wire _GEN_114; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@58151.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@58462.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_address & 9'h3; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@57383.6] assign _T_12 = _T_11 == 9'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@57384.6] assign _T_49 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@57421.6] assign _T_57 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@57433.6] assign _T_61 = $signed(_T_49) & $signed(-10'sh200); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@57438.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@57439.8] assign _T_63 = $signed(_T_62) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@57440.8] assign _T_68 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57445.8] assign _T_80 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57473.8] assign _T_81 = _T_80 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57474.8] assign _T_86 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@57487.8] assign _T_87 = _T_86 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@57488.8] assign _T_89 = _T_87 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57490.8] assign _T_90 = _T_89 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57491.8] assign _T_95 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@57505.6] assign _T_137 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@57585.6] assign _T_150 = _T_63 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57599.8] assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57600.8] assign _T_162 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@57627.8] assign _T_164 = _T_162 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57629.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57630.8] assign _T_170 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@57644.6] assign _T_199 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@57695.6] assign _T_230 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@57748.6] assign _T_256 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@57796.6] assign _T_282 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@57844.6] assign _T_308 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@57894.6] assign _T_310 = _T_308 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57896.6] assign _T_311 = _T_310 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57897.6] assign _T_315 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@57907.6] assign _T_319 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@57916.8] assign _T_321 = _T_319 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57918.8] assign _T_322 = _T_321 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57919.8] assign _T_323 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@57924.8] assign _T_325 = _T_323 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57926.8] assign _T_326 = _T_325 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57927.8] assign _T_327 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@57932.8] assign _T_329 = _T_327 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57934.8] assign _T_330 = _T_329 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57935.8] assign _T_331 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@57940.8] assign _T_333 = _T_331 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57942.8] assign _T_334 = _T_333 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57943.8] assign _T_335 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@57949.6] assign _T_346 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@57973.8] assign _T_348 = _T_346 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57975.8] assign _T_349 = _T_348 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57976.8] assign _T_350 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@57981.8] assign _T_352 = _T_350 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57983.8] assign _T_353 = _T_352 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57984.8] assign _T_363 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@58007.6] assign _T_383 = _T_331 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@58048.8] assign _T_385 = _T_383 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58050.8] assign _T_386 = _T_385 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58051.8] assign _T_392 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@58066.6] assign _T_409 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@58101.6] assign _T_427 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@58137.6] assign _T_456 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@58197.4] assign _T_467 = _T_465 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58208.4] assign _T_468 = _T_465 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58209.4] assign _T_481 = _T_468 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@58225.4] assign _T_482 = io_in_a_valid & _T_481; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@58226.4] assign _T_483 = io_in_a_bits_opcode == _T_476; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@58228.6] assign _T_485 = _T_483 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58230.6] assign _T_486 = _T_485 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58231.6] assign _T_499 = io_in_a_bits_address == _T_480; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@58260.6] assign _T_501 = _T_499 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58262.6] assign _T_502 = _T_501 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58263.6] assign _T_504 = _T_456 & _T_468; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@58270.4] assign _T_505 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@58278.4] assign _T_515 = _T_513 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58288.4] assign _T_516 = _T_513 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58289.4] assign _T_530 = _T_516 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@58306.4] assign _T_531 = io_in_d_valid & _T_530; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@58307.4] assign _T_532 = io_in_d_bits_opcode == _T_524; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@58309.6] assign _T_534 = _T_532 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58311.6] assign _T_535 = _T_534 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58312.6] assign _T_536 = io_in_d_bits_param == _T_525; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@58317.6] assign _T_538 = _T_536 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58319.6] assign _T_539 = _T_538 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58320.6] assign _T_540 = io_in_d_bits_size == _T_526; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@58325.6] assign _T_542 = _T_540 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58327.6] assign _T_543 = _T_542 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58328.6] assign _T_548 = io_in_d_bits_sink == _T_528; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@58341.6] assign _T_550 = _T_548 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58343.6] assign _T_551 = _T_550 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58344.6] assign _T_552 = io_in_d_bits_denied == _T_529; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@58349.6] assign _T_554 = _T_552 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58351.6] assign _T_555 = _T_554 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58352.6] assign _T_557 = _T_505 & _T_516; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@58359.4] assign _T_570 = _T_568 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58380.4] assign _T_571 = _T_568 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58381.4] assign _T_589 = _T_587 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@58402.4] assign _T_590 = _T_587 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@58403.4] assign _T_600 = _T_456 & _T_571; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@58418.4] assign _T_605 = _T_558 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@58425.6] assign _T_607 = _T_605 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58427.6] assign _T_608 = _T_607 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58428.6] assign _GEN_15 = _T_600 ? 2'h1 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@58420.4] assign _T_612 = _T_505 & _T_590; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@58439.4] assign _T_614 = _T_315 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@58441.4] assign _T_615 = _T_612 & _T_614; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@58442.4] assign _T_598 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@58414.4 :freechips.rocketchip.system.TinyConfig.fir@58416.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@58422.6] assign _T_617 = _T_598 | _T_558; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@58446.6] assign _T_621 = _T_617 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58450.6] assign _T_622 = _T_621 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58451.6] assign _GEN_16 = _T_615 ? 2'h1 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@58443.4] assign _T_623 = _T_558 | _T_598; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@58457.4] assign _T_609 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@58434.4 :freechips.rocketchip.system.TinyConfig.fir@58436.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@58445.6] assign _T_624 = ~ _T_609; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@58458.4] assign _T_625 = _T_623 & _T_624; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@58459.4] assign _T_629 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@58466.4] assign _T_630 = _T_605 | _T_629; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@58467.4] assign _T_631 = _T_626 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@58468.4] assign _T_632 = _T_630 | _T_631; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@58469.4] assign _T_634 = _T_632 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58471.4] assign _T_635 = _T_634 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58472.4] assign _T_637 = _T_626 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@58478.4] assign _T_640 = _T_456 | _T_505; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@58482.4] assign _GEN_18 = io_in_a_valid & _T_57; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57447.10] assign _GEN_26 = io_in_a_valid & _T_95; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@57519.10] assign _GEN_36 = io_in_a_valid & _T_137; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57602.10] assign _GEN_42 = io_in_a_valid & _T_170; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@57661.10] assign _GEN_48 = io_in_a_valid & _T_199; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@57712.10] assign _GEN_52 = io_in_a_valid & _T_230; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@57762.10] assign _GEN_58 = io_in_a_valid & _T_256; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@57810.10] assign _GEN_64 = io_in_a_valid & _T_282; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@57858.10] assign _GEN_70 = io_in_d_valid & _T_315; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57921.10] assign _GEN_78 = io_in_d_valid & _T_335; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@57962.10] assign _GEN_90 = io_in_d_valid & _T_363; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@58020.10] assign _GEN_102 = io_in_d_valid & _T_392; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@58080.10] assign _GEN_108 = io_in_d_valid & _T_409; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@58115.10] assign _GEN_114 = io_in_d_valid & _T_427; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@58151.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_465 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_476 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_480 = _RAND_2[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_513 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_524 = _RAND_4[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_525 = _RAND_5[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_526 = _RAND_6[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_528 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_529 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_558 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_568 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_587 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_626 = _RAND_12[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_465 <= 1'h0; end else begin if (_T_456) begin if (_T_468) begin _T_465 <= 1'h0; end else begin _T_465 <= _T_467; end end end if (_T_504) begin _T_476 <= io_in_a_bits_opcode; end if (_T_504) begin _T_480 <= io_in_a_bits_address; end if (reset) begin _T_513 <= 1'h0; end else begin if (_T_505) begin if (_T_516) begin _T_513 <= 1'h0; end else begin _T_513 <= _T_515; end end end if (_T_557) begin _T_524 <= io_in_d_bits_opcode; end if (_T_557) begin _T_525 <= io_in_d_bits_param; end if (_T_557) begin _T_526 <= io_in_d_bits_size; end if (_T_557) begin _T_528 <= io_in_d_bits_sink; end if (_T_557) begin _T_529 <= io_in_d_bits_denied; end if (reset) begin _T_558 <= 1'h0; end else begin _T_558 <= _T_625; end if (reset) begin _T_568 <= 1'h0; end else begin if (_T_456) begin if (_T_571) begin _T_568 <= 1'h0; end else begin _T_568 <= _T_570; end end end if (reset) begin _T_587 <= 1'h0; end else begin if (_T_505) begin if (_T_590) begin _T_587 <= 1'h0; end else begin _T_587 <= _T_589; end end end if (reset) begin _T_626 <= 32'h0; end else begin if (_T_640) begin _T_626 <= 32'h0; end else begin _T_626 <= _T_637; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57447.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_68) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@57448.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:496:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@57454.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_68) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@57455.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57476.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_81) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@57477.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_90) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_90) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@57494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@57519.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_68) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@57520.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:496:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@57526.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_68) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@57527.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@57548.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_81) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@57549.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:496:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@57564.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_68) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@57565.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_90) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@57573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_90) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@57574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57602.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_151) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@57603.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@57616.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_81) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@57617.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57632.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_165) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@57633.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@57661.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_151) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@57662.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@57675.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_81) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@57676.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@57691.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_165) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@57692.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_151) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@57712.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_151) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@57713.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@57726.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_81) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@57727.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@57762.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_68) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@57763.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@57776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_81) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@57777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@57792.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_165) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@57793.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@57810.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_68) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@57811.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@57824.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_81) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@57825.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@57840.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_165) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@57841.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:496:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@57858.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_68) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@57859.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_81) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:496:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@57872.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_81) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@57873.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:496:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@57880.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_165) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@57881.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_311) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:496:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57899.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_311) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@57900.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_322) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:496:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57921.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_322) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@57922.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_326) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:496:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57929.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_326) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@57930.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_330) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57937.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_330) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@57938.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:496:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57945.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_334) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@57946.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:496:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@57962.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_68) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@57963.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_322) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:496:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@57970.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_322) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@57971.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_349) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:496:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_349) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@57979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_353) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:496:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57986.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_353) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@57987.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_330) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@57994.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_330) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@57995.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_78 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:496:18)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@58003.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_78 & _T_334) begin $fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@58004.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_68) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:496:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@58020.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_68) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@58021.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_322) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:496:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@58028.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_322) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@58029.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_349) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:496:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@58036.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_349) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@58037.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_353) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:496:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@58044.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_353) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@58045.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_386) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58053.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_386) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@58054.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_90 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:496:18)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@58062.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_90 & _T_334) begin $fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@58063.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_102 & _T_326) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:496:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@58080.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_102 & _T_326) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@58081.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_102 & _T_330) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@58088.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_102 & _T_330) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@58089.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_102 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:496:18)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@58097.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_102 & _T_334) begin $fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@58098.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_326) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:496:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@58115.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_326) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@58116.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_386) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@58124.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_386) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@58125.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:496:18)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@58133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_334) begin $fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@58134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_114 & _T_326) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:496:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@58151.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_114 & _T_326) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@58152.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_114 & _T_330) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:496:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@58159.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_114 & _T_330) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@58160.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_114 & _T_334) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:496:18)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@58168.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_114 & _T_334) begin $fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@58169.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_482 & _T_486) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58233.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_482 & _T_486) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@58234.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_482 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58265.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_482 & _T_502) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@58266.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_531 & _T_535) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58314.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_531 & _T_535) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@58315.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_531 & _T_539) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58322.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_531 & _T_539) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@58323.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_531 & _T_543) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58330.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_531 & _T_543) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@58331.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_531 & _T_551) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58346.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_531 & _T_551) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@58347.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_531 & _T_555) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:496:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58354.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_531 & _T_555) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@58355.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_600 & _T_608) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:496:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58430.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_600 & _T_608) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@58431.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_615 & _T_622) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:496:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58453.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_615 & _T_622) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@58454.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_635) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:496:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58474.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_635) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@58475.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_7( // @[:freechips.rocketchip.system.TinyConfig.fir@58487.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@58488.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@58489.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [8:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_1_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_out_1_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [6:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [3:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [31:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_out_1_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_1_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [31:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_out_0_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [8:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [3:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output [31:0] auto_out_0_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] output auto_out_0_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [1:0] auto_out_0_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [1:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input [31:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@58490.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [8:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] wire [9:0] _T_35; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58627.4] wire [9:0] _T_36; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58628.4] wire [9:0] _T_37; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58629.4] wire _T_38; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58630.4] wire [8:0] _T_39; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58631.4] wire [9:0] _T_40; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58632.4] wire [9:0] _T_41; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58633.4] wire [9:0] _T_42; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58634.4] wire _T_43; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58635.4] wire [8:0] _T_44; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58636.4] wire [9:0] _T_45; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58637.4] wire [9:0] _T_46; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58638.4] wire [9:0] _T_47; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58639.4] wire _T_48; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58640.4] wire [8:0] _T_49; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58641.4] wire [9:0] _T_50; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58642.4] wire [9:0] _T_51; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58643.4] wire [9:0] _T_52; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58644.4] wire _T_53; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58645.4] wire [8:0] _T_54; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58646.4] wire [9:0] _T_55; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58647.4] wire [9:0] _T_56; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58648.4] wire [9:0] _T_57; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58649.4] wire _T_58; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58650.4] wire [8:0] _T_59; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58651.4] wire [9:0] _T_60; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58652.4] wire [9:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58653.4] wire [9:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58654.4] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58655.4] wire _T_64; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58656.4] wire _T_65; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58657.4] wire _T_66; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58658.4] wire _T_67; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58659.4] wire requestAIO_0_0; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58660.4] wire [8:0] _T_69; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58662.4] wire [9:0] _T_70; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58663.4] wire [9:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58664.4] wire [9:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58665.4] wire _T_73; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58666.4] wire [8:0] _T_74; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58667.4] wire [9:0] _T_75; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58668.4] wire [9:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58669.4] wire [9:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58670.4] wire _T_78; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58671.4] wire requestAIO_0_1; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58672.4] wire _T_142; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58761.4] wire _T_143; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58762.4] reg _T_185; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@58852.4] reg [31:0] _RAND_0; wire _T_186; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@58853.4] wire _T_187; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@58854.4] wire [1:0] _T_188; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@58855.4] wire _T_190; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@58857.4] wire _T_192; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58859.4] wire _T_193; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58860.4] reg [1:0] _T_195; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@58866.4] reg [31:0] _RAND_1; wire [1:0] _T_196; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@58867.4] wire [1:0] _T_197; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@58868.4] wire [3:0] _T_198; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@58869.4] wire [2:0] _T_199; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@58870.4] wire [3:0] _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@58871.4] wire [3:0] _T_200; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@58871.4] wire [2:0] _T_202; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@58873.4] wire [3:0] _T_203; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@58874.4] wire [3:0] _GEN_2; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@58875.4] wire [3:0] _T_204; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@58875.4] wire [1:0] _T_205; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@58876.4] wire [1:0] _T_206; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@58877.4] wire [1:0] _T_207; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@58878.4] wire [1:0] _T_208; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@58879.4] wire _T_209; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@58880.4] wire _T_210; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@58881.4] wire [1:0] _T_211; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@58883.6] wire [2:0] _T_212; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@58884.6] wire [1:0] _T_213; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@58885.6] wire [1:0] _T_214; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@58886.6] wire _T_217; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@58891.4] wire _T_218; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@58892.4] wire _T_220; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@58897.4] wire _T_221; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@58898.4] wire _T_224; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@58904.4] wire _T_226; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@58906.4] wire _T_229; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@58909.4] wire _T_230; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@58910.4] wire _T_233; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58913.4] wire _T_234; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58914.4] wire _T_235; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@58919.4] wire _T_236; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@58920.4] wire _T_238; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@58922.4] wire _T_240; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58924.4] wire _T_241; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58925.4] reg _T_250_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@58942.4] reg [31:0] _RAND_2; wire _T_256; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58951.4] reg _T_250_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@58942.4] reg [31:0] _RAND_3; wire _T_257; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58952.4] wire _T_258; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58953.4] wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@58956.4] wire _T_245; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@58933.4] wire _T_247; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@58935.4] wire _T_251_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@58943.4] wire _T_251_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@58943.4] wire _T_252_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@58945.4] wire _T_252_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@58945.4] wire [42:0] _T_267; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58964.4] wire [42:0] _T_268; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58965.4] wire [42:0] _T_275; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58972.4] wire [42:0] _T_276; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58973.4] wire [42:0] _T_277; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58974.4] TLMonitor_30 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@58497.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); assign _T_35 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58627.4] assign _T_36 = $signed(_T_35) & $signed(10'sh1c0); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58628.4] assign _T_37 = $signed(_T_36); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58629.4] assign _T_38 = $signed(_T_37) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58630.4] assign _T_39 = auto_in_a_bits_address ^ 9'h44; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58631.4] assign _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58632.4] assign _T_41 = $signed(_T_40) & $signed(10'sh1fc); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58633.4] assign _T_42 = $signed(_T_41); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58634.4] assign _T_43 = $signed(_T_42) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58635.4] assign _T_44 = auto_in_a_bits_address ^ 9'h48; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58636.4] assign _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58637.4] assign _T_46 = $signed(_T_45) & $signed(10'sh1e8); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58638.4] assign _T_47 = $signed(_T_46); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58639.4] assign _T_48 = $signed(_T_47) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58640.4] assign _T_49 = auto_in_a_bits_address ^ 9'h60; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58641.4] assign _T_50 = {1'b0,$signed(_T_49)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58642.4] assign _T_51 = $signed(_T_50) & $signed(10'sh1e0); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58643.4] assign _T_52 = $signed(_T_51); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58644.4] assign _T_53 = $signed(_T_52) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58645.4] assign _T_54 = auto_in_a_bits_address ^ 9'h80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58646.4] assign _T_55 = {1'b0,$signed(_T_54)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58647.4] assign _T_56 = $signed(_T_55) & $signed(10'sh180); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58648.4] assign _T_57 = $signed(_T_56); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58649.4] assign _T_58 = $signed(_T_57) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58650.4] assign _T_59 = auto_in_a_bits_address ^ 9'h100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58651.4] assign _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58652.4] assign _T_61 = $signed(_T_60) & $signed(10'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58653.4] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58654.4] assign _T_63 = $signed(_T_62) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58655.4] assign _T_64 = _T_38 | _T_43; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58656.4] assign _T_65 = _T_64 | _T_48; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58657.4] assign _T_66 = _T_65 | _T_53; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58658.4] assign _T_67 = _T_66 | _T_58; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58659.4] assign requestAIO_0_0 = _T_67 | _T_63; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58660.4] assign _T_69 = auto_in_a_bits_address ^ 9'h40; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58662.4] assign _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58663.4] assign _T_71 = $signed(_T_70) & $signed(10'sh1ec); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58664.4] assign _T_72 = $signed(_T_71); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58665.4] assign _T_73 = $signed(_T_72) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58666.4] assign _T_74 = auto_in_a_bits_address ^ 9'h54; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@58667.4] assign _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@58668.4] assign _T_76 = $signed(_T_75) & $signed(10'sh1fc); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58669.4] assign _T_77 = $signed(_T_76); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@58670.4] assign _T_78 = $signed(_T_77) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@58671.4] assign requestAIO_0_1 = _T_73 | _T_78; // @[Xbar.scala 217:92:freechips.rocketchip.system.TinyConfig.fir@58672.4] assign _T_142 = requestAIO_0_0 ? auto_out_0_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58761.4] assign _T_143 = requestAIO_0_1 ? auto_out_1_a_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58762.4] assign _T_186 = _T_185 == 1'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@58853.4] assign _T_187 = _T_186 & auto_in_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@58854.4] assign _T_188 = {auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@58855.4] assign _T_190 = _T_188 == _T_188; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@58857.4] assign _T_192 = _T_190 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58859.4] assign _T_193 = _T_192 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58860.4] assign _T_196 = ~ _T_195; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@58867.4] assign _T_197 = _T_188 & _T_196; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@58868.4] assign _T_198 = {_T_197,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@58869.4] assign _T_199 = _T_198[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@58870.4] assign _GEN_1 = {{1'd0}, _T_199}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@58871.4] assign _T_200 = _T_198 | _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@58871.4] assign _T_202 = _T_200[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@58873.4] assign _T_203 = {_T_195, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@58874.4] assign _GEN_2 = {{1'd0}, _T_202}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@58875.4] assign _T_204 = _GEN_2 | _T_203; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@58875.4] assign _T_205 = _T_204[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@58876.4] assign _T_206 = _T_204[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@58877.4] assign _T_207 = _T_205 & _T_206; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@58878.4] assign _T_208 = ~ _T_207; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@58879.4] assign _T_209 = _T_188 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@58880.4] assign _T_210 = _T_187 & _T_209; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@58881.4] assign _T_211 = _T_208 & _T_188; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@58883.6] assign _T_212 = {_T_211, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@58884.6] assign _T_213 = _T_212[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@58885.6] assign _T_214 = _T_211 | _T_213; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@58886.6] assign _T_217 = _T_208[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@58891.4] assign _T_218 = _T_208[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@58892.4] assign _T_220 = _T_217 & auto_out_0_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@58897.4] assign _T_221 = _T_218 & auto_out_1_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@58898.4] assign _T_224 = _T_220 | _T_221; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@58904.4] assign _T_226 = _T_220 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@58906.4] assign _T_229 = _T_221 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@58909.4] assign _T_230 = _T_226 | _T_229; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@58910.4] assign _T_233 = _T_230 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58913.4] assign _T_234 = _T_233 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58914.4] assign _T_235 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@58919.4] assign _T_236 = _T_235 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@58920.4] assign _T_238 = _T_236 | _T_224; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@58922.4] assign _T_240 = _T_238 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58924.4] assign _T_241 = _T_240 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58925.4] assign _T_256 = _T_250_0 ? auto_out_0_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58951.4] assign _T_257 = _T_250_1 ? auto_out_1_d_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58952.4] assign _T_258 = _T_256 | _T_257; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58953.4] assign in_0_d_valid = _T_186 ? _T_235 : _T_258; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@58956.4] assign _T_245 = auto_in_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@58933.4] assign _T_247 = _T_185 - _T_245; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@58935.4] assign _T_251_0 = _T_186 ? _T_220 : _T_250_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@58943.4] assign _T_251_1 = _T_186 ? _T_221 : _T_250_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@58943.4] assign _T_252_0 = _T_186 ? _T_217 : _T_250_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@58945.4] assign _T_252_1 = _T_186 ? _T_218 : _T_250_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@58945.4] assign _T_267 = {auto_out_0_d_bits_opcode,auto_out_0_d_bits_param,auto_out_0_d_bits_size,auto_out_0_d_bits_source,auto_out_0_d_bits_sink,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58964.4] assign _T_268 = _T_251_0 ? _T_267 : 43'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58965.4] assign _T_275 = {auto_out_1_d_bits_opcode,2'h0,3'h4,2'h0,auto_out_1_d_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58972.4] assign _T_276 = _T_251_1 ? _T_275 : 43'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58973.4] assign _T_277 = _T_268 | _T_276; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@58974.4] assign auto_in_a_ready = _T_142 | _T_143; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@58552.4] assign auto_in_d_valid = _T_186 ? _T_235 : _T_258; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@58552.4] assign auto_in_d_bits_denied = _T_277[33]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@58552.4] assign auto_in_d_bits_data = _T_277[32:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@58552.4] assign auto_in_d_bits_corrupt = _T_277[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@58552.4] assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_1_a_bits_address = auto_in_a_bits_address[6:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_1_d_ready = auto_in_d_ready & _T_252_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58551.4] assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign auto_out_0_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign auto_out_0_d_ready = auto_in_d_ready & _T_252_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@58550.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@58499.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@58500.4] assign TLMonitor_io_in_a_ready = _T_142 | _T_143; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_valid = _T_186 ? _T_235 : _T_258; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_opcode = _T_277[42:40]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_param = _T_277[39:38]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_size = _T_277[37:36]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_sink = _T_277[34]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_denied = _T_277[33]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] assign TLMonitor_io_in_d_bits_corrupt = _T_277[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@58545.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_185 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_195 = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_250_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_250_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_185 <= 1'h0; end else begin if (_T_187) begin _T_185 <= 1'h0; end else begin _T_185 <= _T_247; end end if (reset) begin _T_195 <= 2'h3; end else begin if (_T_210) begin _T_195 <= _T_214; end end if (reset) begin _T_250_0 <= 1'h0; end else begin if (_T_186) begin _T_250_0 <= _T_220; end end if (reset) begin _T_250_1 <= 1'h0; end else begin if (_T_186) begin _T_250_1 <= _T_221; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_193) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58862.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_193) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@58863.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_234) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58916.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_234) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@58917.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_241) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58927.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_241) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@58928.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module DMIToTL( // @[:freechips.rocketchip.system.TinyConfig.fir@58996.2] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output [8:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] input auto_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@58999.4] output io_dmi_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] input io_dmi_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] input [6:0] io_dmi_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] input [31:0] io_dmi_req_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] input [1:0] io_dmi_req_bits_op, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] input io_dmi_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] output io_dmi_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] output [31:0] io_dmi_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] output [1:0] io_dmi_resp_bits_resp // @[:freechips.rocketchip.system.TinyConfig.fir@59000.4] ); wire [8:0] addr; // @[DMI.scala 92:50:freechips.rocketchip.system.TinyConfig.fir@59012.4] wire _T_100; // @[DMI.scala 106:30:freechips.rocketchip.system.TinyConfig.fir@59145.4] wire _T_101; // @[DMI.scala 107:37:freechips.rocketchip.system.TinyConfig.fir@59150.6] wire [2:0] _GEN_0; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] wire [8:0] _GEN_4; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] wire [3:0] _GEN_5; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] wire _T_102; // @[DMI.scala 116:53:freechips.rocketchip.system.TinyConfig.fir@59161.4] assign addr = {io_dmi_req_bits_addr, 2'h0}; // @[DMI.scala 92:50:freechips.rocketchip.system.TinyConfig.fir@59012.4] assign _T_100 = io_dmi_req_bits_op == 2'h2; // @[DMI.scala 106:30:freechips.rocketchip.system.TinyConfig.fir@59145.4] assign _T_101 = io_dmi_req_bits_op == 2'h1; // @[DMI.scala 107:37:freechips.rocketchip.system.TinyConfig.fir@59150.6] assign _GEN_0 = _T_101 ? 3'h4 : 3'h1; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] assign _GEN_4 = _T_101 ? addr : 9'h40; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] assign _GEN_5 = _T_101 ? 4'hf : 4'h0; // @[DMI.scala 107:64:freechips.rocketchip.system.TinyConfig.fir@59151.6] assign _T_102 = auto_out_d_bits_corrupt | auto_out_d_bits_denied; // @[DMI.scala 116:53:freechips.rocketchip.system.TinyConfig.fir@59161.4] assign auto_out_a_valid = io_dmi_req_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign auto_out_a_bits_opcode = _T_100 ? 3'h0 : _GEN_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign auto_out_a_bits_address = _T_100 ? addr : _GEN_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign auto_out_a_bits_mask = _T_100 ? 4'hf : _GEN_5; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign auto_out_a_bits_data = _T_100 ? io_dmi_req_bits_data : 32'h0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign auto_out_d_ready = io_dmi_resp_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@59008.4] assign io_dmi_req_ready = auto_out_a_ready; // @[DMI.scala 112:22:freechips.rocketchip.system.TinyConfig.fir@59158.4] assign io_dmi_resp_valid = auto_out_d_valid; // @[DMI.scala 114:28:freechips.rocketchip.system.TinyConfig.fir@59159.4] assign io_dmi_resp_bits_data = auto_out_d_bits_data; // @[DMI.scala 117:28:freechips.rocketchip.system.TinyConfig.fir@59164.4] assign io_dmi_resp_bits_resp = {{1'd0}, _T_102}; // @[DMI.scala 116:28:freechips.rocketchip.system.TinyConfig.fir@59163.4] endmodule module TLMonitor_31( // @[:freechips.rocketchip.system.TinyConfig.fir@59183.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@59184.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@59185.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input [6:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] input [2:0] io_in_d_bits_opcode // @[:freechips.rocketchip.system.TinyConfig.fir@59186.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@60336.4] wire [6:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@59209.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@59210.6] wire _T_57; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@59259.6] wire [6:0] _T_59; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@59262.8] wire [7:0] _T_60; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@59263.8] wire [7:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59264.8] wire [7:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59265.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@59266.8] wire [6:0] _T_64; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@59267.8] wire [7:0] _T_65; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@59268.8] wire [7:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59269.8] wire [7:0] _T_67; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59270.8] wire _T_68; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@59271.8] wire _T_69; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@59272.8] wire _T_74; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59277.8] wire _T_86; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59305.8] wire _T_87; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59306.8] wire [3:0] _T_92; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@59319.8] wire _T_93; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@59320.8] wire _T_95; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59322.8] wire _T_96; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59323.8] wire _T_101; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@59337.6] wire _T_149; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@59423.6] wire _T_168; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59443.8] wire _T_169; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59444.8] wire _T_180; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@59471.8] wire _T_182; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59473.8] wire _T_183; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59474.8] wire _T_188; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@59488.6] wire _T_223; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@59545.6] wire _T_260; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@59604.6] wire _T_292; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@59658.6] wire _T_324; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@59712.6] wire _T_356; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@59768.6] wire _T_358; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59770.6] wire _T_359; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59771.6] wire _T_363; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@59781.6] wire _T_383; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@59823.6] wire _T_411; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@59881.6] wire _T_504; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@60071.4] reg _T_513; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@60080.4] reg [31:0] _RAND_0; wire _T_515; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60082.4] wire _T_516; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60083.4] reg [2:0] _T_524; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@60094.4] reg [31:0] _RAND_1; reg [6:0] _T_528; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@60098.4] reg [31:0] _RAND_2; wire _T_529; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@60099.4] wire _T_530; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@60100.4] wire _T_531; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@60102.6] wire _T_533; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60104.6] wire _T_534; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60105.6] wire _T_547; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@60134.6] wire _T_549; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60136.6] wire _T_550; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60137.6] wire _T_552; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@60144.4] wire _T_553; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@60152.4] reg _T_561; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@60160.4] reg [31:0] _RAND_3; wire _T_563; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60162.4] wire _T_564; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60163.4] reg [2:0] _T_572; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@60174.4] reg [31:0] _RAND_4; wire _T_578; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@60180.4] wire _T_579; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@60181.4] wire _T_580; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@60183.6] wire _T_582; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60185.6] wire _T_583; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60186.6] wire _T_605; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@60233.4] reg _T_606; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@60242.4] reg [31:0] _RAND_5; reg _T_616; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@60252.4] reg [31:0] _RAND_6; wire _T_618; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60254.4] wire _T_619; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60255.4] reg _T_635; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@60274.4] reg [31:0] _RAND_7; wire _T_637; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60276.4] wire _T_638; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60277.4] wire _T_648; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@60292.4] wire _T_653; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@60299.6] wire _T_655; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60301.6] wire _T_656; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60302.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@60294.4] wire _T_660; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@60313.4] wire _T_662; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@60315.4] wire _T_663; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@60316.4] wire _T_646; // @[:freechips.rocketchip.system.TinyConfig.fir@60288.4 :freechips.rocketchip.system.TinyConfig.fir@60290.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@60296.6] wire _T_665; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@60320.6] wire _T_669; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60324.6] wire _T_670; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60325.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@60317.4] wire _T_671; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@60331.4] wire _T_657; // @[:freechips.rocketchip.system.TinyConfig.fir@60308.4 :freechips.rocketchip.system.TinyConfig.fir@60310.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@60319.6] wire _T_672; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@60332.4] wire _T_673; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@60333.4] reg [31:0] _T_674; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@60335.4] reg [31:0] _RAND_8; wire _T_677; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@60340.4] wire _T_678; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@60341.4] wire _T_679; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@60342.4] wire _T_680; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@60343.4] wire _T_682; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60345.4] wire _T_683; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60346.4] wire [31:0] _T_685; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@60352.4] wire _T_688; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@60356.4] wire _GEN_18; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59279.10] wire _GEN_26; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@59357.10] wire _GEN_36; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59446.10] wire _GEN_42; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@59511.10] wire _GEN_48; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@59568.10] wire _GEN_52; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@59624.10] wire _GEN_58; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@59678.10] wire _GEN_64; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@59732.10] wire _GEN_70; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@59836.10] wire _GEN_72; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@59894.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@60336.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_address & 7'h3; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@59209.6] assign _T_12 = _T_11 == 7'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@59210.6] assign _T_57 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@59259.6] assign _T_59 = io_in_a_bits_address ^ 7'h40; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@59262.8] assign _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@59263.8] assign _T_61 = $signed(_T_60) & $signed(-8'sh14); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59264.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59265.8] assign _T_63 = $signed(_T_62) == $signed(8'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@59266.8] assign _T_64 = io_in_a_bits_address ^ 7'h54; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@59267.8] assign _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@59268.8] assign _T_66 = $signed(_T_65) & $signed(-8'sh4); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59269.8] assign _T_67 = $signed(_T_66); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@59270.8] assign _T_68 = $signed(_T_67) == $signed(8'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@59271.8] assign _T_69 = _T_63 | _T_68; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@59272.8] assign _T_74 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59277.8] assign _T_86 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59305.8] assign _T_87 = _T_86 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59306.8] assign _T_92 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@59319.8] assign _T_93 = _T_92 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@59320.8] assign _T_95 = _T_93 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59322.8] assign _T_96 = _T_95 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59323.8] assign _T_101 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@59337.6] assign _T_149 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@59423.6] assign _T_168 = _T_69 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59443.8] assign _T_169 = _T_168 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59444.8] assign _T_180 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@59471.8] assign _T_182 = _T_180 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59473.8] assign _T_183 = _T_182 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59474.8] assign _T_188 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@59488.6] assign _T_223 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@59545.6] assign _T_260 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@59604.6] assign _T_292 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@59658.6] assign _T_324 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@59712.6] assign _T_356 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@59768.6] assign _T_358 = _T_356 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59770.6] assign _T_359 = _T_358 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59771.6] assign _T_363 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@59781.6] assign _T_383 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@59823.6] assign _T_411 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@59881.6] assign _T_504 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@60071.4] assign _T_515 = _T_513 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60082.4] assign _T_516 = _T_513 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60083.4] assign _T_529 = _T_516 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@60099.4] assign _T_530 = io_in_a_valid & _T_529; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@60100.4] assign _T_531 = io_in_a_bits_opcode == _T_524; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@60102.6] assign _T_533 = _T_531 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60104.6] assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60105.6] assign _T_547 = io_in_a_bits_address == _T_528; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@60134.6] assign _T_549 = _T_547 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60136.6] assign _T_550 = _T_549 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60137.6] assign _T_552 = _T_504 & _T_516; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@60144.4] assign _T_553 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@60152.4] assign _T_563 = _T_561 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60162.4] assign _T_564 = _T_561 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60163.4] assign _T_578 = _T_564 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@60180.4] assign _T_579 = io_in_d_valid & _T_578; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@60181.4] assign _T_580 = io_in_d_bits_opcode == _T_572; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@60183.6] assign _T_582 = _T_580 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60185.6] assign _T_583 = _T_582 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60186.6] assign _T_605 = _T_553 & _T_564; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@60233.4] assign _T_618 = _T_616 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60254.4] assign _T_619 = _T_616 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60255.4] assign _T_637 = _T_635 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@60276.4] assign _T_638 = _T_635 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@60277.4] assign _T_648 = _T_504 & _T_619; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@60292.4] assign _T_653 = _T_606 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@60299.6] assign _T_655 = _T_653 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60301.6] assign _T_656 = _T_655 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60302.6] assign _GEN_15 = _T_648 ? 2'h1 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@60294.4] assign _T_660 = _T_553 & _T_638; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@60313.4] assign _T_662 = _T_363 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@60315.4] assign _T_663 = _T_660 & _T_662; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@60316.4] assign _T_646 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@60288.4 :freechips.rocketchip.system.TinyConfig.fir@60290.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@60296.6] assign _T_665 = _T_646 | _T_606; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@60320.6] assign _T_669 = _T_665 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60324.6] assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60325.6] assign _GEN_16 = _T_663 ? 2'h1 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@60317.4] assign _T_671 = _T_606 | _T_646; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@60331.4] assign _T_657 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@60308.4 :freechips.rocketchip.system.TinyConfig.fir@60310.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@60319.6] assign _T_672 = ~ _T_657; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@60332.4] assign _T_673 = _T_671 & _T_672; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@60333.4] assign _T_677 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@60340.4] assign _T_678 = _T_653 | _T_677; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@60341.4] assign _T_679 = _T_674 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@60342.4] assign _T_680 = _T_678 | _T_679; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@60343.4] assign _T_682 = _T_680 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60345.4] assign _T_683 = _T_682 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60346.4] assign _T_685 = _T_674 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@60352.4] assign _T_688 = _T_504 | _T_553; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@60356.4] assign _GEN_18 = io_in_a_valid & _T_57; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59279.10] assign _GEN_26 = io_in_a_valid & _T_101; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@59357.10] assign _GEN_36 = io_in_a_valid & _T_149; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59446.10] assign _GEN_42 = io_in_a_valid & _T_188; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@59511.10] assign _GEN_48 = io_in_a_valid & _T_223; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@59568.10] assign _GEN_52 = io_in_a_valid & _T_260; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@59624.10] assign _GEN_58 = io_in_a_valid & _T_292; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@59678.10] assign _GEN_64 = io_in_a_valid & _T_324; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@59732.10] assign _GEN_70 = io_in_d_valid & _T_383; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@59836.10] assign _GEN_72 = io_in_d_valid & _T_411; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@59894.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_513 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_524 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_528 = _RAND_2[6:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_561 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_572 = _RAND_4[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_606 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_616 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_635 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_674 = _RAND_8[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_513 <= 1'h0; end else begin if (_T_504) begin if (_T_516) begin _T_513 <= 1'h0; end else begin _T_513 <= _T_515; end end end if (_T_552) begin _T_524 <= io_in_a_bits_opcode; end if (_T_552) begin _T_528 <= io_in_a_bits_address; end if (reset) begin _T_561 <= 1'h0; end else begin if (_T_553) begin if (_T_564) begin _T_561 <= 1'h0; end else begin _T_561 <= _T_563; end end end if (_T_605) begin _T_572 <= io_in_d_bits_opcode; end if (reset) begin _T_606 <= 1'h0; end else begin _T_606 <= _T_673; end if (reset) begin _T_616 <= 1'h0; end else begin if (_T_504) begin if (_T_619) begin _T_616 <= 1'h0; end else begin _T_616 <= _T_618; end end end if (reset) begin _T_635 <= 1'h0; end else begin if (_T_553) begin if (_T_638) begin _T_635 <= 1'h0; end else begin _T_635 <= _T_637; end end end if (reset) begin _T_674 <= 32'h0; end else begin if (_T_688) begin _T_674 <= 32'h0; end else begin _T_674 <= _T_685; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59279.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_74) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@59280.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:518:19)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@59286.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_74) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@59287.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59308.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_87) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@59309.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_96) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59325.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_96) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@59326.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@59357.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_74) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@59358.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:518:19)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@59364.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_74) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@59365.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@59386.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_87) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@59387.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:518:19)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@59402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_74) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@59403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_96) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@59411.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_96) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@59412.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59446.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_169) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@59447.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@59460.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_87) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@59461.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_183) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59476.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_183) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@59477.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@59511.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_169) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@59512.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@59525.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_87) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@59526.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_183) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@59541.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_183) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@59542.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_169) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@59568.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_169) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@59569.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@59582.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_87) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@59583.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@59624.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_74) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@59625.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@59638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_87) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@59639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_183) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@59654.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_183) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@59655.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@59678.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_74) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@59679.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@59692.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_87) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@59693.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_183) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@59708.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_183) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@59709.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:518:19)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@59732.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_74) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@59733.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_87) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:518:19)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@59746.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_87) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@59747.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_183) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:518:19)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@59754.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_183) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@59755.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_359) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:518:19)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59773.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_359) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@59774.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:518:19)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@59836.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_74) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@59837.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_72 & _T_74) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:518:19)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@59894.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_72 & _T_74) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@59895.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_530 & _T_534) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:518:19)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60107.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_530 & _T_534) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@60108.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_530 & _T_550) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:518:19)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60139.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_530 & _T_550) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@60140.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_579 & _T_583) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:518:19)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60188.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_579 & _T_583) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@60189.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_648 & _T_656) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:518:19)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60304.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_648 & _T_656) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@60305.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_663 & _T_670) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:518:19)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60327.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_663 & _T_670) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@60328.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_683) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:518:19)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60348.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_683) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@60349.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module AsyncResetRegVec_w32_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@60681.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@60682.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@60683.4] input [31:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@60684.4] output [31:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@60684.4] ); wire reg_0_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] wire reg_0_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] wire reg_0_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] wire reg_0_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] wire reg_0_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] wire reg_1_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] wire reg_1_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] wire reg_1_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] wire reg_1_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] wire reg_1_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] wire reg_2_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] wire reg_2_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] wire reg_2_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] wire reg_2_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] wire reg_2_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] wire reg_3_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] wire reg_3_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] wire reg_3_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] wire reg_3_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] wire reg_3_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] wire reg_4_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] wire reg_4_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] wire reg_4_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] wire reg_4_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] wire reg_4_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] wire reg_5_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] wire reg_5_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] wire reg_5_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] wire reg_5_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] wire reg_5_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] wire reg_6_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] wire reg_6_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] wire reg_6_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] wire reg_6_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] wire reg_6_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] wire reg_7_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] wire reg_7_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] wire reg_7_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] wire reg_7_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] wire reg_7_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] wire reg_8_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] wire reg_8_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] wire reg_8_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] wire reg_8_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] wire reg_8_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] wire reg_9_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] wire reg_9_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] wire reg_9_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] wire reg_9_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] wire reg_9_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] wire reg_10_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] wire reg_10_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] wire reg_10_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] wire reg_10_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] wire reg_10_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] wire reg_11_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] wire reg_11_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] wire reg_11_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] wire reg_11_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] wire reg_11_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] wire reg_12_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] wire reg_12_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] wire reg_12_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] wire reg_12_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] wire reg_12_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] wire reg_13_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] wire reg_13_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] wire reg_13_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] wire reg_13_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] wire reg_13_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] wire reg_14_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] wire reg_14_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] wire reg_14_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] wire reg_14_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] wire reg_14_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] wire reg_15_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] wire reg_15_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] wire reg_15_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] wire reg_15_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] wire reg_15_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] wire reg_16_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] wire reg_16_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] wire reg_16_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] wire reg_16_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] wire reg_16_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] wire reg_17_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] wire reg_17_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] wire reg_17_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] wire reg_17_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] wire reg_17_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] wire reg_18_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] wire reg_18_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] wire reg_18_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] wire reg_18_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] wire reg_18_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] wire reg_19_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] wire reg_19_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] wire reg_19_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] wire reg_19_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] wire reg_19_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] wire reg_20_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] wire reg_20_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] wire reg_20_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] wire reg_20_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] wire reg_20_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] wire reg_21_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] wire reg_21_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] wire reg_21_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] wire reg_21_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] wire reg_21_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] wire reg_22_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] wire reg_22_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] wire reg_22_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] wire reg_22_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] wire reg_22_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] wire reg_23_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] wire reg_23_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] wire reg_23_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] wire reg_23_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] wire reg_23_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] wire reg_24_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] wire reg_24_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] wire reg_24_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] wire reg_24_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] wire reg_24_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] wire reg_25_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] wire reg_25_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] wire reg_25_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] wire reg_25_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] wire reg_25_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] wire reg_26_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] wire reg_26_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] wire reg_26_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] wire reg_26_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] wire reg_26_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] wire reg_27_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] wire reg_27_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] wire reg_27_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] wire reg_27_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] wire reg_27_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] wire reg_28_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] wire reg_28_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] wire reg_28_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] wire reg_28_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] wire reg_28_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] wire reg_29_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] wire reg_29_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] wire reg_29_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] wire reg_29_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] wire reg_29_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] wire reg_30_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] wire reg_30_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] wire reg_30_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] wire reg_30_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] wire reg_30_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] wire reg_31_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] wire reg_31_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] wire reg_31_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] wire reg_31_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] wire reg_31_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] wire [7:0] _T_38; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61047.4] wire [15:0] _T_46; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61055.4] wire [7:0] _T_53; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61062.4] wire [15:0] _T_61; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61070.4] AsyncResetReg #(.RESET_VALUE(0)) reg_0 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60689.4] .d(reg_0_d), .q(reg_0_q), .en(reg_0_en), .clk(reg_0_clk), .rst(reg_0_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_1 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60695.4] .d(reg_1_d), .q(reg_1_q), .en(reg_1_en), .clk(reg_1_clk), .rst(reg_1_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_2 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60701.4] .d(reg_2_d), .q(reg_2_q), .en(reg_2_en), .clk(reg_2_clk), .rst(reg_2_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_3 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60707.4] .d(reg_3_d), .q(reg_3_q), .en(reg_3_en), .clk(reg_3_clk), .rst(reg_3_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_4 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60713.4] .d(reg_4_d), .q(reg_4_q), .en(reg_4_en), .clk(reg_4_clk), .rst(reg_4_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_5 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60719.4] .d(reg_5_d), .q(reg_5_q), .en(reg_5_en), .clk(reg_5_clk), .rst(reg_5_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_6 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60725.4] .d(reg_6_d), .q(reg_6_q), .en(reg_6_en), .clk(reg_6_clk), .rst(reg_6_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_7 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60731.4] .d(reg_7_d), .q(reg_7_q), .en(reg_7_en), .clk(reg_7_clk), .rst(reg_7_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_8 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60737.4] .d(reg_8_d), .q(reg_8_q), .en(reg_8_en), .clk(reg_8_clk), .rst(reg_8_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_9 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60743.4] .d(reg_9_d), .q(reg_9_q), .en(reg_9_en), .clk(reg_9_clk), .rst(reg_9_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_10 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60749.4] .d(reg_10_d), .q(reg_10_q), .en(reg_10_en), .clk(reg_10_clk), .rst(reg_10_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_11 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60755.4] .d(reg_11_d), .q(reg_11_q), .en(reg_11_en), .clk(reg_11_clk), .rst(reg_11_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_12 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60761.4] .d(reg_12_d), .q(reg_12_q), .en(reg_12_en), .clk(reg_12_clk), .rst(reg_12_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_13 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60767.4] .d(reg_13_d), .q(reg_13_q), .en(reg_13_en), .clk(reg_13_clk), .rst(reg_13_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_14 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60773.4] .d(reg_14_d), .q(reg_14_q), .en(reg_14_en), .clk(reg_14_clk), .rst(reg_14_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_15 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60779.4] .d(reg_15_d), .q(reg_15_q), .en(reg_15_en), .clk(reg_15_clk), .rst(reg_15_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_16 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60785.4] .d(reg_16_d), .q(reg_16_q), .en(reg_16_en), .clk(reg_16_clk), .rst(reg_16_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_17 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60791.4] .d(reg_17_d), .q(reg_17_q), .en(reg_17_en), .clk(reg_17_clk), .rst(reg_17_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_18 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60797.4] .d(reg_18_d), .q(reg_18_q), .en(reg_18_en), .clk(reg_18_clk), .rst(reg_18_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_19 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60803.4] .d(reg_19_d), .q(reg_19_q), .en(reg_19_en), .clk(reg_19_clk), .rst(reg_19_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_20 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60809.4] .d(reg_20_d), .q(reg_20_q), .en(reg_20_en), .clk(reg_20_clk), .rst(reg_20_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_21 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60815.4] .d(reg_21_d), .q(reg_21_q), .en(reg_21_en), .clk(reg_21_clk), .rst(reg_21_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_22 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60821.4] .d(reg_22_d), .q(reg_22_q), .en(reg_22_en), .clk(reg_22_clk), .rst(reg_22_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_23 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60827.4] .d(reg_23_d), .q(reg_23_q), .en(reg_23_en), .clk(reg_23_clk), .rst(reg_23_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_24 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60833.4] .d(reg_24_d), .q(reg_24_q), .en(reg_24_en), .clk(reg_24_clk), .rst(reg_24_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_25 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60839.4] .d(reg_25_d), .q(reg_25_q), .en(reg_25_en), .clk(reg_25_clk), .rst(reg_25_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_26 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60845.4] .d(reg_26_d), .q(reg_26_q), .en(reg_26_en), .clk(reg_26_clk), .rst(reg_26_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_27 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60851.4] .d(reg_27_d), .q(reg_27_q), .en(reg_27_en), .clk(reg_27_clk), .rst(reg_27_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_28 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60857.4] .d(reg_28_d), .q(reg_28_q), .en(reg_28_en), .clk(reg_28_clk), .rst(reg_28_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_29 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60863.4] .d(reg_29_d), .q(reg_29_q), .en(reg_29_en), .clk(reg_29_clk), .rst(reg_29_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_30 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60869.4] .d(reg_30_d), .q(reg_30_q), .en(reg_30_en), .clk(reg_30_clk), .rst(reg_30_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_31 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@60875.4] .d(reg_31_d), .q(reg_31_q), .en(reg_31_en), .clk(reg_31_clk), .rst(reg_31_rst) ); assign _T_38 = {reg_7_q,reg_6_q,reg_5_q,reg_4_q,reg_3_q,reg_2_q,reg_1_q,reg_0_q}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61047.4] assign _T_46 = {reg_15_q,reg_14_q,reg_13_q,reg_12_q,reg_11_q,reg_10_q,reg_9_q,reg_8_q,_T_38}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61055.4] assign _T_53 = {reg_23_q,reg_22_q,reg_21_q,reg_20_q,reg_19_q,reg_18_q,reg_17_q,reg_16_q}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61062.4] assign _T_61 = {reg_31_q,reg_30_q,reg_29_q,reg_28_q,reg_27_q,reg_26_q,reg_25_q,reg_24_q,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61070.4] assign io_q = {_T_61,_T_46}; // @[AsyncResetReg.scala 73:8:freechips.rocketchip.system.TinyConfig.fir@61072.4] assign reg_0_d = io_d[0]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60884.4] assign reg_0_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60885.4] assign reg_0_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60881.4] assign reg_0_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60882.4] assign reg_1_d = io_d[1]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60889.4] assign reg_1_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60890.4] assign reg_1_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60886.4] assign reg_1_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60887.4] assign reg_2_d = io_d[2]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60894.4] assign reg_2_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60895.4] assign reg_2_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60891.4] assign reg_2_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60892.4] assign reg_3_d = io_d[3]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60899.4] assign reg_3_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60900.4] assign reg_3_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60896.4] assign reg_3_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60897.4] assign reg_4_d = io_d[4]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60904.4] assign reg_4_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60905.4] assign reg_4_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60901.4] assign reg_4_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60902.4] assign reg_5_d = io_d[5]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60909.4] assign reg_5_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60910.4] assign reg_5_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60906.4] assign reg_5_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60907.4] assign reg_6_d = io_d[6]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60914.4] assign reg_6_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60915.4] assign reg_6_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60911.4] assign reg_6_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60912.4] assign reg_7_d = io_d[7]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60919.4] assign reg_7_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60920.4] assign reg_7_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60916.4] assign reg_7_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60917.4] assign reg_8_d = io_d[8]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60924.4] assign reg_8_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60925.4] assign reg_8_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60921.4] assign reg_8_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60922.4] assign reg_9_d = io_d[9]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60929.4] assign reg_9_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60930.4] assign reg_9_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60926.4] assign reg_9_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60927.4] assign reg_10_d = io_d[10]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60934.4] assign reg_10_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60935.4] assign reg_10_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60931.4] assign reg_10_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60932.4] assign reg_11_d = io_d[11]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60939.4] assign reg_11_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60940.4] assign reg_11_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60936.4] assign reg_11_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60937.4] assign reg_12_d = io_d[12]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60944.4] assign reg_12_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60945.4] assign reg_12_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60941.4] assign reg_12_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60942.4] assign reg_13_d = io_d[13]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60949.4] assign reg_13_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60950.4] assign reg_13_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60946.4] assign reg_13_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60947.4] assign reg_14_d = io_d[14]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60954.4] assign reg_14_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60955.4] assign reg_14_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60951.4] assign reg_14_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60952.4] assign reg_15_d = io_d[15]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60959.4] assign reg_15_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60960.4] assign reg_15_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60956.4] assign reg_15_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60957.4] assign reg_16_d = io_d[16]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60964.4] assign reg_16_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60965.4] assign reg_16_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60961.4] assign reg_16_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60962.4] assign reg_17_d = io_d[17]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60969.4] assign reg_17_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60970.4] assign reg_17_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60966.4] assign reg_17_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60967.4] assign reg_18_d = io_d[18]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60974.4] assign reg_18_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60975.4] assign reg_18_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60971.4] assign reg_18_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60972.4] assign reg_19_d = io_d[19]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60979.4] assign reg_19_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60980.4] assign reg_19_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60976.4] assign reg_19_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60977.4] assign reg_20_d = io_d[20]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60984.4] assign reg_20_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60985.4] assign reg_20_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60981.4] assign reg_20_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60982.4] assign reg_21_d = io_d[21]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60989.4] assign reg_21_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60990.4] assign reg_21_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60986.4] assign reg_21_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60987.4] assign reg_22_d = io_d[22]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60994.4] assign reg_22_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@60995.4] assign reg_22_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60991.4] assign reg_22_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60992.4] assign reg_23_d = io_d[23]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@60999.4] assign reg_23_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61000.4] assign reg_23_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@60996.4] assign reg_23_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@60997.4] assign reg_24_d = io_d[24]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61004.4] assign reg_24_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61005.4] assign reg_24_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61001.4] assign reg_24_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61002.4] assign reg_25_d = io_d[25]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61009.4] assign reg_25_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61010.4] assign reg_25_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61006.4] assign reg_25_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61007.4] assign reg_26_d = io_d[26]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61014.4] assign reg_26_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61015.4] assign reg_26_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61011.4] assign reg_26_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61012.4] assign reg_27_d = io_d[27]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61019.4] assign reg_27_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61020.4] assign reg_27_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61016.4] assign reg_27_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61017.4] assign reg_28_d = io_d[28]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61024.4] assign reg_28_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61025.4] assign reg_28_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61021.4] assign reg_28_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61022.4] assign reg_29_d = io_d[29]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61029.4] assign reg_29_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61030.4] assign reg_29_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61026.4] assign reg_29_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61027.4] assign reg_30_d = io_d[30]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61034.4] assign reg_30_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61035.4] assign reg_30_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61031.4] assign reg_30_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61032.4] assign reg_31_d = io_d[31]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61039.4] assign reg_31_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61040.4] assign reg_31_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61036.4] assign reg_31_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61037.4] endmodule module AsyncResetRegVec_w1_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@61084.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@61085.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@61086.4] input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@61087.4] output io_q, // @[:freechips.rocketchip.system.TinyConfig.fir@61087.4] input io_en // @[:freechips.rocketchip.system.TinyConfig.fir@61087.4] ); wire reg_0_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] wire reg_0_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] wire reg_0_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] wire reg_0_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] wire reg_0_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] AsyncResetReg #(.RESET_VALUE(0)) reg_0 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@61092.4] .d(reg_0_d), .q(reg_0_q), .en(reg_0_en), .clk(reg_0_clk), .rst(reg_0_rst) ); assign io_q = reg_0_q; // @[AsyncResetReg.scala 73:8:freechips.rocketchip.system.TinyConfig.fir@61103.4] assign reg_0_d = io_d; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@61101.4] assign reg_0_en = io_en; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@61102.4] assign reg_0_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@61098.4] assign reg_0_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@61099.4] endmodule module TLDebugModuleOuter( // @[:freechips.rocketchip.system.TinyConfig.fir@61105.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@61106.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@61107.4] output auto_dmi_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input auto_dmi_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input [2:0] auto_dmi_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input [6:0] auto_dmi_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input [3:0] auto_dmi_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input [31:0] auto_dmi_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] input auto_dmi_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] output auto_dmi_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] output [2:0] auto_dmi_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] output [31:0] auto_dmi_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@61108.4] output io_ctrl_ndreset, // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] output io_ctrl_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] output io_innerCtrl_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] output io_innerCtrl_bits_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] output [9:0] io_innerCtrl_bits_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] output io_innerCtrl_bits_ackhavereset // @[:freechips.rocketchip.system.TinyConfig.fir@61109.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire [6:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] wire DMCONTROL_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61250.4] wire DMCONTROL_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61250.4] wire [31:0] DMCONTROL_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61250.4] wire [31:0] DMCONTROL_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61250.4] wire debugInterrupts_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] wire debugInterrupts_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] wire debugInterrupts_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] wire debugInterrupts_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] wire debugInterrupts_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] wire [31:0] _T_56; // @[:freechips.rocketchip.system.TinyConfig.fir@61258.4 :freechips.rocketchip.system.TinyConfig.fir@61260.4] wire DMCONTROLReg_dmactive; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61261.4] wire _T_86; // @[Debug.scala 318:11:freechips.rocketchip.system.TinyConfig.fir@61339.4] wire DMCONTROLReg_clrresethaltreq; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61265.4] wire DMCONTROLNxt_clrresethaltreq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire _T_113; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@61432.4] wire [4:0] _T_114; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@61434.4] wire [2:0] _T_112_bits_index; // @[RegisterRouter.scala 58:18:freechips.rocketchip.system.TinyConfig.fir@61430.4 RegisterRouter.scala 60:19:freechips.rocketchip.system.TinyConfig.fir@61435.4] wire _T_121; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61448.4] wire _T_217; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61568.4] wire _T_218; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61569.4] wire _T_219; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61570.4] wire _T_222; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61574.4] wire _T_145; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61476.4] wire [7:0] _T_153; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61484.4] wire _T_144; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61475.4] wire [7:0] _T_151; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61482.4] wire _T_143; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61474.4] wire [7:0] _T_149; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61480.4] wire _T_142; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61473.4] wire [7:0] _T_147; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61478.4] wire [31:0] _T_156; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61487.4] wire _T_164; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61495.4] wire DMCONTROLWrEn; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61499.4] wire [31:0] DMCONTROLWrDataVal; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@61503.4] wire DMCONTROLWrData_ndmreset; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61303.4] wire DMCONTROLReg_ndmreset; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61263.4] wire _GEN_0; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire DMCONTROLNxt_ndmreset; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLWrData_dmactive; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61301.4] wire _GEN_18; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLNxt_dmactive; // @[Debug.scala 332:26:freechips.rocketchip.system.TinyConfig.fir@61353.4] wire [9:0] DMCONTROLReg_hartselhi; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61271.4] wire [9:0] DMCONTROLNxt_hartselhi; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire [1:0] DMCONTROLReg_reserved1; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61269.4] wire [1:0] DMCONTROLNxt_reserved1; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLReg_setresethaltreq; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61267.4] wire DMCONTROLNxt_setresethaltreq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire [15:0] _T_47; // @[Debug.scala 295:107:freechips.rocketchip.system.TinyConfig.fir@61242.4] wire DMCONTROLReg_reserved0; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61277.4] wire DMCONTROLNxt_reserved0; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLReg_hasel; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61275.4] wire _GEN_5; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire DMCONTROLNxt_hasel; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire [9:0] DMCONTROLReg_hartsello; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61273.4] wire [9:0] _GEN_1; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire [9:0] DMCONTROLNxt_hartsello; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLReg_hartreset; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61281.4] wire DMCONTROLNxt_hartreset; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLWrData_ackhavereset; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61319.4] wire DMCONTROLReg_ackhavereset; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61279.4] wire _GEN_4; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire DMCONTROLNxt_ackhavereset; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLWrData_haltreq; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61325.4] wire DMCONTROLReg_haltreq; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61285.4] wire _GEN_2; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire DMCONTROLNxt_haltreq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire DMCONTROLWrData_resumereq; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61323.4] wire DMCONTROLReg_resumereq; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61283.4] wire _GEN_3; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] wire DMCONTROLNxt_resumereq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] wire [15:0] _T_53; // @[Debug.scala 295:107:freechips.rocketchip.system.TinyConfig.fir@61248.4] wire [15:0] _T_104; // @[Debug.scala 431:72:freechips.rocketchip.system.TinyConfig.fir@61422.4] wire [31:0] _T_111; // @[Debug.scala 431:72:freechips.rocketchip.system.TinyConfig.fir@61429.4] wire debugIntRegs_0; // @[Debug.scala 447:33:freechips.rocketchip.system.TinyConfig.fir@61649.4] wire _GEN_21; // @[Debug.scala 469:96:freechips.rocketchip.system.TinyConfig.fir@61667.6] TLMonitor_31 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@61119.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode) ); AsyncResetRegVec_w32_i0 DMCONTROL ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61250.4] .clock(DMCONTROL_clock), .reset(DMCONTROL_reset), .io_d(DMCONTROL_io_d), .io_q(DMCONTROL_io_q) ); AsyncResetRegVec_w1_i0 debugInterrupts ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@61643.4] .clock(debugInterrupts_clock), .reset(debugInterrupts_reset), .io_d(debugInterrupts_io_d), .io_q(debugInterrupts_io_q), .io_en(debugInterrupts_io_en) ); assign _T_56 = DMCONTROL_io_q; // @[:freechips.rocketchip.system.TinyConfig.fir@61258.4 :freechips.rocketchip.system.TinyConfig.fir@61260.4] assign DMCONTROLReg_dmactive = _T_56[0]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61261.4] assign _T_86 = ~ DMCONTROLReg_dmactive; // @[Debug.scala 318:11:freechips.rocketchip.system.TinyConfig.fir@61339.4] assign DMCONTROLReg_clrresethaltreq = _T_56[2]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61265.4] assign DMCONTROLNxt_clrresethaltreq = _T_86 ? 1'h0 : DMCONTROLReg_clrresethaltreq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign _T_113 = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@61432.4] assign _T_114 = auto_dmi_in_a_bits_address[6:2]; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@61434.4] assign _T_112_bits_index = _T_114[2:0]; // @[RegisterRouter.scala 58:18:freechips.rocketchip.system.TinyConfig.fir@61430.4 RegisterRouter.scala 60:19:freechips.rocketchip.system.TinyConfig.fir@61435.4] assign _T_121 = _T_112_bits_index == 3'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61448.4] assign _T_217 = auto_dmi_in_a_valid & auto_dmi_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61568.4] assign _T_218 = _T_113 == 1'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61569.4] assign _T_219 = _T_217 & _T_218; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61570.4] assign _T_222 = _T_219 & _T_121; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61574.4] assign _T_145 = auto_dmi_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61476.4] assign _T_153 = _T_145 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61484.4] assign _T_144 = auto_dmi_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61475.4] assign _T_151 = _T_144 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61482.4] assign _T_143 = auto_dmi_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61474.4] assign _T_149 = _T_143 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61480.4] assign _T_142 = auto_dmi_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@61473.4] assign _T_147 = _T_142 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@61478.4] assign _T_156 = {_T_153,_T_151,_T_149,_T_147}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@61487.4] assign _T_164 = _T_156 == 32'hffffffff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61495.4] assign DMCONTROLWrEn = _T_222 & _T_164; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@61499.4] assign DMCONTROLWrDataVal = DMCONTROLWrEn ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@61503.4] assign DMCONTROLWrData_ndmreset = DMCONTROLWrDataVal[1]; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61303.4] assign DMCONTROLReg_ndmreset = _T_56[1]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61263.4] assign _GEN_0 = DMCONTROLWrEn ? DMCONTROLWrData_ndmreset : DMCONTROLReg_ndmreset; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_ndmreset = _T_86 ? 1'h0 : _GEN_0; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLWrData_dmactive = DMCONTROLWrDataVal[0]; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61301.4] assign _GEN_18 = _T_86 ? 1'h0 : DMCONTROLReg_dmactive; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLNxt_dmactive = DMCONTROLWrEn ? DMCONTROLWrData_dmactive : _GEN_18; // @[Debug.scala 332:26:freechips.rocketchip.system.TinyConfig.fir@61353.4] assign DMCONTROLReg_hartselhi = _T_56[15:6]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61271.4] assign DMCONTROLNxt_hartselhi = _T_86 ? 10'h0 : DMCONTROLReg_hartselhi; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLReg_reserved1 = _T_56[5:4]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61269.4] assign DMCONTROLNxt_reserved1 = _T_86 ? 2'h0 : DMCONTROLReg_reserved1; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLReg_setresethaltreq = _T_56[3]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61267.4] assign DMCONTROLNxt_setresethaltreq = _T_86 ? 1'h0 : DMCONTROLReg_setresethaltreq; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign _T_47 = {DMCONTROLNxt_hartselhi,DMCONTROLNxt_reserved1,DMCONTROLNxt_setresethaltreq,DMCONTROLNxt_clrresethaltreq,DMCONTROLNxt_ndmreset,DMCONTROLNxt_dmactive}; // @[Debug.scala 295:107:freechips.rocketchip.system.TinyConfig.fir@61242.4] assign DMCONTROLReg_reserved0 = _T_56[27]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61277.4] assign DMCONTROLNxt_reserved0 = _T_86 ? 1'h0 : DMCONTROLReg_reserved0; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLReg_hasel = _T_56[26]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61275.4] assign _GEN_5 = DMCONTROLWrEn ? 1'h0 : DMCONTROLReg_hasel; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_hasel = _T_86 ? 1'h0 : _GEN_5; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLReg_hartsello = _T_56[25:16]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61273.4] assign _GEN_1 = DMCONTROLWrEn ? 10'h0 : DMCONTROLReg_hartsello; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_hartsello = _T_86 ? 10'h0 : _GEN_1; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLReg_hartreset = _T_56[29]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61281.4] assign DMCONTROLNxt_hartreset = _T_86 ? 1'h0 : DMCONTROLReg_hartreset; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLWrData_ackhavereset = DMCONTROLWrDataVal[28]; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61319.4] assign DMCONTROLReg_ackhavereset = _T_56[28]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61279.4] assign _GEN_4 = DMCONTROLWrEn ? DMCONTROLWrData_ackhavereset : DMCONTROLReg_ackhavereset; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_ackhavereset = _T_86 ? 1'h0 : _GEN_4; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLWrData_haltreq = DMCONTROLWrDataVal[31]; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61325.4] assign DMCONTROLReg_haltreq = _T_56[31]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61285.4] assign _GEN_2 = DMCONTROLWrEn ? DMCONTROLWrData_haltreq : DMCONTROLReg_haltreq; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_haltreq = _T_86 ? 1'h0 : _GEN_2; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign DMCONTROLWrData_resumereq = DMCONTROLWrDataVal[30]; // @[Debug.scala 307:47:freechips.rocketchip.system.TinyConfig.fir@61323.4] assign DMCONTROLReg_resumereq = _T_56[30]; // @[Debug.scala 295:66:freechips.rocketchip.system.TinyConfig.fir@61283.4] assign _GEN_3 = DMCONTROLWrEn ? DMCONTROLWrData_resumereq : DMCONTROLReg_resumereq; // @[Debug.scala 321:28:freechips.rocketchip.system.TinyConfig.fir@61344.6] assign DMCONTROLNxt_resumereq = _T_86 ? 1'h0 : _GEN_3; // @[Debug.scala 318:22:freechips.rocketchip.system.TinyConfig.fir@61340.4] assign _T_53 = {DMCONTROLNxt_haltreq,DMCONTROLNxt_resumereq,DMCONTROLNxt_hartreset,DMCONTROLNxt_ackhavereset,DMCONTROLNxt_reserved0,DMCONTROLNxt_hasel,DMCONTROLNxt_hartsello}; // @[Debug.scala 295:107:freechips.rocketchip.system.TinyConfig.fir@61248.4] assign _T_104 = {DMCONTROLReg_hartselhi,DMCONTROLReg_reserved1,DMCONTROLReg_setresethaltreq,DMCONTROLReg_clrresethaltreq,DMCONTROLReg_ndmreset,DMCONTROLReg_dmactive}; // @[Debug.scala 431:72:freechips.rocketchip.system.TinyConfig.fir@61422.4] assign _T_111 = {DMCONTROLReg_haltreq,DMCONTROLReg_resumereq,DMCONTROLReg_hartreset,DMCONTROLReg_ackhavereset,DMCONTROLReg_reserved0,DMCONTROLReg_hasel,DMCONTROLReg_hartsello,_T_104}; // @[Debug.scala 431:72:freechips.rocketchip.system.TinyConfig.fir@61429.4] assign debugIntRegs_0 = debugInterrupts_io_q; // @[Debug.scala 447:33:freechips.rocketchip.system.TinyConfig.fir@61649.4] assign _GEN_21 = DMCONTROLWrEn ? DMCONTROLWrData_haltreq : debugIntRegs_0; // @[Debug.scala 469:96:freechips.rocketchip.system.TinyConfig.fir@61667.6] assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@61169.4] assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@61169.4] assign auto_dmi_in_d_bits_opcode = {{2'd0}, _T_113}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@61169.4] assign auto_dmi_in_d_bits_data = _T_121 ? _T_111 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@61169.4] assign auto_int_out_0 = debugInterrupts_io_q; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@61168.4] assign io_ctrl_ndreset = _T_56[1]; // @[Debug.scala 484:21:freechips.rocketchip.system.TinyConfig.fir@61680.4] assign io_ctrl_dmactive = _T_56[0]; // @[Debug.scala 485:22:freechips.rocketchip.system.TinyConfig.fir@61681.4] assign io_innerCtrl_valid = _T_222 & _T_164; // @[Debug.scala 475:24:freechips.rocketchip.system.TinyConfig.fir@61673.4] assign io_innerCtrl_bits_resumereq = DMCONTROLWrEn & DMCONTROLWrData_resumereq; // @[Debug.scala 477:36:freechips.rocketchip.system.TinyConfig.fir@61677.4] assign io_innerCtrl_bits_hartsel = DMCONTROLWrEn ? 10'h0 : DMCONTROLReg_hartsello; // @[Debug.scala 476:36:freechips.rocketchip.system.TinyConfig.fir@61675.4] assign io_innerCtrl_bits_ackhavereset = DMCONTROLWrEn & DMCONTROLWrData_ackhavereset; // @[Debug.scala 478:36:freechips.rocketchip.system.TinyConfig.fir@61679.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@61121.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@61122.4] assign TLMonitor_io_in_a_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_a_bits_mask = auto_dmi_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_d_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_113}; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@61167.4] assign DMCONTROL_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@61252.4] assign DMCONTROL_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@61253.4] assign DMCONTROL_io_d = {_T_53,_T_47}; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@61254.4] assign debugInterrupts_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@61645.4] assign debugInterrupts_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@61646.4] assign debugInterrupts_io_d = _T_86 ? 1'h0 : _GEN_21; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@61647.4] assign debugInterrupts_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@61648.4] endmodule module IntSyncCrossingSource( // @[:freechips.rocketchip.system.TinyConfig.fir@61683.2] input auto_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@61686.4] output auto_out_sync_0 // @[:freechips.rocketchip.system.TinyConfig.fir@61686.4] ); assign auto_out_sync_0 = auto_in_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@61695.4] endmodule module TLMonitor_32( // @[:freechips.rocketchip.system.TinyConfig.fir@61707.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@61708.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@61709.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [8:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@61710.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@63063.4] wire [8:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@61733.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@61734.6] wire [9:0] _T_49; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61771.6] wire _T_57; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@61783.6] wire [9:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61788.8] wire [9:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61789.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61790.8] wire [8:0] _T_64; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61791.8] wire [9:0] _T_65; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61792.8] wire [9:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61793.8] wire [9:0] _T_67; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61794.8] wire _T_68; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61795.8] wire [8:0] _T_69; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61796.8] wire [9:0] _T_70; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61797.8] wire [9:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61798.8] wire [9:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61799.8] wire _T_73; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61800.8] wire [8:0] _T_74; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61801.8] wire [9:0] _T_75; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61802.8] wire [9:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61803.8] wire [9:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61804.8] wire _T_78; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61805.8] wire [8:0] _T_79; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61806.8] wire [9:0] _T_80; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61807.8] wire [9:0] _T_81; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61808.8] wire [9:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61809.8] wire _T_83; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61810.8] wire [8:0] _T_84; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61811.8] wire [9:0] _T_85; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61812.8] wire [9:0] _T_86; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61813.8] wire [9:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61814.8] wire _T_88; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61815.8] wire _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61816.8] wire _T_90; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61817.8] wire _T_91; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61818.8] wire _T_92; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61819.8] wire _T_93; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61820.8] wire _T_98; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61825.8] wire _T_110; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61853.8] wire _T_111; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61854.8] wire [3:0] _T_116; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@61867.8] wire _T_117; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@61868.8] wire _T_119; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61870.8] wire _T_120; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61871.8] wire _T_125; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@61885.6] wire _T_197; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@61995.6] wire _T_240; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62039.8] wire _T_241; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62040.8] wire _T_252; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@62067.8] wire _T_254; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62069.8] wire _T_255; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62070.8] wire _T_260; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@62084.6] wire _T_319; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@62165.6] wire _T_380; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@62248.6] wire _T_436; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@62326.6] wire _T_492; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@62404.6] wire _T_548; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@62484.6] wire _T_550; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62486.6] wire _T_551; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62487.6] wire _T_552; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@62492.6] wire _T_555; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@62497.6] wire _T_557; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62500.8] wire _T_558; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62501.8] wire _T_559; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@62506.8] wire _T_561; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62508.8] wire _T_562; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62509.8] wire _T_563; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@62514.8] wire _T_565; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62516.8] wire _T_566; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62517.8] wire _T_567; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@62522.8] wire _T_569; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62524.8] wire _T_570; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62525.8] wire _T_571; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@62530.8] wire _T_573; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62532.8] wire _T_574; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62533.8] wire _T_575; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@62539.6] wire _T_586; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@62563.8] wire _T_588; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62565.8] wire _T_589; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62566.8] wire _T_590; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@62571.8] wire _T_592; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62573.8] wire _T_593; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62574.8] wire _T_603; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@62597.6] wire _T_623; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@62638.8] wire _T_625; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62640.8] wire _T_626; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62641.8] wire _T_632; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@62656.6] wire _T_649; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@62691.6] wire _T_667; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@62727.6] wire _T_696; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@62787.4] reg _T_705; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@62796.4] reg [31:0] _RAND_0; wire _T_707; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62798.4] wire _T_708; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62799.4] reg [2:0] _T_716; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@62810.4] reg [31:0] _RAND_1; reg [8:0] _T_720; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@62814.4] reg [31:0] _RAND_2; wire _T_721; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@62815.4] wire _T_722; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@62816.4] wire _T_723; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@62818.6] wire _T_725; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62820.6] wire _T_726; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62821.6] wire _T_739; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@62850.6] wire _T_741; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62852.6] wire _T_742; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62853.6] wire _T_744; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@62860.4] wire _T_745; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@62868.4] reg _T_753; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@62876.4] reg [31:0] _RAND_3; wire _T_755; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62878.4] wire _T_756; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62879.4] reg [2:0] _T_764; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@62890.4] reg [31:0] _RAND_4; reg [1:0] _T_765; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@62891.4] reg [31:0] _RAND_5; reg [1:0] _T_766; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@62892.4] reg [31:0] _RAND_6; reg _T_767; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@62893.4] reg [31:0] _RAND_7; reg _T_768; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@62894.4] reg [31:0] _RAND_8; reg _T_769; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@62895.4] reg [31:0] _RAND_9; wire _T_770; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@62896.4] wire _T_771; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@62897.4] wire _T_772; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@62899.6] wire _T_774; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62901.6] wire _T_775; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62902.6] wire _T_776; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@62907.6] wire _T_778; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62909.6] wire _T_779; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62910.6] wire _T_780; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@62915.6] wire _T_782; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62917.6] wire _T_783; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62918.6] wire _T_784; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@62923.6] wire _T_786; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62925.6] wire _T_787; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62926.6] wire _T_788; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@62931.6] wire _T_790; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62933.6] wire _T_791; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62934.6] wire _T_792; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@62939.6] wire _T_794; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62941.6] wire _T_795; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62942.6] wire _T_797; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@62949.4] reg _T_798; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@62958.4] reg [31:0] _RAND_10; reg _T_808; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@62968.4] reg [31:0] _RAND_11; wire _T_810; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62970.4] wire _T_811; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62971.4] reg _T_827; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@62990.4] reg [31:0] _RAND_12; wire _T_829; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62992.4] wire _T_830; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62993.4] wire _T_840; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@63008.4] wire _T_845; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@63015.6] wire _T_847; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63017.6] wire _T_848; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63018.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@63010.4] wire _T_852; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@63029.4] wire _T_854; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@63031.4] wire _T_855; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@63032.4] wire [1:0] _T_856; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@63034.6] wire _T_838; // @[:freechips.rocketchip.system.TinyConfig.fir@63004.4 :freechips.rocketchip.system.TinyConfig.fir@63006.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@63012.6] wire _T_857; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@63036.6] wire _T_858; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@63037.6] wire _T_861; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63040.6] wire _T_862; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63041.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@63033.4] wire _T_849; // @[:freechips.rocketchip.system.TinyConfig.fir@63024.4 :freechips.rocketchip.system.TinyConfig.fir@63026.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@63035.6] wire _T_863; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@63047.4] wire _T_865; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@63049.4] wire _T_866; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@63050.4] wire _T_868; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63052.4] wire _T_869; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63053.4] wire _T_870; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@63058.4] wire _T_871; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@63059.4] wire _T_872; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@63060.4] reg [31:0] _T_873; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@63062.4] reg [31:0] _RAND_13; wire _T_876; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@63067.4] wire _T_877; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@63068.4] wire _T_878; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@63069.4] wire _T_879; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@63070.4] wire _T_881; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63072.4] wire _T_882; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63073.4] wire [31:0] _T_884; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@63079.4] wire _T_887; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@63083.4] wire _GEN_18; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61827.10] wire _GEN_26; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@61929.10] wire _GEN_36; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62042.10] wire _GEN_42; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@62131.10] wire _GEN_48; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@62212.10] wire _GEN_52; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@62292.10] wire _GEN_58; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@62370.10] wire _GEN_64; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@62448.10] wire _GEN_70; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62503.10] wire _GEN_80; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@62545.10] wire _GEN_94; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@62603.10] wire _GEN_108; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@62662.10] wire _GEN_116; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@62697.10] wire _GEN_124; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@62733.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@63063.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_address & 9'h3; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@61733.6] assign _T_12 = _T_11 == 9'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@61734.6] assign _T_49 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61771.6] assign _T_57 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@61783.6] assign _T_61 = $signed(_T_49) & $signed(-10'sh40); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61788.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61789.8] assign _T_63 = $signed(_T_62) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61790.8] assign _T_64 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61791.8] assign _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61792.8] assign _T_66 = $signed(_T_65) & $signed(-10'sh4); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61793.8] assign _T_67 = $signed(_T_66); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61794.8] assign _T_68 = $signed(_T_67) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61795.8] assign _T_69 = io_in_a_bits_address ^ 9'h48; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61796.8] assign _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61797.8] assign _T_71 = $signed(_T_70) & $signed(-10'sh18); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61798.8] assign _T_72 = $signed(_T_71); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61799.8] assign _T_73 = $signed(_T_72) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61800.8] assign _T_74 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61801.8] assign _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61802.8] assign _T_76 = $signed(_T_75) & $signed(-10'sh20); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61803.8] assign _T_77 = $signed(_T_76); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61804.8] assign _T_78 = $signed(_T_77) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61805.8] assign _T_79 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61806.8] assign _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61807.8] assign _T_81 = $signed(_T_80) & $signed(-10'sh80); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61808.8] assign _T_82 = $signed(_T_81); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61809.8] assign _T_83 = $signed(_T_82) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61810.8] assign _T_84 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@61811.8] assign _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@61812.8] assign _T_86 = $signed(_T_85) & $signed(-10'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61813.8] assign _T_87 = $signed(_T_86); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@61814.8] assign _T_88 = $signed(_T_87) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@61815.8] assign _T_89 = _T_63 | _T_68; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61816.8] assign _T_90 = _T_89 | _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61817.8] assign _T_91 = _T_90 | _T_78; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61818.8] assign _T_92 = _T_91 | _T_83; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61819.8] assign _T_93 = _T_92 | _T_88; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@61820.8] assign _T_98 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61825.8] assign _T_110 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61853.8] assign _T_111 = _T_110 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61854.8] assign _T_116 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@61867.8] assign _T_117 = _T_116 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@61868.8] assign _T_119 = _T_117 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61870.8] assign _T_120 = _T_119 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61871.8] assign _T_125 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@61885.6] assign _T_197 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@61995.6] assign _T_240 = _T_93 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62039.8] assign _T_241 = _T_240 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62040.8] assign _T_252 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@62067.8] assign _T_254 = _T_252 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62069.8] assign _T_255 = _T_254 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62070.8] assign _T_260 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@62084.6] assign _T_319 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@62165.6] assign _T_380 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@62248.6] assign _T_436 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@62326.6] assign _T_492 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@62404.6] assign _T_548 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@62484.6] assign _T_550 = _T_548 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62486.6] assign _T_551 = _T_550 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62487.6] assign _T_552 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@62492.6] assign _T_555 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@62497.6] assign _T_557 = _T_552 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62500.8] assign _T_558 = _T_557 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62501.8] assign _T_559 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@62506.8] assign _T_561 = _T_559 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62508.8] assign _T_562 = _T_561 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62509.8] assign _T_563 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@62514.8] assign _T_565 = _T_563 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62516.8] assign _T_566 = _T_565 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62517.8] assign _T_567 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@62522.8] assign _T_569 = _T_567 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62524.8] assign _T_570 = _T_569 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62525.8] assign _T_571 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@62530.8] assign _T_573 = _T_571 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62532.8] assign _T_574 = _T_573 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62533.8] assign _T_575 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@62539.6] assign _T_586 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@62563.8] assign _T_588 = _T_586 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62565.8] assign _T_589 = _T_588 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62566.8] assign _T_590 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@62571.8] assign _T_592 = _T_590 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62573.8] assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62574.8] assign _T_603 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@62597.6] assign _T_623 = _T_571 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@62638.8] assign _T_625 = _T_623 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62640.8] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62641.8] assign _T_632 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@62656.6] assign _T_649 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@62691.6] assign _T_667 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@62727.6] assign _T_696 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@62787.4] assign _T_707 = _T_705 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62798.4] assign _T_708 = _T_705 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62799.4] assign _T_721 = _T_708 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@62815.4] assign _T_722 = io_in_a_valid & _T_721; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@62816.4] assign _T_723 = io_in_a_bits_opcode == _T_716; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@62818.6] assign _T_725 = _T_723 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62820.6] assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62821.6] assign _T_739 = io_in_a_bits_address == _T_720; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@62850.6] assign _T_741 = _T_739 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62852.6] assign _T_742 = _T_741 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62853.6] assign _T_744 = _T_696 & _T_708; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@62860.4] assign _T_745 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@62868.4] assign _T_755 = _T_753 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62878.4] assign _T_756 = _T_753 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62879.4] assign _T_770 = _T_756 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@62896.4] assign _T_771 = io_in_d_valid & _T_770; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@62897.4] assign _T_772 = io_in_d_bits_opcode == _T_764; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@62899.6] assign _T_774 = _T_772 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62901.6] assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62902.6] assign _T_776 = io_in_d_bits_param == _T_765; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@62907.6] assign _T_778 = _T_776 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62909.6] assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62910.6] assign _T_780 = io_in_d_bits_size == _T_766; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@62915.6] assign _T_782 = _T_780 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62917.6] assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62918.6] assign _T_784 = io_in_d_bits_source == _T_767; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@62923.6] assign _T_786 = _T_784 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62925.6] assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62926.6] assign _T_788 = io_in_d_bits_sink == _T_768; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@62931.6] assign _T_790 = _T_788 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62933.6] assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62934.6] assign _T_792 = io_in_d_bits_denied == _T_769; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@62939.6] assign _T_794 = _T_792 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62941.6] assign _T_795 = _T_794 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62942.6] assign _T_797 = _T_745 & _T_756; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@62949.4] assign _T_810 = _T_808 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62970.4] assign _T_811 = _T_808 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62971.4] assign _T_829 = _T_827 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@62992.4] assign _T_830 = _T_827 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@62993.4] assign _T_840 = _T_696 & _T_811; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@63008.4] assign _T_845 = _T_798 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@63015.6] assign _T_847 = _T_845 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63017.6] assign _T_848 = _T_847 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63018.6] assign _GEN_15 = _T_840 ? 2'h1 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@63010.4] assign _T_852 = _T_745 & _T_830; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@63029.4] assign _T_854 = _T_555 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@63031.4] assign _T_855 = _T_852 & _T_854; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@63032.4] assign _T_856 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@63034.6] assign _T_838 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@63004.4 :freechips.rocketchip.system.TinyConfig.fir@63006.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@63012.6] assign _T_857 = _T_838 | _T_798; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@63036.6] assign _T_858 = _T_857 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@63037.6] assign _T_861 = _T_858 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63040.6] assign _T_862 = _T_861 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63041.6] assign _GEN_16 = _T_855 ? _T_856 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@63033.4] assign _T_849 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@63024.4 :freechips.rocketchip.system.TinyConfig.fir@63026.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@63035.6] assign _T_863 = _T_838 != _T_849; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@63047.4] assign _T_865 = _T_838 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@63049.4] assign _T_866 = _T_863 | _T_865; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@63050.4] assign _T_868 = _T_866 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63052.4] assign _T_869 = _T_868 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63053.4] assign _T_870 = _T_798 | _T_838; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@63058.4] assign _T_871 = ~ _T_849; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@63059.4] assign _T_872 = _T_870 & _T_871; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@63060.4] assign _T_876 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@63067.4] assign _T_877 = _T_845 | _T_876; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@63068.4] assign _T_878 = _T_873 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@63069.4] assign _T_879 = _T_877 | _T_878; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@63070.4] assign _T_881 = _T_879 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63072.4] assign _T_882 = _T_881 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63073.4] assign _T_884 = _T_873 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@63079.4] assign _T_887 = _T_696 | _T_745; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@63083.4] assign _GEN_18 = io_in_a_valid & _T_57; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61827.10] assign _GEN_26 = io_in_a_valid & _T_125; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@61929.10] assign _GEN_36 = io_in_a_valid & _T_197; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62042.10] assign _GEN_42 = io_in_a_valid & _T_260; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@62131.10] assign _GEN_48 = io_in_a_valid & _T_319; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@62212.10] assign _GEN_52 = io_in_a_valid & _T_380; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@62292.10] assign _GEN_58 = io_in_a_valid & _T_436; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@62370.10] assign _GEN_64 = io_in_a_valid & _T_492; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@62448.10] assign _GEN_70 = io_in_d_valid & _T_555; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62503.10] assign _GEN_80 = io_in_d_valid & _T_575; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@62545.10] assign _GEN_94 = io_in_d_valid & _T_603; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@62603.10] assign _GEN_108 = io_in_d_valid & _T_632; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@62662.10] assign _GEN_116 = io_in_d_valid & _T_649; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@62697.10] assign _GEN_124 = io_in_d_valid & _T_667; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@62733.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_705 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_716 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_720 = _RAND_2[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_753 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_764 = _RAND_4[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_765 = _RAND_5[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_766 = _RAND_6[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_767 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_768 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_769 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_798 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_808 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_827 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_873 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_705 <= 1'h0; end else begin if (_T_696) begin if (_T_708) begin _T_705 <= 1'h0; end else begin _T_705 <= _T_707; end end end if (_T_744) begin _T_716 <= io_in_a_bits_opcode; end if (_T_744) begin _T_720 <= io_in_a_bits_address; end if (reset) begin _T_753 <= 1'h0; end else begin if (_T_745) begin if (_T_756) begin _T_753 <= 1'h0; end else begin _T_753 <= _T_755; end end end if (_T_797) begin _T_764 <= io_in_d_bits_opcode; end if (_T_797) begin _T_765 <= io_in_d_bits_param; end if (_T_797) begin _T_766 <= io_in_d_bits_size; end if (_T_797) begin _T_767 <= io_in_d_bits_source; end if (_T_797) begin _T_768 <= io_in_d_bits_sink; end if (_T_797) begin _T_769 <= io_in_d_bits_denied; end if (reset) begin _T_798 <= 1'h0; end else begin _T_798 <= _T_872; end if (reset) begin _T_808 <= 1'h0; end else begin if (_T_696) begin if (_T_811) begin _T_808 <= 1'h0; end else begin _T_808 <= _T_810; end end end if (reset) begin _T_827 <= 1'h0; end else begin if (_T_745) begin if (_T_830) begin _T_827 <= 1'h0; end else begin _T_827 <= _T_829; end end end if (reset) begin _T_873 <= 32'h0; end else begin if (_T_887) begin _T_873 <= 32'h0; end else begin _T_873 <= _T_884; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61827.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_98) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@61828.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:517:46)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@61834.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_98) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@61835.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61856.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_111) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@61857.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_120) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61873.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_120) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@61874.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@61929.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_98) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@61930.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:517:46)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@61936.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_98) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@61937.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@61958.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_111) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@61959.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:517:46)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@61974.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_98) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@61975.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_120) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@61983.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_120) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@61984.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62042.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_241) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@62043.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@62056.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_111) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@62057.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_255) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@62073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@62131.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_241) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@62132.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@62145.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_111) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@62146.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_42 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@62161.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_42 & _T_255) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@62162.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@62212.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_241) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@62213.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_48 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@62226.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_48 & _T_111) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@62227.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@62292.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_98) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@62293.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@62306.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_111) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@62307.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_52 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@62322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_52 & _T_255) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@62323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@62370.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_98) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@62371.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@62384.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_111) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@62385.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_58 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@62400.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_58 & _T_255) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@62401.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:517:46)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@62448.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_98) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@62449.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:517:46)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@62462.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_111) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@62463.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_64 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:517:46)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@62470.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_64 & _T_255) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@62471.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_551) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:517:46)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62489.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_551) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@62490.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62503.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_558) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@62504.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:517:46)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62511.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_562) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@62512.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_566) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:517:46)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62519.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_566) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@62520.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_570) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62527.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_570) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@62528.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_70 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:517:46)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62535.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_70 & _T_574) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@62536.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@62545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_558) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@62546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:517:46)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@62552.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_98) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@62553.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:517:46)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@62560.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_562) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@62561.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_589) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:517:46)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62568.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_589) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@62569.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_593) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:517:46)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62576.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_593) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@62577.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_570) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@62584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_570) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@62585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_80 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:517:46)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@62593.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_80 & _T_574) begin $fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.TinyConfig.fir@62594.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@62603.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_558) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@62604.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:517:46)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@62610.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_98) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@62611.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:517:46)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@62618.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_562) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@62619.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_589) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:517:46)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@62626.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_589) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@62627.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_593) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:517:46)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@62634.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_593) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@62635.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_626) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62643.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_626) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@62644.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_94 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:517:46)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@62652.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_94 & _T_574) begin $fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.TinyConfig.fir@62653.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@62662.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_558) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@62663.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_566) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:517:46)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@62670.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_566) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@62671.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_570) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@62678.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_570) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@62679.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_108 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:517:46)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@62687.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_108 & _T_574) begin $fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.TinyConfig.fir@62688.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_116 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@62697.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_116 & _T_558) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@62698.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_116 & _T_566) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:517:46)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@62705.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_116 & _T_566) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@62706.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_116 & _T_626) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@62714.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_116 & _T_626) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@62715.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_116 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:517:46)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@62723.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_116 & _T_574) begin $fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@62724.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_124 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:517:46)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@62733.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_124 & _T_558) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@62734.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_124 & _T_566) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:517:46)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@62741.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_124 & _T_566) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@62742.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_124 & _T_570) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:517:46)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@62749.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_124 & _T_570) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@62750.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_124 & _T_574) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:517:46)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@62758.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_124 & _T_574) begin $fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.TinyConfig.fir@62759.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_726) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62823.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_726) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@62824.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_742) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62855.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_742) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@62856.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_775) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62904.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_775) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@62905.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_779) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62912.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_779) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@62913.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_783) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62920.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_783) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@62921.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_787) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62928.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_787) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@62929.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_791) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62936.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_791) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@62937.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_795) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:517:46)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62944.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_795) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@62945.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_840 & _T_848) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:517:46)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63020.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_840 & _T_848) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@63021.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_855 & _T_862) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:517:46)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63043.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_855 & _T_862) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@63044.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_869) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Debug.scala:517:46)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63055.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_869) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@63056.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_882) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:517:46)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63075.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_882) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@63076.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@63212.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63213.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63214.4] input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@63215.4] output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@63215.4] ); wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] wire sync_1_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] wire sync_1_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] wire sync_1_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] wire sync_1_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] wire sync_1_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] wire sync_2_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] wire sync_2_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] wire sync_2_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] wire sync_2_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] wire sync_2_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63220.4] .clock(sync_0_clock), .reset(sync_0_reset), .io_d(sync_0_io_d), .io_q(sync_0_io_q), .io_en(sync_0_io_en) ); AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63224.4] .clock(sync_1_clock), .reset(sync_1_reset), .io_d(sync_1_io_d), .io_q(sync_1_io_q), .io_en(sync_1_io_en) ); AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63228.4] .clock(sync_2_clock), .reset(sync_2_reset), .io_d(sync_2_io_d), .io_q(sync_2_io_q), .io_en(sync_2_io_en) ); assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.TinyConfig.fir@63238.4] assign sync_0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63222.4] assign sync_0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63223.4] assign sync_0_io_d = sync_1_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.TinyConfig.fir@63234.4] assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@63235.4] assign sync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63226.4] assign sync_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63227.4] assign sync_1_io_d = sync_2_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.TinyConfig.fir@63236.4] assign sync_1_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@63237.4] assign sync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63230.4] assign sync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63231.4] assign sync_2_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.TinyConfig.fir@63232.4] assign sync_2_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.TinyConfig.fir@63233.4] endmodule module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@63426.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63427.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63428.4] input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@63429.4] output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@63429.4] ); wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] wire sync_1_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] wire sync_1_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] wire sync_1_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] wire sync_1_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] wire sync_1_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] wire sync_2_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] wire sync_2_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] wire sync_2_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] wire sync_2_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] wire sync_2_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] wire sync_3_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] wire sync_3_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] wire sync_3_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] wire sync_3_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] wire sync_3_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63434.4] .clock(sync_0_clock), .reset(sync_0_reset), .io_d(sync_0_io_d), .io_q(sync_0_io_q), .io_en(sync_0_io_en) ); AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63438.4] .clock(sync_1_clock), .reset(sync_1_reset), .io_d(sync_1_io_d), .io_q(sync_1_io_q), .io_en(sync_1_io_en) ); AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63442.4] .clock(sync_2_clock), .reset(sync_2_reset), .io_d(sync_2_io_d), .io_q(sync_2_io_q), .io_en(sync_2_io_en) ); AsyncResetRegVec_w1_i0 sync_3 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63446.4] .clock(sync_3_clock), .reset(sync_3_reset), .io_d(sync_3_io_d), .io_q(sync_3_io_q), .io_en(sync_3_io_en) ); assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.TinyConfig.fir@63458.4] assign sync_0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63436.4] assign sync_0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63437.4] assign sync_0_io_d = sync_1_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.TinyConfig.fir@63452.4] assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@63453.4] assign sync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63440.4] assign sync_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63441.4] assign sync_1_io_d = sync_2_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.TinyConfig.fir@63454.4] assign sync_1_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@63455.4] assign sync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63444.4] assign sync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63445.4] assign sync_2_io_d = sync_3_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.TinyConfig.fir@63456.4] assign sync_2_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@63457.4] assign sync_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63448.4] assign sync_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63449.4] assign sync_3_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.TinyConfig.fir@63450.4] assign sync_3_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.TinyConfig.fir@63451.4] endmodule module AsyncValidSync( // @[:freechips.rocketchip.system.TinyConfig.fir@63460.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63461.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63462.4] output io_out // @[:freechips.rocketchip.system.TinyConfig.fir@63463.4] ); wire source_valid_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63465.4] wire source_valid_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63465.4] wire source_valid_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63465.4] wire source_valid_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63465.4] AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63465.4] .clock(source_valid_clock), .reset(source_valid_reset), .io_d(source_valid_io_d), .io_q(source_valid_io_q) ); assign io_out = source_valid_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.TinyConfig.fir@63473.4] assign source_valid_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63467.4] assign source_valid_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63468.4] assign source_valid_io_d = 1'h1; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@63469.4] endmodule module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@63506.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63507.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63508.4] input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@63509.4] output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@63509.4] ); wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.TinyConfig.fir@63514.4] .clock(sync_0_clock), .reset(sync_0_reset), .io_d(sync_0_io_d), .io_q(sync_0_io_q), .io_en(sync_0_io_en) ); assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.TinyConfig.fir@63520.4] assign sync_0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63516.4] assign sync_0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63517.4] assign sync_0_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.TinyConfig.fir@63518.4] assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.TinyConfig.fir@63519.4] endmodule module AsyncValidSync_1( // @[:freechips.rocketchip.system.TinyConfig.fir@63522.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63523.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63524.4] input io_in, // @[:freechips.rocketchip.system.TinyConfig.fir@63525.4] output io_out // @[:freechips.rocketchip.system.TinyConfig.fir@63525.4] ); wire sink_extend_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63527.4] wire sink_extend_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63527.4] wire sink_extend_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63527.4] wire sink_extend_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63527.4] AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63527.4] .clock(sink_extend_clock), .reset(sink_extend_reset), .io_d(sink_extend_io_d), .io_q(sink_extend_io_q) ); assign io_out = sink_extend_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.TinyConfig.fir@63535.4] assign sink_extend_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63529.4] assign sink_extend_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63530.4] assign sink_extend_io_d = io_in; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@63531.4] endmodule module AsyncValidSync_2( // @[:freechips.rocketchip.system.TinyConfig.fir@63658.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63659.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63660.4] input io_in, // @[:freechips.rocketchip.system.TinyConfig.fir@63661.4] output io_out // @[:freechips.rocketchip.system.TinyConfig.fir@63661.4] ); wire sink_valid_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63663.4] wire sink_valid_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63663.4] wire sink_valid_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63663.4] wire sink_valid_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63663.4] AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63663.4] .clock(sink_valid_clock), .reset(sink_valid_reset), .io_d(sink_valid_io_d), .io_q(sink_valid_io_q) ); assign io_out = sink_valid_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.TinyConfig.fir@63671.4] assign sink_valid_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63665.4] assign sink_valid_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63666.4] assign sink_valid_io_d = io_in; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@63667.4] endmodule module AsyncQueueSource( // @[:freechips.rocketchip.system.TinyConfig.fir@63673.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63674.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@63675.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input [8:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output [2:0] io_async_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output [8:0] io_async_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output [3:0] io_async_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output [31:0] io_async_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] input io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] output io_async_safe_source_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@63676.4] ); wire widx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] wire widx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] wire widx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] wire widx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] wire widx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] wire ridx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63696.4] wire ridx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63696.4] wire ridx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63696.4] wire ridx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63696.4] wire ready_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] wire ready_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] wire ready_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] wire ready_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] wire ready_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] wire widx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] wire widx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] wire widx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] wire widx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] wire widx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@63742.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@63742.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@63742.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@63745.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@63745.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@63745.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@63745.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@63748.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@63748.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@63748.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@63748.4] reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@63680.4] reg [31:0] _RAND_0; reg [8:0] mem_0_address; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@63680.4] reg [31:0] _RAND_1; reg [3:0] mem_0_mask; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@63680.4] reg [31:0] _RAND_2; reg [31:0] mem_0_data; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@63680.4] reg [31:0] _RAND_3; wire _T; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@63681.4] wire sink_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@63678.4 :freechips.rocketchip.system.TinyConfig.fir@63679.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@63763.4] wire _T_1; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@63682.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@63691.4] wire widx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@63692.4] wire ridx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@63701.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@63703.4] wire _T_7; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@63704.4] wire _T_8; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@63705.4] wire ready_reg_1; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@63724.4] AsyncResetRegVec_w1_i0 widx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63684.4] .clock(widx_bin_clock), .reset(widx_bin_reset), .io_d(widx_bin_io_d), .io_q(widx_bin_io_q), .io_en(widx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@63696.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q) ); AsyncResetRegVec_w1_i0 ready_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63718.4] .clock(ready_reg_clock), .reset(ready_reg_reset), .io_d(ready_reg_io_d), .io_q(ready_reg_io_q), .io_en(ready_reg_io_en) ); AsyncResetRegVec_w1_i0 widx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@63727.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q), .io_en(widx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@63742.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@63745.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@63748.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); assign _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@63681.4] assign sink_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@63678.4 :freechips.rocketchip.system.TinyConfig.fir@63679.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@63763.4] assign _T_1 = sink_ready == 1'h0; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@63682.4] assign _T_4 = widx_bin_io_q + _T; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@63691.4] assign widx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@63692.4] assign ridx = ridx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@63701.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@63703.4] assign _T_7 = ridx ^ 1'h1; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@63704.4] assign _T_8 = widx != _T_7; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@63705.4] assign ready_reg_1 = ready_reg_io_q; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@63724.4] assign io_enq_ready = ready_reg_1 & sink_ready; // @[AsyncQueue.scala 85:16:freechips.rocketchip.system.TinyConfig.fir@63726.4] assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@63741.4] assign io_async_mem_0_address = mem_0_address; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@63737.4] assign io_async_mem_0_mask = mem_0_mask; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@63736.4] assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@63735.4] assign io_async_widx = widx_gray_io_q; // @[AsyncQueue.scala 88:17:freechips.rocketchip.system.TinyConfig.fir@63733.4] assign io_async_safe_widx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 103:20:freechips.rocketchip.system.TinyConfig.fir@63760.4] assign io_async_safe_source_reset_n = reset == 1'h0; // @[AsyncQueue.scala 107:24:freechips.rocketchip.system.TinyConfig.fir@63766.4] assign widx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63686.4] assign widx_bin_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63687.4] assign widx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@63688.4] assign widx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@63689.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63698.4] assign ridx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63699.4] assign ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@63700.4] assign ready_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63720.4] assign ready_reg_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63721.4] assign ready_reg_io_d = sink_ready & _T_8; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@63722.4] assign ready_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@63723.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63729.4] assign widx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63730.4] assign widx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@63731.4] assign widx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@63732.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63743.4] assign AsyncValidSync_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63744.4 AsyncQueue.scala 99:24:freechips.rocketchip.system.TinyConfig.fir@63754.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63746.4] assign AsyncValidSync_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63747.4 AsyncQueue.scala 100:24:freechips.rocketchip.system.TinyConfig.fir@63758.4] assign AsyncValidSync_1_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 104:23:freechips.rocketchip.system.TinyConfig.fir@63761.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@63749.4] assign AsyncValidSync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@63750.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 105:22:freechips.rocketchip.system.TinyConfig.fir@63762.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; mem_0_opcode = _RAND_0[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; mem_0_address = _RAND_1[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; mem_0_mask = _RAND_2[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; mem_0_data = _RAND_3[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (_T) begin mem_0_opcode <= io_enq_bits_opcode; end if (_T) begin mem_0_address <= io_enq_bits_address; end if (_T) begin mem_0_mask <= io_enq_bits_mask; end if (_T) begin mem_0_data <= io_enq_bits_data; end end endmodule module SynchronizerShiftReg_w43_d1( // @[:freechips.rocketchip.system.TinyConfig.fir@63920.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@63921.4] input [42:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@63923.4] output [42:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@63923.4] ); reg [42:0] sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@63928.4] reg [63:0] _RAND_0; assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@63930.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {2{`RANDOM}}; sync_0 = _RAND_0[42:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin sync_0 <= io_d; end endmodule module AsyncQueueSink( // @[:freechips.rocketchip.system.TinyConfig.fir@64396.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@64397.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@64398.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output [1:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_deq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_deq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_deq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input [2:0] io_async_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input [1:0] io_async_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input io_async_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input [31:0] io_async_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] input io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] output io_async_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@64399.4] ); wire ridx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] wire ridx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] wire ridx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] wire ridx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] wire ridx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] wire widx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64418.4] wire widx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64418.4] wire widx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64418.4] wire widx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64418.4] wire deq_bits_reg_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64429.4] wire [42:0] deq_bits_reg_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64429.4] wire [42:0] deq_bits_reg_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64429.4] wire valid_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] wire valid_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] wire valid_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] wire valid_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] wire valid_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] wire ridx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] wire ridx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] wire ridx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] wire ridx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] wire ridx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@64486.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@64486.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@64486.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@64489.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@64489.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@64489.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@64489.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@64492.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@64492.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@64492.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@64492.4] wire AsyncResetRegVec_w1_i0_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] wire AsyncResetRegVec_w1_i0_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] wire AsyncResetRegVec_w1_i0_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] wire AsyncResetRegVec_w1_i0_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] wire AsyncResetRegVec_w1_i0_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] wire _T; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@64403.4] wire source_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@64401.4 :freechips.rocketchip.system.TinyConfig.fir@64402.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@64507.4] wire _T_1; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@64404.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@64413.4] wire ridx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@64414.4] wire widx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@64423.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@64425.4] wire _T_7; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@64426.4] wire valid; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@64427.4] wire [2:0] deq_bits_nxt_opcode; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire [1:0] deq_bits_nxt_param; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire [1:0] deq_bits_nxt_size; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire deq_bits_nxt_source; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire deq_bits_nxt_sink; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire deq_bits_nxt_denied; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire [31:0] deq_bits_nxt_data; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire deq_bits_nxt_corrupt; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] wire [34:0] _T_10; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@64435.4] wire [7:0] _T_13; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@64438.4] wire [42:0] _T_16; // @[:freechips.rocketchip.system.TinyConfig.fir@64443.4 :freechips.rocketchip.system.TinyConfig.fir@64445.4] wire valid_reg_1; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@64476.4] AsyncResetRegVec_w1_i0 ridx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64406.4] .clock(ridx_bin_clock), .reset(ridx_bin_reset), .io_d(ridx_bin_io_d), .io_q(ridx_bin_io_q), .io_en(ridx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64418.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q) ); SynchronizerShiftReg_w43_d1 deq_bits_reg ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@64429.4] .clock(deq_bits_reg_clock), .io_d(deq_bits_reg_io_d), .io_q(deq_bits_reg_io_q) ); AsyncResetRegVec_w1_i0 valid_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64470.4] .clock(valid_reg_clock), .reset(valid_reg_reset), .io_d(valid_reg_io_d), .io_q(valid_reg_io_q), .io_en(valid_reg_io_en) ); AsyncResetRegVec_w1_i0 ridx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64479.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q), .io_en(ridx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@64486.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@64489.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@64492.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); AsyncResetRegVec_w1_i0 AsyncResetRegVec_w1_i0 ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@64521.4] .clock(AsyncResetRegVec_w1_i0_clock), .reset(AsyncResetRegVec_w1_i0_reset), .io_d(AsyncResetRegVec_w1_i0_io_d), .io_q(AsyncResetRegVec_w1_i0_io_q), .io_en(AsyncResetRegVec_w1_i0_io_en) ); assign _T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@64403.4] assign source_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@64401.4 :freechips.rocketchip.system.TinyConfig.fir@64402.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@64507.4] assign _T_1 = source_ready == 1'h0; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@64404.4] assign _T_4 = ridx_bin_io_q + _T; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@64413.4] assign ridx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@64414.4] assign widx = widx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@64423.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@64425.4] assign _T_7 = ridx != widx; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@64426.4] assign valid = source_ready & _T_7; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@64427.4] assign deq_bits_nxt_opcode = valid ? io_async_mem_0_opcode : io_deq_bits_opcode; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_param = valid ? 2'h0 : io_deq_bits_param; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_size = valid ? io_async_mem_0_size : io_deq_bits_size; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_source = valid ? io_async_mem_0_source : io_deq_bits_source; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_sink = valid ? 1'h0 : io_deq_bits_sink; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_denied = valid ? 1'h0 : io_deq_bits_denied; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_data = valid ? io_async_mem_0_data : io_deq_bits_data; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign deq_bits_nxt_corrupt = valid ? 1'h0 : io_deq_bits_corrupt; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@64428.4] assign _T_10 = {deq_bits_nxt_sink,deq_bits_nxt_denied,deq_bits_nxt_data,deq_bits_nxt_corrupt}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@64435.4] assign _T_13 = {deq_bits_nxt_opcode,deq_bits_nxt_param,deq_bits_nxt_size,deq_bits_nxt_source}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@64438.4] assign _T_16 = deq_bits_reg_io_q; // @[:freechips.rocketchip.system.TinyConfig.fir@64443.4 :freechips.rocketchip.system.TinyConfig.fir@64445.4] assign valid_reg_1 = valid_reg_io_q; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@64476.4] assign io_deq_valid = valid_reg_1 & source_ready; // @[AsyncQueue.scala 148:16:freechips.rocketchip.system.TinyConfig.fir@64478.4] assign io_deq_bits_opcode = _T_16[42:40]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64469.4] assign io_deq_bits_param = _T_16[39:38]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64468.4] assign io_deq_bits_size = _T_16[37:36]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64467.4] assign io_deq_bits_source = _T_16[35]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64466.4] assign io_deq_bits_sink = _T_16[34]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64465.4] assign io_deq_bits_denied = _T_16[33]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64464.4] assign io_deq_bits_data = _T_16[32:1]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64463.4] assign io_deq_bits_corrupt = _T_16[0]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@64462.4] assign io_async_ridx = ridx_gray_io_q; // @[AsyncQueue.scala 151:17:freechips.rocketchip.system.TinyConfig.fir@64485.4] assign io_async_safe_ridx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 161:20:freechips.rocketchip.system.TinyConfig.fir@64504.4] assign io_async_safe_sink_reset_n = reset == 1'h0; // @[AsyncQueue.scala 165:22:freechips.rocketchip.system.TinyConfig.fir@64510.4] assign ridx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64408.4] assign ridx_bin_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64409.4] assign ridx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@64410.4] assign ridx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@64411.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64420.4] assign widx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64421.4] assign widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@64422.4] assign deq_bits_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64431.4] assign deq_bits_reg_io_d = {_T_13,_T_10}; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@64440.4] assign valid_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64472.4] assign valid_reg_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64473.4] assign valid_reg_io_d = source_ready & _T_7; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@64474.4] assign valid_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@64475.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64481.4] assign ridx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64482.4] assign ridx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@64483.4] assign ridx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@64484.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64487.4] assign AsyncValidSync_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64488.4 AsyncQueue.scala 157:25:freechips.rocketchip.system.TinyConfig.fir@64498.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64490.4] assign AsyncValidSync_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64491.4 AsyncQueue.scala 158:25:freechips.rocketchip.system.TinyConfig.fir@64502.4] assign AsyncValidSync_1_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 162:25:freechips.rocketchip.system.TinyConfig.fir@64505.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64493.4] assign AsyncValidSync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64494.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 163:24:freechips.rocketchip.system.TinyConfig.fir@64506.4] assign AsyncResetRegVec_w1_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64523.4] assign AsyncResetRegVec_w1_i0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64524.4] assign AsyncResetRegVec_w1_i0_io_d = io_async_widx == io_async_ridx; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@64525.4] assign AsyncResetRegVec_w1_i0_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@64526.4] endmodule module TLAsyncCrossingSource( // @[:freechips.rocketchip.system.TinyConfig.fir@64528.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@64529.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@64530.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [8:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [2:0] auto_out_a_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [8:0] auto_out_a_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [3:0] auto_out_a_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output [31:0] auto_out_a_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_out_a_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_a_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_out_a_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_a_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_a_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [2:0] auto_out_d_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [1:0] auto_out_d_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_out_d_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input [31:0] auto_out_d_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_d_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_out_d_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_d_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] input auto_out_d_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] output auto_out_d_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@64531.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [8:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] wire AsyncQueueSource_clock; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_reset; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_enq_ready; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_enq_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [2:0] AsyncQueueSource_io_enq_bits_opcode; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [8:0] AsyncQueueSource_io_enq_bits_address; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [3:0] AsyncQueueSource_io_enq_bits_mask; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [31:0] AsyncQueueSource_io_enq_bits_data; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [2:0] AsyncQueueSource_io_async_mem_0_opcode; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [8:0] AsyncQueueSource_io_async_mem_0_address; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [3:0] AsyncQueueSource_io_async_mem_0_mask; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire [31:0] AsyncQueueSource_io_async_mem_0_data; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_async_ridx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_async_widx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_async_safe_ridx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_async_safe_widx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSource_io_async_safe_source_reset_n; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] wire AsyncQueueSink_clock; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_reset; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_ready; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [2:0] AsyncQueueSink_io_deq_bits_opcode; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [1:0] AsyncQueueSink_io_deq_bits_param; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [1:0] AsyncQueueSink_io_deq_bits_size; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_bits_source; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_bits_sink; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_bits_denied; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [31:0] AsyncQueueSink_io_deq_bits_data; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_deq_bits_corrupt; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [2:0] AsyncQueueSink_io_async_mem_0_opcode; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [1:0] AsyncQueueSink_io_async_mem_0_size; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_mem_0_source; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire [31:0] AsyncQueueSink_io_async_mem_0_data; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_ridx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_widx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_safe_widx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] wire AsyncQueueSink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] TLMonitor_32 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@64538.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); AsyncQueueSource AsyncQueueSource ( // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@64591.4] .clock(AsyncQueueSource_clock), .reset(AsyncQueueSource_reset), .io_enq_ready(AsyncQueueSource_io_enq_ready), .io_enq_valid(AsyncQueueSource_io_enq_valid), .io_enq_bits_opcode(AsyncQueueSource_io_enq_bits_opcode), .io_enq_bits_address(AsyncQueueSource_io_enq_bits_address), .io_enq_bits_mask(AsyncQueueSource_io_enq_bits_mask), .io_enq_bits_data(AsyncQueueSource_io_enq_bits_data), .io_async_mem_0_opcode(AsyncQueueSource_io_async_mem_0_opcode), .io_async_mem_0_address(AsyncQueueSource_io_async_mem_0_address), .io_async_mem_0_mask(AsyncQueueSource_io_async_mem_0_mask), .io_async_mem_0_data(AsyncQueueSource_io_async_mem_0_data), .io_async_ridx(AsyncQueueSource_io_async_ridx), .io_async_widx(AsyncQueueSource_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSource_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSource_io_async_safe_widx_valid), .io_async_safe_source_reset_n(AsyncQueueSource_io_async_safe_source_reset_n) ); AsyncQueueSink AsyncQueueSink ( // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@64598.4] .clock(AsyncQueueSink_clock), .reset(AsyncQueueSink_reset), .io_deq_ready(AsyncQueueSink_io_deq_ready), .io_deq_valid(AsyncQueueSink_io_deq_valid), .io_deq_bits_opcode(AsyncQueueSink_io_deq_bits_opcode), .io_deq_bits_param(AsyncQueueSink_io_deq_bits_param), .io_deq_bits_size(AsyncQueueSink_io_deq_bits_size), .io_deq_bits_source(AsyncQueueSink_io_deq_bits_source), .io_deq_bits_sink(AsyncQueueSink_io_deq_bits_sink), .io_deq_bits_denied(AsyncQueueSink_io_deq_bits_denied), .io_deq_bits_data(AsyncQueueSink_io_deq_bits_data), .io_deq_bits_corrupt(AsyncQueueSink_io_deq_bits_corrupt), .io_async_mem_0_opcode(AsyncQueueSink_io_async_mem_0_opcode), .io_async_mem_0_size(AsyncQueueSink_io_async_mem_0_size), .io_async_mem_0_source(AsyncQueueSink_io_async_mem_0_source), .io_async_mem_0_data(AsyncQueueSink_io_async_mem_0_data), .io_async_ridx(AsyncQueueSink_io_async_ridx), .io_async_widx(AsyncQueueSink_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSink_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSink_io_async_safe_widx_valid), .io_async_safe_sink_reset_n(AsyncQueueSink_io_async_safe_sink_reset_n) ); assign auto_in_a_ready = AsyncQueueSource_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_valid = AsyncQueueSink_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_opcode = AsyncQueueSink_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_param = AsyncQueueSink_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_size = AsyncQueueSink_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_source = AsyncQueueSink_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_sink = AsyncQueueSink_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_denied = AsyncQueueSink_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_data = AsyncQueueSink_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_in_d_bits_corrupt = AsyncQueueSink_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@64590.4] assign auto_out_a_mem_0_opcode = AsyncQueueSource_io_async_mem_0_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_mem_0_address = AsyncQueueSource_io_async_mem_0_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_mem_0_mask = AsyncQueueSource_io_async_mem_0_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_mem_0_data = AsyncQueueSource_io_async_mem_0_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_widx = AsyncQueueSource_io_async_widx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_safe_widx_valid = AsyncQueueSource_io_async_safe_widx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_a_safe_source_reset_n = AsyncQueueSource_io_async_safe_source_reset_n; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_d_ridx = AsyncQueueSink_io_async_ridx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_d_safe_ridx_valid = AsyncQueueSink_io_async_safe_ridx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign auto_out_d_safe_sink_reset_n = AsyncQueueSink_io_async_safe_sink_reset_n; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@64589.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64540.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64541.4] assign TLMonitor_io_in_a_ready = AsyncQueueSource_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_valid = AsyncQueueSink_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_opcode = AsyncQueueSink_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_param = AsyncQueueSink_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_size = AsyncQueueSink_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_source = AsyncQueueSink_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_sink = AsyncQueueSink_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_denied = AsyncQueueSink_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign TLMonitor_io_in_d_bits_corrupt = AsyncQueueSink_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@64586.4] assign AsyncQueueSource_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64592.4] assign AsyncQueueSource_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64593.4] assign AsyncQueueSource_io_enq_valid = auto_in_a_valid; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@64595.4] assign AsyncQueueSource_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@64594.4] assign AsyncQueueSource_io_enq_bits_address = auto_in_a_bits_address; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@64594.4] assign AsyncQueueSource_io_enq_bits_mask = auto_in_a_bits_mask; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@64594.4] assign AsyncQueueSource_io_enq_bits_data = auto_in_a_bits_data; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@64594.4] assign AsyncQueueSource_io_async_ridx = auto_out_a_ridx; // @[AsyncCrossing.scala 25:13:freechips.rocketchip.system.TinyConfig.fir@64597.4] assign AsyncQueueSource_io_async_safe_ridx_valid = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala 25:13:freechips.rocketchip.system.TinyConfig.fir@64597.4] assign AsyncQueueSink_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@64599.4] assign AsyncQueueSink_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@64600.4] assign AsyncQueueSink_io_deq_ready = auto_in_d_ready; // @[AsyncCrossing.scala 26:12:freechips.rocketchip.system.TinyConfig.fir@64608.4] assign AsyncQueueSink_io_async_mem_0_opcode = auto_out_d_mem_0_opcode; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64607.4] assign AsyncQueueSink_io_async_mem_0_size = auto_out_d_mem_0_size; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64607.4] assign AsyncQueueSink_io_async_mem_0_source = auto_out_d_mem_0_source; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64607.4] assign AsyncQueueSink_io_async_mem_0_data = auto_out_d_mem_0_data; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64607.4] assign AsyncQueueSink_io_async_widx = auto_out_d_widx; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64605.4] assign AsyncQueueSink_io_async_safe_widx_valid = auto_out_d_safe_widx_valid; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@64603.4] endmodule module AsyncQueueSource_1( // @[:freechips.rocketchip.system.TinyConfig.fir@65223.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@65224.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@65225.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_enq_bits_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input [9:0] io_enq_bits_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_enq_bits_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output io_async_mem_0_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output [9:0] io_async_mem_0_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output io_async_mem_0_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] output io_async_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] input io_async_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@65226.4] ); wire widx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] wire widx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] wire widx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] wire widx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] wire widx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] wire ridx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@65246.4] wire ridx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@65246.4] wire ridx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@65246.4] wire ridx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@65246.4] wire ready_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] wire ready_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] wire ready_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] wire ready_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] wire ready_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] wire widx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] wire widx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] wire widx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] wire widx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] wire widx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@65286.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@65286.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@65286.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@65289.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@65289.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@65289.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@65289.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@65292.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@65292.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@65292.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@65292.4] reg mem_0_resumereq; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@65230.4] reg [31:0] _RAND_0; reg [9:0] mem_0_hartsel; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@65230.4] reg [31:0] _RAND_1; reg mem_0_ackhavereset; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@65230.4] reg [31:0] _RAND_2; wire _T; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@65231.4] wire sink_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@65228.4 :freechips.rocketchip.system.TinyConfig.fir@65229.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@65307.4] wire _T_1; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@65232.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@65241.4] wire widx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@65242.4] wire ridx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@65251.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@65253.4] wire _T_7; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@65254.4] wire _T_8; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@65255.4] wire ready_reg_1; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@65271.4] wire _T_12; // @[AsyncQueue.scala 99:43:freechips.rocketchip.system.TinyConfig.fir@65296.4] AsyncResetRegVec_w1_i0 widx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65234.4] .clock(widx_bin_clock), .reset(widx_bin_reset), .io_d(widx_bin_io_d), .io_q(widx_bin_io_q), .io_en(widx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@65246.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q) ); AsyncResetRegVec_w1_i0 ready_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65265.4] .clock(ready_reg_clock), .reset(ready_reg_reset), .io_d(ready_reg_io_d), .io_q(ready_reg_io_q), .io_en(ready_reg_io_en) ); AsyncResetRegVec_w1_i0 widx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@65274.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q), .io_en(widx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@65286.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@65289.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@65292.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); assign _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@65231.4] assign sink_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@65228.4 :freechips.rocketchip.system.TinyConfig.fir@65229.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@65307.4] assign _T_1 = sink_ready == 1'h0; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@65232.4] assign _T_4 = widx_bin_io_q + _T; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@65241.4] assign widx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@65242.4] assign ridx = ridx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@65251.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@65253.4] assign _T_7 = ridx ^ 1'h1; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@65254.4] assign _T_8 = widx != _T_7; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@65255.4] assign ready_reg_1 = ready_reg_io_q; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@65271.4] assign _T_12 = io_async_safe_sink_reset_n == 1'h0; // @[AsyncQueue.scala 99:43:freechips.rocketchip.system.TinyConfig.fir@65296.4] assign io_enq_ready = ready_reg_1 & sink_ready; // @[AsyncQueue.scala 85:16:freechips.rocketchip.system.TinyConfig.fir@65273.4] assign io_async_mem_0_resumereq = mem_0_resumereq; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@65285.4] assign io_async_mem_0_hartsel = mem_0_hartsel; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@65284.4] assign io_async_mem_0_ackhavereset = mem_0_ackhavereset; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@65283.4] assign io_async_widx = widx_gray_io_q; // @[AsyncQueue.scala 88:17:freechips.rocketchip.system.TinyConfig.fir@65280.4] assign io_async_safe_widx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 103:20:freechips.rocketchip.system.TinyConfig.fir@65304.4] assign io_async_safe_source_reset_n = reset == 1'h0; // @[AsyncQueue.scala 107:24:freechips.rocketchip.system.TinyConfig.fir@65310.4] assign widx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65236.4] assign widx_bin_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65237.4] assign widx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@65238.4] assign widx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@65239.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65248.4] assign ridx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65249.4] assign ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@65250.4] assign ready_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65267.4] assign ready_reg_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65268.4] assign ready_reg_io_d = sink_ready & _T_8; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@65269.4] assign ready_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@65270.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65276.4] assign widx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65277.4] assign widx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@65278.4] assign widx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@65279.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65287.4] assign AsyncValidSync_reset = reset | _T_12; // @[:freechips.rocketchip.system.TinyConfig.fir@65288.4 AsyncQueue.scala 99:24:freechips.rocketchip.system.TinyConfig.fir@65298.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65290.4] assign AsyncValidSync_1_reset = reset | _T_12; // @[:freechips.rocketchip.system.TinyConfig.fir@65291.4 AsyncQueue.scala 100:24:freechips.rocketchip.system.TinyConfig.fir@65302.4] assign AsyncValidSync_1_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 104:23:freechips.rocketchip.system.TinyConfig.fir@65305.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65293.4] assign AsyncValidSync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65294.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 105:22:freechips.rocketchip.system.TinyConfig.fir@65306.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; mem_0_resumereq = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; mem_0_hartsel = _RAND_1[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; mem_0_ackhavereset = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (_T) begin mem_0_resumereq <= io_enq_bits_resumereq; end if (_T) begin mem_0_hartsel <= io_enq_bits_hartsel; end if (_T) begin mem_0_ackhavereset <= io_enq_bits_ackhavereset; end end endmodule module TLDebugModuleOuterAsync( // @[:freechips.rocketchip.system.TinyConfig.fir@65312.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@65313.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@65314.4] output [2:0] auto_asource_out_a_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output [8:0] auto_asource_out_a_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output [3:0] auto_asource_out_a_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output [31:0] auto_asource_out_a_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input auto_asource_out_a_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_a_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input auto_asource_out_a_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_a_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_a_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input [2:0] auto_asource_out_d_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input [1:0] auto_asource_out_d_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input auto_asource_out_d_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input [31:0] auto_asource_out_d_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_d_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input auto_asource_out_d_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_d_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] input auto_asource_out_d_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_asource_out_d_safe_sink_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output auto_intsource_out_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@65315.4] output io_dmi_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input io_dmi_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input [6:0] io_dmi_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input [31:0] io_dmi_req_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input [1:0] io_dmi_req_bits_op, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input io_dmi_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_dmi_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output [31:0] io_dmi_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output [1:0] io_dmi_resp_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_ctrl_ndreset, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_ctrl_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_innerCtrl_mem_0_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output [9:0] io_innerCtrl_mem_0_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_innerCtrl_mem_0_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input io_innerCtrl_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_innerCtrl_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input io_innerCtrl_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_innerCtrl_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] output io_innerCtrl_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] input io_innerCtrl_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@65316.4] ); wire dmiXbar_clock; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_reset; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_a_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_a_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [2:0] dmiXbar_auto_in_a_bits_opcode; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [8:0] dmiXbar_auto_in_a_bits_address; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [3:0] dmiXbar_auto_in_a_bits_mask; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_in_a_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_d_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_d_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_d_bits_denied; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_in_d_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_in_d_bits_corrupt; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_1_a_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_1_a_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [2:0] dmiXbar_auto_out_1_a_bits_opcode; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [6:0] dmiXbar_auto_out_1_a_bits_address; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [3:0] dmiXbar_auto_out_1_a_bits_mask; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_out_1_a_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_1_d_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_1_d_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [2:0] dmiXbar_auto_out_1_d_bits_opcode; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_out_1_d_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_a_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_a_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [2:0] dmiXbar_auto_out_0_a_bits_opcode; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [8:0] dmiXbar_auto_out_0_a_bits_address; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [3:0] dmiXbar_auto_out_0_a_bits_mask; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_out_0_a_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_ready; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_valid; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [2:0] dmiXbar_auto_out_0_d_bits_opcode; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [1:0] dmiXbar_auto_out_0_d_bits_param; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [1:0] dmiXbar_auto_out_0_d_bits_size; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_bits_source; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_bits_sink; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_bits_denied; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire [31:0] dmiXbar_auto_out_0_d_bits_data; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmiXbar_auto_out_0_d_bits_corrupt; // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] wire dmi2tl_auto_out_a_ready; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_auto_out_a_valid; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [2:0] dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [8:0] dmi2tl_auto_out_a_bits_address; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [3:0] dmi2tl_auto_out_a_bits_mask; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [31:0] dmi2tl_auto_out_a_bits_data; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_auto_out_d_ready; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_auto_out_d_valid; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_auto_out_d_bits_denied; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [31:0] dmi2tl_auto_out_d_bits_data; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_auto_out_d_bits_corrupt; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_io_dmi_req_ready; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_io_dmi_req_valid; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [6:0] dmi2tl_io_dmi_req_bits_addr; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [31:0] dmi2tl_io_dmi_req_bits_data; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [1:0] dmi2tl_io_dmi_req_bits_op; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_io_dmi_resp_ready; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmi2tl_io_dmi_resp_valid; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [31:0] dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire [1:0] dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] wire dmOuter_clock; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_reset; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_auto_dmi_in_a_ready; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_auto_dmi_in_a_valid; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [2:0] dmOuter_auto_dmi_in_a_bits_opcode; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [6:0] dmOuter_auto_dmi_in_a_bits_address; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [3:0] dmOuter_auto_dmi_in_a_bits_mask; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [31:0] dmOuter_auto_dmi_in_a_bits_data; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_auto_dmi_in_d_ready; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_auto_dmi_in_d_valid; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [2:0] dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [31:0] dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_auto_int_out_0; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_io_ctrl_ndreset; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_io_ctrl_dmactive; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_io_innerCtrl_valid; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire [9:0] dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] wire intsource_auto_in_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@65342.4] wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@65342.4] wire asource_clock; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_reset; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_a_ready; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_a_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [2:0] asource_auto_in_a_bits_opcode; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [8:0] asource_auto_in_a_bits_address; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [3:0] asource_auto_in_a_bits_mask; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [31:0] asource_auto_in_a_bits_data; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_ready; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [2:0] asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [1:0] asource_auto_in_d_bits_param; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [1:0] asource_auto_in_d_bits_size; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_bits_source; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [31:0] asource_auto_in_d_bits_data; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [2:0] asource_auto_out_a_mem_0_opcode; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [8:0] asource_auto_out_a_mem_0_address; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [3:0] asource_auto_out_a_mem_0_mask; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [31:0] asource_auto_out_a_mem_0_data; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_a_ridx; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_a_widx; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_a_safe_widx_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_a_safe_source_reset_n; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [2:0] asource_auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [1:0] asource_auto_out_d_mem_0_size; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_mem_0_source; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire [31:0] asource_auto_out_d_mem_0_data; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_ridx; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_widx; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_safe_ridx_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire asource_auto_out_d_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] wire AsyncQueueSource_clock; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_reset; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_enq_ready; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_enq_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_enq_bits_resumereq; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire [9:0] AsyncQueueSource_io_enq_bits_hartsel; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_enq_bits_ackhavereset; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_mem_0_resumereq; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire [9:0] AsyncQueueSource_io_async_mem_0_hartsel; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_ridx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_widx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_safe_ridx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_safe_widx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_safe_source_reset_n; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] wire AsyncQueueSource_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] TLXbar_7 dmiXbar ( // @[Debug.scala 492:28:freechips.rocketchip.system.TinyConfig.fir@65322.4] .clock(dmiXbar_clock), .reset(dmiXbar_reset), .auto_in_a_ready(dmiXbar_auto_in_a_ready), .auto_in_a_valid(dmiXbar_auto_in_a_valid), .auto_in_a_bits_opcode(dmiXbar_auto_in_a_bits_opcode), .auto_in_a_bits_address(dmiXbar_auto_in_a_bits_address), .auto_in_a_bits_mask(dmiXbar_auto_in_a_bits_mask), .auto_in_a_bits_data(dmiXbar_auto_in_a_bits_data), .auto_in_d_ready(dmiXbar_auto_in_d_ready), .auto_in_d_valid(dmiXbar_auto_in_d_valid), .auto_in_d_bits_denied(dmiXbar_auto_in_d_bits_denied), .auto_in_d_bits_data(dmiXbar_auto_in_d_bits_data), .auto_in_d_bits_corrupt(dmiXbar_auto_in_d_bits_corrupt), .auto_out_1_a_ready(dmiXbar_auto_out_1_a_ready), .auto_out_1_a_valid(dmiXbar_auto_out_1_a_valid), .auto_out_1_a_bits_opcode(dmiXbar_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_address(dmiXbar_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask(dmiXbar_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data(dmiXbar_auto_out_1_a_bits_data), .auto_out_1_d_ready(dmiXbar_auto_out_1_d_ready), .auto_out_1_d_valid(dmiXbar_auto_out_1_d_valid), .auto_out_1_d_bits_opcode(dmiXbar_auto_out_1_d_bits_opcode), .auto_out_1_d_bits_data(dmiXbar_auto_out_1_d_bits_data), .auto_out_0_a_ready(dmiXbar_auto_out_0_a_ready), .auto_out_0_a_valid(dmiXbar_auto_out_0_a_valid), .auto_out_0_a_bits_opcode(dmiXbar_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_address(dmiXbar_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask(dmiXbar_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data(dmiXbar_auto_out_0_a_bits_data), .auto_out_0_d_ready(dmiXbar_auto_out_0_d_ready), .auto_out_0_d_valid(dmiXbar_auto_out_0_d_valid), .auto_out_0_d_bits_opcode(dmiXbar_auto_out_0_d_bits_opcode), .auto_out_0_d_bits_param(dmiXbar_auto_out_0_d_bits_param), .auto_out_0_d_bits_size(dmiXbar_auto_out_0_d_bits_size), .auto_out_0_d_bits_source(dmiXbar_auto_out_0_d_bits_source), .auto_out_0_d_bits_sink(dmiXbar_auto_out_0_d_bits_sink), .auto_out_0_d_bits_denied(dmiXbar_auto_out_0_d_bits_denied), .auto_out_0_d_bits_data(dmiXbar_auto_out_0_d_bits_data), .auto_out_0_d_bits_corrupt(dmiXbar_auto_out_0_d_bits_corrupt) ); DMIToTL dmi2tl ( // @[Debug.scala 495:28:freechips.rocketchip.system.TinyConfig.fir@65328.4] .auto_out_a_ready(dmi2tl_auto_out_a_ready), .auto_out_a_valid(dmi2tl_auto_out_a_valid), .auto_out_a_bits_opcode(dmi2tl_auto_out_a_bits_opcode), .auto_out_a_bits_address(dmi2tl_auto_out_a_bits_address), .auto_out_a_bits_mask(dmi2tl_auto_out_a_bits_mask), .auto_out_a_bits_data(dmi2tl_auto_out_a_bits_data), .auto_out_d_ready(dmi2tl_auto_out_d_ready), .auto_out_d_valid(dmi2tl_auto_out_d_valid), .auto_out_d_bits_denied(dmi2tl_auto_out_d_bits_denied), .auto_out_d_bits_data(dmi2tl_auto_out_d_bits_data), .auto_out_d_bits_corrupt(dmi2tl_auto_out_d_bits_corrupt), .io_dmi_req_ready(dmi2tl_io_dmi_req_ready), .io_dmi_req_valid(dmi2tl_io_dmi_req_valid), .io_dmi_req_bits_addr(dmi2tl_io_dmi_req_bits_addr), .io_dmi_req_bits_data(dmi2tl_io_dmi_req_bits_data), .io_dmi_req_bits_op(dmi2tl_io_dmi_req_bits_op), .io_dmi_resp_ready(dmi2tl_io_dmi_resp_ready), .io_dmi_resp_valid(dmi2tl_io_dmi_resp_valid), .io_dmi_resp_bits_data(dmi2tl_io_dmi_resp_bits_data), .io_dmi_resp_bits_resp(dmi2tl_io_dmi_resp_bits_resp) ); TLDebugModuleOuter dmOuter ( // @[Debug.scala 514:27:freechips.rocketchip.system.TinyConfig.fir@65335.4] .clock(dmOuter_clock), .reset(dmOuter_reset), .auto_dmi_in_a_ready(dmOuter_auto_dmi_in_a_ready), .auto_dmi_in_a_valid(dmOuter_auto_dmi_in_a_valid), .auto_dmi_in_a_bits_opcode(dmOuter_auto_dmi_in_a_bits_opcode), .auto_dmi_in_a_bits_address(dmOuter_auto_dmi_in_a_bits_address), .auto_dmi_in_a_bits_mask(dmOuter_auto_dmi_in_a_bits_mask), .auto_dmi_in_a_bits_data(dmOuter_auto_dmi_in_a_bits_data), .auto_dmi_in_d_ready(dmOuter_auto_dmi_in_d_ready), .auto_dmi_in_d_valid(dmOuter_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode(dmOuter_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_data(dmOuter_auto_dmi_in_d_bits_data), .auto_int_out_0(dmOuter_auto_int_out_0), .io_ctrl_ndreset(dmOuter_io_ctrl_ndreset), .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive), .io_innerCtrl_valid(dmOuter_io_innerCtrl_valid), .io_innerCtrl_bits_resumereq(dmOuter_io_innerCtrl_bits_resumereq), .io_innerCtrl_bits_hartsel(dmOuter_io_innerCtrl_bits_hartsel), .io_innerCtrl_bits_ackhavereset(dmOuter_io_innerCtrl_bits_ackhavereset) ); IntSyncCrossingSource intsource ( // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@65342.4] .auto_in_0(intsource_auto_in_0), .auto_out_sync_0(intsource_auto_out_sync_0) ); TLAsyncCrossingSource asource ( // @[AsyncCrossing.scala 87:29:freechips.rocketchip.system.TinyConfig.fir@65348.4] .clock(asource_clock), .reset(asource_reset), .auto_in_a_ready(asource_auto_in_a_ready), .auto_in_a_valid(asource_auto_in_a_valid), .auto_in_a_bits_opcode(asource_auto_in_a_bits_opcode), .auto_in_a_bits_address(asource_auto_in_a_bits_address), .auto_in_a_bits_mask(asource_auto_in_a_bits_mask), .auto_in_a_bits_data(asource_auto_in_a_bits_data), .auto_in_d_ready(asource_auto_in_d_ready), .auto_in_d_valid(asource_auto_in_d_valid), .auto_in_d_bits_opcode(asource_auto_in_d_bits_opcode), .auto_in_d_bits_param(asource_auto_in_d_bits_param), .auto_in_d_bits_size(asource_auto_in_d_bits_size), .auto_in_d_bits_source(asource_auto_in_d_bits_source), .auto_in_d_bits_sink(asource_auto_in_d_bits_sink), .auto_in_d_bits_denied(asource_auto_in_d_bits_denied), .auto_in_d_bits_data(asource_auto_in_d_bits_data), .auto_in_d_bits_corrupt(asource_auto_in_d_bits_corrupt), .auto_out_a_mem_0_opcode(asource_auto_out_a_mem_0_opcode), .auto_out_a_mem_0_address(asource_auto_out_a_mem_0_address), .auto_out_a_mem_0_mask(asource_auto_out_a_mem_0_mask), .auto_out_a_mem_0_data(asource_auto_out_a_mem_0_data), .auto_out_a_ridx(asource_auto_out_a_ridx), .auto_out_a_widx(asource_auto_out_a_widx), .auto_out_a_safe_ridx_valid(asource_auto_out_a_safe_ridx_valid), .auto_out_a_safe_widx_valid(asource_auto_out_a_safe_widx_valid), .auto_out_a_safe_source_reset_n(asource_auto_out_a_safe_source_reset_n), .auto_out_d_mem_0_opcode(asource_auto_out_d_mem_0_opcode), .auto_out_d_mem_0_size(asource_auto_out_d_mem_0_size), .auto_out_d_mem_0_source(asource_auto_out_d_mem_0_source), .auto_out_d_mem_0_data(asource_auto_out_d_mem_0_data), .auto_out_d_ridx(asource_auto_out_d_ridx), .auto_out_d_widx(asource_auto_out_d_widx), .auto_out_d_safe_ridx_valid(asource_auto_out_d_safe_ridx_valid), .auto_out_d_safe_widx_valid(asource_auto_out_d_safe_widx_valid), .auto_out_d_safe_sink_reset_n(asource_auto_out_d_safe_sink_reset_n) ); AsyncQueueSource_1 AsyncQueueSource ( // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@65362.4] .clock(AsyncQueueSource_clock), .reset(AsyncQueueSource_reset), .io_enq_ready(AsyncQueueSource_io_enq_ready), .io_enq_valid(AsyncQueueSource_io_enq_valid), .io_enq_bits_resumereq(AsyncQueueSource_io_enq_bits_resumereq), .io_enq_bits_hartsel(AsyncQueueSource_io_enq_bits_hartsel), .io_enq_bits_ackhavereset(AsyncQueueSource_io_enq_bits_ackhavereset), .io_async_mem_0_resumereq(AsyncQueueSource_io_async_mem_0_resumereq), .io_async_mem_0_hartsel(AsyncQueueSource_io_async_mem_0_hartsel), .io_async_mem_0_ackhavereset(AsyncQueueSource_io_async_mem_0_ackhavereset), .io_async_ridx(AsyncQueueSource_io_async_ridx), .io_async_widx(AsyncQueueSource_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSource_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSource_io_async_safe_widx_valid), .io_async_safe_source_reset_n(AsyncQueueSource_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n(AsyncQueueSource_io_async_safe_sink_reset_n) ); assign auto_asource_out_a_mem_0_opcode = asource_auto_out_a_mem_0_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_mem_0_address = asource_auto_out_a_mem_0_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_mem_0_mask = asource_auto_out_a_mem_0_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_mem_0_data = asource_auto_out_a_mem_0_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_widx = asource_auto_out_a_widx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_safe_widx_valid = asource_auto_out_a_safe_widx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_a_safe_source_reset_n = asource_auto_out_a_safe_source_reset_n; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_d_ridx = asource_auto_out_d_ridx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_d_safe_ridx_valid = asource_auto_out_d_safe_ridx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_asource_out_d_safe_sink_reset_n = asource_auto_out_d_safe_sink_reset_n; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign auto_intsource_out_sync_0 = intsource_auto_out_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65358.4] assign io_dmi_req_ready = dmi2tl_io_dmi_req_ready; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign io_dmi_resp_valid = dmi2tl_io_dmi_resp_valid; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign io_dmi_resp_bits_data = dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign io_dmi_resp_bits_resp = dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign io_ctrl_ndreset = dmOuter_io_ctrl_ndreset; // @[Debug.scala 534:13:freechips.rocketchip.system.TinyConfig.fir@65361.4] assign io_ctrl_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 534:13:freechips.rocketchip.system.TinyConfig.fir@65361.4] assign io_innerCtrl_mem_0_resumereq = AsyncQueueSource_io_async_mem_0_resumereq; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign io_innerCtrl_mem_0_hartsel = AsyncQueueSource_io_async_mem_0_hartsel; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign io_innerCtrl_mem_0_ackhavereset = AsyncQueueSource_io_async_mem_0_ackhavereset; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign io_innerCtrl_widx = AsyncQueueSource_io_async_widx; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign io_innerCtrl_safe_widx_valid = AsyncQueueSource_io_async_safe_widx_valid; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign io_innerCtrl_safe_source_reset_n = AsyncQueueSource_io_async_safe_source_reset_n; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign dmiXbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65326.4] assign dmiXbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65327.4] assign dmiXbar_auto_in_a_valid = dmi2tl_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_in_a_bits_opcode = dmi2tl_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_in_a_bits_address = dmi2tl_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_in_a_bits_mask = dmi2tl_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_in_a_bits_data = dmi2tl_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_in_d_ready = dmi2tl_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmiXbar_auto_out_1_a_ready = dmOuter_auto_dmi_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmiXbar_auto_out_1_d_valid = dmOuter_auto_dmi_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmiXbar_auto_out_1_d_bits_opcode = dmOuter_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmiXbar_auto_out_1_d_bits_data = dmOuter_auto_dmi_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmiXbar_auto_out_0_a_ready = asource_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_valid = asource_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_opcode = asource_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_param = asource_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_size = asource_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_source = asource_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_sink = asource_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_denied = asource_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_data = asource_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmiXbar_auto_out_0_d_bits_corrupt = asource_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign dmi2tl_auto_out_a_ready = dmiXbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmi2tl_auto_out_d_valid = dmiXbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmi2tl_auto_out_d_bits_denied = dmiXbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmi2tl_auto_out_d_bits_data = dmiXbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmi2tl_auto_out_d_bits_corrupt = dmiXbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@65356.4] assign dmi2tl_io_dmi_req_valid = io_dmi_req_valid; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign dmi2tl_io_dmi_req_bits_addr = io_dmi_req_bits_addr; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign dmi2tl_io_dmi_req_bits_data = io_dmi_req_bits_data; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign dmi2tl_io_dmi_req_bits_op = io_dmi_req_bits_op; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign dmi2tl_io_dmi_resp_ready = io_dmi_resp_ready; // @[Debug.scala 532:41:freechips.rocketchip.system.TinyConfig.fir@65360.4] assign dmOuter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65340.4] assign dmOuter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65341.4] assign dmOuter_auto_dmi_in_a_valid = dmiXbar_auto_out_1_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmOuter_auto_dmi_in_a_bits_opcode = dmiXbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmOuter_auto_dmi_in_a_bits_address = dmiXbar_auto_out_1_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmOuter_auto_dmi_in_a_bits_mask = dmiXbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmOuter_auto_dmi_in_a_bits_data = dmiXbar_auto_out_1_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign dmOuter_auto_dmi_in_d_ready = dmiXbar_auto_out_1_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65355.4] assign intsource_auto_in_0 = dmOuter_auto_int_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65357.4] assign asource_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65352.4] assign asource_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65353.4] assign asource_auto_in_a_valid = dmiXbar_auto_out_0_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_in_a_bits_opcode = dmiXbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_in_a_bits_address = dmiXbar_auto_out_0_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_in_a_bits_mask = dmiXbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_in_a_bits_data = dmiXbar_auto_out_0_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_in_d_ready = dmiXbar_auto_out_0_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@65354.4] assign asource_auto_out_a_ridx = auto_asource_out_a_ridx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_a_safe_ridx_valid = auto_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_mem_0_opcode = auto_asource_out_d_mem_0_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_mem_0_size = auto_asource_out_d_mem_0_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_mem_0_source = auto_asource_out_d_mem_0_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_mem_0_data = auto_asource_out_d_mem_0_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_widx = auto_asource_out_d_widx; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign asource_auto_out_d_safe_widx_valid = auto_asource_out_d_safe_widx_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@65359.4] assign AsyncQueueSource_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@65363.4] assign AsyncQueueSource_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@65364.4] assign AsyncQueueSource_io_enq_valid = dmOuter_io_innerCtrl_valid; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@65366.4] assign AsyncQueueSource_io_enq_bits_resumereq = dmOuter_io_innerCtrl_bits_resumereq; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@65365.4] assign AsyncQueueSource_io_enq_bits_hartsel = dmOuter_io_innerCtrl_bits_hartsel; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@65365.4] assign AsyncQueueSource_io_enq_bits_ackhavereset = dmOuter_io_innerCtrl_bits_ackhavereset; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@65365.4] assign AsyncQueueSource_io_async_ridx = io_innerCtrl_ridx; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign AsyncQueueSource_io_async_safe_ridx_valid = io_innerCtrl_safe_ridx_valid; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] assign AsyncQueueSource_io_async_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 535:18:freechips.rocketchip.system.TinyConfig.fir@65368.4] endmodule module TLMonitor_33( // @[:freechips.rocketchip.system.TinyConfig.fir@65379.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@65380.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@65381.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [8:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] input io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@65382.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@66724.4] wire _T_5; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@65397.6] wire [4:0] _T_8; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@65402.6] wire [1:0] _T_9; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@65403.6] wire [1:0] _T_10; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@65404.6] wire [8:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@65405.6] wire [8:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@65405.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@65406.6] wire _T_14; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@65408.6] wire [1:0] _T_15; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@65409.6] wire [1:0] _T_17; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@65411.6] wire _T_18; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@65412.6] wire _T_19; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65413.6] wire _T_20; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@65414.6] wire _T_21; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@65415.6] wire _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65417.6] wire _T_24; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65418.6] wire _T_26; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65420.6] wire _T_27; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65421.6] wire _T_28; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65422.6] wire _T_29; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@65423.6] wire _T_30; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@65424.6] wire _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65425.6] wire _T_32; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65426.6] wire _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65427.6] wire _T_34; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65428.6] wire _T_35; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65429.6] wire _T_36; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65430.6] wire _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65431.6] wire _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65432.6] wire _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65433.6] wire _T_40; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65434.6] wire _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65435.6] wire _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65436.6] wire [3:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@65439.6] wire [9:0] _T_49; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65443.6] wire _T_57; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@65455.6] wire [9:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65460.8] wire [9:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65461.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65462.8] wire [8:0] _T_64; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65463.8] wire [9:0] _T_65; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65464.8] wire [9:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65465.8] wire [9:0] _T_67; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65466.8] wire _T_68; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65467.8] wire [8:0] _T_69; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65468.8] wire [9:0] _T_70; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65469.8] wire [9:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65470.8] wire [9:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65471.8] wire _T_73; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65472.8] wire [8:0] _T_74; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65473.8] wire [9:0] _T_75; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65474.8] wire [9:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65475.8] wire [9:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65476.8] wire _T_78; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65477.8] wire [8:0] _T_79; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65478.8] wire [9:0] _T_80; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65479.8] wire [9:0] _T_81; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65480.8] wire [9:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65481.8] wire _T_83; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65482.8] wire [8:0] _T_84; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65483.8] wire [9:0] _T_85; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65484.8] wire [9:0] _T_86; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65485.8] wire [9:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65486.8] wire _T_88; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65487.8] wire _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65488.8] wire _T_90; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65489.8] wire _T_91; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65490.8] wire _T_92; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65491.8] wire _T_93; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65492.8] wire _T_98; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65497.8] wire _T_103; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65510.8] wire _T_104; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65511.8] wire _T_107; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65518.8] wire _T_108; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65519.8] wire _T_110; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65525.8] wire _T_111; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65526.8] wire _T_112; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@65531.8] wire _T_114; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65533.8] wire _T_115; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65534.8] wire [3:0] _T_116; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@65539.8] wire _T_117; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@65540.8] wire _T_119; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65542.8] wire _T_120; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65543.8] wire _T_121; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@65548.8] wire _T_123; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65550.8] wire _T_124; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65551.8] wire _T_125; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@65557.6] wire _T_184; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@65641.8] wire _T_186; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65643.8] wire _T_187; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65644.8] wire _T_197; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@65667.6] wire _T_199; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@65670.8] wire _T_237; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@65708.8] wire _T_240; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65711.8] wire _T_241; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65712.8] wire _T_248; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@65731.8] wire _T_250; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65733.8] wire _T_251; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65734.8] wire _T_252; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@65739.8] wire _T_254; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65741.8] wire _T_255; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65742.8] wire _T_260; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@65756.6] wire _T_319; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@65837.6] wire [3:0] _T_374; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@65909.8] wire [3:0] _T_375; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@65910.8] wire _T_376; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@65911.8] wire _T_378; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65913.8] wire _T_379; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65914.8] wire _T_380; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@65920.6] wire _T_428; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@65981.8] wire _T_430; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65983.8] wire _T_431; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65984.8] wire _T_436; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@65998.6] wire _T_484; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@66059.8] wire _T_486; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66061.8] wire _T_487; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66062.8] wire _T_492; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@66076.6] wire _T_548; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@66156.6] wire _T_550; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66158.6] wire _T_551; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66159.6] wire _T_552; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@66164.6] wire _T_555; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@66169.6] wire _T_557; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66172.8] wire _T_558; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66173.8] wire _T_559; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@66178.8] wire _T_561; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66180.8] wire _T_562; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66181.8] wire _T_575; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@66211.6] wire _T_603; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@66269.6] wire _T_632; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@66328.6] wire _T_649; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@66363.6] wire _T_667; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@66399.6] wire _T_696; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@66459.4] reg _T_705; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@66468.4] reg [31:0] _RAND_0; wire _T_707; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66470.4] wire _T_708; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66471.4] reg [2:0] _T_716; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@66482.4] reg [31:0] _RAND_1; reg [2:0] _T_717; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@66483.4] reg [31:0] _RAND_2; reg [1:0] _T_718; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@66484.4] reg [31:0] _RAND_3; reg _T_719; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@66485.4] reg [31:0] _RAND_4; reg [8:0] _T_720; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@66486.4] reg [31:0] _RAND_5; wire _T_721; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@66487.4] wire _T_722; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@66488.4] wire _T_723; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@66490.6] wire _T_725; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66492.6] wire _T_726; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66493.6] wire _T_727; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@66498.6] wire _T_729; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66500.6] wire _T_730; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66501.6] wire _T_731; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@66506.6] wire _T_733; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66508.6] wire _T_734; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66509.6] wire _T_735; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@66514.6] wire _T_737; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66516.6] wire _T_738; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66517.6] wire _T_739; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@66522.6] wire _T_741; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66524.6] wire _T_742; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66525.6] wire _T_744; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@66532.4] wire _T_745; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@66540.4] reg _T_753; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@66548.4] reg [31:0] _RAND_6; wire _T_755; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66550.4] wire _T_756; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66551.4] reg [2:0] _T_764; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@66562.4] reg [31:0] _RAND_7; reg [1:0] _T_766; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@66564.4] reg [31:0] _RAND_8; reg _T_767; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@66565.4] reg [31:0] _RAND_9; wire _T_770; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@66568.4] wire _T_771; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@66569.4] wire _T_772; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@66571.6] wire _T_774; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66573.6] wire _T_775; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66574.6] wire _T_780; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@66587.6] wire _T_782; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66589.6] wire _T_783; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66590.6] wire _T_784; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@66595.6] wire _T_786; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66597.6] wire _T_787; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66598.6] wire _T_797; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@66621.4] reg _T_798; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@66630.4] reg [31:0] _RAND_10; reg _T_808; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@66640.4] reg [31:0] _RAND_11; wire _T_810; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66642.4] wire _T_811; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66643.4] reg _T_827; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@66662.4] reg [31:0] _RAND_12; wire _T_829; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66664.4] wire _T_830; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66665.4] wire _T_840; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@66680.4] wire [1:0] _T_842; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@66683.6] wire _T_843; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@66685.6] wire _T_845; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@66687.6] wire _T_847; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66689.6] wire _T_848; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66690.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@66682.4] wire _T_852; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@66701.4] wire _T_854; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@66703.4] wire _T_855; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@66704.4] wire [1:0] _T_856; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@66706.6] wire _T_838; // @[:freechips.rocketchip.system.TinyConfig.fir@66676.4 :freechips.rocketchip.system.TinyConfig.fir@66678.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@66684.6] wire _T_857; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@66708.6] wire _T_858; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@66709.6] wire _T_861; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66712.6] wire _T_862; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66713.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@66705.4] wire _T_863; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@66719.4] wire _T_849; // @[:freechips.rocketchip.system.TinyConfig.fir@66696.4 :freechips.rocketchip.system.TinyConfig.fir@66698.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@66707.6] wire _T_864; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@66720.4] wire _T_865; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@66721.4] reg [31:0] _T_866; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@66723.4] reg [31:0] _RAND_13; wire _T_868; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@66727.4] wire _T_869; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@66728.4] wire _T_870; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@66729.4] wire _T_871; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@66730.4] wire _T_872; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@66731.4] wire _T_874; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66733.4] wire _T_875; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66734.4] wire [31:0] _T_877; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@66740.4] wire _T_880; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@66744.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65499.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@65601.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65714.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@65803.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@65884.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@65964.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@66042.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@66120.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66175.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@66217.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@66275.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@66334.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@66369.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@66405.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@66724.4] .out(plusarg_reader_out) ); assign _T_5 = io_in_a_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@65397.6] assign _T_8 = 5'h3 << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@65402.6] assign _T_9 = _T_8[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@65403.6] assign _T_10 = ~ _T_9; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@65404.6] assign _GEN_18 = {{7'd0}, _T_10}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@65405.6] assign _T_11 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@65405.6] assign _T_12 = _T_11 == 9'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@65406.6] assign _T_14 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@65408.6] assign _T_15 = 2'h1 << _T_14; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@65409.6] assign _T_17 = _T_15 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@65411.6] assign _T_18 = io_in_a_bits_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@65412.6] assign _T_19 = _T_17[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65413.6] assign _T_20 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@65414.6] assign _T_21 = _T_20 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@65415.6] assign _T_23 = _T_19 & _T_21; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65417.6] assign _T_24 = _T_18 | _T_23; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65418.6] assign _T_26 = _T_19 & _T_20; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65420.6] assign _T_27 = _T_18 | _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65421.6] assign _T_28 = _T_17[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@65422.6] assign _T_29 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@65423.6] assign _T_30 = _T_29 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@65424.6] assign _T_31 = _T_21 & _T_30; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65425.6] assign _T_32 = _T_28 & _T_31; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65426.6] assign _T_33 = _T_24 | _T_32; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65427.6] assign _T_34 = _T_21 & _T_29; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65428.6] assign _T_35 = _T_28 & _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65429.6] assign _T_36 = _T_24 | _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65430.6] assign _T_37 = _T_20 & _T_30; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65431.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65432.6] assign _T_39 = _T_27 | _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65433.6] assign _T_40 = _T_20 & _T_29; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@65434.6] assign _T_41 = _T_28 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@65435.6] assign _T_42 = _T_27 | _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@65436.6] assign _T_45 = {_T_42,_T_39,_T_36,_T_33}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@65439.6] assign _T_49 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65443.6] assign _T_57 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@65455.6] assign _T_61 = $signed(_T_49) & $signed(-10'sh40); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65460.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65461.8] assign _T_63 = $signed(_T_62) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65462.8] assign _T_64 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65463.8] assign _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65464.8] assign _T_66 = $signed(_T_65) & $signed(-10'sh4); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65465.8] assign _T_67 = $signed(_T_66); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65466.8] assign _T_68 = $signed(_T_67) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65467.8] assign _T_69 = io_in_a_bits_address ^ 9'h48; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65468.8] assign _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65469.8] assign _T_71 = $signed(_T_70) & $signed(-10'sh18); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65470.8] assign _T_72 = $signed(_T_71); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65471.8] assign _T_73 = $signed(_T_72) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65472.8] assign _T_74 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65473.8] assign _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65474.8] assign _T_76 = $signed(_T_75) & $signed(-10'sh20); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65475.8] assign _T_77 = $signed(_T_76); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65476.8] assign _T_78 = $signed(_T_77) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65477.8] assign _T_79 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65478.8] assign _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65479.8] assign _T_81 = $signed(_T_80) & $signed(-10'sh80); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65480.8] assign _T_82 = $signed(_T_81); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65481.8] assign _T_83 = $signed(_T_82) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65482.8] assign _T_84 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@65483.8] assign _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@65484.8] assign _T_86 = $signed(_T_85) & $signed(-10'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65485.8] assign _T_87 = $signed(_T_86); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@65486.8] assign _T_88 = $signed(_T_87) == $signed(10'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@65487.8] assign _T_89 = _T_63 | _T_68; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65488.8] assign _T_90 = _T_89 | _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65489.8] assign _T_91 = _T_90 | _T_78; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65490.8] assign _T_92 = _T_91 | _T_83; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65491.8] assign _T_93 = _T_92 | _T_88; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@65492.8] assign _T_98 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65497.8] assign _T_103 = _T_5 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65510.8] assign _T_104 = _T_103 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65511.8] assign _T_107 = _T_18 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65518.8] assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65519.8] assign _T_110 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65525.8] assign _T_111 = _T_110 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65526.8] assign _T_112 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@65531.8] assign _T_114 = _T_112 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65533.8] assign _T_115 = _T_114 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65534.8] assign _T_116 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@65539.8] assign _T_117 = _T_116 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@65540.8] assign _T_119 = _T_117 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65542.8] assign _T_120 = _T_119 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65543.8] assign _T_121 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@65548.8] assign _T_123 = _T_121 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65550.8] assign _T_124 = _T_123 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65551.8] assign _T_125 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@65557.6] assign _T_184 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@65641.8] assign _T_186 = _T_184 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65643.8] assign _T_187 = _T_186 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65644.8] assign _T_197 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@65667.6] assign _T_199 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@65670.8] assign _T_237 = _T_199 & _T_93; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@65708.8] assign _T_240 = _T_237 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65711.8] assign _T_241 = _T_240 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65712.8] assign _T_248 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@65731.8] assign _T_250 = _T_248 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65733.8] assign _T_251 = _T_250 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65734.8] assign _T_252 = io_in_a_bits_mask == _T_45; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@65739.8] assign _T_254 = _T_252 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65741.8] assign _T_255 = _T_254 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65742.8] assign _T_260 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@65756.6] assign _T_319 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@65837.6] assign _T_374 = ~ _T_45; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@65909.8] assign _T_375 = io_in_a_bits_mask & _T_374; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@65910.8] assign _T_376 = _T_375 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@65911.8] assign _T_378 = _T_376 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65913.8] assign _T_379 = _T_378 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65914.8] assign _T_380 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@65920.6] assign _T_428 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@65981.8] assign _T_430 = _T_428 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65983.8] assign _T_431 = _T_430 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65984.8] assign _T_436 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@65998.6] assign _T_484 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@66059.8] assign _T_486 = _T_484 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66061.8] assign _T_487 = _T_486 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66062.8] assign _T_492 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@66076.6] assign _T_548 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@66156.6] assign _T_550 = _T_548 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66158.6] assign _T_551 = _T_550 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66159.6] assign _T_552 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@66164.6] assign _T_555 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@66169.6] assign _T_557 = _T_552 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66172.8] assign _T_558 = _T_557 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66173.8] assign _T_559 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@66178.8] assign _T_561 = _T_559 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66180.8] assign _T_562 = _T_561 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66181.8] assign _T_575 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@66211.6] assign _T_603 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@66269.6] assign _T_632 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@66328.6] assign _T_649 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@66363.6] assign _T_667 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@66399.6] assign _T_696 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@66459.4] assign _T_707 = _T_705 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66470.4] assign _T_708 = _T_705 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66471.4] assign _T_721 = _T_708 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@66487.4] assign _T_722 = io_in_a_valid & _T_721; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@66488.4] assign _T_723 = io_in_a_bits_opcode == _T_716; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@66490.6] assign _T_725 = _T_723 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66492.6] assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66493.6] assign _T_727 = io_in_a_bits_param == _T_717; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@66498.6] assign _T_729 = _T_727 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66500.6] assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66501.6] assign _T_731 = io_in_a_bits_size == _T_718; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@66506.6] assign _T_733 = _T_731 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66508.6] assign _T_734 = _T_733 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66509.6] assign _T_735 = io_in_a_bits_source == _T_719; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@66514.6] assign _T_737 = _T_735 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66516.6] assign _T_738 = _T_737 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66517.6] assign _T_739 = io_in_a_bits_address == _T_720; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@66522.6] assign _T_741 = _T_739 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66524.6] assign _T_742 = _T_741 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66525.6] assign _T_744 = _T_696 & _T_708; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@66532.4] assign _T_745 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@66540.4] assign _T_755 = _T_753 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66550.4] assign _T_756 = _T_753 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66551.4] assign _T_770 = _T_756 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@66568.4] assign _T_771 = io_in_d_valid & _T_770; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@66569.4] assign _T_772 = io_in_d_bits_opcode == _T_764; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@66571.6] assign _T_774 = _T_772 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66573.6] assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66574.6] assign _T_780 = io_in_d_bits_size == _T_766; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@66587.6] assign _T_782 = _T_780 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66589.6] assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66590.6] assign _T_784 = io_in_d_bits_source == _T_767; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@66595.6] assign _T_786 = _T_784 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66597.6] assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66598.6] assign _T_797 = _T_745 & _T_756; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@66621.4] assign _T_810 = _T_808 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66642.4] assign _T_811 = _T_808 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66643.4] assign _T_829 = _T_827 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@66664.4] assign _T_830 = _T_827 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@66665.4] assign _T_840 = _T_696 & _T_811; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@66680.4] assign _T_842 = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@66683.6] assign _T_843 = _T_798 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@66685.6] assign _T_845 = _T_843 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@66687.6] assign _T_847 = _T_845 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66689.6] assign _T_848 = _T_847 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66690.6] assign _GEN_15 = _T_840 ? _T_842 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@66682.4] assign _T_852 = _T_745 & _T_830; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@66701.4] assign _T_854 = _T_555 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@66703.4] assign _T_855 = _T_852 & _T_854; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@66704.4] assign _T_856 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@66706.6] assign _T_838 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@66676.4 :freechips.rocketchip.system.TinyConfig.fir@66678.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@66684.6] assign _T_857 = _T_838 | _T_798; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@66708.6] assign _T_858 = _T_857 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@66709.6] assign _T_861 = _T_858 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66712.6] assign _T_862 = _T_861 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66713.6] assign _GEN_16 = _T_855 ? _T_856 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@66705.4] assign _T_863 = _T_798 | _T_838; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@66719.4] assign _T_849 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@66696.4 :freechips.rocketchip.system.TinyConfig.fir@66698.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@66707.6] assign _T_864 = ~ _T_849; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@66720.4] assign _T_865 = _T_863 & _T_864; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@66721.4] assign _T_868 = _T_798 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@66727.4] assign _T_869 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@66728.4] assign _T_870 = _T_868 | _T_869; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@66729.4] assign _T_871 = _T_866 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@66730.4] assign _T_872 = _T_870 | _T_871; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@66731.4] assign _T_874 = _T_872 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66733.4] assign _T_875 = _T_874 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66734.4] assign _T_877 = _T_866 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@66740.4] assign _T_880 = _T_696 | _T_745; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@66744.4] assign _GEN_19 = io_in_a_valid & _T_57; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65499.10] assign _GEN_35 = io_in_a_valid & _T_125; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@65601.10] assign _GEN_53 = io_in_a_valid & _T_197; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65714.10] assign _GEN_65 = io_in_a_valid & _T_260; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@65803.10] assign _GEN_75 = io_in_a_valid & _T_319; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@65884.10] assign _GEN_85 = io_in_a_valid & _T_380; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@65964.10] assign _GEN_95 = io_in_a_valid & _T_436; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@66042.10] assign _GEN_105 = io_in_a_valid & _T_492; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@66120.10] assign _GEN_115 = io_in_d_valid & _T_555; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66175.10] assign _GEN_119 = io_in_d_valid & _T_575; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@66217.10] assign _GEN_125 = io_in_d_valid & _T_603; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@66275.10] assign _GEN_131 = io_in_d_valid & _T_632; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@66334.10] assign _GEN_133 = io_in_d_valid & _T_649; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@66369.10] assign _GEN_135 = io_in_d_valid & _T_667; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@66405.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_705 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_716 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_717 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_718 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_719 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_720 = _RAND_5[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_753 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_764 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_766 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_767 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_798 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_808 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_827 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_866 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_705 <= 1'h0; end else begin if (_T_696) begin if (_T_708) begin _T_705 <= 1'h0; end else begin _T_705 <= _T_707; end end end if (_T_744) begin _T_716 <= io_in_a_bits_opcode; end if (_T_744) begin _T_717 <= io_in_a_bits_param; end if (_T_744) begin _T_718 <= io_in_a_bits_size; end if (_T_744) begin _T_719 <= io_in_a_bits_source; end if (_T_744) begin _T_720 <= io_in_a_bits_address; end if (reset) begin _T_753 <= 1'h0; end else begin if (_T_745) begin if (_T_756) begin _T_753 <= 1'h0; end else begin _T_753 <= _T_755; end end end if (_T_797) begin _T_764 <= io_in_d_bits_opcode; end if (_T_797) begin _T_766 <= io_in_d_bits_size; end if (_T_797) begin _T_767 <= io_in_d_bits_source; end if (reset) begin _T_798 <= 1'h0; end else begin _T_798 <= _T_865; end if (reset) begin _T_808 <= 1'h0; end else begin if (_T_696) begin if (_T_811) begin _T_808 <= 1'h0; end else begin _T_808 <= _T_810; end end end if (reset) begin _T_827 <= 1'h0; end else begin if (_T_745) begin if (_T_830) begin _T_827 <= 1'h0; end else begin _T_827 <= _T_829; end end end if (reset) begin _T_866 <= 32'h0; end else begin if (_T_880) begin _T_866 <= 32'h0; end else begin _T_866 <= _T_877; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65499.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_98) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@65500.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:1394:19)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@65506.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_98) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@65507.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65513.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@65514.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:1394:19)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65521.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_108) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@65522.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65528.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_111) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@65529.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:1394:19)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65536.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@65537.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_120) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65545.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_120) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@65546.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_124) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:1394:19)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65553.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_124) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@65554.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@65601.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_98) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@65602.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:1394:19)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@65608.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_98) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@65609.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@65615.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_104) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@65616.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:1394:19)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@65623.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_108) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@65624.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@65630.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_111) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@65631.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:1394:19)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@65638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@65639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_187) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:1394:19)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65646.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_187) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@65647.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_120) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@65655.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_120) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@65656.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_124) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:1394:19)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@65663.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_124) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@65664.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65714.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_241) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@65715.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@65721.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_104) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@65722.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@65728.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_111) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@65729.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_251) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:1394:19)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65736.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_251) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@65737.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65744.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_255) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@65745.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_124) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:1394:19)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@65752.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_124) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@65753.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@65803.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_241) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@65804.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@65810.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_104) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@65811.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@65817.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_111) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@65818.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_251) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:1394:19)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@65825.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_251) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@65826.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@65833.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_255) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@65834.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_241) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@65884.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_241) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@65885.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@65891.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_104) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@65892.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@65898.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_111) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@65899.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_251) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:1394:19)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@65906.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_251) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@65907.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_379) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65916.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_379) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@65917.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@65964.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_98) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@65965.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@65971.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_104) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@65972.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@65978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_111) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@65979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_431) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:1394:19)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65986.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_431) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@65987.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@65994.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_255) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@65995.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@66042.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_98) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@66043.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@66049.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_104) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@66050.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@66056.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_111) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@66057.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_487) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:1394:19)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66064.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_487) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@66065.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@66072.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_255) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@66073.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:1394:19)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@66120.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_98) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@66121.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@66127.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_104) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@66128.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_111) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:1394:19)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@66134.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_111) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@66135.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_255) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:1394:19)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@66142.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_255) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@66143.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_124) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:1394:19)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@66150.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_124) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@66151.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_551) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:1394:19)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66161.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_551) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@66162.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66175.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_558) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@66176.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:1394:19)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66183.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_562) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@66184.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@66217.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_558) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@66218.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:1394:19)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@66224.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_98) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@66225.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:1394:19)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@66232.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_562) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@66233.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@66275.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_558) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@66276.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_98) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:1394:19)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@66282.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_98) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@66283.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:1394:19)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@66290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_562) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@66291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@66334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_558) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@66335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@66369.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_558) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@66370.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@66405.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_558) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@66406.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_726) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66495.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_726) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@66496.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_730) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66503.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_730) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@66504.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_734) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66511.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_734) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@66512.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_738) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66519.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_738) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@66520.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_722 & _T_742) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66527.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_722 & _T_742) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@66528.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_775) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66576.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_775) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@66577.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_783) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66592.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_783) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@66593.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_771 & _T_787) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:1394:19)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66600.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_771 & _T_787) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@66601.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_840 & _T_848) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:1394:19)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66692.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_840 & _T_848) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@66693.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_855 & _T_862) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:1394:19)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66715.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_855 & _T_862) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@66716.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_875) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:1394:19)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66736.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_875) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@66737.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_34( // @[:freechips.rocketchip.system.TinyConfig.fir@66757.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@66758.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@66759.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [9:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [11:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] input [9:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@66760.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@67883.4] wire _T_11; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@66781.6] wire [4:0] _T_15; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@66787.6] wire [1:0] _T_16; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@66788.6] wire [1:0] _T_17; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@66789.6] wire [11:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@66790.6] wire [11:0] _T_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@66790.6] wire _T_19; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@66791.6] wire _T_21; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@66793.6] wire [1:0] _T_22; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@66794.6] wire [1:0] _T_24; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@66796.6] wire _T_25; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@66797.6] wire _T_26; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@66798.6] wire _T_27; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66799.6] wire _T_28; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@66800.6] wire _T_30; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66802.6] wire _T_31; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66803.6] wire _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66805.6] wire _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66806.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@66807.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66808.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@66809.6] wire _T_38; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66810.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66811.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66812.6] wire _T_41; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66813.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66814.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66815.6] wire _T_44; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66816.6] wire _T_45; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66817.6] wire _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66818.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66819.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66820.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66821.6] wire [3:0] _T_52; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@66824.6] wire [12:0] _T_63; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@66835.6] wire _T_71; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@66847.6] wire [12:0] _T_75; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@66852.8] wire [12:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@66853.8] wire _T_77; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@66854.8] wire _T_82; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66859.8] wire _T_87; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66872.8] wire _T_88; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66873.8] wire _T_91; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66880.8] wire _T_92; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66881.8] wire _T_94; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66887.8] wire _T_95; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66888.8] wire _T_96; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@66893.8] wire _T_98; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66895.8] wire _T_99; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66896.8] wire [3:0] _T_100; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@66901.8] wire _T_101; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@66902.8] wire _T_103; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66904.8] wire _T_104; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66905.8] wire _T_105; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@66910.8] wire _T_107; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66912.8] wire _T_108; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66913.8] wire _T_109; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@66919.6] wire _T_138; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@66973.8] wire _T_140; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66975.8] wire _T_141; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66976.8] wire _T_151; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@66999.6] wire _T_153; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@67002.8] wire _T_161; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@67010.8] wire _T_164; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67013.8] wire _T_165; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67014.8] wire _T_172; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@67033.8] wire _T_174; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67035.8] wire _T_175; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67036.8] wire _T_176; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@67041.8] wire _T_178; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67043.8] wire _T_179; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67044.8] wire _T_184; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@67058.6] wire _T_213; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@67109.6] wire [3:0] _T_238; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@67151.8] wire [3:0] _T_239; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@67152.8] wire _T_240; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@67153.8] wire _T_242; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67155.8] wire _T_243; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67156.8] wire _T_244; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@67162.6] wire _T_262; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@67193.8] wire _T_264; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67195.8] wire _T_265; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67196.8] wire _T_270; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@67210.6] wire _T_288; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@67241.8] wire _T_290; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67243.8] wire _T_291; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67244.8] wire _T_296; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@67258.6] wire _T_322; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@67308.6] wire _T_324; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67310.6] wire _T_325; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67311.6] wire _T_332; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@67322.6] wire _T_336; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@67328.6] wire _T_338; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67331.8] wire _T_339; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67332.8] wire _T_340; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@67337.8] wire _T_342; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67339.8] wire _T_343; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67340.8] wire _T_356; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@67370.6] wire _T_384; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@67428.6] wire _T_413; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@67487.6] wire _T_430; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@67522.6] wire _T_448; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@67558.6] wire _T_477; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@67618.4] reg _T_486; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@67627.4] reg [31:0] _RAND_0; wire _T_488; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67629.4] wire _T_489; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67630.4] reg [2:0] _T_497; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@67641.4] reg [31:0] _RAND_1; reg [2:0] _T_498; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@67642.4] reg [31:0] _RAND_2; reg [1:0] _T_499; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@67643.4] reg [31:0] _RAND_3; reg [9:0] _T_500; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@67644.4] reg [31:0] _RAND_4; reg [11:0] _T_501; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@67645.4] reg [31:0] _RAND_5; wire _T_502; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@67646.4] wire _T_503; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@67647.4] wire _T_504; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@67649.6] wire _T_506; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67651.6] wire _T_507; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67652.6] wire _T_508; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@67657.6] wire _T_510; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67659.6] wire _T_511; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67660.6] wire _T_512; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@67665.6] wire _T_514; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67667.6] wire _T_515; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67668.6] wire _T_516; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@67673.6] wire _T_518; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67675.6] wire _T_519; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67676.6] wire _T_520; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@67681.6] wire _T_522; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67683.6] wire _T_523; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67684.6] wire _T_525; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@67691.4] wire _T_526; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@67699.4] reg _T_534; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@67707.4] reg [31:0] _RAND_6; wire _T_536; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67709.4] wire _T_537; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67710.4] reg [2:0] _T_545; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@67721.4] reg [31:0] _RAND_7; reg [1:0] _T_547; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@67723.4] reg [31:0] _RAND_8; reg [9:0] _T_548; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@67724.4] reg [31:0] _RAND_9; wire _T_551; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@67727.4] wire _T_552; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@67728.4] wire _T_553; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@67730.6] wire _T_555; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67732.6] wire _T_556; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67733.6] wire _T_561; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@67746.6] wire _T_563; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67748.6] wire _T_564; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67749.6] wire _T_565; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@67754.6] wire _T_567; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67756.6] wire _T_568; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67757.6] wire _T_578; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@67780.4] reg [575:0] _T_579; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@67789.4] reg [575:0] _RAND_10; reg _T_589; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@67799.4] reg [31:0] _RAND_11; wire _T_591; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67801.4] wire _T_592; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67802.4] reg _T_608; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@67821.4] reg [31:0] _RAND_12; wire _T_610; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67823.4] wire _T_611; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67824.4] wire _T_621; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@67839.4] wire [1023:0] _T_623; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@67842.6] wire [575:0] _T_624; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@67844.6] wire _T_625; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@67845.6] wire _T_626; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@67846.6] wire _T_628; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67848.6] wire _T_629; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67849.6] wire [1023:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@67841.4] wire _T_633; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@67860.4] wire _T_635; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@67862.4] wire _T_636; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@67863.4] wire [1023:0] _T_637; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@67865.6] wire [575:0] _T_619; // @[:freechips.rocketchip.system.TinyConfig.fir@67835.4 :freechips.rocketchip.system.TinyConfig.fir@67837.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@67843.6] wire [575:0] _T_638; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@67867.6] wire [575:0] _T_639; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@67868.6] wire _T_640; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@67869.6] wire _T_642; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67871.6] wire _T_643; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67872.6] wire [1023:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@67864.4] wire [575:0] _T_644; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@67878.4] wire [575:0] _T_630; // @[:freechips.rocketchip.system.TinyConfig.fir@67855.4 :freechips.rocketchip.system.TinyConfig.fir@67857.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@67866.6] wire [575:0] _T_645; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@67879.4] wire [575:0] _T_646; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@67880.4] reg [31:0] _T_647; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@67882.4] reg [31:0] _RAND_13; wire _T_648; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@67885.4] wire _T_649; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@67886.4] wire _T_650; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@67887.4] wire _T_651; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@67888.4] wire _T_652; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@67889.4] wire _T_653; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@67890.4] wire _T_655; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67892.4] wire _T_656; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67893.4] wire [31:0] _T_658; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@67899.4] wire _T_661; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@67903.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66861.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@66933.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67016.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@67075.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@67126.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@67176.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@67224.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@67272.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67334.10] wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@67376.10] wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@67434.10] wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@67493.10] wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@67528.10] wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@67564.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@67883.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@66781.6] assign _T_15 = 5'h3 << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@66787.6] assign _T_16 = _T_15[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@66788.6] assign _T_17 = ~ _T_16; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@66789.6] assign _GEN_18 = {{10'd0}, _T_17}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@66790.6] assign _T_18 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@66790.6] assign _T_19 = _T_18 == 12'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@66791.6] assign _T_21 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@66793.6] assign _T_22 = 2'h1 << _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@66794.6] assign _T_24 = _T_22 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@66796.6] assign _T_25 = io_in_a_bits_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@66797.6] assign _T_26 = _T_24[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@66798.6] assign _T_27 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66799.6] assign _T_28 = _T_27 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@66800.6] assign _T_30 = _T_26 & _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66802.6] assign _T_31 = _T_25 | _T_30; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66803.6] assign _T_33 = _T_26 & _T_27; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66805.6] assign _T_34 = _T_25 | _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66806.6] assign _T_35 = _T_24[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@66807.6] assign _T_36 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@66808.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@66809.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66810.6] assign _T_39 = _T_35 & _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66811.6] assign _T_40 = _T_31 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66812.6] assign _T_41 = _T_28 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66813.6] assign _T_42 = _T_35 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66814.6] assign _T_43 = _T_31 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66815.6] assign _T_44 = _T_27 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66816.6] assign _T_45 = _T_35 & _T_44; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66817.6] assign _T_46 = _T_34 | _T_45; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66818.6] assign _T_47 = _T_27 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@66819.6] assign _T_48 = _T_35 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@66820.6] assign _T_49 = _T_34 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@66821.6] assign _T_52 = {_T_49,_T_46,_T_43,_T_40}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@66824.6] assign _T_63 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@66835.6] assign _T_71 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@66847.6] assign _T_75 = $signed(_T_63) & $signed(-13'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@66852.8] assign _T_76 = $signed(_T_75); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@66853.8] assign _T_77 = $signed(_T_76) == $signed(13'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@66854.8] assign _T_82 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66859.8] assign _T_87 = _T_11 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66872.8] assign _T_88 = _T_87 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66873.8] assign _T_91 = _T_25 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66880.8] assign _T_92 = _T_91 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66881.8] assign _T_94 = _T_19 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66887.8] assign _T_95 = _T_94 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66888.8] assign _T_96 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@66893.8] assign _T_98 = _T_96 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66895.8] assign _T_99 = _T_98 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66896.8] assign _T_100 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@66901.8] assign _T_101 = _T_100 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@66902.8] assign _T_103 = _T_101 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66904.8] assign _T_104 = _T_103 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66905.8] assign _T_105 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@66910.8] assign _T_107 = _T_105 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66912.8] assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66913.8] assign _T_109 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@66919.6] assign _T_138 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@66973.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66975.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66976.8] assign _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@66999.6] assign _T_153 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@67002.8] assign _T_161 = _T_153 & _T_77; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@67010.8] assign _T_164 = _T_161 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67013.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67014.8] assign _T_172 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@67033.8] assign _T_174 = _T_172 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67035.8] assign _T_175 = _T_174 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67036.8] assign _T_176 = io_in_a_bits_mask == _T_52; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@67041.8] assign _T_178 = _T_176 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67043.8] assign _T_179 = _T_178 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67044.8] assign _T_184 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@67058.6] assign _T_213 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@67109.6] assign _T_238 = ~ _T_52; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@67151.8] assign _T_239 = io_in_a_bits_mask & _T_238; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@67152.8] assign _T_240 = _T_239 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@67153.8] assign _T_242 = _T_240 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67155.8] assign _T_243 = _T_242 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67156.8] assign _T_244 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@67162.6] assign _T_262 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@67193.8] assign _T_264 = _T_262 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67195.8] assign _T_265 = _T_264 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67196.8] assign _T_270 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@67210.6] assign _T_288 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@67241.8] assign _T_290 = _T_288 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67243.8] assign _T_291 = _T_290 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67244.8] assign _T_296 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@67258.6] assign _T_322 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@67308.6] assign _T_324 = _T_322 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67310.6] assign _T_325 = _T_324 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67311.6] assign _T_332 = io_in_d_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@67322.6] assign _T_336 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@67328.6] assign _T_338 = _T_332 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67331.8] assign _T_339 = _T_338 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67332.8] assign _T_340 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@67337.8] assign _T_342 = _T_340 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67339.8] assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67340.8] assign _T_356 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@67370.6] assign _T_384 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@67428.6] assign _T_413 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@67487.6] assign _T_430 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@67522.6] assign _T_448 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@67558.6] assign _T_477 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@67618.4] assign _T_488 = _T_486 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67629.4] assign _T_489 = _T_486 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67630.4] assign _T_502 = _T_489 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@67646.4] assign _T_503 = io_in_a_valid & _T_502; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@67647.4] assign _T_504 = io_in_a_bits_opcode == _T_497; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@67649.6] assign _T_506 = _T_504 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67651.6] assign _T_507 = _T_506 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67652.6] assign _T_508 = io_in_a_bits_param == _T_498; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@67657.6] assign _T_510 = _T_508 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67659.6] assign _T_511 = _T_510 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67660.6] assign _T_512 = io_in_a_bits_size == _T_499; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@67665.6] assign _T_514 = _T_512 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67667.6] assign _T_515 = _T_514 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67668.6] assign _T_516 = io_in_a_bits_source == _T_500; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@67673.6] assign _T_518 = _T_516 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67675.6] assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67676.6] assign _T_520 = io_in_a_bits_address == _T_501; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@67681.6] assign _T_522 = _T_520 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67683.6] assign _T_523 = _T_522 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67684.6] assign _T_525 = _T_477 & _T_489; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@67691.4] assign _T_526 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@67699.4] assign _T_536 = _T_534 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67709.4] assign _T_537 = _T_534 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67710.4] assign _T_551 = _T_537 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@67727.4] assign _T_552 = io_in_d_valid & _T_551; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@67728.4] assign _T_553 = io_in_d_bits_opcode == _T_545; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@67730.6] assign _T_555 = _T_553 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67732.6] assign _T_556 = _T_555 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67733.6] assign _T_561 = io_in_d_bits_size == _T_547; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@67746.6] assign _T_563 = _T_561 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67748.6] assign _T_564 = _T_563 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67749.6] assign _T_565 = io_in_d_bits_source == _T_548; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@67754.6] assign _T_567 = _T_565 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67756.6] assign _T_568 = _T_567 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67757.6] assign _T_578 = _T_526 & _T_537; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@67780.4] assign _T_591 = _T_589 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67801.4] assign _T_592 = _T_589 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67802.4] assign _T_610 = _T_608 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@67823.4] assign _T_611 = _T_608 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@67824.4] assign _T_621 = _T_477 & _T_592; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@67839.4] assign _T_623 = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@67842.6] assign _T_624 = _T_579 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@67844.6] assign _T_625 = _T_624[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@67845.6] assign _T_626 = _T_625 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@67846.6] assign _T_628 = _T_626 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67848.6] assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67849.6] assign _GEN_15 = _T_621 ? _T_623 : 1024'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@67841.4] assign _T_633 = _T_526 & _T_611; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@67860.4] assign _T_635 = _T_336 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@67862.4] assign _T_636 = _T_633 & _T_635; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@67863.4] assign _T_637 = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@67865.6] assign _T_619 = _GEN_15[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@67835.4 :freechips.rocketchip.system.TinyConfig.fir@67837.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@67843.6] assign _T_638 = _T_619 | _T_579; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@67867.6] assign _T_639 = _T_638 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@67868.6] assign _T_640 = _T_639[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@67869.6] assign _T_642 = _T_640 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67871.6] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67872.6] assign _GEN_16 = _T_636 ? _T_637 : 1024'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@67864.4] assign _T_644 = _T_579 | _T_619; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@67878.4] assign _T_630 = _GEN_16[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@67855.4 :freechips.rocketchip.system.TinyConfig.fir@67857.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@67866.6] assign _T_645 = ~ _T_630; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@67879.4] assign _T_646 = _T_644 & _T_645; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@67880.4] assign _T_648 = _T_579 != 576'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@67885.4] assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@67886.4] assign _T_650 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@67887.4] assign _T_651 = _T_649 | _T_650; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@67888.4] assign _T_652 = _T_647 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@67889.4] assign _T_653 = _T_651 | _T_652; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@67890.4] assign _T_655 = _T_653 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67892.4] assign _T_656 = _T_655 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67893.4] assign _T_658 = _T_647 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@67899.4] assign _T_661 = _T_477 | _T_526; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@67903.4] assign _GEN_19 = io_in_a_valid & _T_71; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66861.10] assign _GEN_35 = io_in_a_valid & _T_109; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@66933.10] assign _GEN_53 = io_in_a_valid & _T_151; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67016.10] assign _GEN_65 = io_in_a_valid & _T_184; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@67075.10] assign _GEN_75 = io_in_a_valid & _T_213; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@67126.10] assign _GEN_85 = io_in_a_valid & _T_244; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@67176.10] assign _GEN_95 = io_in_a_valid & _T_270; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@67224.10] assign _GEN_105 = io_in_a_valid & _T_296; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@67272.10] assign _GEN_115 = io_in_d_valid & _T_336; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67334.10] assign _GEN_119 = io_in_d_valid & _T_356; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@67376.10] assign _GEN_125 = io_in_d_valid & _T_384; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@67434.10] assign _GEN_131 = io_in_d_valid & _T_413; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@67493.10] assign _GEN_133 = io_in_d_valid & _T_430; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@67528.10] assign _GEN_135 = io_in_d_valid & _T_448; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@67564.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_486 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_497 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_498 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_499 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_500 = _RAND_4[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_501 = _RAND_5[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_534 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_545 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_547 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_548 = _RAND_9[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {18{`RANDOM}}; _T_579 = _RAND_10[575:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_589 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_608 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_647 = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_486 <= 1'h0; end else begin if (_T_477) begin if (_T_489) begin _T_486 <= 1'h0; end else begin _T_486 <= _T_488; end end end if (_T_525) begin _T_497 <= io_in_a_bits_opcode; end if (_T_525) begin _T_498 <= io_in_a_bits_param; end if (_T_525) begin _T_499 <= io_in_a_bits_size; end if (_T_525) begin _T_500 <= io_in_a_bits_source; end if (_T_525) begin _T_501 <= io_in_a_bits_address; end if (reset) begin _T_534 <= 1'h0; end else begin if (_T_526) begin if (_T_537) begin _T_534 <= 1'h0; end else begin _T_534 <= _T_536; end end end if (_T_578) begin _T_545 <= io_in_d_bits_opcode; end if (_T_578) begin _T_547 <= io_in_d_bits_size; end if (_T_578) begin _T_548 <= io_in_d_bits_source; end if (reset) begin _T_579 <= 576'h0; end else begin _T_579 <= _T_646; end if (reset) begin _T_589 <= 1'h0; end else begin if (_T_477) begin if (_T_592) begin _T_589 <= 1'h0; end else begin _T_589 <= _T_591; end end end if (reset) begin _T_608 <= 1'h0; end else begin if (_T_526) begin if (_T_611) begin _T_608 <= 1'h0; end else begin _T_608 <= _T_610; end end end if (reset) begin _T_647 <= 32'h0; end else begin if (_T_661) begin _T_647 <= 32'h0; end else begin _T_647 <= _T_658; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66861.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@66862.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:49:14)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@66868.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@66869.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66875.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_88) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@66876.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:49:14)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66883.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_92) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@66884.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66890.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_95) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@66891.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:49:14)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66898.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_99) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@66899.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66907.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@66908.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:49:14)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66915.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_108) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@66916.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@66933.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@66934.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:49:14)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@66940.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@66941.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@66947.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_88) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@66948.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:49:14)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@66955.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_92) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@66956.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@66962.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_95) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@66963.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:49:14)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@66970.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_99) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@66971.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:49:14)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66978.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@66979.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@66987.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_104) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@66988.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:49:14)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@66995.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_108) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@66996.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67016.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@67017.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@67023.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_88) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@67024.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@67030.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_95) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@67031.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:49:14)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67038.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_175) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@67039.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67046.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_179) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@67047.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:49:14)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@67054.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_108) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@67055.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@67075.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_165) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@67076.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@67082.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_88) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@67083.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@67089.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_95) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@67090.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:49:14)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@67097.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_175) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@67098.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@67105.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_179) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@67106.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@67126.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_165) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@67127.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@67133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_88) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@67134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@67140.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_95) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@67141.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:49:14)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@67148.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_175) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@67149.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_243) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67158.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_243) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@67159.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@67176.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_82) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@67177.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@67183.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_88) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@67184.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@67190.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_95) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@67191.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_265) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:49:14)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67198.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_265) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@67199.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@67206.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_179) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@67207.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@67224.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_82) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@67225.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@67231.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_88) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@67232.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@67238.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_95) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@67239.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_291) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:49:14)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67246.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_291) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@67247.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@67254.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_179) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@67255.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:49:14)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@67272.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_82) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@67273.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@67279.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_88) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@67280.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:49:14)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@67286.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_95) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@67287.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:49:14)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@67294.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_179) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@67295.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:49:14)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@67302.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_108) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@67303.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_325) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:49:14)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67313.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_325) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@67314.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67334.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_339) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@67335.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:49:14)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67342.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_343) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@67343.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@67376.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_339) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@67377.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:49:14)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@67383.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_82) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@67384.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:49:14)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@67391.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_343) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@67392.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@67434.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_339) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@67435.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:49:14)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@67441.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_82) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@67442.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_343) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:49:14)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@67449.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_343) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@67450.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_131 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@67493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_131 & _T_339) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@67494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_133 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@67528.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_133 & _T_339) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@67529.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_135 & _T_339) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@67564.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_135 & _T_339) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@67565.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_507) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67654.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_507) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@67655.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_511) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67662.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_511) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@67663.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_515) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67670.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_515) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@67671.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_519) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67678.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_519) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@67679.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_503 & _T_523) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67686.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_503 & _T_523) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@67687.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_556) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67735.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_556) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@67736.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_564) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67751.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_564) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@67752.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_552 & _T_568) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:49:14)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67759.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_552 & _T_568) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@67760.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_621 & _T_629) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:49:14)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67851.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_621 & _T_629) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@67852.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_636 & _T_643) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:49:14)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67874.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_636 & _T_643) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@67875.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_656) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Periphery.scala:49:14)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67895.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_656) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@67896.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLDebugModuleInner( // @[:freechips.rocketchip.system.TinyConfig.fir@67908.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@67909.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@67910.4] output auto_tl_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_tl_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [2:0] auto_tl_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [2:0] auto_tl_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [1:0] auto_tl_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [9:0] auto_tl_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [11:0] auto_tl_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [3:0] auto_tl_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [31:0] auto_tl_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_tl_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_tl_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output auto_tl_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [2:0] auto_tl_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [1:0] auto_tl_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [9:0] auto_tl_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [31:0] auto_tl_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output auto_dmi_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_dmi_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [2:0] auto_dmi_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [2:0] auto_dmi_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [1:0] auto_dmi_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_dmi_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [8:0] auto_dmi_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [3:0] auto_dmi_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input [31:0] auto_dmi_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_dmi_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input auto_dmi_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output auto_dmi_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [2:0] auto_dmi_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [1:0] auto_dmi_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output auto_dmi_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] output [31:0] auto_dmi_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@67911.4] input io_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] output io_innerCtrl_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] input io_innerCtrl_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] input io_innerCtrl_bits_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] input [9:0] io_innerCtrl_bits_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] input io_innerCtrl_bits_ackhavereset // @[:freechips.rocketchip.system.TinyConfig.fir@67912.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [8:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] wire TLMonitor_1_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [2:0] TLMonitor_1_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [2:0] TLMonitor_1_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [1:0] TLMonitor_1_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [9:0] TLMonitor_1_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [11:0] TLMonitor_1_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [3:0] TLMonitor_1_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire TLMonitor_1_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [2:0] TLMonitor_1_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [1:0] TLMonitor_1_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] wire [9:0] TLMonitor_1_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] reg haltedBitRegs_0; // @[Debug.scala 611:35:freechips.rocketchip.system.TinyConfig.fir@68028.4] reg [31:0] _RAND_0; reg resumeReqRegs_0; // @[Debug.scala 612:35:freechips.rocketchip.system.TinyConfig.fir@68032.4] reg [31:0] _RAND_1; reg haveResetBitRegs_0; // @[Debug.scala 613:35:freechips.rocketchip.system.TinyConfig.fir@68036.4] reg [31:0] _RAND_2; wire hamaskWrSel_0; // @[Debug.scala 669:61:freechips.rocketchip.system.TinyConfig.fir@68233.4] wire _T_60; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@68286.4] wire resumereq; // @[Debug.scala 683:41:freechips.rocketchip.system.TinyConfig.fir@68287.4] wire DMSTATUSRdData_anyrunning; // @[package.scala 62:38:freechips.rocketchip.system.TinyConfig.fir@68303.6] wire DMSTATUSRdData_anyresumeack; // @[package.scala 62:38:freechips.rocketchip.system.TinyConfig.fir@68309.6] wire _T_95; // @[Debug.scala 705:33:freechips.rocketchip.system.TinyConfig.fir@68338.4] wire _T_96; // @[Debug.scala 705:67:freechips.rocketchip.system.TinyConfig.fir@68339.4] wire [31:0] haltedStatus_0; // @[Debug.scala 850:30:freechips.rocketchip.system.TinyConfig.fir@68402.4 Debug.scala 853:24:freechips.rocketchip.system.TinyConfig.fir@68404.4] wire haltedSummary; // @[Debug.scala 856:48:freechips.rocketchip.system.TinyConfig.fir@68405.4] wire [31:0] HALTSUM1RdData_haltsum1; // @[:freechips.rocketchip.system.TinyConfig.fir@68408.4 :freechips.rocketchip.system.TinyConfig.fir@68410.4] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala 870:34:freechips.rocketchip.system.TinyConfig.fir@68450.4] reg [31:0] _RAND_3; wire _T_399; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@69091.4] wire [6:0] _T_400; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@69093.4] wire _T_2321; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71380.4] wire _T_2319; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71378.4] wire _T_2318; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71377.4] wire _T_2317; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71376.4] wire _T_2316; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71375.4] wire [4:0] _T_2326; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71385.4] wire [6:0] _T_405; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69105.4] wire _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69153.4] wire _T_409; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69109.4] wire _T_427; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69127.4] wire _T_2900; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72475.4] wire _T_2901; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72476.4] wire _T_2902; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72477.4] wire [31:0] _T_2371; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@71430.4] wire _T_2378; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71437.4] wire _T_2934; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72530.4] wire _T_2935; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72531.4] wire _T_477; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69181.4] wire [7:0] _T_485; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69189.4] wire _T_476; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69180.4] wire [7:0] _T_483; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69187.4] wire _T_475; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69179.4] wire [7:0] _T_481; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69185.4] wire _T_474; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69178.4] wire [7:0] _T_479; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69183.4] wire [31:0] _T_488; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69192.4] wire _T_1447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70336.4] wire ABSTRACTCSWrEnMaybe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70340.4] wire [31:0] ABSTRACTCSWrDataVal; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@70344.4] wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala 872:64:freechips.rocketchip.system.TinyConfig.fir@68463.4] reg [1:0] ctrlStateReg; // @[Debug.scala 1267:27:freechips.rocketchip.system.TinyConfig.fir@96512.4] reg [31:0] _RAND_4; wire ABSTRACTCSWrEnLegal; // @[Debug.scala 1277:44:freechips.rocketchip.system.TinyConfig.fir@96518.4] wire ABSTRACTCSWrEn; // @[Debug.scala 879:51:freechips.rocketchip.system.TinyConfig.fir@68487.4] wire _T_139; // @[Debug.scala 886:10:freechips.rocketchip.system.TinyConfig.fir@68500.4] wire [2:0] _T_140; // @[Debug.scala 899:58:freechips.rocketchip.system.TinyConfig.fir@68522.16] wire [2:0] _T_141; // @[Debug.scala 899:56:freechips.rocketchip.system.TinyConfig.fir@68523.16] wire _T_18846; // @[Debug.scala 1330:30:freechips.rocketchip.system.TinyConfig.fir@96595.6] reg [7:0] COMMANDRdData_cmdtype; // @[Debug.scala 949:25:freechips.rocketchip.system.TinyConfig.fir@68982.4] reg [31:0] _RAND_5; wire commandRegIsAccessRegister; // @[Debug.scala 1291:58:freechips.rocketchip.system.TinyConfig.fir@96544.4] reg [23:0] COMMANDRdData_control; // @[Debug.scala 949:25:freechips.rocketchip.system.TinyConfig.fir@68982.4] reg [31:0] _RAND_6; wire [31:0] _T_3245; // @[Debug.scala 1127:104:freechips.rocketchip.system.TinyConfig.fir@73396.4] wire accessRegisterCommandReg_transfer; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73406.4] wire accessRegisterCommandReg_write; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73404.4] wire _T_18836; // @[Debug.scala 1309:19:freechips.rocketchip.system.TinyConfig.fir@96564.8] wire [15:0] accessRegisterCommandReg_regno; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73402.4] wire _T_18831; // @[Debug.scala 1299:58:freechips.rocketchip.system.TinyConfig.fir@96553.4] wire _T_18832; // @[Debug.scala 1299:104:freechips.rocketchip.system.TinyConfig.fir@96554.4] wire accessRegIsGPR; // @[Debug.scala 1299:70:freechips.rocketchip.system.TinyConfig.fir@96555.4] wire _T_18837; // @[Debug.scala 1309:54:freechips.rocketchip.system.TinyConfig.fir@96565.8] wire _GEN_2664; // @[Debug.scala 1309:73:freechips.rocketchip.system.TinyConfig.fir@96566.8] wire commandRegIsUnsupported; // @[Debug.scala 1306:39:freechips.rocketchip.system.TinyConfig.fir@96556.4] wire _T_18838; // @[Debug.scala 1311:36:freechips.rocketchip.system.TinyConfig.fir@96568.10] wire _GEN_2665; // @[Debug.scala 1309:73:freechips.rocketchip.system.TinyConfig.fir@96566.8] wire commandRegBadHaltResume; // @[Debug.scala 1306:39:freechips.rocketchip.system.TinyConfig.fir@96556.4] wire _GEN_2681; // @[Debug.scala 1337:38:freechips.rocketchip.system.TinyConfig.fir@96597.8] wire _GEN_2694; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] wire errorHaltResume; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] wire _T_2379; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71438.4] wire _T_2939; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72538.4] wire _T_2940; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72539.4] wire COMMANDWrEnMaybe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70981.4] wire COMMANDWrEn; // @[Debug.scala 957:40:freechips.rocketchip.system.TinyConfig.fir@69007.4] wire [31:0] COMMANDWrDataVal; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@70985.4] wire [7:0] COMMANDWrData_cmdtype; // @[Debug.scala 952:73:freechips.rocketchip.system.TinyConfig.fir@68993.4] wire commandWrIsAccessRegister; // @[Debug.scala 1290:60:freechips.rocketchip.system.TinyConfig.fir@96543.4] wire _T_18839; // @[Debug.scala 1315:48:freechips.rocketchip.system.TinyConfig.fir@96572.4] wire _T_18840; // @[Debug.scala 1315:103:freechips.rocketchip.system.TinyConfig.fir@96573.4] wire wrAccessRegisterCommand; // @[Debug.scala 1315:78:freechips.rocketchip.system.TinyConfig.fir@96574.4] wire _T_2376; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71435.4] wire _T_2924; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72512.4] wire _T_2925; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72513.4] wire [7:0] _T_2126; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71145.4] wire _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71146.4] wire dmiAbstractDataWrEnMaybe_0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71150.4] wire _T_2736; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72139.4] wire _T_2758; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72174.4] wire _T_2759; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72175.4] wire _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71144.4] wire dmiAbstractDataRdEn_0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71148.4] wire dmiAbstractDataAccessVec_0; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68594.4] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala 911:36:freechips.rocketchip.system.TinyConfig.fir@68546.4] reg [31:0] _RAND_7; wire _T_290; // @[Debug.scala 941:54:freechips.rocketchip.system.TinyConfig.fir@68892.4] wire autoexecData_0; // @[Debug.scala 941:140:freechips.rocketchip.system.TinyConfig.fir@68904.4] wire _T_2388; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71447.4] wire _T_2984; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72603.4] wire _T_2985; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72604.4] wire dmiProgramBufferWrEnMaybe_0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69940.4] wire _T_2818; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72265.4] wire _T_2819; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72266.4] wire dmiProgramBufferRdEn_0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69938.4] wire dmiProgramBufferAccessVec_0; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68671.4] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala 911:36:freechips.rocketchip.system.TinyConfig.fir@68546.4] reg [31:0] _RAND_8; wire _T_303; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68906.4] wire autoexecProg_0; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68922.4] wire _T_2389; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71448.4] wire _T_2989; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72614.4] wire _T_2990; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72615.4] wire dmiProgramBufferWrEnMaybe_4; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69704.4] wire _T_2823; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72276.4] wire _T_2824; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72277.4] wire dmiProgramBufferRdEn_4; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69702.4] wire dmiProgramBufferAccessVec_4; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68675.4] wire _T_304; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68907.4] wire autoexecProg_1; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68924.4] wire _T_335; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68954.4] wire _T_2390; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71449.4] wire _T_2994; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72625.4] wire _T_2995; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72626.4] wire dmiProgramBufferWrEnMaybe_8; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70058.4] wire _T_2828; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72287.4] wire _T_2829; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72288.4] wire dmiProgramBufferRdEn_8; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70056.4] wire dmiProgramBufferAccessVec_8; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68679.4] wire _T_305; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68908.4] wire autoexecProg_2; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68926.4] wire _T_336; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68955.4] wire _T_2391; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71450.4] wire _T_2999; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72636.4] wire _T_3000; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72637.4] wire dmiProgramBufferWrEnMaybe_12; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70604.4] wire _T_2833; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72298.4] wire _T_2834; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72299.4] wire dmiProgramBufferRdEn_12; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70602.4] wire dmiProgramBufferAccessVec_12; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68683.4] wire _T_306; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68909.4] wire autoexecProg_3; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68928.4] wire _T_337; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68956.4] wire _T_2392; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71451.4] wire _T_3004; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72647.4] wire _T_3005; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72648.4] wire dmiProgramBufferWrEnMaybe_16; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71009.4] wire _T_2838; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72309.4] wire _T_2839; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72310.4] wire dmiProgramBufferRdEn_16; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71007.4] wire dmiProgramBufferAccessVec_16; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68687.4] wire _T_307; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68910.4] wire autoexecProg_4; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68930.4] wire _T_338; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68957.4] wire _T_2393; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71452.4] wire _T_3009; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72658.4] wire _T_3010; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72659.4] wire dmiProgramBufferWrEnMaybe_20; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69350.4] wire _T_2843; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72320.4] wire _T_2844; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72321.4] wire dmiProgramBufferRdEn_20; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69348.4] wire dmiProgramBufferAccessVec_20; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68691.4] wire _T_308; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68911.4] wire autoexecProg_5; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68932.4] wire _T_339; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68958.4] wire _T_2394; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71453.4] wire _T_3014; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72669.4] wire _T_3015; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72670.4] wire dmiProgramBufferWrEnMaybe_24; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69586.4] wire _T_2848; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72331.4] wire _T_2849; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72332.4] wire dmiProgramBufferRdEn_24; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69584.4] wire dmiProgramBufferAccessVec_24; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68695.4] wire _T_309; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68912.4] wire autoexecProg_6; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68934.4] wire _T_340; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68959.4] wire _T_2395; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71454.4] wire _T_3019; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72680.4] wire _T_3020; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72681.4] wire dmiProgramBufferWrEnMaybe_28; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70486.4] wire _T_2853; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72342.4] wire _T_2854; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72343.4] wire dmiProgramBufferRdEn_28; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70484.4] wire dmiProgramBufferAccessVec_28; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68699.4] wire _T_310; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68913.4] wire autoexecProg_7; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68936.4] wire _T_341; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68960.4] wire _T_2396; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71455.4] wire _T_3024; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72691.4] wire _T_3025; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72692.4] wire dmiProgramBufferWrEnMaybe_32; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70863.4] wire _T_2858; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72353.4] wire _T_2859; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72354.4] wire dmiProgramBufferRdEn_32; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70861.4] wire dmiProgramBufferAccessVec_32; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68703.4] wire _T_311; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68914.4] wire autoexecProg_8; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68938.4] wire _T_342; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68961.4] wire _T_2397; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71456.4] wire _T_3029; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72702.4] wire _T_3030; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72703.4] wire dmiProgramBufferWrEnMaybe_36; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69822.4] wire _T_2863; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72364.4] wire _T_2864; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72365.4] wire dmiProgramBufferRdEn_36; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69820.4] wire dmiProgramBufferAccessVec_36; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68707.4] wire _T_312; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68915.4] wire autoexecProg_9; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68940.4] wire _T_343; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68962.4] wire _T_2398; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71457.4] wire _T_3034; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72713.4] wire _T_3035; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72714.4] wire dmiProgramBufferWrEnMaybe_40; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69204.4] wire _T_2868; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72375.4] wire _T_2869; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72376.4] wire dmiProgramBufferRdEn_40; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69202.4] wire dmiProgramBufferAccessVec_40; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68711.4] wire _T_313; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68916.4] wire autoexecProg_10; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68942.4] wire _T_344; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68963.4] wire _T_2399; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71458.4] wire _T_3039; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72724.4] wire _T_3040; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72725.4] wire dmiProgramBufferWrEnMaybe_44; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70745.4] wire _T_2873; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72386.4] wire _T_2874; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72387.4] wire dmiProgramBufferRdEn_44; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70743.4] wire dmiProgramBufferAccessVec_44; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68715.4] wire _T_314; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68917.4] wire autoexecProg_11; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68944.4] wire _T_345; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68964.4] wire _T_2400; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71459.4] wire _T_3044; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72735.4] wire _T_3045; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72736.4] wire dmiProgramBufferWrEnMaybe_48; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70368.4] wire _T_2878; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72397.4] wire _T_2879; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72398.4] wire dmiProgramBufferRdEn_48; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70366.4] wire dmiProgramBufferAccessVec_48; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68719.4] wire _T_315; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68918.4] wire autoexecProg_12; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68946.4] wire _T_346; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68965.4] wire _T_2401; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71460.4] wire _T_3049; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72746.4] wire _T_3050; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72747.4] wire dmiProgramBufferWrEnMaybe_52; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70176.4] wire _T_2883; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72408.4] wire _T_2884; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72409.4] wire dmiProgramBufferRdEn_52; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70174.4] wire dmiProgramBufferAccessVec_52; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68723.4] wire _T_316; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68919.4] wire autoexecProg_13; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68948.4] wire _T_347; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68966.4] wire _T_2402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71461.4] wire _T_3054; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72757.4] wire _T_3055; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72758.4] wire dmiProgramBufferWrEnMaybe_56; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69468.4] wire _T_2888; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72419.4] wire _T_2889; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72420.4] wire dmiProgramBufferRdEn_56; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69466.4] wire dmiProgramBufferAccessVec_56; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68727.4] wire _T_317; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68920.4] wire autoexecProg_14; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68950.4] wire _T_348; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68967.4] wire _T_2403; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71462.4] wire _T_3059; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72768.4] wire _T_3060; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72769.4] wire dmiProgramBufferWrEnMaybe_60; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71268.4] wire _T_2893; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72430.4] wire _T_2894; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72431.4] wire dmiProgramBufferRdEn_60; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71266.4] wire dmiProgramBufferAccessVec_60; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68731.4] wire _T_318; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68921.4] wire autoexecProg_15; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68952.4] wire _T_349; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68968.4] wire autoexec; // @[Debug.scala 944:48:freechips.rocketchip.system.TinyConfig.fir@68969.4] wire _T_18841; // @[Debug.scala 1316:48:freechips.rocketchip.system.TinyConfig.fir@96575.4] wire regAccessRegisterCommand; // @[Debug.scala 1316:78:freechips.rocketchip.system.TinyConfig.fir@96577.4] wire _T_18844; // @[Debug.scala 1323:37:freechips.rocketchip.system.TinyConfig.fir@96580.6] wire _T_18830; // @[Debug.scala 1293:49:freechips.rocketchip.system.TinyConfig.fir@96545.4] wire commandWrIsUnsupported; // @[Debug.scala 1293:46:freechips.rocketchip.system.TinyConfig.fir@96546.4] wire _T_18845; // @[Debug.scala 1327:28:freechips.rocketchip.system.TinyConfig.fir@96589.10] wire _GEN_2671; // @[Debug.scala 1325:43:freechips.rocketchip.system.TinyConfig.fir@96585.8] wire _GEN_2673; // @[Debug.scala 1323:66:freechips.rocketchip.system.TinyConfig.fir@96581.6] wire _GEN_2692; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] wire errorUnsupported; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] wire _T_18847; // @[Debug.scala 1351:30:freechips.rocketchip.system.TinyConfig.fir@96617.8] wire _T_3310; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@73527.4] wire [9:0] _T_3311; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@73529.4] wire _T_7386; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77827.4] wire _T_7384; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77825.4] wire _T_7383; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77824.4] wire _T_7382; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77823.4] wire _T_7381; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77822.4] wire _T_7380; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77821.4] wire _T_7379; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77820.4] wire _T_7378; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77819.4] wire _T_7377; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77818.4] wire [8:0] _T_7394; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@77835.4] wire [9:0] _T_3316; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73541.4] wire _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73627.4] wire _T_3352; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73577.4] wire _T_16135; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91670.4] wire _T_16136; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91671.4] wire _T_16137; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91672.4] wire [511:0] _T_7926; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@78367.4] wire _T_7994; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78435.4] wire _T_16474; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92149.4] wire _T_16475; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92150.4] wire _T_3432; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73661.4] wire [7:0] _T_3440; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73669.4] wire _T_3431; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73660.4] wire [7:0] _T_3438; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73667.4] wire _T_3430; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73659.4] wire [7:0] _T_3436; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73665.4] wire _T_3429; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73658.4] wire [7:0] _T_3434; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73663.4] wire [31:0] _T_3443; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@73672.4] wire [9:0] _T_6455; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76834.4] wire _T_6456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76835.4] wire hartExceptionWrEn; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76839.4] wire _GEN_2690; // @[Debug.scala 1351:51:freechips.rocketchip.system.TinyConfig.fir@96618.8] wire _GEN_2696; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] wire errorException; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] wire _T_18816; // @[Debug.scala 1283:45:freechips.rocketchip.system.TinyConfig.fir@96528.4] wire _T_18817; // @[Debug.scala 1283:42:freechips.rocketchip.system.TinyConfig.fir@96529.4] wire _T_2380; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71439.4] wire _T_2944; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72546.4] wire _T_2945; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72547.4] wire ABSTRACTAUTOWrEnMaybe; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69322.4] wire _T_18819; // @[Debug.scala 1284:42:freechips.rocketchip.system.TinyConfig.fir@96531.4] wire _T_18820; // @[Debug.scala 1283:74:freechips.rocketchip.system.TinyConfig.fir@96532.4] wire _T_18822; // @[Debug.scala 1285:42:freechips.rocketchip.system.TinyConfig.fir@96534.4] wire _T_18823; // @[Debug.scala 1284:74:freechips.rocketchip.system.TinyConfig.fir@96535.4] wire [7:0] _T_2149; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71173.4] wire _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71174.4] wire dmiAbstractDataWrEnMaybe_1; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71178.4] wire _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71172.4] wire dmiAbstractDataRdEn_1; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71176.4] wire dmiAbstractDataAccessVec_1; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68595.4] wire _T_224; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68799.4] wire [7:0] _T_2174; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71203.4] wire _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71204.4] wire dmiAbstractDataWrEnMaybe_2; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71208.4] wire _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71202.4] wire dmiAbstractDataRdEn_2; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71206.4] wire dmiAbstractDataAccessVec_2; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68596.4] wire _T_225; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68800.4] wire [7:0] _T_2199; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71233.4] wire _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71234.4] wire dmiAbstractDataWrEnMaybe_3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71238.4] wire _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71232.4] wire dmiAbstractDataRdEn_3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71236.4] wire dmiAbstractDataAccessVec_3; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68597.4] wire dmiAbstractDataAccess; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68801.4] wire _T_18825; // @[Debug.scala 1286:42:freechips.rocketchip.system.TinyConfig.fir@96537.4] wire _T_18826; // @[Debug.scala 1285:74:freechips.rocketchip.system.TinyConfig.fir@96538.4] wire dmiProgramBufferWrEnMaybe_1; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69968.4] wire dmiProgramBufferRdEn_1; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69966.4] wire dmiProgramBufferAccessVec_1; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68672.4] wire _T_226; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68802.4] wire dmiProgramBufferWrEnMaybe_2; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69998.4] wire dmiProgramBufferRdEn_2; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69996.4] wire dmiProgramBufferAccessVec_2; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68673.4] wire _T_227; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68803.4] wire dmiProgramBufferWrEnMaybe_3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70028.4] wire dmiProgramBufferRdEn_3; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70026.4] wire dmiProgramBufferAccessVec_3; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68674.4] wire _T_228; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68804.4] wire _T_229; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68805.4] wire dmiProgramBufferWrEnMaybe_5; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69732.4] wire dmiProgramBufferRdEn_5; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69730.4] wire dmiProgramBufferAccessVec_5; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68676.4] wire _T_230; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68806.4] wire dmiProgramBufferWrEnMaybe_6; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69762.4] wire dmiProgramBufferRdEn_6; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69760.4] wire dmiProgramBufferAccessVec_6; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68677.4] wire _T_231; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68807.4] wire dmiProgramBufferWrEnMaybe_7; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69792.4] wire dmiProgramBufferRdEn_7; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69790.4] wire dmiProgramBufferAccessVec_7; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68678.4] wire _T_232; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68808.4] wire _T_233; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68809.4] wire dmiProgramBufferWrEnMaybe_9; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70086.4] wire dmiProgramBufferRdEn_9; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70084.4] wire dmiProgramBufferAccessVec_9; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68680.4] wire _T_234; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68810.4] wire dmiProgramBufferWrEnMaybe_10; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70116.4] wire dmiProgramBufferRdEn_10; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70114.4] wire dmiProgramBufferAccessVec_10; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68681.4] wire _T_235; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68811.4] wire dmiProgramBufferWrEnMaybe_11; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70146.4] wire dmiProgramBufferRdEn_11; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70144.4] wire dmiProgramBufferAccessVec_11; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68682.4] wire _T_236; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68812.4] wire _T_237; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68813.4] wire dmiProgramBufferWrEnMaybe_13; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70632.4] wire dmiProgramBufferRdEn_13; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70630.4] wire dmiProgramBufferAccessVec_13; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68684.4] wire _T_238; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68814.4] wire dmiProgramBufferWrEnMaybe_14; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70662.4] wire dmiProgramBufferRdEn_14; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70660.4] wire dmiProgramBufferAccessVec_14; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68685.4] wire _T_239; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68815.4] wire dmiProgramBufferWrEnMaybe_15; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70692.4] wire dmiProgramBufferRdEn_15; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70690.4] wire dmiProgramBufferAccessVec_15; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68686.4] wire _T_240; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68816.4] wire _T_241; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68817.4] wire dmiProgramBufferWrEnMaybe_17; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71037.4] wire dmiProgramBufferRdEn_17; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71035.4] wire dmiProgramBufferAccessVec_17; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68688.4] wire _T_242; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68818.4] wire dmiProgramBufferWrEnMaybe_18; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71067.4] wire dmiProgramBufferRdEn_18; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71065.4] wire dmiProgramBufferAccessVec_18; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68689.4] wire _T_243; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68819.4] wire dmiProgramBufferWrEnMaybe_19; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71097.4] wire dmiProgramBufferRdEn_19; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71095.4] wire dmiProgramBufferAccessVec_19; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68690.4] wire _T_244; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68820.4] wire _T_245; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68821.4] wire dmiProgramBufferWrEnMaybe_21; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69378.4] wire dmiProgramBufferRdEn_21; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69376.4] wire dmiProgramBufferAccessVec_21; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68692.4] wire _T_246; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68822.4] wire dmiProgramBufferWrEnMaybe_22; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69408.4] wire dmiProgramBufferRdEn_22; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69406.4] wire dmiProgramBufferAccessVec_22; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68693.4] wire _T_247; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68823.4] wire dmiProgramBufferWrEnMaybe_23; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69438.4] wire dmiProgramBufferRdEn_23; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69436.4] wire dmiProgramBufferAccessVec_23; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68694.4] wire _T_248; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68824.4] wire _T_249; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68825.4] wire dmiProgramBufferWrEnMaybe_25; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69614.4] wire dmiProgramBufferRdEn_25; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69612.4] wire dmiProgramBufferAccessVec_25; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68696.4] wire _T_250; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68826.4] wire dmiProgramBufferWrEnMaybe_26; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69644.4] wire dmiProgramBufferRdEn_26; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69642.4] wire dmiProgramBufferAccessVec_26; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68697.4] wire _T_251; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68827.4] wire dmiProgramBufferWrEnMaybe_27; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69674.4] wire dmiProgramBufferRdEn_27; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69672.4] wire dmiProgramBufferAccessVec_27; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68698.4] wire _T_252; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68828.4] wire _T_253; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68829.4] wire dmiProgramBufferWrEnMaybe_29; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70514.4] wire dmiProgramBufferRdEn_29; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70512.4] wire dmiProgramBufferAccessVec_29; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68700.4] wire _T_254; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68830.4] wire dmiProgramBufferWrEnMaybe_30; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70544.4] wire dmiProgramBufferRdEn_30; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70542.4] wire dmiProgramBufferAccessVec_30; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68701.4] wire _T_255; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68831.4] wire dmiProgramBufferWrEnMaybe_31; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70574.4] wire dmiProgramBufferRdEn_31; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70572.4] wire dmiProgramBufferAccessVec_31; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68702.4] wire _T_256; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68832.4] wire _T_257; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68833.4] wire dmiProgramBufferWrEnMaybe_33; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70891.4] wire dmiProgramBufferRdEn_33; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70889.4] wire dmiProgramBufferAccessVec_33; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68704.4] wire _T_258; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68834.4] wire dmiProgramBufferWrEnMaybe_34; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70921.4] wire dmiProgramBufferRdEn_34; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70919.4] wire dmiProgramBufferAccessVec_34; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68705.4] wire _T_259; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68835.4] wire dmiProgramBufferWrEnMaybe_35; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70951.4] wire dmiProgramBufferRdEn_35; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70949.4] wire dmiProgramBufferAccessVec_35; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68706.4] wire _T_260; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68836.4] wire _T_261; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68837.4] wire dmiProgramBufferWrEnMaybe_37; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69850.4] wire dmiProgramBufferRdEn_37; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69848.4] wire dmiProgramBufferAccessVec_37; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68708.4] wire _T_262; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68838.4] wire dmiProgramBufferWrEnMaybe_38; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69880.4] wire dmiProgramBufferRdEn_38; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69878.4] wire dmiProgramBufferAccessVec_38; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68709.4] wire _T_263; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68839.4] wire dmiProgramBufferWrEnMaybe_39; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69910.4] wire dmiProgramBufferRdEn_39; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69908.4] wire dmiProgramBufferAccessVec_39; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68710.4] wire _T_264; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68840.4] wire _T_265; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68841.4] wire dmiProgramBufferWrEnMaybe_41; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69232.4] wire dmiProgramBufferRdEn_41; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69230.4] wire dmiProgramBufferAccessVec_41; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68712.4] wire _T_266; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68842.4] wire dmiProgramBufferWrEnMaybe_42; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69262.4] wire dmiProgramBufferRdEn_42; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69260.4] wire dmiProgramBufferAccessVec_42; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68713.4] wire _T_267; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68843.4] wire dmiProgramBufferWrEnMaybe_43; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69292.4] wire dmiProgramBufferRdEn_43; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69290.4] wire dmiProgramBufferAccessVec_43; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68714.4] wire _T_268; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68844.4] wire _T_269; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68845.4] wire dmiProgramBufferWrEnMaybe_45; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70773.4] wire dmiProgramBufferRdEn_45; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70771.4] wire dmiProgramBufferAccessVec_45; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68716.4] wire _T_270; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68846.4] wire dmiProgramBufferWrEnMaybe_46; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70803.4] wire dmiProgramBufferRdEn_46; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70801.4] wire dmiProgramBufferAccessVec_46; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68717.4] wire _T_271; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68847.4] wire dmiProgramBufferWrEnMaybe_47; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70833.4] wire dmiProgramBufferRdEn_47; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70831.4] wire dmiProgramBufferAccessVec_47; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68718.4] wire _T_272; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68848.4] wire _T_273; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68849.4] wire dmiProgramBufferWrEnMaybe_49; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70396.4] wire dmiProgramBufferRdEn_49; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70394.4] wire dmiProgramBufferAccessVec_49; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68720.4] wire _T_274; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68850.4] wire dmiProgramBufferWrEnMaybe_50; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70426.4] wire dmiProgramBufferRdEn_50; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70424.4] wire dmiProgramBufferAccessVec_50; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68721.4] wire _T_275; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68851.4] wire dmiProgramBufferWrEnMaybe_51; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70456.4] wire dmiProgramBufferRdEn_51; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70454.4] wire dmiProgramBufferAccessVec_51; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68722.4] wire _T_276; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68852.4] wire _T_277; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68853.4] wire dmiProgramBufferWrEnMaybe_53; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70204.4] wire dmiProgramBufferRdEn_53; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70202.4] wire dmiProgramBufferAccessVec_53; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68724.4] wire _T_278; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68854.4] wire dmiProgramBufferWrEnMaybe_54; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70234.4] wire dmiProgramBufferRdEn_54; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70232.4] wire dmiProgramBufferAccessVec_54; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68725.4] wire _T_279; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68855.4] wire dmiProgramBufferWrEnMaybe_55; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70264.4] wire dmiProgramBufferRdEn_55; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70262.4] wire dmiProgramBufferAccessVec_55; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68726.4] wire _T_280; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68856.4] wire _T_281; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68857.4] wire dmiProgramBufferWrEnMaybe_57; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69496.4] wire dmiProgramBufferRdEn_57; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69494.4] wire dmiProgramBufferAccessVec_57; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68728.4] wire _T_282; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68858.4] wire dmiProgramBufferWrEnMaybe_58; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69526.4] wire dmiProgramBufferRdEn_58; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69524.4] wire dmiProgramBufferAccessVec_58; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68729.4] wire _T_283; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68859.4] wire dmiProgramBufferWrEnMaybe_59; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69556.4] wire dmiProgramBufferRdEn_59; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69554.4] wire dmiProgramBufferAccessVec_59; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68730.4] wire _T_284; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68860.4] wire _T_285; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68861.4] wire dmiProgramBufferWrEnMaybe_61; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71296.4] wire dmiProgramBufferRdEn_61; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71294.4] wire dmiProgramBufferAccessVec_61; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68732.4] wire _T_286; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68862.4] wire dmiProgramBufferWrEnMaybe_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71326.4] wire dmiProgramBufferRdEn_62; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71324.4] wire dmiProgramBufferAccessVec_62; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68733.4] wire _T_287; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68863.4] wire dmiProgramBufferWrEnMaybe_63; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71356.4] wire dmiProgramBufferRdEn_63; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71354.4] wire dmiProgramBufferAccessVec_63; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68734.4] wire dmiProgramBufferAccess; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68864.4] wire _T_18828; // @[Debug.scala 1287:42:freechips.rocketchip.system.TinyConfig.fir@96540.4] wire errorBusy; // @[Debug.scala 1286:74:freechips.rocketchip.system.TinyConfig.fir@96541.4] wire [31:0] ABSTRACTAUTOWrDataVal; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@69326.4] wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala 913:68:freechips.rocketchip.system.TinyConfig.fir@68555.4] wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala 913:68:freechips.rocketchip.system.TinyConfig.fir@68559.4] wire ABSTRACTAUTOWrEn; // @[Debug.scala 920:55:freechips.rocketchip.system.TinyConfig.fir@68573.4] wire [11:0] _T_153; // @[Debug.scala 926:71:freechips.rocketchip.system.TinyConfig.fir@68582.8] wire [23:0] COMMANDWrData_control; // @[Debug.scala 952:73:freechips.rocketchip.system.TinyConfig.fir@68991.4] reg [7:0] abstractDataMem_0; // @[Debug.scala 972:36:freechips.rocketchip.system.TinyConfig.fir@69017.4] reg [31:0] _RAND_9; reg [7:0] abstractDataMem_1; // @[Debug.scala 972:36:freechips.rocketchip.system.TinyConfig.fir@69017.4] reg [31:0] _RAND_10; reg [7:0] abstractDataMem_2; // @[Debug.scala 972:36:freechips.rocketchip.system.TinyConfig.fir@69017.4] reg [31:0] _RAND_11; reg [7:0] abstractDataMem_3; // @[Debug.scala 972:36:freechips.rocketchip.system.TinyConfig.fir@69017.4] reg [31:0] _RAND_12; reg [7:0] programBufferMem_0; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_13; reg [7:0] programBufferMem_1; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_14; reg [7:0] programBufferMem_2; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_15; reg [7:0] programBufferMem_3; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_16; reg [7:0] programBufferMem_4; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_17; reg [7:0] programBufferMem_5; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_18; reg [7:0] programBufferMem_6; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_19; reg [7:0] programBufferMem_7; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_20; reg [7:0] programBufferMem_8; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_21; reg [7:0] programBufferMem_9; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_22; reg [7:0] programBufferMem_10; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_23; reg [7:0] programBufferMem_11; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_24; reg [7:0] programBufferMem_12; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_25; reg [7:0] programBufferMem_13; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_26; reg [7:0] programBufferMem_14; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_27; reg [7:0] programBufferMem_15; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_28; reg [7:0] programBufferMem_16; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_29; reg [7:0] programBufferMem_17; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_30; reg [7:0] programBufferMem_18; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_31; reg [7:0] programBufferMem_19; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_32; reg [7:0] programBufferMem_20; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_33; reg [7:0] programBufferMem_21; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_34; reg [7:0] programBufferMem_22; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_35; reg [7:0] programBufferMem_23; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_36; reg [7:0] programBufferMem_24; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_37; reg [7:0] programBufferMem_25; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_38; reg [7:0] programBufferMem_26; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_39; reg [7:0] programBufferMem_27; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_40; reg [7:0] programBufferMem_28; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_41; reg [7:0] programBufferMem_29; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_42; reg [7:0] programBufferMem_30; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_43; reg [7:0] programBufferMem_31; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_44; reg [7:0] programBufferMem_32; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_45; reg [7:0] programBufferMem_33; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_46; reg [7:0] programBufferMem_34; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_47; reg [7:0] programBufferMem_35; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_48; reg [7:0] programBufferMem_36; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_49; reg [7:0] programBufferMem_37; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_50; reg [7:0] programBufferMem_38; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_51; reg [7:0] programBufferMem_39; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_52; reg [7:0] programBufferMem_40; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_53; reg [7:0] programBufferMem_41; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_54; reg [7:0] programBufferMem_42; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_55; reg [7:0] programBufferMem_43; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_56; reg [7:0] programBufferMem_44; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_57; reg [7:0] programBufferMem_45; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_58; reg [7:0] programBufferMem_46; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_59; reg [7:0] programBufferMem_47; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_60; reg [7:0] programBufferMem_48; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_61; reg [7:0] programBufferMem_49; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_62; reg [7:0] programBufferMem_50; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_63; reg [7:0] programBufferMem_51; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_64; reg [7:0] programBufferMem_52; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_65; reg [7:0] programBufferMem_53; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_66; reg [7:0] programBufferMem_54; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_67; reg [7:0] programBufferMem_55; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_68; reg [7:0] programBufferMem_56; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_69; reg [7:0] programBufferMem_57; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_70; reg [7:0] programBufferMem_58; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_71; reg [7:0] programBufferMem_59; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_72; reg [7:0] programBufferMem_60; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_73; reg [7:0] programBufferMem_61; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_74; reg [7:0] programBufferMem_62; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_75; reg [7:0] programBufferMem_63; // @[Debug.scala 976:34:freechips.rocketchip.system.TinyConfig.fir@69021.4] reg [31:0] _RAND_76; wire [9:0] hartHaltedId; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75750.4] wire _T_360; // @[Debug.scala 991:60:freechips.rocketchip.system.TinyConfig.fir@69032.8] wire _T_7993; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78434.4] wire _T_16469; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92141.4] wire _T_16470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92142.4] wire hartResumingWrEn; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76202.4] wire _T_7991; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78432.4] wire _T_16459; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92125.4] wire _T_16460; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92126.4] wire hartHaltedWrEn; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75749.4] wire _T_363; // @[Debug.scala 1009:25:freechips.rocketchip.system.TinyConfig.fir@69050.6] wire [12:0] _T_372; // @[Debug.scala 1024:73:freechips.rocketchip.system.TinyConfig.fir@69063.4] wire [31:0] _T_382; // @[Debug.scala 1024:73:freechips.rocketchip.system.TinyConfig.fir@69073.4] wire abstractCommandBusy; // @[Debug.scala 1275:42:freechips.rocketchip.system.TinyConfig.fir@96516.4] wire [31:0] _T_394; // @[Debug.scala 1031:73:freechips.rocketchip.system.TinyConfig.fir@69085.4] wire [31:0] _T_396; // @[Debug.scala 1033:75:freechips.rocketchip.system.TinyConfig.fir@69087.4] wire [2:0] _T_401; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69097.4] wire [7:0] _T_501; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69206.4] wire [7:0] _T_524; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69234.4] wire [7:0] _T_549; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69264.4] wire [7:0] _T_574; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69294.4] wire [31:0] _T_584; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69308.4] wire [31:0] _T_705; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69454.4] wire [31:0] _T_803; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69572.4] wire [31:0] _T_901; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69690.4] wire [31:0] _T_999; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69808.4] wire [31:0] _T_1097; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69926.4] wire [31:0] _T_1195; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70044.4] wire [31:0] _T_1293; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70162.4] wire [31:0] _T_1391; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70280.4] wire [31:0] _T_1558; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70472.4] wire [31:0] _T_1656; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70590.4] wire [31:0] _T_1754; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70708.4] wire [31:0] _T_1875; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70849.4] wire [31:0] _T_1973; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70967.4] wire [31:0] _T_2094; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71113.4] wire [31:0] _T_2215; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71254.4] wire [31:0] _T_2313; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71372.4] wire _GEN_248; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_249; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_250; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_251; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_252; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_253; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_254; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_255; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_256; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_257; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_258; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_259; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_260; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_261; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_262; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_263; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_264; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_265; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_266; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_267; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_268; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_269; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_270; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_271; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_272; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_273; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_274; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_275; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_276; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_277; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire _GEN_278; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] wire [31:0] _GEN_280; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_281; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_282; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_283; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_284; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_285; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_286; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_287; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_288; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_289; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_290; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_291; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_292; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_293; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_294; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_295; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_296; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_297; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_298; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_299; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_300; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_301; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_302; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_303; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_304; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_305; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_306; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_307; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_308; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_309; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire [31:0] _GEN_310; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] wire _T_3086; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72928.4] wire _T_3087; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72932.4] wire _T_3088; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72936.4] wire _T_3089; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72940.4] wire _T_3090; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72944.4] wire _T_3091; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72948.4] wire _T_3092; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72952.4] wire _T_3093; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72956.4] wire _T_3094; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72960.4] wire _T_3095; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72964.4] wire _T_3096; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72968.4] wire _T_3097; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72972.4] wire _T_3098; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72976.4] wire _T_3099; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72980.4] wire _T_3100; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72984.4] wire _T_3101; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72988.4] wire _T_3102; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72992.4] wire _T_3103; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72996.4] wire _T_3104; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73000.4] wire _T_3105; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73004.4] wire _T_3106; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73008.4] wire _T_3107; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73012.4] wire _T_3108; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73016.4] wire _T_3109; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73020.4] wire _T_3110; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73024.4] wire _T_3111; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73028.4] wire _T_3112; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73032.4] wire _T_3113; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73036.4] wire _T_3114; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73040.4] wire _T_3115; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73044.4] wire _T_3116; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73048.4] wire _T_3117; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73052.4] wire _T_3118; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73056.4] wire _T_3119; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73060.4] wire _T_3120; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73064.4] wire _T_3121; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73068.4] wire _T_3122; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73072.4] wire _T_3123; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73076.4] wire _T_3124; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73080.4] wire _T_3125; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73084.4] wire _T_3126; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73088.4] wire _T_3127; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73092.4] wire _T_3128; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73096.4] wire _T_3129; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73100.4] wire _T_3130; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73104.4] wire _T_3131; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73108.4] wire _T_3132; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73112.4] wire _T_3133; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73116.4] wire _T_3134; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73120.4] wire _T_3135; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73124.4] wire _T_3136; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73128.4] wire _T_3137; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73132.4] wire _T_3138; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73136.4] wire _T_3139; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73140.4] wire _T_3140; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73144.4] wire _T_3141; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73148.4] wire _T_3142; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73152.4] wire _T_3143; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73156.4] wire _T_3144; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73160.4] wire _T_3145; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73164.4] wire _T_3146; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73168.4] wire _T_3147; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73172.4] wire _T_3148; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73176.4] wire _T_3149; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73180.4] wire _T_3150; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73184.4] wire _T_3151; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73188.4] wire _T_3152; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73192.4] wire _T_3153; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73196.4] reg goReg; // @[Debug.scala 1089:27:freechips.rocketchip.system.TinyConfig.fir@73200.4] reg [31:0] _RAND_77; wire _T_3214; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73318.10] wire _T_3215; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73319.10] wire _T_7992; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78433.4] wire _T_16464; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92133.4] wire _T_16465; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92134.4] wire hartGoingWrEn; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74868.4] wire _GEN_2678; // @[Debug.scala 1340:43:freechips.rocketchip.system.TinyConfig.fir@96602.10] wire _GEN_2682; // @[Debug.scala 1337:38:freechips.rocketchip.system.TinyConfig.fir@96597.8] wire _GEN_2695; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] wire goAbstract; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] wire accessRegisterCommandReg_postexec; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73408.4] wire [2:0] accessRegisterCommandReg_size; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73412.4] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala 1170:35:freechips.rocketchip.system.TinyConfig.fir@73421.4] reg [31:0] _RAND_78; reg [31:0] abstractGeneratedMem_1; // @[Debug.scala 1170:35:freechips.rocketchip.system.TinyConfig.fir@73421.4] reg [31:0] _RAND_79; wire [15:0] _T_3263; // @[Debug.scala 1176:66:freechips.rocketchip.system.TinyConfig.fir@73444.4] wire [4:0] abstractGeneratedI_rd; // @[Debug.scala 1171:34:freechips.rocketchip.system.TinyConfig.fir@73422.4 Debug.scala 1176:31:freechips.rocketchip.system.TinyConfig.fir@73445.4] wire [31:0] _T_3283; // @[Debug.scala 1197:36:freechips.rocketchip.system.TinyConfig.fir@73496.6] wire [31:0] _T_3288; // @[Debug.scala 1199:36:freechips.rocketchip.system.TinyConfig.fir@73501.6] wire [11:0] _T_3312; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@73533.4] wire [7:0] _T_3444; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73673.4] wire _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73676.4] wire [7:0] _T_3456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73685.4] wire [7:0] _T_3467; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73696.4] wire _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73699.4] wire [7:0] _T_3479; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73708.4] wire [7:0] _T_3492; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73721.4] wire _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73724.4] wire [7:0] _T_3504; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73733.4] wire [7:0] _T_3517; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73746.4] wire _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73749.4] wire [7:0] _T_3529; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73758.4] wire _T_7631; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78072.4] wire _T_12093; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84712.4] wire _T_12094; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84713.4] wire _T_3650; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73879.4] wire _T_3673; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73905.4] wire _T_3698; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73933.4] wire _T_3723; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73961.4] wire _T_7630; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78071.4] wire _T_12088; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84701.4] wire _T_12089; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84702.4] wire _T_3748; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73989.4] wire _T_3771; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74015.4] wire _T_3796; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74043.4] wire _T_3821; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74071.4] wire _T_7625; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78066.4] wire _T_12063; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84646.4] wire _T_12064; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84647.4] wire _T_3846; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74099.4] wire _T_3869; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74125.4] wire _T_3894; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74153.4] wire _T_3919; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74181.4] wire _T_7635; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78076.4] wire _T_12113; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84756.4] wire _T_12114; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84757.4] wire _T_4042; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74307.4] wire _T_4065; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74333.4] wire _T_4090; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74361.4] wire _T_4115; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74389.4] wire _T_7634; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78075.4] wire _T_12108; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84745.4] wire _T_12109; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84746.4] wire _T_4457; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74734.4] wire _T_4480; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74760.4] wire _T_4505; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74788.4] wire _T_4530; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74816.4] wire _T_7638; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78079.4] wire _T_12128; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84789.4] wire _T_12129; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84790.4] wire _T_4699; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74990.4] wire _T_4722; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75016.4] wire _T_4747; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75044.4] wire _T_4772; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75072.4] wire [15:0] _T_4930; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@75233.4] wire _T_7626; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78067.4] wire _T_12068; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84657.4] wire _T_12069; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84658.4] wire _T_5041; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75344.4] wire _T_5064; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75370.4] wire _T_5089; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75398.4] wire _T_5114; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75426.4] wire _T_7633; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78074.4] wire _T_12103; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84734.4] wire _T_12104; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84735.4] wire _T_5456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75773.4] wire _T_5479; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75799.4] wire _T_5504; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75827.4] wire _T_5529; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75855.4] wire _T_7622; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78063.4] wire _T_12048; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84613.4] wire _T_12049; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84614.4] wire _T_5554; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75883.4] wire _T_5577; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75909.4] wire _T_5602; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75937.4] wire _T_5627; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75965.4] wire _T_7627; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78068.4] wire _T_12073; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84668.4] wire _T_12074; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84669.4] wire _T_5652; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75993.4] wire _T_5675; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76019.4] wire _T_5700; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76047.4] wire _T_5725; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76075.4] wire _T_7637; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78078.4] wire _T_12123; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84778.4] wire _T_12124; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84779.4] wire _T_5969; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76324.4] wire _T_5992; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76350.4] wire _T_6017; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76378.4] wire _T_6042; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76406.4] wire _T_7623; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78064.4] wire _T_12053; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84624.4] wire _T_12054; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84625.4] wire _T_6165; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76532.4] wire _T_6188; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76558.4] wire _T_6213; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76586.4] wire _T_6238; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76614.4] wire _T_7632; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78073.4] wire _T_12098; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84723.4] wire _T_12099; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84724.4] wire _T_6580; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76961.4] wire _T_6603; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76987.4] wire _T_6628; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77015.4] wire _T_6653; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77043.4] wire _T_7628; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78069.4] wire _T_12078; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84679.4] wire _T_12079; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84680.4] wire _T_6799; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77192.4] wire _T_6822; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77218.4] wire _T_6847; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77246.4] wire _T_6872; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77274.4] wire _T_7624; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78065.4] wire _T_12058; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84635.4] wire _T_12059; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84636.4] wire _T_6897; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77302.4] wire _T_6920; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77328.4] wire _T_6945; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77356.4] wire _T_6970; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77384.4] wire _T_7629; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78070.4] wire _T_12083; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84690.4] wire _T_12084; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84691.4] wire _T_7191; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77608.4] wire _T_7214; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77634.4] wire _T_7239; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77662.4] wire _T_7264; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77690.4] wire _T_7636; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78077.4] wire _T_12118; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84767.4] wire _T_12119; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84768.4] wire _T_7289; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77718.4] wire _T_7312; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77744.4] wire _T_7337; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77772.4] wire _T_7362; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77800.4] wire _T_18708; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95948.4] wire _T_18709; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95953.6] wire _T_18710; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95958.8] wire _T_18711; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95963.10] wire _T_18712; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95968.12] wire _T_18713; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95973.14] wire _T_18714; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95978.16] wire _T_18715; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95983.18] wire _T_18716; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95988.20] wire _T_18717; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95993.22] wire _T_18718; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95998.24] wire _T_18719; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96003.26] wire _T_18720; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96008.28] wire _T_18721; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96013.30] wire _T_18722; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96018.32] wire _T_18723; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96023.34] wire _T_18724; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96028.36] wire _T_18725; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96033.38] wire _T_18726; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96038.40] wire _T_18727; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96043.42] wire _T_18728; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96048.44] wire _T_18729; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96053.46] wire _T_18730; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96058.48] wire _T_18731; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96063.50] wire _T_18732; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96068.52] wire _T_18733; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96073.54] wire _T_18734; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96078.56] wire _T_18735; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96083.58] wire _T_18736; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96088.60] wire _T_18737; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96093.62] wire _T_18738; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96098.64] wire _T_18739; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96103.66] wire _T_18740; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96108.68] wire _T_18741; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96113.70] wire _T_18742; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96118.72] wire _T_18743; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96123.74] wire _T_18744; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96128.76] wire _T_18745; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96133.78] wire _T_18746; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96138.80] wire _T_18747; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96143.82] wire _T_18748; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96148.84] wire _T_18749; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96153.86] wire _T_18750; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96158.88] wire _T_18751; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96163.90] wire _T_18752; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96168.92] wire _T_18753; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96173.94] wire _GEN_2504; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96174.94] wire _GEN_2505; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96169.92] wire _GEN_2506; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96164.90] wire _GEN_2507; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96159.88] wire _GEN_2508; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96154.86] wire _GEN_2509; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96149.84] wire _GEN_2510; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96144.82] wire _GEN_2511; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96139.80] wire _GEN_2512; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96134.78] wire _GEN_2513; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96129.76] wire _GEN_2514; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96124.74] wire _GEN_2515; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96119.72] wire _GEN_2516; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96114.70] wire _GEN_2517; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96109.68] wire _GEN_2518; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96104.66] wire _GEN_2519; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96099.64] wire _GEN_2520; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96094.62] wire _GEN_2521; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96089.60] wire _GEN_2522; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96084.58] wire _GEN_2523; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96079.56] wire _GEN_2524; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96074.54] wire _GEN_2525; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96069.52] wire _GEN_2526; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96064.50] wire _GEN_2527; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96059.48] wire _GEN_2528; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96054.46] wire _GEN_2529; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96049.44] wire _GEN_2530; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96044.42] wire _GEN_2531; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96039.40] wire _GEN_2532; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96034.38] wire _GEN_2533; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96029.36] wire _GEN_2534; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96024.34] wire _GEN_2535; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96019.32] wire _GEN_2536; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96014.30] wire _GEN_2537; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96009.28] wire _GEN_2538; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96004.26] wire _GEN_2539; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95999.24] wire _GEN_2540; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95994.22] wire _GEN_2541; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95989.20] wire _GEN_2542; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95984.18] wire _GEN_2543; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95979.16] wire _GEN_2544; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95974.14] wire _GEN_2545; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95969.12] wire _GEN_2546; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95964.10] wire _GEN_2547; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95959.8] wire _GEN_2548; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95954.6] wire _GEN_2549; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@95949.4] wire [31:0] _GEN_2550; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96406.94] wire [31:0] _GEN_2551; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96401.92] wire [31:0] _GEN_2552; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96396.90] wire [31:0] _GEN_2553; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96391.88] wire [31:0] _GEN_2554; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96386.86] wire [31:0] _GEN_2555; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96381.84] wire [31:0] _GEN_2556; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96376.82] wire [31:0] _GEN_2557; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96371.80] wire [31:0] _GEN_2558; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96366.78] wire [31:0] _GEN_2559; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96361.76] wire [31:0] _GEN_2560; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96356.74] wire [31:0] _GEN_2561; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96351.72] wire [31:0] _GEN_2562; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96346.70] wire [31:0] _GEN_2563; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96341.68] wire [31:0] _GEN_2564; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96336.66] wire [31:0] _GEN_2565; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96331.64] wire [31:0] _GEN_2566; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96326.62] wire [31:0] _GEN_2567; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96321.60] wire [31:0] _GEN_2568; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96316.58] wire [31:0] _GEN_2569; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96311.56] wire [31:0] _GEN_2570; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96306.54] wire [31:0] _GEN_2571; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96301.52] wire [31:0] _GEN_2572; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96296.50] wire [31:0] _GEN_2573; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96291.48] wire [31:0] _GEN_2574; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96286.46] wire [31:0] _GEN_2575; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96281.44] wire [31:0] _GEN_2576; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96276.42] wire [31:0] _GEN_2577; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96271.40] wire [31:0] _GEN_2578; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96266.38] wire [31:0] _GEN_2579; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96261.36] wire [31:0] _GEN_2580; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96256.34] wire [31:0] _GEN_2581; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96251.32] wire [31:0] _GEN_2582; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96246.30] wire [31:0] _GEN_2583; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96241.28] wire [31:0] _GEN_2584; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96236.26] wire [31:0] _GEN_2585; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96231.24] wire [31:0] _GEN_2586; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96226.22] wire [31:0] _GEN_2587; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96221.20] wire [31:0] _GEN_2588; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96216.18] wire [31:0] _GEN_2589; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96211.16] wire [31:0] _GEN_2590; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96206.14] wire [31:0] _GEN_2591; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96201.12] wire [31:0] _GEN_2592; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96196.10] wire [31:0] _GEN_2593; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96191.8] wire [31:0] _GEN_2594; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96186.6] wire [31:0] _GEN_2595; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@96181.4] wire _T_18848; // @[Debug.scala 1356:18:freechips.rocketchip.system.TinyConfig.fir@96619.10] wire _T_18849; // @[Debug.scala 1356:30:freechips.rocketchip.system.TinyConfig.fir@96620.10] wire _T_18851; // @[Debug.scala 1356:48:freechips.rocketchip.system.TinyConfig.fir@96622.10] wire _T_18856; // @[Debug.scala 1364:30:freechips.rocketchip.system.TinyConfig.fir@96640.10] wire _T_18859; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96644.12] wire _T_18862; // @[Debug.scala 1378:14:freechips.rocketchip.system.TinyConfig.fir@96662.4] wire _T_18863; // @[Debug.scala 1378:30:freechips.rocketchip.system.TinyConfig.fir@96663.4] wire _T_18864; // @[Debug.scala 1378:27:freechips.rocketchip.system.TinyConfig.fir@96664.4] wire _T_18866; // @[Debug.scala 1378:49:freechips.rocketchip.system.TinyConfig.fir@96666.4] wire _T_18868; // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96668.4] wire _T_18869; // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96669.4] wire _GEN_2705; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] wire _GEN_2706; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] wire _GEN_2707; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] wire _GEN_2708; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] wire _GEN_2713; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] wire _GEN_2714; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] wire _GEN_2715; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] wire _GEN_2716; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] wire _GEN_2717; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] wire _GEN_2726; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] wire _GEN_2727; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] wire _GEN_2728; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] TLMonitor_33 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67920.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); TLMonitor_34 TLMonitor_1 ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@67971.4] .clock(TLMonitor_1_clock), .reset(TLMonitor_1_reset), .io_in_a_ready(TLMonitor_1_io_in_a_ready), .io_in_a_valid(TLMonitor_1_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_1_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_1_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_1_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_1_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_1_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_1_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_1_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_1_io_in_d_ready), .io_in_d_valid(TLMonitor_1_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_1_io_in_d_bits_opcode), .io_in_d_bits_size(TLMonitor_1_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_1_io_in_d_bits_source) ); assign hamaskWrSel_0 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala 669:61:freechips.rocketchip.system.TinyConfig.fir@68233.4] assign _T_60 = io_innerCtrl_ready & io_innerCtrl_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@68286.4] assign resumereq = _T_60 & io_innerCtrl_bits_resumereq; // @[Debug.scala 683:41:freechips.rocketchip.system.TinyConfig.fir@68287.4] assign DMSTATUSRdData_anyrunning = haltedBitRegs_0 == 1'h0; // @[package.scala 62:38:freechips.rocketchip.system.TinyConfig.fir@68303.6] assign DMSTATUSRdData_anyresumeack = resumeReqRegs_0 == 1'h0; // @[package.scala 62:38:freechips.rocketchip.system.TinyConfig.fir@68309.6] assign _T_95 = _T_60 & io_innerCtrl_bits_ackhavereset; // @[Debug.scala 705:33:freechips.rocketchip.system.TinyConfig.fir@68338.4] assign _T_96 = _T_95 & hamaskWrSel_0; // @[Debug.scala 705:67:freechips.rocketchip.system.TinyConfig.fir@68339.4] assign haltedStatus_0 = {{31'd0}, haltedBitRegs_0}; // @[Debug.scala 850:30:freechips.rocketchip.system.TinyConfig.fir@68402.4 Debug.scala 853:24:freechips.rocketchip.system.TinyConfig.fir@68404.4] assign haltedSummary = haltedStatus_0 != 32'h0; // @[Debug.scala 856:48:freechips.rocketchip.system.TinyConfig.fir@68405.4] assign HALTSUM1RdData_haltsum1 = {{31'd0}, haltedSummary}; // @[:freechips.rocketchip.system.TinyConfig.fir@68408.4 :freechips.rocketchip.system.TinyConfig.fir@68410.4] assign _T_399 = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@69091.4] assign _T_400 = auto_dmi_in_a_bits_address[8:2]; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@69093.4] assign _T_2321 = _T_400[5]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71380.4] assign _T_2319 = _T_400[3]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71378.4] assign _T_2318 = _T_400[2]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71377.4] assign _T_2317 = _T_400[1]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71376.4] assign _T_2316 = _T_400[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71375.4] assign _T_2326 = {_T_2321,_T_2319,_T_2318,_T_2317,_T_2316}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71385.4] assign _T_405 = _T_400 & 7'h50; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69105.4] assign _T_453 = _T_405 == 7'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69153.4] assign _T_409 = _T_405 == 7'h10; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69109.4] assign _T_427 = _T_405 == 7'h40; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69127.4] assign _T_2900 = auto_dmi_in_a_valid & auto_dmi_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72475.4] assign _T_2901 = _T_399 == 1'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72476.4] assign _T_2902 = _T_2900 & _T_2901; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72477.4] assign _T_2371 = 32'h1 << _T_2326; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@71430.4] assign _T_2378 = _T_2371[6]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71437.4] assign _T_2934 = _T_2902 & _T_2378; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72530.4] assign _T_2935 = _T_2934 & _T_409; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72531.4] assign _T_477 = auto_dmi_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69181.4] assign _T_485 = _T_477 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69189.4] assign _T_476 = auto_dmi_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69180.4] assign _T_483 = _T_476 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69187.4] assign _T_475 = auto_dmi_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69179.4] assign _T_481 = _T_475 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69185.4] assign _T_474 = auto_dmi_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@69178.4] assign _T_479 = _T_474 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@69183.4] assign _T_488 = {_T_485,_T_483,_T_481,_T_479}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69192.4] assign _T_1447 = _T_488 == 32'hffffffff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70336.4] assign ABSTRACTCSWrEnMaybe = _T_2935 & _T_1447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70340.4] assign ABSTRACTCSWrDataVal = ABSTRACTCSWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@70344.4] assign ABSTRACTCSWrData_cmderr = ABSTRACTCSWrDataVal[10:8]; // @[Debug.scala 872:64:freechips.rocketchip.system.TinyConfig.fir@68463.4] assign ABSTRACTCSWrEnLegal = ctrlStateReg == 2'h0; // @[Debug.scala 1277:44:freechips.rocketchip.system.TinyConfig.fir@96518.4] assign ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala 879:51:freechips.rocketchip.system.TinyConfig.fir@68487.4] assign _T_139 = ~ io_dmactive; // @[Debug.scala 886:10:freechips.rocketchip.system.TinyConfig.fir@68500.4] assign _T_140 = ~ ABSTRACTCSWrData_cmderr; // @[Debug.scala 899:58:freechips.rocketchip.system.TinyConfig.fir@68522.16] assign _T_141 = ABSTRACTCSReg_cmderr & _T_140; // @[Debug.scala 899:56:freechips.rocketchip.system.TinyConfig.fir@68523.16] assign _T_18846 = ctrlStateReg == 2'h1; // @[Debug.scala 1330:30:freechips.rocketchip.system.TinyConfig.fir@96595.6] assign commandRegIsAccessRegister = COMMANDRdData_cmdtype == 8'h0; // @[Debug.scala 1291:58:freechips.rocketchip.system.TinyConfig.fir@96544.4] assign _T_3245 = {COMMANDRdData_cmdtype,COMMANDRdData_control}; // @[Debug.scala 1127:104:freechips.rocketchip.system.TinyConfig.fir@73396.4] assign accessRegisterCommandReg_transfer = _T_3245[17]; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73406.4] assign accessRegisterCommandReg_write = _T_3245[16]; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73404.4] assign _T_18836 = accessRegisterCommandReg_transfer == 1'h0; // @[Debug.scala 1309:19:freechips.rocketchip.system.TinyConfig.fir@96564.8] assign accessRegisterCommandReg_regno = _T_3245[15:0]; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73402.4] assign _T_18831 = accessRegisterCommandReg_regno >= 16'h1000; // @[Debug.scala 1299:58:freechips.rocketchip.system.TinyConfig.fir@96553.4] assign _T_18832 = accessRegisterCommandReg_regno <= 16'h101f; // @[Debug.scala 1299:104:freechips.rocketchip.system.TinyConfig.fir@96554.4] assign accessRegIsGPR = _T_18831 & _T_18832; // @[Debug.scala 1299:70:freechips.rocketchip.system.TinyConfig.fir@96555.4] assign _T_18837 = _T_18836 | accessRegIsGPR; // @[Debug.scala 1309:54:freechips.rocketchip.system.TinyConfig.fir@96565.8] assign _GEN_2664 = _T_18837 ? 1'h0 : 1'h1; // @[Debug.scala 1309:73:freechips.rocketchip.system.TinyConfig.fir@96566.8] assign commandRegIsUnsupported = commandRegIsAccessRegister ? _GEN_2664 : 1'h1; // @[Debug.scala 1306:39:freechips.rocketchip.system.TinyConfig.fir@96556.4] assign _T_18838 = ~ haltedBitRegs_0; // @[Debug.scala 1311:36:freechips.rocketchip.system.TinyConfig.fir@96568.10] assign _GEN_2665 = _T_18837 ? _T_18838 : 1'h0; // @[Debug.scala 1309:73:freechips.rocketchip.system.TinyConfig.fir@96566.8] assign commandRegBadHaltResume = commandRegIsAccessRegister ? _GEN_2665 : 1'h0; // @[Debug.scala 1306:39:freechips.rocketchip.system.TinyConfig.fir@96556.4] assign _GEN_2681 = commandRegIsUnsupported ? 1'h0 : commandRegBadHaltResume; // @[Debug.scala 1337:38:freechips.rocketchip.system.TinyConfig.fir@96597.8] assign _GEN_2694 = _T_18846 ? _GEN_2681 : 1'h0; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] assign errorHaltResume = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2694; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] assign _T_2379 = _T_2371[7]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71438.4] assign _T_2939 = _T_2902 & _T_2379; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72538.4] assign _T_2940 = _T_2939 & _T_409; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72539.4] assign COMMANDWrEnMaybe = _T_2940 & _T_1447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70981.4] assign COMMANDWrEn = COMMANDWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala 957:40:freechips.rocketchip.system.TinyConfig.fir@69007.4] assign COMMANDWrDataVal = COMMANDWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@70985.4] assign COMMANDWrData_cmdtype = COMMANDWrDataVal[31:24]; // @[Debug.scala 952:73:freechips.rocketchip.system.TinyConfig.fir@68993.4] assign commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala 1290:60:freechips.rocketchip.system.TinyConfig.fir@96543.4] assign _T_18839 = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala 1315:48:freechips.rocketchip.system.TinyConfig.fir@96572.4] assign _T_18840 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala 1315:103:freechips.rocketchip.system.TinyConfig.fir@96573.4] assign wrAccessRegisterCommand = _T_18839 & _T_18840; // @[Debug.scala 1315:78:freechips.rocketchip.system.TinyConfig.fir@96574.4] assign _T_2376 = _T_2371[4]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71435.4] assign _T_2924 = _T_2902 & _T_2376; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72512.4] assign _T_2925 = _T_2924 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72513.4] assign _T_2126 = _T_488[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71145.4] assign _T_2127 = _T_2126 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71146.4] assign dmiAbstractDataWrEnMaybe_0 = _T_2925 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71150.4] assign _T_2736 = _T_2900 & _T_399; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72139.4] assign _T_2758 = _T_2736 & _T_2376; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72174.4] assign _T_2759 = _T_2758 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72175.4] assign _T_2125 = _T_2126 != 8'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71144.4] assign dmiAbstractDataRdEn_0 = _T_2759 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71148.4] assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68594.4] assign _T_290 = ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala 941:54:freechips.rocketchip.system.TinyConfig.fir@68892.4] assign autoexecData_0 = dmiAbstractDataAccessVec_0 & _T_290; // @[Debug.scala 941:140:freechips.rocketchip.system.TinyConfig.fir@68904.4] assign _T_2388 = _T_2371[16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71447.4] assign _T_2984 = _T_2902 & _T_2388; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72603.4] assign _T_2985 = _T_2984 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72604.4] assign dmiProgramBufferWrEnMaybe_0 = _T_2985 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69940.4] assign _T_2818 = _T_2736 & _T_2388; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72265.4] assign _T_2819 = _T_2818 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72266.4] assign dmiProgramBufferRdEn_0 = _T_2819 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69938.4] assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68671.4] assign _T_303 = ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68906.4] assign autoexecProg_0 = dmiProgramBufferAccessVec_0 & _T_303; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68922.4] assign _T_2389 = _T_2371[17]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71448.4] assign _T_2989 = _T_2902 & _T_2389; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72614.4] assign _T_2990 = _T_2989 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72615.4] assign dmiProgramBufferWrEnMaybe_4 = _T_2990 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69704.4] assign _T_2823 = _T_2736 & _T_2389; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72276.4] assign _T_2824 = _T_2823 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72277.4] assign dmiProgramBufferRdEn_4 = _T_2824 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69702.4] assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68675.4] assign _T_304 = ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68907.4] assign autoexecProg_1 = dmiProgramBufferAccessVec_4 & _T_304; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68924.4] assign _T_335 = autoexecProg_0 | autoexecProg_1; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68954.4] assign _T_2390 = _T_2371[18]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71449.4] assign _T_2994 = _T_2902 & _T_2390; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72625.4] assign _T_2995 = _T_2994 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72626.4] assign dmiProgramBufferWrEnMaybe_8 = _T_2995 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70058.4] assign _T_2828 = _T_2736 & _T_2390; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72287.4] assign _T_2829 = _T_2828 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72288.4] assign dmiProgramBufferRdEn_8 = _T_2829 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70056.4] assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68679.4] assign _T_305 = ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68908.4] assign autoexecProg_2 = dmiProgramBufferAccessVec_8 & _T_305; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68926.4] assign _T_336 = _T_335 | autoexecProg_2; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68955.4] assign _T_2391 = _T_2371[19]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71450.4] assign _T_2999 = _T_2902 & _T_2391; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72636.4] assign _T_3000 = _T_2999 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72637.4] assign dmiProgramBufferWrEnMaybe_12 = _T_3000 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70604.4] assign _T_2833 = _T_2736 & _T_2391; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72298.4] assign _T_2834 = _T_2833 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72299.4] assign dmiProgramBufferRdEn_12 = _T_2834 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70602.4] assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68683.4] assign _T_306 = ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68909.4] assign autoexecProg_3 = dmiProgramBufferAccessVec_12 & _T_306; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68928.4] assign _T_337 = _T_336 | autoexecProg_3; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68956.4] assign _T_2392 = _T_2371[20]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71451.4] assign _T_3004 = _T_2902 & _T_2392; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72647.4] assign _T_3005 = _T_3004 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72648.4] assign dmiProgramBufferWrEnMaybe_16 = _T_3005 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71009.4] assign _T_2838 = _T_2736 & _T_2392; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72309.4] assign _T_2839 = _T_2838 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72310.4] assign dmiProgramBufferRdEn_16 = _T_2839 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71007.4] assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68687.4] assign _T_307 = ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68910.4] assign autoexecProg_4 = dmiProgramBufferAccessVec_16 & _T_307; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68930.4] assign _T_338 = _T_337 | autoexecProg_4; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68957.4] assign _T_2393 = _T_2371[21]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71452.4] assign _T_3009 = _T_2902 & _T_2393; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72658.4] assign _T_3010 = _T_3009 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72659.4] assign dmiProgramBufferWrEnMaybe_20 = _T_3010 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69350.4] assign _T_2843 = _T_2736 & _T_2393; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72320.4] assign _T_2844 = _T_2843 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72321.4] assign dmiProgramBufferRdEn_20 = _T_2844 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69348.4] assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68691.4] assign _T_308 = ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68911.4] assign autoexecProg_5 = dmiProgramBufferAccessVec_20 & _T_308; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68932.4] assign _T_339 = _T_338 | autoexecProg_5; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68958.4] assign _T_2394 = _T_2371[22]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71453.4] assign _T_3014 = _T_2902 & _T_2394; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72669.4] assign _T_3015 = _T_3014 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72670.4] assign dmiProgramBufferWrEnMaybe_24 = _T_3015 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69586.4] assign _T_2848 = _T_2736 & _T_2394; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72331.4] assign _T_2849 = _T_2848 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72332.4] assign dmiProgramBufferRdEn_24 = _T_2849 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69584.4] assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68695.4] assign _T_309 = ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68912.4] assign autoexecProg_6 = dmiProgramBufferAccessVec_24 & _T_309; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68934.4] assign _T_340 = _T_339 | autoexecProg_6; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68959.4] assign _T_2395 = _T_2371[23]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71454.4] assign _T_3019 = _T_2902 & _T_2395; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72680.4] assign _T_3020 = _T_3019 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72681.4] assign dmiProgramBufferWrEnMaybe_28 = _T_3020 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70486.4] assign _T_2853 = _T_2736 & _T_2395; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72342.4] assign _T_2854 = _T_2853 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72343.4] assign dmiProgramBufferRdEn_28 = _T_2854 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70484.4] assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68699.4] assign _T_310 = ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68913.4] assign autoexecProg_7 = dmiProgramBufferAccessVec_28 & _T_310; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68936.4] assign _T_341 = _T_340 | autoexecProg_7; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68960.4] assign _T_2396 = _T_2371[24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71455.4] assign _T_3024 = _T_2902 & _T_2396; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72691.4] assign _T_3025 = _T_3024 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72692.4] assign dmiProgramBufferWrEnMaybe_32 = _T_3025 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70863.4] assign _T_2858 = _T_2736 & _T_2396; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72353.4] assign _T_2859 = _T_2858 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72354.4] assign dmiProgramBufferRdEn_32 = _T_2859 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70861.4] assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68703.4] assign _T_311 = ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68914.4] assign autoexecProg_8 = dmiProgramBufferAccessVec_32 & _T_311; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68938.4] assign _T_342 = _T_341 | autoexecProg_8; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68961.4] assign _T_2397 = _T_2371[25]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71456.4] assign _T_3029 = _T_2902 & _T_2397; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72702.4] assign _T_3030 = _T_3029 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72703.4] assign dmiProgramBufferWrEnMaybe_36 = _T_3030 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69822.4] assign _T_2863 = _T_2736 & _T_2397; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72364.4] assign _T_2864 = _T_2863 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72365.4] assign dmiProgramBufferRdEn_36 = _T_2864 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69820.4] assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68707.4] assign _T_312 = ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68915.4] assign autoexecProg_9 = dmiProgramBufferAccessVec_36 & _T_312; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68940.4] assign _T_343 = _T_342 | autoexecProg_9; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68962.4] assign _T_2398 = _T_2371[26]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71457.4] assign _T_3034 = _T_2902 & _T_2398; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72713.4] assign _T_3035 = _T_3034 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72714.4] assign dmiProgramBufferWrEnMaybe_40 = _T_3035 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69204.4] assign _T_2868 = _T_2736 & _T_2398; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72375.4] assign _T_2869 = _T_2868 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72376.4] assign dmiProgramBufferRdEn_40 = _T_2869 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69202.4] assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68711.4] assign _T_313 = ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68916.4] assign autoexecProg_10 = dmiProgramBufferAccessVec_40 & _T_313; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68942.4] assign _T_344 = _T_343 | autoexecProg_10; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68963.4] assign _T_2399 = _T_2371[27]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71458.4] assign _T_3039 = _T_2902 & _T_2399; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72724.4] assign _T_3040 = _T_3039 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72725.4] assign dmiProgramBufferWrEnMaybe_44 = _T_3040 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70745.4] assign _T_2873 = _T_2736 & _T_2399; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72386.4] assign _T_2874 = _T_2873 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72387.4] assign dmiProgramBufferRdEn_44 = _T_2874 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70743.4] assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68715.4] assign _T_314 = ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68917.4] assign autoexecProg_11 = dmiProgramBufferAccessVec_44 & _T_314; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68944.4] assign _T_345 = _T_344 | autoexecProg_11; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68964.4] assign _T_2400 = _T_2371[28]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71459.4] assign _T_3044 = _T_2902 & _T_2400; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72735.4] assign _T_3045 = _T_3044 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72736.4] assign dmiProgramBufferWrEnMaybe_48 = _T_3045 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70368.4] assign _T_2878 = _T_2736 & _T_2400; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72397.4] assign _T_2879 = _T_2878 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72398.4] assign dmiProgramBufferRdEn_48 = _T_2879 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70366.4] assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68719.4] assign _T_315 = ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68918.4] assign autoexecProg_12 = dmiProgramBufferAccessVec_48 & _T_315; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68946.4] assign _T_346 = _T_345 | autoexecProg_12; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68965.4] assign _T_2401 = _T_2371[29]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71460.4] assign _T_3049 = _T_2902 & _T_2401; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72746.4] assign _T_3050 = _T_3049 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72747.4] assign dmiProgramBufferWrEnMaybe_52 = _T_3050 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70176.4] assign _T_2883 = _T_2736 & _T_2401; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72408.4] assign _T_2884 = _T_2883 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72409.4] assign dmiProgramBufferRdEn_52 = _T_2884 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70174.4] assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68723.4] assign _T_316 = ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68919.4] assign autoexecProg_13 = dmiProgramBufferAccessVec_52 & _T_316; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68948.4] assign _T_347 = _T_346 | autoexecProg_13; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68966.4] assign _T_2402 = _T_2371[30]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71461.4] assign _T_3054 = _T_2902 & _T_2402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72757.4] assign _T_3055 = _T_3054 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72758.4] assign dmiProgramBufferWrEnMaybe_56 = _T_3055 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69468.4] assign _T_2888 = _T_2736 & _T_2402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72419.4] assign _T_2889 = _T_2888 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72420.4] assign dmiProgramBufferRdEn_56 = _T_2889 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69466.4] assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68727.4] assign _T_317 = ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68920.4] assign autoexecProg_14 = dmiProgramBufferAccessVec_56 & _T_317; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68950.4] assign _T_348 = _T_347 | autoexecProg_14; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68967.4] assign _T_2403 = _T_2371[31]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71462.4] assign _T_3059 = _T_2902 & _T_2403; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72768.4] assign _T_3060 = _T_3059 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72769.4] assign dmiProgramBufferWrEnMaybe_60 = _T_3060 & _T_2127; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71268.4] assign _T_2893 = _T_2736 & _T_2403; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72430.4] assign _T_2894 = _T_2893 & _T_453; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72431.4] assign dmiProgramBufferRdEn_60 = _T_2894 & _T_2125; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71266.4] assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68731.4] assign _T_318 = ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala 942:57:freechips.rocketchip.system.TinyConfig.fir@68921.4] assign autoexecProg_15 = dmiProgramBufferAccessVec_60 & _T_318; // @[Debug.scala 942:144:freechips.rocketchip.system.TinyConfig.fir@68952.4] assign _T_349 = _T_348 | autoexecProg_15; // @[Debug.scala 944:73:freechips.rocketchip.system.TinyConfig.fir@68968.4] assign autoexec = autoexecData_0 | _T_349; // @[Debug.scala 944:48:freechips.rocketchip.system.TinyConfig.fir@68969.4] assign _T_18841 = autoexec & commandRegIsAccessRegister; // @[Debug.scala 1316:48:freechips.rocketchip.system.TinyConfig.fir@96575.4] assign regAccessRegisterCommand = _T_18841 & _T_18840; // @[Debug.scala 1316:78:freechips.rocketchip.system.TinyConfig.fir@96577.4] assign _T_18844 = wrAccessRegisterCommand | regAccessRegisterCommand; // @[Debug.scala 1323:37:freechips.rocketchip.system.TinyConfig.fir@96580.6] assign _T_18830 = commandWrIsAccessRegister == 1'h0; // @[Debug.scala 1293:49:freechips.rocketchip.system.TinyConfig.fir@96545.4] assign commandWrIsUnsupported = COMMANDWrEn & _T_18830; // @[Debug.scala 1293:46:freechips.rocketchip.system.TinyConfig.fir@96546.4] assign _T_18845 = autoexec & commandRegIsUnsupported; // @[Debug.scala 1327:28:freechips.rocketchip.system.TinyConfig.fir@96589.10] assign _GEN_2671 = commandWrIsUnsupported ? 1'h1 : _T_18845; // @[Debug.scala 1325:43:freechips.rocketchip.system.TinyConfig.fir@96585.8] assign _GEN_2673 = _T_18844 ? 1'h0 : _GEN_2671; // @[Debug.scala 1323:66:freechips.rocketchip.system.TinyConfig.fir@96581.6] assign _GEN_2692 = _T_18846 ? commandRegIsUnsupported : 1'h0; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] assign errorUnsupported = ABSTRACTCSWrEnLegal ? _GEN_2673 : _GEN_2692; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] assign _T_18847 = ctrlStateReg == 2'h2; // @[Debug.scala 1351:30:freechips.rocketchip.system.TinyConfig.fir@96617.8] assign _T_3310 = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 59:36:freechips.rocketchip.system.TinyConfig.fir@73527.4] assign _T_3311 = auto_tl_in_a_bits_address[11:2]; // @[Edges.scala 193:34:freechips.rocketchip.system.TinyConfig.fir@73529.4] assign _T_7386 = _T_3311[9]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77827.4] assign _T_7384 = _T_3311[7]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77825.4] assign _T_7383 = _T_3311[6]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77824.4] assign _T_7382 = _T_3311[5]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77823.4] assign _T_7381 = _T_3311[4]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77822.4] assign _T_7380 = _T_3311[3]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77821.4] assign _T_7379 = _T_3311[2]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77820.4] assign _T_7378 = _T_3311[1]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77819.4] assign _T_7377 = _T_3311[0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77818.4] assign _T_7394 = {_T_7386,_T_7384,_T_7383,_T_7382,_T_7381,_T_7380,_T_7379,_T_7378,_T_7377}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@77835.4] assign _T_3316 = _T_3311 & 10'h100; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73541.4] assign _T_3402 = _T_3316 == 10'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73627.4] assign _T_3352 = _T_3316 == 10'h100; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73577.4] assign _T_16135 = auto_tl_in_a_valid & auto_tl_in_d_ready; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91670.4] assign _T_16136 = _T_3310 == 1'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91671.4] assign _T_16137 = _T_16135 & _T_16136; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@91672.4] assign _T_7926 = 512'h1 << _T_7394; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@78367.4] assign _T_7994 = _T_7926[67]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78435.4] assign _T_16474 = _T_16137 & _T_7994; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92149.4] assign _T_16475 = _T_16474 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92150.4] assign _T_3432 = auto_tl_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73661.4] assign _T_3440 = _T_3432 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73669.4] assign _T_3431 = auto_tl_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73660.4] assign _T_3438 = _T_3431 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73667.4] assign _T_3430 = auto_tl_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73659.4] assign _T_3436 = _T_3430 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73665.4] assign _T_3429 = auto_tl_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@73658.4] assign _T_3434 = _T_3429 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@73663.4] assign _T_3443 = {_T_3440,_T_3438,_T_3436,_T_3434}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@73672.4] assign _T_6455 = _T_3443[9:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76834.4] assign _T_6456 = _T_6455 == 10'h3ff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76835.4] assign hartExceptionWrEn = _T_16475 & _T_6456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76839.4] assign _GEN_2690 = _T_18847 ? hartExceptionWrEn : 1'h0; // @[Debug.scala 1351:51:freechips.rocketchip.system.TinyConfig.fir@96618.8] assign _GEN_2696 = _T_18846 ? 1'h0 : _GEN_2690; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] assign errorException = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2696; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] assign _T_18816 = ~ ABSTRACTCSWrEnLegal; // @[Debug.scala 1283:45:freechips.rocketchip.system.TinyConfig.fir@96528.4] assign _T_18817 = ABSTRACTCSWrEnMaybe & _T_18816; // @[Debug.scala 1283:42:freechips.rocketchip.system.TinyConfig.fir@96529.4] assign _T_2380 = _T_2371[8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71439.4] assign _T_2944 = _T_2902 & _T_2380; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72546.4] assign _T_2945 = _T_2944 & _T_409; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@72547.4] assign ABSTRACTAUTOWrEnMaybe = _T_2945 & _T_1447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69322.4] assign _T_18819 = ABSTRACTAUTOWrEnMaybe & _T_18816; // @[Debug.scala 1284:42:freechips.rocketchip.system.TinyConfig.fir@96531.4] assign _T_18820 = _T_18817 | _T_18819; // @[Debug.scala 1283:74:freechips.rocketchip.system.TinyConfig.fir@96532.4] assign _T_18822 = COMMANDWrEnMaybe & _T_18816; // @[Debug.scala 1285:42:freechips.rocketchip.system.TinyConfig.fir@96534.4] assign _T_18823 = _T_18820 | _T_18822; // @[Debug.scala 1284:74:freechips.rocketchip.system.TinyConfig.fir@96535.4] assign _T_2149 = _T_488[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71173.4] assign _T_2150 = _T_2149 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71174.4] assign dmiAbstractDataWrEnMaybe_1 = _T_2925 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71178.4] assign _T_2148 = _T_2149 != 8'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71172.4] assign dmiAbstractDataRdEn_1 = _T_2759 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71176.4] assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 | dmiAbstractDataRdEn_1; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68595.4] assign _T_224 = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68799.4] assign _T_2174 = _T_488[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71203.4] assign _T_2175 = _T_2174 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71204.4] assign dmiAbstractDataWrEnMaybe_2 = _T_2925 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71208.4] assign _T_2173 = _T_2174 != 8'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71202.4] assign dmiAbstractDataRdEn_2 = _T_2759 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71206.4] assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68596.4] assign _T_225 = _T_224 | dmiAbstractDataAccessVec_2; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68800.4] assign _T_2199 = _T_488[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71233.4] assign _T_2200 = _T_2199 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71234.4] assign dmiAbstractDataWrEnMaybe_3 = _T_2925 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71238.4] assign _T_2198 = _T_2199 != 8'h0; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71232.4] assign dmiAbstractDataRdEn_3 = _T_2759 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71236.4] assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3; // @[Debug.scala 930:105:freechips.rocketchip.system.TinyConfig.fir@68597.4] assign dmiAbstractDataAccess = _T_225 | dmiAbstractDataAccessVec_3; // @[Debug.scala 935:68:freechips.rocketchip.system.TinyConfig.fir@68801.4] assign _T_18825 = dmiAbstractDataAccess & _T_18816; // @[Debug.scala 1286:42:freechips.rocketchip.system.TinyConfig.fir@96537.4] assign _T_18826 = _T_18823 | _T_18825; // @[Debug.scala 1285:74:freechips.rocketchip.system.TinyConfig.fir@96538.4] assign dmiProgramBufferWrEnMaybe_1 = _T_2985 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69968.4] assign dmiProgramBufferRdEn_1 = _T_2819 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69966.4] assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 | dmiProgramBufferRdEn_1; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68672.4] assign _T_226 = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68802.4] assign dmiProgramBufferWrEnMaybe_2 = _T_2985 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69998.4] assign dmiProgramBufferRdEn_2 = _T_2819 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69996.4] assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 | dmiProgramBufferRdEn_2; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68673.4] assign _T_227 = _T_226 | dmiProgramBufferAccessVec_2; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68803.4] assign dmiProgramBufferWrEnMaybe_3 = _T_2985 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70028.4] assign dmiProgramBufferRdEn_3 = _T_2819 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70026.4] assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 | dmiProgramBufferRdEn_3; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68674.4] assign _T_228 = _T_227 | dmiProgramBufferAccessVec_3; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68804.4] assign _T_229 = _T_228 | dmiProgramBufferAccessVec_4; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68805.4] assign dmiProgramBufferWrEnMaybe_5 = _T_2990 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69732.4] assign dmiProgramBufferRdEn_5 = _T_2824 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69730.4] assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68676.4] assign _T_230 = _T_229 | dmiProgramBufferAccessVec_5; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68806.4] assign dmiProgramBufferWrEnMaybe_6 = _T_2990 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69762.4] assign dmiProgramBufferRdEn_6 = _T_2824 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69760.4] assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68677.4] assign _T_231 = _T_230 | dmiProgramBufferAccessVec_6; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68807.4] assign dmiProgramBufferWrEnMaybe_7 = _T_2990 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69792.4] assign dmiProgramBufferRdEn_7 = _T_2824 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69790.4] assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68678.4] assign _T_232 = _T_231 | dmiProgramBufferAccessVec_7; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68808.4] assign _T_233 = _T_232 | dmiProgramBufferAccessVec_8; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68809.4] assign dmiProgramBufferWrEnMaybe_9 = _T_2995 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70086.4] assign dmiProgramBufferRdEn_9 = _T_2829 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70084.4] assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 | dmiProgramBufferRdEn_9; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68680.4] assign _T_234 = _T_233 | dmiProgramBufferAccessVec_9; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68810.4] assign dmiProgramBufferWrEnMaybe_10 = _T_2995 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70116.4] assign dmiProgramBufferRdEn_10 = _T_2829 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70114.4] assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 | dmiProgramBufferRdEn_10; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68681.4] assign _T_235 = _T_234 | dmiProgramBufferAccessVec_10; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68811.4] assign dmiProgramBufferWrEnMaybe_11 = _T_2995 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70146.4] assign dmiProgramBufferRdEn_11 = _T_2829 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70144.4] assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 | dmiProgramBufferRdEn_11; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68682.4] assign _T_236 = _T_235 | dmiProgramBufferAccessVec_11; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68812.4] assign _T_237 = _T_236 | dmiProgramBufferAccessVec_12; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68813.4] assign dmiProgramBufferWrEnMaybe_13 = _T_3000 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70632.4] assign dmiProgramBufferRdEn_13 = _T_2834 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70630.4] assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68684.4] assign _T_238 = _T_237 | dmiProgramBufferAccessVec_13; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68814.4] assign dmiProgramBufferWrEnMaybe_14 = _T_3000 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70662.4] assign dmiProgramBufferRdEn_14 = _T_2834 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70660.4] assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68685.4] assign _T_239 = _T_238 | dmiProgramBufferAccessVec_14; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68815.4] assign dmiProgramBufferWrEnMaybe_15 = _T_3000 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70692.4] assign dmiProgramBufferRdEn_15 = _T_2834 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70690.4] assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68686.4] assign _T_240 = _T_239 | dmiProgramBufferAccessVec_15; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68816.4] assign _T_241 = _T_240 | dmiProgramBufferAccessVec_16; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68817.4] assign dmiProgramBufferWrEnMaybe_17 = _T_3005 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71037.4] assign dmiProgramBufferRdEn_17 = _T_2839 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71035.4] assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 | dmiProgramBufferRdEn_17; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68688.4] assign _T_242 = _T_241 | dmiProgramBufferAccessVec_17; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68818.4] assign dmiProgramBufferWrEnMaybe_18 = _T_3005 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71067.4] assign dmiProgramBufferRdEn_18 = _T_2839 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71065.4] assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 | dmiProgramBufferRdEn_18; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68689.4] assign _T_243 = _T_242 | dmiProgramBufferAccessVec_18; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68819.4] assign dmiProgramBufferWrEnMaybe_19 = _T_3005 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71097.4] assign dmiProgramBufferRdEn_19 = _T_2839 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71095.4] assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 | dmiProgramBufferRdEn_19; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68690.4] assign _T_244 = _T_243 | dmiProgramBufferAccessVec_19; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68820.4] assign _T_245 = _T_244 | dmiProgramBufferAccessVec_20; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68821.4] assign dmiProgramBufferWrEnMaybe_21 = _T_3010 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69378.4] assign dmiProgramBufferRdEn_21 = _T_2844 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69376.4] assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68692.4] assign _T_246 = _T_245 | dmiProgramBufferAccessVec_21; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68822.4] assign dmiProgramBufferWrEnMaybe_22 = _T_3010 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69408.4] assign dmiProgramBufferRdEn_22 = _T_2844 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69406.4] assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68693.4] assign _T_247 = _T_246 | dmiProgramBufferAccessVec_22; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68823.4] assign dmiProgramBufferWrEnMaybe_23 = _T_3010 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69438.4] assign dmiProgramBufferRdEn_23 = _T_2844 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69436.4] assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68694.4] assign _T_248 = _T_247 | dmiProgramBufferAccessVec_23; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68824.4] assign _T_249 = _T_248 | dmiProgramBufferAccessVec_24; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68825.4] assign dmiProgramBufferWrEnMaybe_25 = _T_3015 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69614.4] assign dmiProgramBufferRdEn_25 = _T_2849 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69612.4] assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 | dmiProgramBufferRdEn_25; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68696.4] assign _T_250 = _T_249 | dmiProgramBufferAccessVec_25; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68826.4] assign dmiProgramBufferWrEnMaybe_26 = _T_3015 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69644.4] assign dmiProgramBufferRdEn_26 = _T_2849 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69642.4] assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 | dmiProgramBufferRdEn_26; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68697.4] assign _T_251 = _T_250 | dmiProgramBufferAccessVec_26; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68827.4] assign dmiProgramBufferWrEnMaybe_27 = _T_3015 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69674.4] assign dmiProgramBufferRdEn_27 = _T_2849 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69672.4] assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 | dmiProgramBufferRdEn_27; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68698.4] assign _T_252 = _T_251 | dmiProgramBufferAccessVec_27; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68828.4] assign _T_253 = _T_252 | dmiProgramBufferAccessVec_28; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68829.4] assign dmiProgramBufferWrEnMaybe_29 = _T_3020 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70514.4] assign dmiProgramBufferRdEn_29 = _T_2854 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70512.4] assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68700.4] assign _T_254 = _T_253 | dmiProgramBufferAccessVec_29; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68830.4] assign dmiProgramBufferWrEnMaybe_30 = _T_3020 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70544.4] assign dmiProgramBufferRdEn_30 = _T_2854 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70542.4] assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68701.4] assign _T_255 = _T_254 | dmiProgramBufferAccessVec_30; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68831.4] assign dmiProgramBufferWrEnMaybe_31 = _T_3020 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70574.4] assign dmiProgramBufferRdEn_31 = _T_2854 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70572.4] assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68702.4] assign _T_256 = _T_255 | dmiProgramBufferAccessVec_31; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68832.4] assign _T_257 = _T_256 | dmiProgramBufferAccessVec_32; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68833.4] assign dmiProgramBufferWrEnMaybe_33 = _T_3025 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70891.4] assign dmiProgramBufferRdEn_33 = _T_2859 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70889.4] assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 | dmiProgramBufferRdEn_33; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68704.4] assign _T_258 = _T_257 | dmiProgramBufferAccessVec_33; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68834.4] assign dmiProgramBufferWrEnMaybe_34 = _T_3025 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70921.4] assign dmiProgramBufferRdEn_34 = _T_2859 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70919.4] assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 | dmiProgramBufferRdEn_34; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68705.4] assign _T_259 = _T_258 | dmiProgramBufferAccessVec_34; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68835.4] assign dmiProgramBufferWrEnMaybe_35 = _T_3025 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70951.4] assign dmiProgramBufferRdEn_35 = _T_2859 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70949.4] assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 | dmiProgramBufferRdEn_35; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68706.4] assign _T_260 = _T_259 | dmiProgramBufferAccessVec_35; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68836.4] assign _T_261 = _T_260 | dmiProgramBufferAccessVec_36; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68837.4] assign dmiProgramBufferWrEnMaybe_37 = _T_3030 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69850.4] assign dmiProgramBufferRdEn_37 = _T_2864 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69848.4] assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68708.4] assign _T_262 = _T_261 | dmiProgramBufferAccessVec_37; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68838.4] assign dmiProgramBufferWrEnMaybe_38 = _T_3030 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69880.4] assign dmiProgramBufferRdEn_38 = _T_2864 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69878.4] assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68709.4] assign _T_263 = _T_262 | dmiProgramBufferAccessVec_38; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68839.4] assign dmiProgramBufferWrEnMaybe_39 = _T_3030 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69910.4] assign dmiProgramBufferRdEn_39 = _T_2864 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69908.4] assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68710.4] assign _T_264 = _T_263 | dmiProgramBufferAccessVec_39; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68840.4] assign _T_265 = _T_264 | dmiProgramBufferAccessVec_40; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68841.4] assign dmiProgramBufferWrEnMaybe_41 = _T_3035 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69232.4] assign dmiProgramBufferRdEn_41 = _T_2869 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69230.4] assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 | dmiProgramBufferRdEn_41; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68712.4] assign _T_266 = _T_265 | dmiProgramBufferAccessVec_41; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68842.4] assign dmiProgramBufferWrEnMaybe_42 = _T_3035 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69262.4] assign dmiProgramBufferRdEn_42 = _T_2869 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69260.4] assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 | dmiProgramBufferRdEn_42; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68713.4] assign _T_267 = _T_266 | dmiProgramBufferAccessVec_42; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68843.4] assign dmiProgramBufferWrEnMaybe_43 = _T_3035 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69292.4] assign dmiProgramBufferRdEn_43 = _T_2869 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69290.4] assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 | dmiProgramBufferRdEn_43; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68714.4] assign _T_268 = _T_267 | dmiProgramBufferAccessVec_43; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68844.4] assign _T_269 = _T_268 | dmiProgramBufferAccessVec_44; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68845.4] assign dmiProgramBufferWrEnMaybe_45 = _T_3040 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70773.4] assign dmiProgramBufferRdEn_45 = _T_2874 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70771.4] assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68716.4] assign _T_270 = _T_269 | dmiProgramBufferAccessVec_45; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68846.4] assign dmiProgramBufferWrEnMaybe_46 = _T_3040 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70803.4] assign dmiProgramBufferRdEn_46 = _T_2874 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70801.4] assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68717.4] assign _T_271 = _T_270 | dmiProgramBufferAccessVec_46; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68847.4] assign dmiProgramBufferWrEnMaybe_47 = _T_3040 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70833.4] assign dmiProgramBufferRdEn_47 = _T_2874 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70831.4] assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68718.4] assign _T_272 = _T_271 | dmiProgramBufferAccessVec_47; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68848.4] assign _T_273 = _T_272 | dmiProgramBufferAccessVec_48; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68849.4] assign dmiProgramBufferWrEnMaybe_49 = _T_3045 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70396.4] assign dmiProgramBufferRdEn_49 = _T_2879 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70394.4] assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 | dmiProgramBufferRdEn_49; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68720.4] assign _T_274 = _T_273 | dmiProgramBufferAccessVec_49; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68850.4] assign dmiProgramBufferWrEnMaybe_50 = _T_3045 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70426.4] assign dmiProgramBufferRdEn_50 = _T_2879 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70424.4] assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 | dmiProgramBufferRdEn_50; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68721.4] assign _T_275 = _T_274 | dmiProgramBufferAccessVec_50; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68851.4] assign dmiProgramBufferWrEnMaybe_51 = _T_3045 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70456.4] assign dmiProgramBufferRdEn_51 = _T_2879 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70454.4] assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 | dmiProgramBufferRdEn_51; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68722.4] assign _T_276 = _T_275 | dmiProgramBufferAccessVec_51; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68852.4] assign _T_277 = _T_276 | dmiProgramBufferAccessVec_52; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68853.4] assign dmiProgramBufferWrEnMaybe_53 = _T_3050 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70204.4] assign dmiProgramBufferRdEn_53 = _T_2884 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70202.4] assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68724.4] assign _T_278 = _T_277 | dmiProgramBufferAccessVec_53; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68854.4] assign dmiProgramBufferWrEnMaybe_54 = _T_3050 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70234.4] assign dmiProgramBufferRdEn_54 = _T_2884 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70232.4] assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68725.4] assign _T_279 = _T_278 | dmiProgramBufferAccessVec_54; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68855.4] assign dmiProgramBufferWrEnMaybe_55 = _T_3050 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70264.4] assign dmiProgramBufferRdEn_55 = _T_2884 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@70262.4] assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68726.4] assign _T_280 = _T_279 | dmiProgramBufferAccessVec_55; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68856.4] assign _T_281 = _T_280 | dmiProgramBufferAccessVec_56; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68857.4] assign dmiProgramBufferWrEnMaybe_57 = _T_3055 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69496.4] assign dmiProgramBufferRdEn_57 = _T_2889 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69494.4] assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 | dmiProgramBufferRdEn_57; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68728.4] assign _T_282 = _T_281 | dmiProgramBufferAccessVec_57; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68858.4] assign dmiProgramBufferWrEnMaybe_58 = _T_3055 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69526.4] assign dmiProgramBufferRdEn_58 = _T_2889 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69524.4] assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 | dmiProgramBufferRdEn_58; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68729.4] assign _T_283 = _T_282 | dmiProgramBufferAccessVec_58; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68859.4] assign dmiProgramBufferWrEnMaybe_59 = _T_3055 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69556.4] assign dmiProgramBufferRdEn_59 = _T_2889 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69554.4] assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 | dmiProgramBufferRdEn_59; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68730.4] assign _T_284 = _T_283 | dmiProgramBufferAccessVec_59; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68860.4] assign _T_285 = _T_284 | dmiProgramBufferAccessVec_60; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68861.4] assign dmiProgramBufferWrEnMaybe_61 = _T_3060 & _T_2150; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71296.4] assign dmiProgramBufferRdEn_61 = _T_2894 & _T_2148; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71294.4] assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68732.4] assign _T_286 = _T_285 | dmiProgramBufferAccessVec_61; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68862.4] assign dmiProgramBufferWrEnMaybe_62 = _T_3060 & _T_2175; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71326.4] assign dmiProgramBufferRdEn_62 = _T_2894 & _T_2173; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71324.4] assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68733.4] assign _T_287 = _T_286 | dmiProgramBufferAccessVec_62; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68863.4] assign dmiProgramBufferWrEnMaybe_63 = _T_3060 & _T_2200; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71356.4] assign dmiProgramBufferRdEn_63 = _T_2894 & _T_2198; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@71354.4] assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63; // @[Debug.scala 933:108:freechips.rocketchip.system.TinyConfig.fir@68734.4] assign dmiProgramBufferAccess = _T_287 | dmiProgramBufferAccessVec_63; // @[Debug.scala 936:69:freechips.rocketchip.system.TinyConfig.fir@68864.4] assign _T_18828 = dmiProgramBufferAccess & _T_18816; // @[Debug.scala 1287:42:freechips.rocketchip.system.TinyConfig.fir@96540.4] assign errorBusy = _T_18826 | _T_18828; // @[Debug.scala 1286:74:freechips.rocketchip.system.TinyConfig.fir@96541.4] assign ABSTRACTAUTOWrDataVal = ABSTRACTAUTOWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 245:24:freechips.rocketchip.system.TinyConfig.fir@69326.4] assign ABSTRACTAUTOWrData_autoexecdata = ABSTRACTAUTOWrDataVal[11:0]; // @[Debug.scala 913:68:freechips.rocketchip.system.TinyConfig.fir@68555.4] assign ABSTRACTAUTOWrData_autoexecprogbuf = ABSTRACTAUTOWrDataVal[31:16]; // @[Debug.scala 913:68:freechips.rocketchip.system.TinyConfig.fir@68559.4] assign ABSTRACTAUTOWrEn = ABSTRACTAUTOWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala 920:55:freechips.rocketchip.system.TinyConfig.fir@68573.4] assign _T_153 = ABSTRACTAUTOWrData_autoexecdata & 12'h1; // @[Debug.scala 926:71:freechips.rocketchip.system.TinyConfig.fir@68582.8] assign COMMANDWrData_control = COMMANDWrDataVal[23:0]; // @[Debug.scala 952:73:freechips.rocketchip.system.TinyConfig.fir@68991.4] assign hartHaltedId = auto_tl_in_a_bits_data[9:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75750.4] assign _T_360 = hartHaltedId == 10'h0; // @[Debug.scala 991:60:freechips.rocketchip.system.TinyConfig.fir@69032.8] assign _T_7993 = _T_7926[66]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78434.4] assign _T_16469 = _T_16137 & _T_7993; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92141.4] assign _T_16470 = _T_16469 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92142.4] assign hartResumingWrEn = _T_16470 & _T_6456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76202.4] assign _T_7991 = _T_7926[64]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78432.4] assign _T_16459 = _T_16137 & _T_7991; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92125.4] assign _T_16460 = _T_16459 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92126.4] assign hartHaltedWrEn = _T_16460 & _T_6456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75749.4] assign _T_363 = resumereq & hamaskWrSel_0; // @[Debug.scala 1009:25:freechips.rocketchip.system.TinyConfig.fir@69050.6] assign _T_372 = {1'h0,DMSTATUSRdData_anyrunning,DMSTATUSRdData_anyrunning,haltedBitRegs_0,haltedBitRegs_0,8'h82}; // @[Debug.scala 1024:73:freechips.rocketchip.system.TinyConfig.fir@69063.4] assign _T_382 = {12'h0,haveResetBitRegs_0,haveResetBitRegs_0,DMSTATUSRdData_anyresumeack,DMSTATUSRdData_anyresumeack,1'h0,2'h0,_T_372}; // @[Debug.scala 1024:73:freechips.rocketchip.system.TinyConfig.fir@69073.4] assign abstractCommandBusy = ctrlStateReg != 2'h0; // @[Debug.scala 1275:42:freechips.rocketchip.system.TinyConfig.fir@96516.4] assign _T_394 = {8'h10,11'h0,abstractCommandBusy,1'h0,ABSTRACTCSReg_cmderr,8'h1}; // @[Debug.scala 1031:73:freechips.rocketchip.system.TinyConfig.fir@69085.4] assign _T_396 = {ABSTRACTAUTOReg_autoexecprogbuf,4'h0,ABSTRACTAUTOReg_autoexecdata}; // @[Debug.scala 1033:75:freechips.rocketchip.system.TinyConfig.fir@69087.4] assign _T_401 = {auto_dmi_in_a_bits_source,auto_dmi_in_a_bits_size}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69097.4] assign _T_501 = auto_dmi_in_a_bits_data[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69206.4] assign _T_524 = auto_dmi_in_a_bits_data[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69234.4] assign _T_549 = auto_dmi_in_a_bits_data[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69264.4] assign _T_574 = auto_dmi_in_a_bits_data[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@69294.4] assign _T_584 = {programBufferMem_43,programBufferMem_42,programBufferMem_41,programBufferMem_40}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69308.4] assign _T_705 = {programBufferMem_23,programBufferMem_22,programBufferMem_21,programBufferMem_20}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69454.4] assign _T_803 = {programBufferMem_59,programBufferMem_58,programBufferMem_57,programBufferMem_56}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69572.4] assign _T_901 = {programBufferMem_27,programBufferMem_26,programBufferMem_25,programBufferMem_24}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69690.4] assign _T_999 = {programBufferMem_7,programBufferMem_6,programBufferMem_5,programBufferMem_4}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69808.4] assign _T_1097 = {programBufferMem_39,programBufferMem_38,programBufferMem_37,programBufferMem_36}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@69926.4] assign _T_1195 = {programBufferMem_3,programBufferMem_2,programBufferMem_1,programBufferMem_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70044.4] assign _T_1293 = {programBufferMem_11,programBufferMem_10,programBufferMem_9,programBufferMem_8}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70162.4] assign _T_1391 = {programBufferMem_55,programBufferMem_54,programBufferMem_53,programBufferMem_52}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70280.4] assign _T_1558 = {programBufferMem_51,programBufferMem_50,programBufferMem_49,programBufferMem_48}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70472.4] assign _T_1656 = {programBufferMem_31,programBufferMem_30,programBufferMem_29,programBufferMem_28}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70590.4] assign _T_1754 = {programBufferMem_15,programBufferMem_14,programBufferMem_13,programBufferMem_12}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70708.4] assign _T_1875 = {programBufferMem_47,programBufferMem_46,programBufferMem_45,programBufferMem_44}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70849.4] assign _T_1973 = {programBufferMem_35,programBufferMem_34,programBufferMem_33,programBufferMem_32}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@70967.4] assign _T_2094 = {programBufferMem_19,programBufferMem_18,programBufferMem_17,programBufferMem_16}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71113.4] assign _T_2215 = {abstractDataMem_3,abstractDataMem_2,abstractDataMem_1,abstractDataMem_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71254.4] assign _T_2313 = {programBufferMem_63,programBufferMem_62,programBufferMem_61,programBufferMem_60}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@71372.4] assign _GEN_248 = 5'h1 == _T_2326 ? _T_409 : _T_427; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_249 = 5'h2 == _T_2326 ? _T_409 : _GEN_248; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_250 = 5'h3 == _T_2326 ? _T_409 : _GEN_249; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_251 = 5'h4 == _T_2326 ? _T_453 : _GEN_250; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_252 = 5'h5 == _T_2326 ? 1'h1 : _GEN_251; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_253 = 5'h6 == _T_2326 ? _T_409 : _GEN_252; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_254 = 5'h7 == _T_2326 ? _T_409 : _GEN_253; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_255 = 5'h8 == _T_2326 ? _T_409 : _GEN_254; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_256 = 5'h9 == _T_2326 ? 1'h1 : _GEN_255; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_257 = 5'ha == _T_2326 ? 1'h1 : _GEN_256; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_258 = 5'hb == _T_2326 ? 1'h1 : _GEN_257; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_259 = 5'hc == _T_2326 ? 1'h1 : _GEN_258; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_260 = 5'hd == _T_2326 ? 1'h1 : _GEN_259; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_261 = 5'he == _T_2326 ? 1'h1 : _GEN_260; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_262 = 5'hf == _T_2326 ? 1'h1 : _GEN_261; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_263 = 5'h10 == _T_2326 ? _T_453 : _GEN_262; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_264 = 5'h11 == _T_2326 ? _T_453 : _GEN_263; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_265 = 5'h12 == _T_2326 ? _T_453 : _GEN_264; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_266 = 5'h13 == _T_2326 ? _T_453 : _GEN_265; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_267 = 5'h14 == _T_2326 ? _T_453 : _GEN_266; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_268 = 5'h15 == _T_2326 ? _T_453 : _GEN_267; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_269 = 5'h16 == _T_2326 ? _T_453 : _GEN_268; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_270 = 5'h17 == _T_2326 ? _T_453 : _GEN_269; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_271 = 5'h18 == _T_2326 ? _T_453 : _GEN_270; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_272 = 5'h19 == _T_2326 ? _T_453 : _GEN_271; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_273 = 5'h1a == _T_2326 ? _T_453 : _GEN_272; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_274 = 5'h1b == _T_2326 ? _T_453 : _GEN_273; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_275 = 5'h1c == _T_2326 ? _T_453 : _GEN_274; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_276 = 5'h1d == _T_2326 ? _T_453 : _GEN_275; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_277 = 5'h1e == _T_2326 ? _T_453 : _GEN_276; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_278 = 5'h1f == _T_2326 ? _T_453 : _GEN_277; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72859.4] assign _GEN_280 = 5'h1 == _T_2326 ? _T_382 : haltedStatus_0; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_281 = 5'h2 == _T_2326 ? 32'h111380 : _GEN_280; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_282 = 5'h3 == _T_2326 ? HALTSUM1RdData_haltsum1 : _GEN_281; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_283 = 5'h4 == _T_2326 ? _T_2215 : _GEN_282; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_284 = 5'h5 == _T_2326 ? 32'h0 : _GEN_283; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_285 = 5'h6 == _T_2326 ? _T_394 : _GEN_284; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_286 = 5'h7 == _T_2326 ? _T_3245 : _GEN_285; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_287 = 5'h8 == _T_2326 ? _T_396 : _GEN_286; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_288 = 5'h9 == _T_2326 ? 32'h0 : _GEN_287; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_289 = 5'ha == _T_2326 ? 32'h0 : _GEN_288; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_290 = 5'hb == _T_2326 ? 32'h0 : _GEN_289; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_291 = 5'hc == _T_2326 ? 32'h0 : _GEN_290; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_292 = 5'hd == _T_2326 ? 32'h0 : _GEN_291; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_293 = 5'he == _T_2326 ? 32'h0 : _GEN_292; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_294 = 5'hf == _T_2326 ? 32'h0 : _GEN_293; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_295 = 5'h10 == _T_2326 ? _T_1195 : _GEN_294; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_296 = 5'h11 == _T_2326 ? _T_999 : _GEN_295; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_297 = 5'h12 == _T_2326 ? _T_1293 : _GEN_296; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_298 = 5'h13 == _T_2326 ? _T_1754 : _GEN_297; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_299 = 5'h14 == _T_2326 ? _T_2094 : _GEN_298; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_300 = 5'h15 == _T_2326 ? _T_705 : _GEN_299; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_301 = 5'h16 == _T_2326 ? _T_901 : _GEN_300; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_302 = 5'h17 == _T_2326 ? _T_1656 : _GEN_301; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_303 = 5'h18 == _T_2326 ? _T_1973 : _GEN_302; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_304 = 5'h19 == _T_2326 ? _T_1097 : _GEN_303; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_305 = 5'h1a == _T_2326 ? _T_584 : _GEN_304; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_306 = 5'h1b == _T_2326 ? _T_1875 : _GEN_305; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_307 = 5'h1c == _T_2326 ? _T_1558 : _GEN_306; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_308 = 5'h1d == _T_2326 ? _T_1391 : _GEN_307; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_309 = 5'h1e == _T_2326 ? _T_803 : _GEN_308; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _GEN_310 = 5'h1f == _T_2326 ? _T_2313 : _GEN_309; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.TinyConfig.fir@72895.4] assign _T_3086 = dmiAbstractDataWrEnMaybe_0 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72928.4] assign _T_3087 = dmiAbstractDataWrEnMaybe_1 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72932.4] assign _T_3088 = dmiAbstractDataWrEnMaybe_2 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72936.4] assign _T_3089 = dmiAbstractDataWrEnMaybe_3 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1058:41:freechips.rocketchip.system.TinyConfig.fir@72940.4] assign _T_3090 = dmiProgramBufferWrEnMaybe_0 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72944.4] assign _T_3091 = dmiProgramBufferWrEnMaybe_1 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72948.4] assign _T_3092 = dmiProgramBufferWrEnMaybe_2 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72952.4] assign _T_3093 = dmiProgramBufferWrEnMaybe_3 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72956.4] assign _T_3094 = dmiProgramBufferWrEnMaybe_4 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72960.4] assign _T_3095 = dmiProgramBufferWrEnMaybe_5 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72964.4] assign _T_3096 = dmiProgramBufferWrEnMaybe_6 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72968.4] assign _T_3097 = dmiProgramBufferWrEnMaybe_7 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72972.4] assign _T_3098 = dmiProgramBufferWrEnMaybe_8 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72976.4] assign _T_3099 = dmiProgramBufferWrEnMaybe_9 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72980.4] assign _T_3100 = dmiProgramBufferWrEnMaybe_10 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72984.4] assign _T_3101 = dmiProgramBufferWrEnMaybe_11 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72988.4] assign _T_3102 = dmiProgramBufferWrEnMaybe_12 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72992.4] assign _T_3103 = dmiProgramBufferWrEnMaybe_13 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@72996.4] assign _T_3104 = dmiProgramBufferWrEnMaybe_14 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73000.4] assign _T_3105 = dmiProgramBufferWrEnMaybe_15 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73004.4] assign _T_3106 = dmiProgramBufferWrEnMaybe_16 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73008.4] assign _T_3107 = dmiProgramBufferWrEnMaybe_17 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73012.4] assign _T_3108 = dmiProgramBufferWrEnMaybe_18 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73016.4] assign _T_3109 = dmiProgramBufferWrEnMaybe_19 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73020.4] assign _T_3110 = dmiProgramBufferWrEnMaybe_20 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73024.4] assign _T_3111 = dmiProgramBufferWrEnMaybe_21 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73028.4] assign _T_3112 = dmiProgramBufferWrEnMaybe_22 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73032.4] assign _T_3113 = dmiProgramBufferWrEnMaybe_23 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73036.4] assign _T_3114 = dmiProgramBufferWrEnMaybe_24 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73040.4] assign _T_3115 = dmiProgramBufferWrEnMaybe_25 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73044.4] assign _T_3116 = dmiProgramBufferWrEnMaybe_26 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73048.4] assign _T_3117 = dmiProgramBufferWrEnMaybe_27 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73052.4] assign _T_3118 = dmiProgramBufferWrEnMaybe_28 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73056.4] assign _T_3119 = dmiProgramBufferWrEnMaybe_29 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73060.4] assign _T_3120 = dmiProgramBufferWrEnMaybe_30 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73064.4] assign _T_3121 = dmiProgramBufferWrEnMaybe_31 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73068.4] assign _T_3122 = dmiProgramBufferWrEnMaybe_32 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73072.4] assign _T_3123 = dmiProgramBufferWrEnMaybe_33 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73076.4] assign _T_3124 = dmiProgramBufferWrEnMaybe_34 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73080.4] assign _T_3125 = dmiProgramBufferWrEnMaybe_35 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73084.4] assign _T_3126 = dmiProgramBufferWrEnMaybe_36 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73088.4] assign _T_3127 = dmiProgramBufferWrEnMaybe_37 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73092.4] assign _T_3128 = dmiProgramBufferWrEnMaybe_38 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73096.4] assign _T_3129 = dmiProgramBufferWrEnMaybe_39 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73100.4] assign _T_3130 = dmiProgramBufferWrEnMaybe_40 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73104.4] assign _T_3131 = dmiProgramBufferWrEnMaybe_41 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73108.4] assign _T_3132 = dmiProgramBufferWrEnMaybe_42 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73112.4] assign _T_3133 = dmiProgramBufferWrEnMaybe_43 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73116.4] assign _T_3134 = dmiProgramBufferWrEnMaybe_44 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73120.4] assign _T_3135 = dmiProgramBufferWrEnMaybe_45 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73124.4] assign _T_3136 = dmiProgramBufferWrEnMaybe_46 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73128.4] assign _T_3137 = dmiProgramBufferWrEnMaybe_47 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73132.4] assign _T_3138 = dmiProgramBufferWrEnMaybe_48 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73136.4] assign _T_3139 = dmiProgramBufferWrEnMaybe_49 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73140.4] assign _T_3140 = dmiProgramBufferWrEnMaybe_50 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73144.4] assign _T_3141 = dmiProgramBufferWrEnMaybe_51 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73148.4] assign _T_3142 = dmiProgramBufferWrEnMaybe_52 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73152.4] assign _T_3143 = dmiProgramBufferWrEnMaybe_53 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73156.4] assign _T_3144 = dmiProgramBufferWrEnMaybe_54 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73160.4] assign _T_3145 = dmiProgramBufferWrEnMaybe_55 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73164.4] assign _T_3146 = dmiProgramBufferWrEnMaybe_56 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73168.4] assign _T_3147 = dmiProgramBufferWrEnMaybe_57 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73172.4] assign _T_3148 = dmiProgramBufferWrEnMaybe_58 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73176.4] assign _T_3149 = dmiProgramBufferWrEnMaybe_59 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73180.4] assign _T_3150 = dmiProgramBufferWrEnMaybe_60 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73184.4] assign _T_3151 = dmiProgramBufferWrEnMaybe_61 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73188.4] assign _T_3152 = dmiProgramBufferWrEnMaybe_62 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73192.4] assign _T_3153 = dmiProgramBufferWrEnMaybe_63 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1080:42:freechips.rocketchip.system.TinyConfig.fir@73196.4] assign _T_3214 = _T_360 | reset; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73318.10] assign _T_3215 = _T_3214 == 1'h0; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73319.10] assign _T_7992 = _T_7926[65]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78433.4] assign _T_16464 = _T_16137 & _T_7992; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92133.4] assign _T_16465 = _T_16464 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@92134.4] assign hartGoingWrEn = _T_16465 & _T_6456; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74868.4] assign _GEN_2678 = commandRegBadHaltResume ? 1'h0 : 1'h1; // @[Debug.scala 1340:43:freechips.rocketchip.system.TinyConfig.fir@96602.10] assign _GEN_2682 = commandRegIsUnsupported ? 1'h0 : _GEN_2678; // @[Debug.scala 1337:38:freechips.rocketchip.system.TinyConfig.fir@96597.8] assign _GEN_2695 = _T_18846 ? _GEN_2682 : 1'h0; // @[Debug.scala 1330:59:freechips.rocketchip.system.TinyConfig.fir@96596.6] assign goAbstract = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2695; // @[Debug.scala 1322:47:freechips.rocketchip.system.TinyConfig.fir@96579.4] assign accessRegisterCommandReg_postexec = _T_3245[18]; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73408.4] assign accessRegisterCommandReg_size = _T_3245[22:20]; // @[Debug.scala 1127:86:freechips.rocketchip.system.TinyConfig.fir@73412.4] assign _T_3263 = accessRegisterCommandReg_regno & 16'h1f; // @[Debug.scala 1176:66:freechips.rocketchip.system.TinyConfig.fir@73444.4] assign abstractGeneratedI_rd = _T_3263[4:0]; // @[Debug.scala 1171:34:freechips.rocketchip.system.TinyConfig.fir@73422.4 Debug.scala 1176:31:freechips.rocketchip.system.TinyConfig.fir@73445.4] assign _T_3283 = {17'h7000,accessRegisterCommandReg_size,abstractGeneratedI_rd,7'h3}; // @[Debug.scala 1197:36:freechips.rocketchip.system.TinyConfig.fir@73496.6] assign _T_3288 = {7'h1c,abstractGeneratedI_rd,5'h0,accessRegisterCommandReg_size,5'h0,7'h23}; // @[Debug.scala 1199:36:freechips.rocketchip.system.TinyConfig.fir@73501.6] assign _T_3312 = {auto_tl_in_a_bits_source,auto_tl_in_a_bits_size}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@73533.4] assign _T_3444 = _T_3443[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73673.4] assign _T_3447 = _T_3444 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73676.4] assign _T_3456 = auto_tl_in_a_bits_data[7:0]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73685.4] assign _T_3467 = _T_3443[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73696.4] assign _T_3470 = _T_3467 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73699.4] assign _T_3479 = auto_tl_in_a_bits_data[15:8]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73708.4] assign _T_3492 = _T_3443[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73721.4] assign _T_3495 = _T_3492 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73724.4] assign _T_3504 = auto_tl_in_a_bits_data[23:16]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73733.4] assign _T_3517 = _T_3443[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73746.4] assign _T_3520 = _T_3517 == 8'hff; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73749.4] assign _T_3529 = auto_tl_in_a_bits_data[31:24]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73758.4] assign _T_7631 = _T_7926[217]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78072.4] assign _T_12093 = _T_16137 & _T_7631; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84712.4] assign _T_12094 = _T_12093 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84713.4] assign _T_3650 = _T_12094 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73879.4] assign _T_3673 = _T_12094 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73905.4] assign _T_3698 = _T_12094 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73933.4] assign _T_3723 = _T_12094 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73961.4] assign _T_7630 = _T_7926[216]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78071.4] assign _T_12088 = _T_16137 & _T_7630; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84701.4] assign _T_12089 = _T_12088 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84702.4] assign _T_3748 = _T_12089 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@73989.4] assign _T_3771 = _T_12089 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74015.4] assign _T_3796 = _T_12089 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74043.4] assign _T_3821 = _T_12089 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74071.4] assign _T_7625 = _T_7926[211]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78066.4] assign _T_12063 = _T_16137 & _T_7625; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84646.4] assign _T_12064 = _T_12063 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84647.4] assign _T_3846 = _T_12064 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74099.4] assign _T_3869 = _T_12064 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74125.4] assign _T_3894 = _T_12064 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74153.4] assign _T_3919 = _T_12064 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74181.4] assign _T_7635 = _T_7926[221]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78076.4] assign _T_12113 = _T_16137 & _T_7635; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84756.4] assign _T_12114 = _T_12113 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84757.4] assign _T_4042 = _T_12114 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74307.4] assign _T_4065 = _T_12114 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74333.4] assign _T_4090 = _T_12114 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74361.4] assign _T_4115 = _T_12114 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74389.4] assign _T_7634 = _T_7926[220]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78075.4] assign _T_12108 = _T_16137 & _T_7634; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84745.4] assign _T_12109 = _T_12108 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84746.4] assign _T_4457 = _T_12109 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74734.4] assign _T_4480 = _T_12109 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74760.4] assign _T_4505 = _T_12109 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74788.4] assign _T_4530 = _T_12109 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74816.4] assign _T_7638 = _T_7926[224]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78079.4] assign _T_12128 = _T_16137 & _T_7638; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84789.4] assign _T_12129 = _T_12128 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84790.4] assign _T_4699 = _T_12129 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@74990.4] assign _T_4722 = _T_12129 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75016.4] assign _T_4747 = _T_12129 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75044.4] assign _T_4772 = _T_12129 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75072.4] assign _T_4930 = {8'h0,6'h0,resumeReqRegs_0,goReg}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@75233.4] assign _T_7626 = _T_7926[212]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78067.4] assign _T_12068 = _T_16137 & _T_7626; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84657.4] assign _T_12069 = _T_12068 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84658.4] assign _T_5041 = _T_12069 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75344.4] assign _T_5064 = _T_12069 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75370.4] assign _T_5089 = _T_12069 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75398.4] assign _T_5114 = _T_12069 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75426.4] assign _T_7633 = _T_7926[219]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78074.4] assign _T_12103 = _T_16137 & _T_7633; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84734.4] assign _T_12104 = _T_12103 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84735.4] assign _T_5456 = _T_12104 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75773.4] assign _T_5479 = _T_12104 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75799.4] assign _T_5504 = _T_12104 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75827.4] assign _T_5529 = _T_12104 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75855.4] assign _T_7622 = _T_7926[208]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78063.4] assign _T_12048 = _T_16137 & _T_7622; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84613.4] assign _T_12049 = _T_12048 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84614.4] assign _T_5554 = _T_12049 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75883.4] assign _T_5577 = _T_12049 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75909.4] assign _T_5602 = _T_12049 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75937.4] assign _T_5627 = _T_12049 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75965.4] assign _T_7627 = _T_7926[213]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78068.4] assign _T_12073 = _T_16137 & _T_7627; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84668.4] assign _T_12074 = _T_12073 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84669.4] assign _T_5652 = _T_12074 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@75993.4] assign _T_5675 = _T_12074 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76019.4] assign _T_5700 = _T_12074 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76047.4] assign _T_5725 = _T_12074 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76075.4] assign _T_7637 = _T_7926[223]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78078.4] assign _T_12123 = _T_16137 & _T_7637; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84778.4] assign _T_12124 = _T_12123 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84779.4] assign _T_5969 = _T_12124 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76324.4] assign _T_5992 = _T_12124 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76350.4] assign _T_6017 = _T_12124 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76378.4] assign _T_6042 = _T_12124 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76406.4] assign _T_7623 = _T_7926[209]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78064.4] assign _T_12053 = _T_16137 & _T_7623; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84624.4] assign _T_12054 = _T_12053 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84625.4] assign _T_6165 = _T_12054 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76532.4] assign _T_6188 = _T_12054 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76558.4] assign _T_6213 = _T_12054 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76586.4] assign _T_6238 = _T_12054 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76614.4] assign _T_7632 = _T_7926[218]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78073.4] assign _T_12098 = _T_16137 & _T_7632; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84723.4] assign _T_12099 = _T_12098 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84724.4] assign _T_6580 = _T_12099 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76961.4] assign _T_6603 = _T_12099 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@76987.4] assign _T_6628 = _T_12099 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77015.4] assign _T_6653 = _T_12099 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77043.4] assign _T_7628 = _T_7926[214]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78069.4] assign _T_12078 = _T_16137 & _T_7628; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84679.4] assign _T_12079 = _T_12078 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84680.4] assign _T_6799 = _T_12079 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77192.4] assign _T_6822 = _T_12079 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77218.4] assign _T_6847 = _T_12079 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77246.4] assign _T_6872 = _T_12079 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77274.4] assign _T_7624 = _T_7926[210]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78065.4] assign _T_12058 = _T_16137 & _T_7624; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84635.4] assign _T_12059 = _T_12058 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84636.4] assign _T_6897 = _T_12059 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77302.4] assign _T_6920 = _T_12059 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77328.4] assign _T_6945 = _T_12059 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77356.4] assign _T_6970 = _T_12059 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77384.4] assign _T_7629 = _T_7926[215]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78070.4] assign _T_12083 = _T_16137 & _T_7629; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84690.4] assign _T_12084 = _T_12083 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84691.4] assign _T_7191 = _T_12084 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77608.4] assign _T_7214 = _T_12084 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77634.4] assign _T_7239 = _T_12084 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77662.4] assign _T_7264 = _T_12084 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77690.4] assign _T_7636 = _T_7926[222]; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@78077.4] assign _T_12118 = _T_16137 & _T_7636; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84767.4] assign _T_12119 = _T_12118 & _T_3402; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@84768.4] assign _T_7289 = _T_12119 & _T_3447; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77718.4] assign _T_7312 = _T_12119 & _T_3470; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77744.4] assign _T_7337 = _T_12119 & _T_3495; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77772.4] assign _T_7362 = _T_12119 & _T_3520; // @[RegisterRouter.scala 66:24:freechips.rocketchip.system.TinyConfig.fir@77800.4] assign _T_18708 = 9'h0 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95948.4] assign _T_18709 = 9'h40 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95953.6] assign _T_18710 = 9'h41 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95958.8] assign _T_18711 = 9'h42 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95963.10] assign _T_18712 = 9'h43 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95968.12] assign _T_18713 = 9'hc0 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95973.14] assign _T_18714 = 9'hce == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95978.16] assign _T_18715 = 9'hcf == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95983.18] assign _T_18716 = 9'hd0 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95988.20] assign _T_18717 = 9'hd1 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95993.22] assign _T_18718 = 9'hd2 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@95998.24] assign _T_18719 = 9'hd3 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96003.26] assign _T_18720 = 9'hd4 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96008.28] assign _T_18721 = 9'hd5 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96013.30] assign _T_18722 = 9'hd6 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96018.32] assign _T_18723 = 9'hd7 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96023.34] assign _T_18724 = 9'hd8 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96028.36] assign _T_18725 = 9'hd9 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96033.38] assign _T_18726 = 9'hda == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96038.40] assign _T_18727 = 9'hdb == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96043.42] assign _T_18728 = 9'hdc == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96048.44] assign _T_18729 = 9'hdd == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96053.46] assign _T_18730 = 9'hde == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96058.48] assign _T_18731 = 9'hdf == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96063.50] assign _T_18732 = 9'he0 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96068.52] assign _T_18733 = 9'h100 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96073.54] assign _T_18734 = 9'h101 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96078.56] assign _T_18735 = 9'h102 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96083.58] assign _T_18736 = 9'h103 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96088.60] assign _T_18737 = 9'h104 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96093.62] assign _T_18738 = 9'h105 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96098.64] assign _T_18739 = 9'h106 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96103.66] assign _T_18740 = 9'h107 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96108.68] assign _T_18741 = 9'h108 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96113.70] assign _T_18742 = 9'h109 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96118.72] assign _T_18743 = 9'h10a == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96123.74] assign _T_18744 = 9'h10b == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96128.76] assign _T_18745 = 9'h10c == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96133.78] assign _T_18746 = 9'h10d == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96138.80] assign _T_18747 = 9'h10e == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96143.82] assign _T_18748 = 9'h10f == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96148.84] assign _T_18749 = 9'h110 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96153.86] assign _T_18750 = 9'h111 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96158.88] assign _T_18751 = 9'h112 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96163.90] assign _T_18752 = 9'h113 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96168.92] assign _T_18753 = 9'h114 == _T_7394; // @[Conditional.scala 37:30:freechips.rocketchip.system.TinyConfig.fir@96173.94] assign _GEN_2504 = _T_18753 ? _T_3402 : 1'h1; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96174.94] assign _GEN_2505 = _T_18752 ? _T_3402 : _GEN_2504; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96169.92] assign _GEN_2506 = _T_18751 ? _T_3402 : _GEN_2505; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96164.90] assign _GEN_2507 = _T_18750 ? _T_3402 : _GEN_2506; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96159.88] assign _GEN_2508 = _T_18749 ? _T_3402 : _GEN_2507; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96154.86] assign _GEN_2509 = _T_18748 ? _T_3402 : _GEN_2508; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96149.84] assign _GEN_2510 = _T_18747 ? _T_3402 : _GEN_2509; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96144.82] assign _GEN_2511 = _T_18746 ? _T_3402 : _GEN_2510; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96139.80] assign _GEN_2512 = _T_18745 ? _T_3402 : _GEN_2511; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96134.78] assign _GEN_2513 = _T_18744 ? _T_3402 : _GEN_2512; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96129.76] assign _GEN_2514 = _T_18743 ? _T_3402 : _GEN_2513; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96124.74] assign _GEN_2515 = _T_18742 ? _T_3402 : _GEN_2514; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96119.72] assign _GEN_2516 = _T_18741 ? _T_3402 : _GEN_2515; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96114.70] assign _GEN_2517 = _T_18740 ? _T_3402 : _GEN_2516; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96109.68] assign _GEN_2518 = _T_18739 ? _T_3402 : _GEN_2517; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96104.66] assign _GEN_2519 = _T_18738 ? _T_3402 : _GEN_2518; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96099.64] assign _GEN_2520 = _T_18737 ? _T_3402 : _GEN_2519; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96094.62] assign _GEN_2521 = _T_18736 ? _T_3402 : _GEN_2520; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96089.60] assign _GEN_2522 = _T_18735 ? _T_3402 : _GEN_2521; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96084.58] assign _GEN_2523 = _T_18734 ? _T_3402 : _GEN_2522; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96079.56] assign _GEN_2524 = _T_18733 ? _T_3402 : _GEN_2523; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96074.54] assign _GEN_2525 = _T_18732 ? _T_3402 : _GEN_2524; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96069.52] assign _GEN_2526 = _T_18731 ? _T_3402 : _GEN_2525; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96064.50] assign _GEN_2527 = _T_18730 ? _T_3402 : _GEN_2526; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96059.48] assign _GEN_2528 = _T_18729 ? _T_3402 : _GEN_2527; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96054.46] assign _GEN_2529 = _T_18728 ? _T_3402 : _GEN_2528; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96049.44] assign _GEN_2530 = _T_18727 ? _T_3402 : _GEN_2529; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96044.42] assign _GEN_2531 = _T_18726 ? _T_3402 : _GEN_2530; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96039.40] assign _GEN_2532 = _T_18725 ? _T_3402 : _GEN_2531; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96034.38] assign _GEN_2533 = _T_18724 ? _T_3402 : _GEN_2532; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96029.36] assign _GEN_2534 = _T_18723 ? _T_3402 : _GEN_2533; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96024.34] assign _GEN_2535 = _T_18722 ? _T_3402 : _GEN_2534; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96019.32] assign _GEN_2536 = _T_18721 ? _T_3402 : _GEN_2535; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96014.30] assign _GEN_2537 = _T_18720 ? _T_3402 : _GEN_2536; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96009.28] assign _GEN_2538 = _T_18719 ? _T_3402 : _GEN_2537; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96004.26] assign _GEN_2539 = _T_18718 ? _T_3402 : _GEN_2538; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95999.24] assign _GEN_2540 = _T_18717 ? _T_3402 : _GEN_2539; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95994.22] assign _GEN_2541 = _T_18716 ? _T_3402 : _GEN_2540; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95989.20] assign _GEN_2542 = _T_18715 ? _T_3402 : _GEN_2541; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95984.18] assign _GEN_2543 = _T_18714 ? _T_3402 : _GEN_2542; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95979.16] assign _GEN_2544 = _T_18713 ? _T_3402 : _GEN_2543; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95974.14] assign _GEN_2545 = _T_18712 ? _T_3402 : _GEN_2544; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95969.12] assign _GEN_2546 = _T_18711 ? _T_3402 : _GEN_2545; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95964.10] assign _GEN_2547 = _T_18710 ? _T_3402 : _GEN_2546; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95959.8] assign _GEN_2548 = _T_18709 ? _T_3402 : _GEN_2547; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@95954.6] assign _GEN_2549 = _T_18708 ? _T_3352 : _GEN_2548; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@95949.4] assign _GEN_2550 = _T_18753 ? 32'h100073 : 32'h0; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96406.94] assign _GEN_2551 = _T_18752 ? 32'h10002623 : _GEN_2550; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96401.92] assign _GEN_2552 = _T_18751 ? 32'h7b200073 : _GEN_2551; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96396.90] assign _GEN_2553 = _T_18750 ? 32'h7b202473 : _GEN_2552; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96391.88] assign _GEN_2554 = _T_18749 ? 32'h10802423 : _GEN_2553; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96386.86] assign _GEN_2555 = _T_18748 ? 32'hf1402473 : _GEN_2554; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96381.84] assign _GEN_2556 = _T_18747 ? 32'h30000067 : _GEN_2555; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96376.82] assign _GEN_2557 = _T_18746 ? 32'h10002223 : _GEN_2556; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96371.80] assign _GEN_2558 = _T_18745 ? 32'h7b202473 : _GEN_2557; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96366.78] assign _GEN_2559 = _T_18744 ? 32'h40863 : _GEN_2558; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96361.76] assign _GEN_2560 = _T_18743 ? 32'h147413 : _GEN_2559; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96356.74] assign _GEN_2561 = _T_18742 ? 32'hfe0408e3 : _GEN_2560; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96351.72] assign _GEN_2562 = _T_18741 ? 32'h347413 : _GEN_2561; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96346.70] assign _GEN_2563 = _T_18740 ? 32'h40044403 : _GEN_2562; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96341.68] assign _GEN_2564 = _T_18739 ? 32'h10802023 : _GEN_2563; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96336.66] assign _GEN_2565 = _T_18738 ? 32'hf1402473 : _GEN_2564; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96331.64] assign _GEN_2566 = _T_18737 ? 32'h7b241073 : _GEN_2565; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96326.62] assign _GEN_2567 = _T_18736 ? 32'hff0000f : _GEN_2566; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96321.60] assign _GEN_2568 = _T_18735 ? 32'h440006f : _GEN_2567; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96316.58] assign _GEN_2569 = _T_18734 ? 32'h380006f : _GEN_2568; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96311.56] assign _GEN_2570 = _T_18733 ? 32'hc0006f : _GEN_2569; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96306.54] assign _GEN_2571 = _T_18732 ? _T_2215 : _GEN_2570; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96301.52] assign _GEN_2572 = _T_18731 ? _T_2313 : _GEN_2571; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96296.50] assign _GEN_2573 = _T_18730 ? _T_803 : _GEN_2572; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96291.48] assign _GEN_2574 = _T_18729 ? _T_1391 : _GEN_2573; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96286.46] assign _GEN_2575 = _T_18728 ? _T_1558 : _GEN_2574; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96281.44] assign _GEN_2576 = _T_18727 ? _T_1875 : _GEN_2575; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96276.42] assign _GEN_2577 = _T_18726 ? _T_584 : _GEN_2576; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96271.40] assign _GEN_2578 = _T_18725 ? _T_1097 : _GEN_2577; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96266.38] assign _GEN_2579 = _T_18724 ? _T_1973 : _GEN_2578; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96261.36] assign _GEN_2580 = _T_18723 ? _T_1656 : _GEN_2579; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96256.34] assign _GEN_2581 = _T_18722 ? _T_901 : _GEN_2580; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96251.32] assign _GEN_2582 = _T_18721 ? _T_705 : _GEN_2581; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96246.30] assign _GEN_2583 = _T_18720 ? _T_2094 : _GEN_2582; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96241.28] assign _GEN_2584 = _T_18719 ? _T_1754 : _GEN_2583; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96236.26] assign _GEN_2585 = _T_18718 ? _T_1293 : _GEN_2584; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96231.24] assign _GEN_2586 = _T_18717 ? _T_999 : _GEN_2585; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96226.22] assign _GEN_2587 = _T_18716 ? _T_1195 : _GEN_2586; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96221.20] assign _GEN_2588 = _T_18715 ? abstractGeneratedMem_1 : _GEN_2587; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96216.18] assign _GEN_2589 = _T_18714 ? abstractGeneratedMem_0 : _GEN_2588; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96211.16] assign _GEN_2590 = _T_18713 ? 32'h380006f : _GEN_2589; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96206.14] assign _GEN_2591 = _T_18712 ? 32'h0 : _GEN_2590; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96201.12] assign _GEN_2592 = _T_18711 ? 32'h0 : _GEN_2591; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96196.10] assign _GEN_2593 = _T_18710 ? 32'h0 : _GEN_2592; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96191.8] assign _GEN_2594 = _T_18709 ? 32'h0 : _GEN_2593; // @[Conditional.scala 39:67:freechips.rocketchip.system.TinyConfig.fir@96186.6] assign _GEN_2595 = _T_18708 ? {{16'd0}, _T_4930} : _GEN_2594; // @[Conditional.scala 40:58:freechips.rocketchip.system.TinyConfig.fir@96181.4] assign _T_18848 = goReg == 1'h0; // @[Debug.scala 1356:18:freechips.rocketchip.system.TinyConfig.fir@96619.10] assign _T_18849 = _T_18848 & hartHaltedWrEn; // @[Debug.scala 1356:30:freechips.rocketchip.system.TinyConfig.fir@96620.10] assign _T_18851 = _T_18849 & _T_360; // @[Debug.scala 1356:48:freechips.rocketchip.system.TinyConfig.fir@96622.10] assign _T_18856 = ctrlStateReg == 2'h3; // @[Debug.scala 1364:30:freechips.rocketchip.system.TinyConfig.fir@96640.10] assign _T_18859 = reset == 1'h0; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96644.12] assign _T_18862 = io_dmactive == 1'h0; // @[Debug.scala 1378:14:freechips.rocketchip.system.TinyConfig.fir@96662.4] assign _T_18863 = hartExceptionWrEn == 1'h0; // @[Debug.scala 1378:30:freechips.rocketchip.system.TinyConfig.fir@96663.4] assign _T_18864 = _T_18862 | _T_18863; // @[Debug.scala 1378:27:freechips.rocketchip.system.TinyConfig.fir@96664.4] assign _T_18866 = _T_18864 | _T_18847; // @[Debug.scala 1378:49:freechips.rocketchip.system.TinyConfig.fir@96666.4] assign _T_18868 = _T_18866 | reset; // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96668.4] assign _T_18869 = _T_18868 == 1'h0; // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96669.4] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_tl_in_d_bits_opcode = {{2'd0}, _T_3310}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_tl_in_d_bits_size = _T_3312[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_tl_in_d_bits_source = _T_3312[11:2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_tl_in_d_bits_data = _GEN_2549 ? _GEN_2595 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68023.4] assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign auto_dmi_in_d_bits_opcode = {{2'd0}, _T_399}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign auto_dmi_in_d_bits_size = _T_401[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign auto_dmi_in_d_bits_source = _T_401[2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign auto_dmi_in_d_bits_data = _GEN_278 ? _GEN_310 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@68022.4] assign io_innerCtrl_ready = 1'h1; // @[Debug.scala 663:24:freechips.rocketchip.system.TinyConfig.fir@68226.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@67922.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@67923.4] assign TLMonitor_io_in_a_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_param = auto_dmi_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_mask = auto_dmi_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_a_bits_corrupt = auto_dmi_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_d_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_399}; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_d_bits_size = _T_401[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_io_in_d_bits_source = _T_401[2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@67968.4] assign TLMonitor_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@67973.4] assign TLMonitor_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@67974.4] assign TLMonitor_1_io_in_a_ready = auto_tl_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_d_valid = auto_tl_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_d_bits_opcode = {{2'd0}, _T_3310}; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_d_bits_size = _T_3312[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign TLMonitor_1_io_in_d_bits_source = _T_3312[11:2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@68019.4] assign _GEN_2705 = _T_139 == 1'h0; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] assign _GEN_2706 = goAbstract == 1'h0; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] assign _GEN_2707 = _GEN_2705 & _GEN_2706; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] assign _GEN_2708 = _GEN_2707 & hartGoingWrEn; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] assign _GEN_2713 = ABSTRACTCSWrEnLegal == 1'h0; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] assign _GEN_2714 = _T_18846 == 1'h0; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] assign _GEN_2715 = _GEN_2713 & _GEN_2714; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] assign _GEN_2716 = _GEN_2715 & _T_18847; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] assign _GEN_2717 = _GEN_2716 & hartExceptionWrEn; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] assign _GEN_2726 = _T_18847 == 1'h0; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] assign _GEN_2727 = _GEN_2715 & _GEN_2726; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] assign _GEN_2728 = _GEN_2727 & _T_18856; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; haltedBitRegs_0 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; resumeReqRegs_0 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; haveResetBitRegs_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; ABSTRACTCSReg_cmderr = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; ctrlStateReg = _RAND_4[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; COMMANDRdData_cmdtype = _RAND_5[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; COMMANDRdData_control = _RAND_6[23:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; ABSTRACTAUTOReg_autoexecdata = _RAND_7[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; ABSTRACTAUTOReg_autoexecprogbuf = _RAND_8[15:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; abstractDataMem_0 = _RAND_9[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; abstractDataMem_1 = _RAND_10[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; abstractDataMem_2 = _RAND_11[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; abstractDataMem_3 = _RAND_12[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; programBufferMem_0 = _RAND_13[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; programBufferMem_1 = _RAND_14[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; programBufferMem_2 = _RAND_15[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; programBufferMem_3 = _RAND_16[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; programBufferMem_4 = _RAND_17[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; programBufferMem_5 = _RAND_18[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; programBufferMem_6 = _RAND_19[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; programBufferMem_7 = _RAND_20[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; programBufferMem_8 = _RAND_21[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; programBufferMem_9 = _RAND_22[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; programBufferMem_10 = _RAND_23[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_24 = {1{`RANDOM}}; programBufferMem_11 = _RAND_24[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_25 = {1{`RANDOM}}; programBufferMem_12 = _RAND_25[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_26 = {1{`RANDOM}}; programBufferMem_13 = _RAND_26[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_27 = {1{`RANDOM}}; programBufferMem_14 = _RAND_27[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_28 = {1{`RANDOM}}; programBufferMem_15 = _RAND_28[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_29 = {1{`RANDOM}}; programBufferMem_16 = _RAND_29[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_30 = {1{`RANDOM}}; programBufferMem_17 = _RAND_30[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_31 = {1{`RANDOM}}; programBufferMem_18 = _RAND_31[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_32 = {1{`RANDOM}}; programBufferMem_19 = _RAND_32[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_33 = {1{`RANDOM}}; programBufferMem_20 = _RAND_33[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_34 = {1{`RANDOM}}; programBufferMem_21 = _RAND_34[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_35 = {1{`RANDOM}}; programBufferMem_22 = _RAND_35[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_36 = {1{`RANDOM}}; programBufferMem_23 = _RAND_36[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_37 = {1{`RANDOM}}; programBufferMem_24 = _RAND_37[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_38 = {1{`RANDOM}}; programBufferMem_25 = _RAND_38[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_39 = {1{`RANDOM}}; programBufferMem_26 = _RAND_39[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_40 = {1{`RANDOM}}; programBufferMem_27 = _RAND_40[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_41 = {1{`RANDOM}}; programBufferMem_28 = _RAND_41[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_42 = {1{`RANDOM}}; programBufferMem_29 = _RAND_42[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_43 = {1{`RANDOM}}; programBufferMem_30 = _RAND_43[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_44 = {1{`RANDOM}}; programBufferMem_31 = _RAND_44[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_45 = {1{`RANDOM}}; programBufferMem_32 = _RAND_45[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_46 = {1{`RANDOM}}; programBufferMem_33 = _RAND_46[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_47 = {1{`RANDOM}}; programBufferMem_34 = _RAND_47[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_48 = {1{`RANDOM}}; programBufferMem_35 = _RAND_48[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_49 = {1{`RANDOM}}; programBufferMem_36 = _RAND_49[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_50 = {1{`RANDOM}}; programBufferMem_37 = _RAND_50[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_51 = {1{`RANDOM}}; programBufferMem_38 = _RAND_51[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_52 = {1{`RANDOM}}; programBufferMem_39 = _RAND_52[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_53 = {1{`RANDOM}}; programBufferMem_40 = _RAND_53[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_54 = {1{`RANDOM}}; programBufferMem_41 = _RAND_54[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_55 = {1{`RANDOM}}; programBufferMem_42 = _RAND_55[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_56 = {1{`RANDOM}}; programBufferMem_43 = _RAND_56[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_57 = {1{`RANDOM}}; programBufferMem_44 = _RAND_57[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_58 = {1{`RANDOM}}; programBufferMem_45 = _RAND_58[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_59 = {1{`RANDOM}}; programBufferMem_46 = _RAND_59[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_60 = {1{`RANDOM}}; programBufferMem_47 = _RAND_60[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_61 = {1{`RANDOM}}; programBufferMem_48 = _RAND_61[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_62 = {1{`RANDOM}}; programBufferMem_49 = _RAND_62[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_63 = {1{`RANDOM}}; programBufferMem_50 = _RAND_63[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_64 = {1{`RANDOM}}; programBufferMem_51 = _RAND_64[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_65 = {1{`RANDOM}}; programBufferMem_52 = _RAND_65[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_66 = {1{`RANDOM}}; programBufferMem_53 = _RAND_66[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_67 = {1{`RANDOM}}; programBufferMem_54 = _RAND_67[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_68 = {1{`RANDOM}}; programBufferMem_55 = _RAND_68[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_69 = {1{`RANDOM}}; programBufferMem_56 = _RAND_69[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_70 = {1{`RANDOM}}; programBufferMem_57 = _RAND_70[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_71 = {1{`RANDOM}}; programBufferMem_58 = _RAND_71[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_72 = {1{`RANDOM}}; programBufferMem_59 = _RAND_72[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_73 = {1{`RANDOM}}; programBufferMem_60 = _RAND_73[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_74 = {1{`RANDOM}}; programBufferMem_61 = _RAND_74[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_75 = {1{`RANDOM}}; programBufferMem_62 = _RAND_75[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_76 = {1{`RANDOM}}; programBufferMem_63 = _RAND_76[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_77 = {1{`RANDOM}}; goReg = _RAND_77[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_78 = {1{`RANDOM}}; abstractGeneratedMem_0 = _RAND_78[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_79 = {1{`RANDOM}}; abstractGeneratedMem_1 = _RAND_79[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin haltedBitRegs_0 <= 1'h0; end else begin if (_T_139) begin haltedBitRegs_0 <= 1'h0; end else begin if (hartHaltedWrEn) begin if (_T_360) begin haltedBitRegs_0 <= 1'h1; end end else begin if (hartResumingWrEn) begin if (_T_360) begin haltedBitRegs_0 <= 1'h0; end end end end end if (reset) begin resumeReqRegs_0 <= 1'h0; end else begin if (_T_139) begin resumeReqRegs_0 <= 1'h0; end else begin if (_T_363) begin resumeReqRegs_0 <= 1'h1; end else begin if (hartResumingWrEn) begin if (_T_360) begin resumeReqRegs_0 <= 1'h0; end end end end end if (reset) begin haveResetBitRegs_0 <= 1'h1; end else begin if (_T_96) begin haveResetBitRegs_0 <= 1'h0; end end if (_T_139) begin ABSTRACTCSReg_cmderr <= 3'h0; end else begin if (errorBusy) begin ABSTRACTCSReg_cmderr <= 3'h1; end else begin if (errorException) begin ABSTRACTCSReg_cmderr <= 3'h3; end else begin if (errorUnsupported) begin ABSTRACTCSReg_cmderr <= 3'h2; end else begin if (errorHaltResume) begin ABSTRACTCSReg_cmderr <= 3'h4; end else begin if (ABSTRACTCSWrEn) begin ABSTRACTCSReg_cmderr <= _T_141; end end end end end end if (_T_139) begin ctrlStateReg <= 2'h0; end else begin if (ABSTRACTCSWrEnLegal) begin if (_T_18844) begin ctrlStateReg <= 2'h1; end end else begin if (_T_18846) begin if (commandRegIsUnsupported) begin ctrlStateReg <= 2'h0; end else begin if (commandRegBadHaltResume) begin ctrlStateReg <= 2'h0; end else begin ctrlStateReg <= 2'h2; end end end else begin if (_T_18847) begin if (hartExceptionWrEn) begin ctrlStateReg <= 2'h0; end else begin if (_T_18851) begin ctrlStateReg <= 2'h0; end end end end end end if (_T_139) begin COMMANDRdData_cmdtype <= 8'h0; end else begin if (COMMANDWrEn) begin COMMANDRdData_cmdtype <= COMMANDWrData_cmdtype; end end if (_T_139) begin COMMANDRdData_control <= 24'h0; end else begin if (COMMANDWrEn) begin COMMANDRdData_control <= COMMANDWrData_control; end end if (_T_139) begin ABSTRACTAUTOReg_autoexecdata <= 12'h0; end else begin if (ABSTRACTAUTOWrEn) begin ABSTRACTAUTOReg_autoexecdata <= _T_153; end end if (_T_139) begin ABSTRACTAUTOReg_autoexecprogbuf <= 16'h0; end else begin if (ABSTRACTAUTOWrEn) begin ABSTRACTAUTOReg_autoexecprogbuf <= ABSTRACTAUTOWrData_autoexecprogbuf; end end if (_T_139) begin abstractDataMem_0 <= 8'h0; end else begin if (_T_4699) begin abstractDataMem_0 <= _T_3456; end else begin if (_T_3086) begin if (dmiAbstractDataWrEnMaybe_0) begin abstractDataMem_0 <= _T_501; end end end end if (_T_139) begin abstractDataMem_1 <= 8'h0; end else begin if (_T_4722) begin abstractDataMem_1 <= _T_3479; end else begin if (_T_3087) begin if (dmiAbstractDataWrEnMaybe_1) begin abstractDataMem_1 <= _T_524; end end end end if (_T_139) begin abstractDataMem_2 <= 8'h0; end else begin if (_T_4747) begin abstractDataMem_2 <= _T_3504; end else begin if (_T_3088) begin if (dmiAbstractDataWrEnMaybe_2) begin abstractDataMem_2 <= _T_549; end end end end if (_T_139) begin abstractDataMem_3 <= 8'h0; end else begin if (_T_4772) begin abstractDataMem_3 <= _T_3529; end else begin if (_T_3089) begin if (dmiAbstractDataWrEnMaybe_3) begin abstractDataMem_3 <= _T_574; end end end end if (_T_139) begin programBufferMem_0 <= 8'h0; end else begin if (_T_5554) begin programBufferMem_0 <= _T_3456; end else begin if (_T_3090) begin if (dmiProgramBufferWrEnMaybe_0) begin programBufferMem_0 <= _T_501; end end end end if (_T_139) begin programBufferMem_1 <= 8'h0; end else begin if (_T_5577) begin programBufferMem_1 <= _T_3479; end else begin if (_T_3091) begin if (dmiProgramBufferWrEnMaybe_1) begin programBufferMem_1 <= _T_524; end end end end if (_T_139) begin programBufferMem_2 <= 8'h0; end else begin if (_T_5602) begin programBufferMem_2 <= _T_3504; end else begin if (_T_3092) begin if (dmiProgramBufferWrEnMaybe_2) begin programBufferMem_2 <= _T_549; end end end end if (_T_139) begin programBufferMem_3 <= 8'h0; end else begin if (_T_5627) begin programBufferMem_3 <= _T_3529; end else begin if (_T_3093) begin if (dmiProgramBufferWrEnMaybe_3) begin programBufferMem_3 <= _T_574; end end end end if (_T_139) begin programBufferMem_4 <= 8'h0; end else begin if (_T_6165) begin programBufferMem_4 <= _T_3456; end else begin if (_T_3094) begin if (dmiProgramBufferWrEnMaybe_4) begin programBufferMem_4 <= _T_501; end end end end if (_T_139) begin programBufferMem_5 <= 8'h0; end else begin if (_T_6188) begin programBufferMem_5 <= _T_3479; end else begin if (_T_3095) begin if (dmiProgramBufferWrEnMaybe_5) begin programBufferMem_5 <= _T_524; end end end end if (_T_139) begin programBufferMem_6 <= 8'h0; end else begin if (_T_6213) begin programBufferMem_6 <= _T_3504; end else begin if (_T_3096) begin if (dmiProgramBufferWrEnMaybe_6) begin programBufferMem_6 <= _T_549; end end end end if (_T_139) begin programBufferMem_7 <= 8'h0; end else begin if (_T_6238) begin programBufferMem_7 <= _T_3529; end else begin if (_T_3097) begin if (dmiProgramBufferWrEnMaybe_7) begin programBufferMem_7 <= _T_574; end end end end if (_T_139) begin programBufferMem_8 <= 8'h0; end else begin if (_T_6897) begin programBufferMem_8 <= _T_3456; end else begin if (_T_3098) begin if (dmiProgramBufferWrEnMaybe_8) begin programBufferMem_8 <= _T_501; end end end end if (_T_139) begin programBufferMem_9 <= 8'h0; end else begin if (_T_6920) begin programBufferMem_9 <= _T_3479; end else begin if (_T_3099) begin if (dmiProgramBufferWrEnMaybe_9) begin programBufferMem_9 <= _T_524; end end end end if (_T_139) begin programBufferMem_10 <= 8'h0; end else begin if (_T_6945) begin programBufferMem_10 <= _T_3504; end else begin if (_T_3100) begin if (dmiProgramBufferWrEnMaybe_10) begin programBufferMem_10 <= _T_549; end end end end if (_T_139) begin programBufferMem_11 <= 8'h0; end else begin if (_T_6970) begin programBufferMem_11 <= _T_3529; end else begin if (_T_3101) begin if (dmiProgramBufferWrEnMaybe_11) begin programBufferMem_11 <= _T_574; end end end end if (_T_139) begin programBufferMem_12 <= 8'h0; end else begin if (_T_3846) begin programBufferMem_12 <= _T_3456; end else begin if (_T_3102) begin if (dmiProgramBufferWrEnMaybe_12) begin programBufferMem_12 <= _T_501; end end end end if (_T_139) begin programBufferMem_13 <= 8'h0; end else begin if (_T_3869) begin programBufferMem_13 <= _T_3479; end else begin if (_T_3103) begin if (dmiProgramBufferWrEnMaybe_13) begin programBufferMem_13 <= _T_524; end end end end if (_T_139) begin programBufferMem_14 <= 8'h0; end else begin if (_T_3894) begin programBufferMem_14 <= _T_3504; end else begin if (_T_3104) begin if (dmiProgramBufferWrEnMaybe_14) begin programBufferMem_14 <= _T_549; end end end end if (_T_139) begin programBufferMem_15 <= 8'h0; end else begin if (_T_3919) begin programBufferMem_15 <= _T_3529; end else begin if (_T_3105) begin if (dmiProgramBufferWrEnMaybe_15) begin programBufferMem_15 <= _T_574; end end end end if (_T_139) begin programBufferMem_16 <= 8'h0; end else begin if (_T_5041) begin programBufferMem_16 <= _T_3456; end else begin if (_T_3106) begin if (dmiProgramBufferWrEnMaybe_16) begin programBufferMem_16 <= _T_501; end end end end if (_T_139) begin programBufferMem_17 <= 8'h0; end else begin if (_T_5064) begin programBufferMem_17 <= _T_3479; end else begin if (_T_3107) begin if (dmiProgramBufferWrEnMaybe_17) begin programBufferMem_17 <= _T_524; end end end end if (_T_139) begin programBufferMem_18 <= 8'h0; end else begin if (_T_5089) begin programBufferMem_18 <= _T_3504; end else begin if (_T_3108) begin if (dmiProgramBufferWrEnMaybe_18) begin programBufferMem_18 <= _T_549; end end end end if (_T_139) begin programBufferMem_19 <= 8'h0; end else begin if (_T_5114) begin programBufferMem_19 <= _T_3529; end else begin if (_T_3109) begin if (dmiProgramBufferWrEnMaybe_19) begin programBufferMem_19 <= _T_574; end end end end if (_T_139) begin programBufferMem_20 <= 8'h0; end else begin if (_T_5652) begin programBufferMem_20 <= _T_3456; end else begin if (_T_3110) begin if (dmiProgramBufferWrEnMaybe_20) begin programBufferMem_20 <= _T_501; end end end end if (_T_139) begin programBufferMem_21 <= 8'h0; end else begin if (_T_5675) begin programBufferMem_21 <= _T_3479; end else begin if (_T_3111) begin if (dmiProgramBufferWrEnMaybe_21) begin programBufferMem_21 <= _T_524; end end end end if (_T_139) begin programBufferMem_22 <= 8'h0; end else begin if (_T_5700) begin programBufferMem_22 <= _T_3504; end else begin if (_T_3112) begin if (dmiProgramBufferWrEnMaybe_22) begin programBufferMem_22 <= _T_549; end end end end if (_T_139) begin programBufferMem_23 <= 8'h0; end else begin if (_T_5725) begin programBufferMem_23 <= _T_3529; end else begin if (_T_3113) begin if (dmiProgramBufferWrEnMaybe_23) begin programBufferMem_23 <= _T_574; end end end end if (_T_139) begin programBufferMem_24 <= 8'h0; end else begin if (_T_6799) begin programBufferMem_24 <= _T_3456; end else begin if (_T_3114) begin if (dmiProgramBufferWrEnMaybe_24) begin programBufferMem_24 <= _T_501; end end end end if (_T_139) begin programBufferMem_25 <= 8'h0; end else begin if (_T_6822) begin programBufferMem_25 <= _T_3479; end else begin if (_T_3115) begin if (dmiProgramBufferWrEnMaybe_25) begin programBufferMem_25 <= _T_524; end end end end if (_T_139) begin programBufferMem_26 <= 8'h0; end else begin if (_T_6847) begin programBufferMem_26 <= _T_3504; end else begin if (_T_3116) begin if (dmiProgramBufferWrEnMaybe_26) begin programBufferMem_26 <= _T_549; end end end end if (_T_139) begin programBufferMem_27 <= 8'h0; end else begin if (_T_6872) begin programBufferMem_27 <= _T_3529; end else begin if (_T_3117) begin if (dmiProgramBufferWrEnMaybe_27) begin programBufferMem_27 <= _T_574; end end end end if (_T_139) begin programBufferMem_28 <= 8'h0; end else begin if (_T_7191) begin programBufferMem_28 <= _T_3456; end else begin if (_T_3118) begin if (dmiProgramBufferWrEnMaybe_28) begin programBufferMem_28 <= _T_501; end end end end if (_T_139) begin programBufferMem_29 <= 8'h0; end else begin if (_T_7214) begin programBufferMem_29 <= _T_3479; end else begin if (_T_3119) begin if (dmiProgramBufferWrEnMaybe_29) begin programBufferMem_29 <= _T_524; end end end end if (_T_139) begin programBufferMem_30 <= 8'h0; end else begin if (_T_7239) begin programBufferMem_30 <= _T_3504; end else begin if (_T_3120) begin if (dmiProgramBufferWrEnMaybe_30) begin programBufferMem_30 <= _T_549; end end end end if (_T_139) begin programBufferMem_31 <= 8'h0; end else begin if (_T_7264) begin programBufferMem_31 <= _T_3529; end else begin if (_T_3121) begin if (dmiProgramBufferWrEnMaybe_31) begin programBufferMem_31 <= _T_574; end end end end if (_T_139) begin programBufferMem_32 <= 8'h0; end else begin if (_T_3748) begin programBufferMem_32 <= _T_3456; end else begin if (_T_3122) begin if (dmiProgramBufferWrEnMaybe_32) begin programBufferMem_32 <= _T_501; end end end end if (_T_139) begin programBufferMem_33 <= 8'h0; end else begin if (_T_3771) begin programBufferMem_33 <= _T_3479; end else begin if (_T_3123) begin if (dmiProgramBufferWrEnMaybe_33) begin programBufferMem_33 <= _T_524; end end end end if (_T_139) begin programBufferMem_34 <= 8'h0; end else begin if (_T_3796) begin programBufferMem_34 <= _T_3504; end else begin if (_T_3124) begin if (dmiProgramBufferWrEnMaybe_34) begin programBufferMem_34 <= _T_549; end end end end if (_T_139) begin programBufferMem_35 <= 8'h0; end else begin if (_T_3821) begin programBufferMem_35 <= _T_3529; end else begin if (_T_3125) begin if (dmiProgramBufferWrEnMaybe_35) begin programBufferMem_35 <= _T_574; end end end end if (_T_139) begin programBufferMem_36 <= 8'h0; end else begin if (_T_3650) begin programBufferMem_36 <= _T_3456; end else begin if (_T_3126) begin if (dmiProgramBufferWrEnMaybe_36) begin programBufferMem_36 <= _T_501; end end end end if (_T_139) begin programBufferMem_37 <= 8'h0; end else begin if (_T_3673) begin programBufferMem_37 <= _T_3479; end else begin if (_T_3127) begin if (dmiProgramBufferWrEnMaybe_37) begin programBufferMem_37 <= _T_524; end end end end if (_T_139) begin programBufferMem_38 <= 8'h0; end else begin if (_T_3698) begin programBufferMem_38 <= _T_3504; end else begin if (_T_3128) begin if (dmiProgramBufferWrEnMaybe_38) begin programBufferMem_38 <= _T_549; end end end end if (_T_139) begin programBufferMem_39 <= 8'h0; end else begin if (_T_3723) begin programBufferMem_39 <= _T_3529; end else begin if (_T_3129) begin if (dmiProgramBufferWrEnMaybe_39) begin programBufferMem_39 <= _T_574; end end end end if (_T_139) begin programBufferMem_40 <= 8'h0; end else begin if (_T_6580) begin programBufferMem_40 <= _T_3456; end else begin if (_T_3130) begin if (dmiProgramBufferWrEnMaybe_40) begin programBufferMem_40 <= _T_501; end end end end if (_T_139) begin programBufferMem_41 <= 8'h0; end else begin if (_T_6603) begin programBufferMem_41 <= _T_3479; end else begin if (_T_3131) begin if (dmiProgramBufferWrEnMaybe_41) begin programBufferMem_41 <= _T_524; end end end end if (_T_139) begin programBufferMem_42 <= 8'h0; end else begin if (_T_6628) begin programBufferMem_42 <= _T_3504; end else begin if (_T_3132) begin if (dmiProgramBufferWrEnMaybe_42) begin programBufferMem_42 <= _T_549; end end end end if (_T_139) begin programBufferMem_43 <= 8'h0; end else begin if (_T_6653) begin programBufferMem_43 <= _T_3529; end else begin if (_T_3133) begin if (dmiProgramBufferWrEnMaybe_43) begin programBufferMem_43 <= _T_574; end end end end if (_T_139) begin programBufferMem_44 <= 8'h0; end else begin if (_T_5456) begin programBufferMem_44 <= _T_3456; end else begin if (_T_3134) begin if (dmiProgramBufferWrEnMaybe_44) begin programBufferMem_44 <= _T_501; end end end end if (_T_139) begin programBufferMem_45 <= 8'h0; end else begin if (_T_5479) begin programBufferMem_45 <= _T_3479; end else begin if (_T_3135) begin if (dmiProgramBufferWrEnMaybe_45) begin programBufferMem_45 <= _T_524; end end end end if (_T_139) begin programBufferMem_46 <= 8'h0; end else begin if (_T_5504) begin programBufferMem_46 <= _T_3504; end else begin if (_T_3136) begin if (dmiProgramBufferWrEnMaybe_46) begin programBufferMem_46 <= _T_549; end end end end if (_T_139) begin programBufferMem_47 <= 8'h0; end else begin if (_T_5529) begin programBufferMem_47 <= _T_3529; end else begin if (_T_3137) begin if (dmiProgramBufferWrEnMaybe_47) begin programBufferMem_47 <= _T_574; end end end end if (_T_139) begin programBufferMem_48 <= 8'h0; end else begin if (_T_4457) begin programBufferMem_48 <= _T_3456; end else begin if (_T_3138) begin if (dmiProgramBufferWrEnMaybe_48) begin programBufferMem_48 <= _T_501; end end end end if (_T_139) begin programBufferMem_49 <= 8'h0; end else begin if (_T_4480) begin programBufferMem_49 <= _T_3479; end else begin if (_T_3139) begin if (dmiProgramBufferWrEnMaybe_49) begin programBufferMem_49 <= _T_524; end end end end if (_T_139) begin programBufferMem_50 <= 8'h0; end else begin if (_T_4505) begin programBufferMem_50 <= _T_3504; end else begin if (_T_3140) begin if (dmiProgramBufferWrEnMaybe_50) begin programBufferMem_50 <= _T_549; end end end end if (_T_139) begin programBufferMem_51 <= 8'h0; end else begin if (_T_4530) begin programBufferMem_51 <= _T_3529; end else begin if (_T_3141) begin if (dmiProgramBufferWrEnMaybe_51) begin programBufferMem_51 <= _T_574; end end end end if (_T_139) begin programBufferMem_52 <= 8'h0; end else begin if (_T_4042) begin programBufferMem_52 <= _T_3456; end else begin if (_T_3142) begin if (dmiProgramBufferWrEnMaybe_52) begin programBufferMem_52 <= _T_501; end end end end if (_T_139) begin programBufferMem_53 <= 8'h0; end else begin if (_T_4065) begin programBufferMem_53 <= _T_3479; end else begin if (_T_3143) begin if (dmiProgramBufferWrEnMaybe_53) begin programBufferMem_53 <= _T_524; end end end end if (_T_139) begin programBufferMem_54 <= 8'h0; end else begin if (_T_4090) begin programBufferMem_54 <= _T_3504; end else begin if (_T_3144) begin if (dmiProgramBufferWrEnMaybe_54) begin programBufferMem_54 <= _T_549; end end end end if (_T_139) begin programBufferMem_55 <= 8'h0; end else begin if (_T_4115) begin programBufferMem_55 <= _T_3529; end else begin if (_T_3145) begin if (dmiProgramBufferWrEnMaybe_55) begin programBufferMem_55 <= _T_574; end end end end if (_T_139) begin programBufferMem_56 <= 8'h0; end else begin if (_T_7289) begin programBufferMem_56 <= _T_3456; end else begin if (_T_3146) begin if (dmiProgramBufferWrEnMaybe_56) begin programBufferMem_56 <= _T_501; end end end end if (_T_139) begin programBufferMem_57 <= 8'h0; end else begin if (_T_7312) begin programBufferMem_57 <= _T_3479; end else begin if (_T_3147) begin if (dmiProgramBufferWrEnMaybe_57) begin programBufferMem_57 <= _T_524; end end end end if (_T_139) begin programBufferMem_58 <= 8'h0; end else begin if (_T_7337) begin programBufferMem_58 <= _T_3504; end else begin if (_T_3148) begin if (dmiProgramBufferWrEnMaybe_58) begin programBufferMem_58 <= _T_549; end end end end if (_T_139) begin programBufferMem_59 <= 8'h0; end else begin if (_T_7362) begin programBufferMem_59 <= _T_3529; end else begin if (_T_3149) begin if (dmiProgramBufferWrEnMaybe_59) begin programBufferMem_59 <= _T_574; end end end end if (_T_139) begin programBufferMem_60 <= 8'h0; end else begin if (_T_5969) begin programBufferMem_60 <= _T_3456; end else begin if (_T_3150) begin if (dmiProgramBufferWrEnMaybe_60) begin programBufferMem_60 <= _T_501; end end end end if (_T_139) begin programBufferMem_61 <= 8'h0; end else begin if (_T_5992) begin programBufferMem_61 <= _T_3479; end else begin if (_T_3151) begin if (dmiProgramBufferWrEnMaybe_61) begin programBufferMem_61 <= _T_524; end end end end if (_T_139) begin programBufferMem_62 <= 8'h0; end else begin if (_T_6017) begin programBufferMem_62 <= _T_3504; end else begin if (_T_3152) begin if (dmiProgramBufferWrEnMaybe_62) begin programBufferMem_62 <= _T_549; end end end end if (_T_139) begin programBufferMem_63 <= 8'h0; end else begin if (_T_6042) begin programBufferMem_63 <= _T_3529; end else begin if (_T_3153) begin if (dmiProgramBufferWrEnMaybe_63) begin programBufferMem_63 <= _T_574; end end end end if (_T_139) begin goReg <= 1'h0; end else begin if (goAbstract) begin goReg <= 1'h1; end else begin if (hartGoingWrEn) begin goReg <= 1'h0; end end end if (goAbstract) begin if (accessRegisterCommandReg_transfer) begin if (accessRegisterCommandReg_write) begin abstractGeneratedMem_0 <= _T_3283; end else begin abstractGeneratedMem_0 <= _T_3288; end end else begin abstractGeneratedMem_0 <= 32'h13; end end if (goAbstract) begin if (accessRegisterCommandReg_postexec) begin abstractGeneratedMem_1 <= 32'h13; end else begin abstractGeneratedMem_1 <= 32'h100073; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_2708 & _T_3215) begin $fwrite(32'h80000002,"Assertion failed: Unexpected 'GOING' hart.\n at Debug.scala:1101 assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %%x, expected %%x\", hartGoingId, 0.U)\n"); // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73321.12] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_2708 & _T_3215) begin $fatal; // @[Debug.scala 1101:15:freechips.rocketchip.system.TinyConfig.fir@73322.12] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_2717 & _T_3215) begin $fwrite(32'h80000002,"Assertion failed: Unexpected 'EXCEPTION' hart\n at Debug.scala:1360 assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %%x, expected %%x\", hartExceptionId, 0.U)\n"); // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96632.14] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_2717 & _T_3215) begin $fatal; // @[Debug.scala 1360:15:freechips.rocketchip.system.TinyConfig.fir@96633.14] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_2728 & _T_18859) begin $fwrite(32'h80000002,"Assertion failed: Should not be in custom state unless we need it.\n at Debug.scala:1365 assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n"); // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96646.14] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_2728 & _T_18859) begin $fatal; // @[Debug.scala 1365:13:freechips.rocketchip.system.TinyConfig.fir@96647.14] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_18869) begin $fwrite(32'h80000002,"Assertion failed: Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\n at Debug.scala:1378 assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n"); // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96671.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_18869) begin $fatal; // @[Debug.scala 1378:12:freechips.rocketchip.system.TinyConfig.fir@96672.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SynchronizerShiftReg_w55_d1( // @[:freechips.rocketchip.system.TinyConfig.fir@96827.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@96828.4] input [54:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@96830.4] output [54:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@96830.4] ); reg [54:0] sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@96835.4] reg [63:0] _RAND_0; assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@96837.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {2{`RANDOM}}; sync_0 = _RAND_0[54:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin sync_0 <= io_d; end endmodule module AsyncQueueSink_1( // @[:freechips.rocketchip.system.TinyConfig.fir@97303.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@97304.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [1:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [8:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output io_deq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input [2:0] io_async_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input [8:0] io_async_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input [3:0] io_async_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input [31:0] io_async_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] output io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] input io_async_safe_source_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@97306.4] ); wire ridx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] wire ridx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] wire ridx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] wire ridx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] wire ridx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] wire widx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97325.4] wire widx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97325.4] wire widx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97325.4] wire widx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97325.4] wire deq_bits_reg_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97336.4] wire [54:0] deq_bits_reg_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97336.4] wire [54:0] deq_bits_reg_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97336.4] wire valid_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] wire valid_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] wire valid_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] wire valid_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] wire valid_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] wire ridx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] wire ridx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] wire ridx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] wire ridx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] wire ridx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@97393.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@97393.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@97393.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@97396.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@97396.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@97396.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@97396.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@97399.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@97399.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@97399.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@97399.4] wire AsyncResetRegVec_w1_i0_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] wire AsyncResetRegVec_w1_i0_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] wire AsyncResetRegVec_w1_i0_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] wire AsyncResetRegVec_w1_i0_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] wire AsyncResetRegVec_w1_i0_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] wire _T; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@97310.4] wire source_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@97308.4 :freechips.rocketchip.system.TinyConfig.fir@97309.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@97414.4] wire _T_1; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@97311.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@97320.4] wire ridx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@97321.4] wire widx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@97330.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@97332.4] wire _T_7; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@97333.4] wire valid; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@97334.4] wire [2:0] deq_bits_nxt_opcode; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [2:0] deq_bits_nxt_param; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [1:0] deq_bits_nxt_size; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire deq_bits_nxt_source; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [8:0] deq_bits_nxt_address; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [3:0] deq_bits_nxt_mask; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [31:0] deq_bits_nxt_data; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire deq_bits_nxt_corrupt; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] wire [45:0] _T_10; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@97342.4] wire [8:0] _T_13; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@97345.4] wire [54:0] _T_16; // @[:freechips.rocketchip.system.TinyConfig.fir@97350.4 :freechips.rocketchip.system.TinyConfig.fir@97352.4] wire valid_reg_1; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@97383.4] AsyncResetRegVec_w1_i0 ridx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97313.4] .clock(ridx_bin_clock), .reset(ridx_bin_reset), .io_d(ridx_bin_io_d), .io_q(ridx_bin_io_q), .io_en(ridx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97325.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q) ); SynchronizerShiftReg_w55_d1 deq_bits_reg ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@97336.4] .clock(deq_bits_reg_clock), .io_d(deq_bits_reg_io_d), .io_q(deq_bits_reg_io_q) ); AsyncResetRegVec_w1_i0 valid_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97377.4] .clock(valid_reg_clock), .reset(valid_reg_reset), .io_d(valid_reg_io_d), .io_q(valid_reg_io_q), .io_en(valid_reg_io_en) ); AsyncResetRegVec_w1_i0 ridx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97386.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q), .io_en(ridx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@97393.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@97396.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@97399.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); AsyncResetRegVec_w1_i0 AsyncResetRegVec_w1_i0 ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@97428.4] .clock(AsyncResetRegVec_w1_i0_clock), .reset(AsyncResetRegVec_w1_i0_reset), .io_d(AsyncResetRegVec_w1_i0_io_d), .io_q(AsyncResetRegVec_w1_i0_io_q), .io_en(AsyncResetRegVec_w1_i0_io_en) ); assign _T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@97310.4] assign source_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@97308.4 :freechips.rocketchip.system.TinyConfig.fir@97309.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@97414.4] assign _T_1 = source_ready == 1'h0; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@97311.4] assign _T_4 = ridx_bin_io_q + _T; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@97320.4] assign ridx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@97321.4] assign widx = widx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@97330.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@97332.4] assign _T_7 = ridx != widx; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@97333.4] assign valid = source_ready & _T_7; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@97334.4] assign deq_bits_nxt_opcode = valid ? io_async_mem_0_opcode : io_deq_bits_opcode; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_param = valid ? 3'h0 : io_deq_bits_param; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_size = valid ? 2'h2 : io_deq_bits_size; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_source = valid ? 1'h0 : io_deq_bits_source; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_address = valid ? io_async_mem_0_address : io_deq_bits_address; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_mask = valid ? io_async_mem_0_mask : io_deq_bits_mask; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_data = valid ? io_async_mem_0_data : io_deq_bits_data; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign deq_bits_nxt_corrupt = valid ? 1'h0 : io_deq_bits_corrupt; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@97335.4] assign _T_10 = {deq_bits_nxt_address,deq_bits_nxt_mask,deq_bits_nxt_data,deq_bits_nxt_corrupt}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@97342.4] assign _T_13 = {deq_bits_nxt_opcode,deq_bits_nxt_param,deq_bits_nxt_size,deq_bits_nxt_source}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@97345.4] assign _T_16 = deq_bits_reg_io_q; // @[:freechips.rocketchip.system.TinyConfig.fir@97350.4 :freechips.rocketchip.system.TinyConfig.fir@97352.4] assign valid_reg_1 = valid_reg_io_q; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@97383.4] assign io_deq_valid = valid_reg_1 & source_ready; // @[AsyncQueue.scala 148:16:freechips.rocketchip.system.TinyConfig.fir@97385.4] assign io_deq_bits_opcode = _T_16[54:52]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97376.4] assign io_deq_bits_param = _T_16[51:49]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97375.4] assign io_deq_bits_size = _T_16[48:47]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97374.4] assign io_deq_bits_source = _T_16[46]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97373.4] assign io_deq_bits_address = _T_16[45:37]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97372.4] assign io_deq_bits_mask = _T_16[36:33]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97371.4] assign io_deq_bits_data = _T_16[32:1]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97370.4] assign io_deq_bits_corrupt = _T_16[0]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@97369.4] assign io_async_ridx = ridx_gray_io_q; // @[AsyncQueue.scala 151:17:freechips.rocketchip.system.TinyConfig.fir@97392.4] assign io_async_safe_ridx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 161:20:freechips.rocketchip.system.TinyConfig.fir@97411.4] assign ridx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97315.4] assign ridx_bin_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97316.4] assign ridx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@97317.4] assign ridx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@97318.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97327.4] assign widx_gray_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97328.4] assign widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@97329.4] assign deq_bits_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97338.4] assign deq_bits_reg_io_d = {_T_13,_T_10}; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@97347.4] assign valid_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97379.4] assign valid_reg_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97380.4] assign valid_reg_io_d = source_ready & _T_7; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@97381.4] assign valid_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@97382.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97388.4] assign ridx_gray_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97389.4] assign ridx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@97390.4] assign ridx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@97391.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97394.4] assign AsyncValidSync_reset = io_async_safe_source_reset_n == 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97395.4 AsyncQueue.scala 157:25:freechips.rocketchip.system.TinyConfig.fir@97405.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97397.4] assign AsyncValidSync_1_reset = io_async_safe_source_reset_n == 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97398.4 AsyncQueue.scala 158:25:freechips.rocketchip.system.TinyConfig.fir@97409.4] assign AsyncValidSync_1_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 162:25:freechips.rocketchip.system.TinyConfig.fir@97412.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97400.4] assign AsyncValidSync_2_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97401.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 163:24:freechips.rocketchip.system.TinyConfig.fir@97413.4] assign AsyncResetRegVec_w1_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@97430.4] assign AsyncResetRegVec_w1_i0_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@97431.4] assign AsyncResetRegVec_w1_i0_io_d = io_async_widx == io_async_ridx; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@97432.4] assign AsyncResetRegVec_w1_i0_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@97433.4] endmodule module AsyncQueueSource_2( // @[:freechips.rocketchip.system.TinyConfig.fir@98020.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@98021.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input [1:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output [2:0] io_async_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output [1:0] io_async_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output io_async_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output [31:0] io_async_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] output io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] input io_async_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@98023.4] ); wire widx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] wire widx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] wire widx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] wire widx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] wire widx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] wire ridx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98043.4] wire ridx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98043.4] wire ridx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98043.4] wire ridx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98043.4] wire ready_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] wire ready_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] wire ready_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] wire ready_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] wire ready_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] wire widx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] wire widx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] wire widx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] wire widx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] wire widx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@98089.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@98089.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@98089.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@98092.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@98092.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@98092.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@98092.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@98095.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@98095.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@98095.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@98095.4] reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@98027.4] reg [31:0] _RAND_0; reg [1:0] mem_0_size; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@98027.4] reg [31:0] _RAND_1; reg mem_0_source; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@98027.4] reg [31:0] _RAND_2; reg [31:0] mem_0_data; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.TinyConfig.fir@98027.4] reg [31:0] _RAND_3; wire _T; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@98028.4] wire sink_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@98025.4 :freechips.rocketchip.system.TinyConfig.fir@98026.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@98110.4] wire _T_1; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@98029.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@98038.4] wire widx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@98039.4] wire ridx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98048.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98050.4] wire _T_7; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@98051.4] wire _T_8; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@98052.4] wire ready_reg_1; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@98071.4] AsyncResetRegVec_w1_i0 widx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98031.4] .clock(widx_bin_clock), .reset(widx_bin_reset), .io_d(widx_bin_io_d), .io_q(widx_bin_io_q), .io_en(widx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98043.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q) ); AsyncResetRegVec_w1_i0 ready_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98065.4] .clock(ready_reg_clock), .reset(ready_reg_reset), .io_d(ready_reg_io_d), .io_q(ready_reg_io_q), .io_en(ready_reg_io_en) ); AsyncResetRegVec_w1_i0 widx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98074.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q), .io_en(widx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.TinyConfig.fir@98089.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@98092.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.TinyConfig.fir@98095.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); assign _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@98028.4] assign sink_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@98025.4 :freechips.rocketchip.system.TinyConfig.fir@98026.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.TinyConfig.fir@98110.4] assign _T_1 = sink_ready == 1'h0; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.TinyConfig.fir@98029.4] assign _T_4 = widx_bin_io_q + _T; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@98038.4] assign widx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@98039.4] assign ridx = ridx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98048.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98050.4] assign _T_7 = ridx ^ 1'h1; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@98051.4] assign _T_8 = widx != _T_7; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.TinyConfig.fir@98052.4] assign ready_reg_1 = ready_reg_io_q; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.TinyConfig.fir@98071.4] assign io_enq_ready = ready_reg_1 & sink_ready; // @[AsyncQueue.scala 85:16:freechips.rocketchip.system.TinyConfig.fir@98073.4] assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@98088.4] assign io_async_mem_0_size = mem_0_size; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@98086.4] assign io_async_mem_0_source = mem_0_source; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@98085.4] assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.TinyConfig.fir@98082.4] assign io_async_widx = widx_gray_io_q; // @[AsyncQueue.scala 88:17:freechips.rocketchip.system.TinyConfig.fir@98080.4] assign io_async_safe_widx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 103:20:freechips.rocketchip.system.TinyConfig.fir@98107.4] assign widx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98033.4] assign widx_bin_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98034.4] assign widx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@98035.4] assign widx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@98036.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98045.4] assign ridx_gray_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98046.4] assign ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@98047.4] assign ready_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98067.4] assign ready_reg_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98068.4] assign ready_reg_io_d = sink_ready & _T_8; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@98069.4] assign ready_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@98070.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98076.4] assign widx_gray_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98077.4] assign widx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@98078.4] assign widx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@98079.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98090.4] assign AsyncValidSync_reset = io_async_safe_sink_reset_n == 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98091.4 AsyncQueue.scala 99:24:freechips.rocketchip.system.TinyConfig.fir@98101.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98093.4] assign AsyncValidSync_1_reset = io_async_safe_sink_reset_n == 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98094.4 AsyncQueue.scala 100:24:freechips.rocketchip.system.TinyConfig.fir@98105.4] assign AsyncValidSync_1_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 104:23:freechips.rocketchip.system.TinyConfig.fir@98108.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98096.4] assign AsyncValidSync_2_reset = 1'h0; // @[:freechips.rocketchip.system.TinyConfig.fir@98097.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 105:22:freechips.rocketchip.system.TinyConfig.fir@98109.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; mem_0_opcode = _RAND_0[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; mem_0_size = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; mem_0_source = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; mem_0_data = _RAND_3[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (_T) begin mem_0_opcode <= io_enq_bits_opcode; end if (_T) begin mem_0_size <= io_enq_bits_size; end if (_T) begin mem_0_source <= io_enq_bits_source; end if (_T) begin mem_0_data <= io_enq_bits_data; end end endmodule module TLAsyncCrossingSink( // @[:freechips.rocketchip.system.TinyConfig.fir@98115.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@98116.4] input [2:0] auto_in_a_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [8:0] auto_in_a_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [3:0] auto_in_a_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [31:0] auto_in_a_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_in_a_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_a_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_in_a_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_a_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_a_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [2:0] auto_in_d_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [1:0] auto_in_d_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_in_d_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [31:0] auto_in_d_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_d_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_in_d_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_d_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_in_d_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_in_d_safe_sink_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [8:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@98118.4] ); wire AsyncQueueSink_clock; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_deq_ready; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_deq_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [2:0] AsyncQueueSink_io_deq_bits_opcode; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [2:0] AsyncQueueSink_io_deq_bits_param; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [1:0] AsyncQueueSink_io_deq_bits_size; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_deq_bits_source; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [8:0] AsyncQueueSink_io_deq_bits_address; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [3:0] AsyncQueueSink_io_deq_bits_mask; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [31:0] AsyncQueueSink_io_deq_bits_data; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_deq_bits_corrupt; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [2:0] AsyncQueueSink_io_async_mem_0_opcode; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [8:0] AsyncQueueSink_io_async_mem_0_address; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [3:0] AsyncQueueSink_io_async_mem_0_mask; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire [31:0] AsyncQueueSink_io_async_mem_0_data; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_async_ridx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_async_widx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_async_safe_widx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] wire AsyncQueueSource_clock; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_enq_ready; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_enq_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [2:0] AsyncQueueSource_io_enq_bits_opcode; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [1:0] AsyncQueueSource_io_enq_bits_size; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_enq_bits_source; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [31:0] AsyncQueueSource_io_enq_bits_data; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [2:0] AsyncQueueSource_io_async_mem_0_opcode; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [1:0] AsyncQueueSource_io_async_mem_0_size; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_mem_0_source; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire [31:0] AsyncQueueSource_io_async_mem_0_data; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_ridx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_widx; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_safe_ridx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_safe_widx_valid; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] wire AsyncQueueSource_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] AsyncQueueSink_1 AsyncQueueSink ( // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@98129.4] .clock(AsyncQueueSink_clock), .io_deq_ready(AsyncQueueSink_io_deq_ready), .io_deq_valid(AsyncQueueSink_io_deq_valid), .io_deq_bits_opcode(AsyncQueueSink_io_deq_bits_opcode), .io_deq_bits_param(AsyncQueueSink_io_deq_bits_param), .io_deq_bits_size(AsyncQueueSink_io_deq_bits_size), .io_deq_bits_source(AsyncQueueSink_io_deq_bits_source), .io_deq_bits_address(AsyncQueueSink_io_deq_bits_address), .io_deq_bits_mask(AsyncQueueSink_io_deq_bits_mask), .io_deq_bits_data(AsyncQueueSink_io_deq_bits_data), .io_deq_bits_corrupt(AsyncQueueSink_io_deq_bits_corrupt), .io_async_mem_0_opcode(AsyncQueueSink_io_async_mem_0_opcode), .io_async_mem_0_address(AsyncQueueSink_io_async_mem_0_address), .io_async_mem_0_mask(AsyncQueueSink_io_async_mem_0_mask), .io_async_mem_0_data(AsyncQueueSink_io_async_mem_0_data), .io_async_ridx(AsyncQueueSink_io_async_ridx), .io_async_widx(AsyncQueueSink_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSink_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSink_io_async_safe_widx_valid), .io_async_safe_source_reset_n(AsyncQueueSink_io_async_safe_source_reset_n) ); AsyncQueueSource_2 AsyncQueueSource ( // @[AsyncQueue.scala 192:24:freechips.rocketchip.system.TinyConfig.fir@98140.4] .clock(AsyncQueueSource_clock), .io_enq_ready(AsyncQueueSource_io_enq_ready), .io_enq_valid(AsyncQueueSource_io_enq_valid), .io_enq_bits_opcode(AsyncQueueSource_io_enq_bits_opcode), .io_enq_bits_size(AsyncQueueSource_io_enq_bits_size), .io_enq_bits_source(AsyncQueueSource_io_enq_bits_source), .io_enq_bits_data(AsyncQueueSource_io_enq_bits_data), .io_async_mem_0_opcode(AsyncQueueSource_io_async_mem_0_opcode), .io_async_mem_0_size(AsyncQueueSource_io_async_mem_0_size), .io_async_mem_0_source(AsyncQueueSource_io_async_mem_0_source), .io_async_mem_0_data(AsyncQueueSource_io_async_mem_0_data), .io_async_ridx(AsyncQueueSource_io_async_ridx), .io_async_widx(AsyncQueueSource_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSource_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSource_io_async_safe_widx_valid), .io_async_safe_sink_reset_n(AsyncQueueSource_io_async_safe_sink_reset_n) ); assign auto_in_a_ridx = AsyncQueueSink_io_async_ridx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_a_safe_ridx_valid = AsyncQueueSink_io_async_safe_ridx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_mem_0_opcode = AsyncQueueSource_io_async_mem_0_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_mem_0_size = AsyncQueueSource_io_async_mem_0_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_mem_0_source = AsyncQueueSource_io_async_mem_0_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_mem_0_data = AsyncQueueSource_io_async_mem_0_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_widx = AsyncQueueSource_io_async_widx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_in_d_safe_widx_valid = AsyncQueueSource_io_async_safe_widx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@98128.4] assign auto_out_a_valid = AsyncQueueSink_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_opcode = AsyncQueueSink_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_param = AsyncQueueSink_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_size = AsyncQueueSink_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_source = AsyncQueueSink_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_address = AsyncQueueSink_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_mask = AsyncQueueSink_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_data = AsyncQueueSink_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_a_bits_corrupt = AsyncQueueSink_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign auto_out_d_ready = AsyncQueueSource_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@98127.4] assign AsyncQueueSink_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98130.4] assign AsyncQueueSink_io_deq_ready = auto_out_a_ready; // @[AsyncCrossing.scala 57:13:freechips.rocketchip.system.TinyConfig.fir@98139.4] assign AsyncQueueSink_io_async_mem_0_opcode = auto_in_a_mem_0_opcode; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98138.4] assign AsyncQueueSink_io_async_mem_0_address = auto_in_a_mem_0_address; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98138.4] assign AsyncQueueSink_io_async_mem_0_mask = auto_in_a_mem_0_mask; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98138.4] assign AsyncQueueSink_io_async_mem_0_data = auto_in_a_mem_0_data; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98138.4] assign AsyncQueueSink_io_async_widx = auto_in_a_widx; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98136.4] assign AsyncQueueSink_io_async_safe_widx_valid = auto_in_a_safe_widx_valid; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98134.4] assign AsyncQueueSink_io_async_safe_source_reset_n = auto_in_a_safe_source_reset_n; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@98133.4] assign AsyncQueueSource_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98141.4] assign AsyncQueueSource_io_enq_valid = auto_out_d_valid; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@98144.4] assign AsyncQueueSource_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@98143.4] assign AsyncQueueSource_io_enq_bits_size = auto_out_d_bits_size; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@98143.4] assign AsyncQueueSource_io_enq_bits_source = auto_out_d_bits_source; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@98143.4] assign AsyncQueueSource_io_enq_bits_data = auto_out_d_bits_data; // @[AsyncQueue.scala 193:19:freechips.rocketchip.system.TinyConfig.fir@98143.4] assign AsyncQueueSource_io_async_ridx = auto_in_d_ridx; // @[AsyncCrossing.scala 58:12:freechips.rocketchip.system.TinyConfig.fir@98146.4] assign AsyncQueueSource_io_async_safe_ridx_valid = auto_in_d_safe_ridx_valid; // @[AsyncCrossing.scala 58:12:freechips.rocketchip.system.TinyConfig.fir@98146.4] assign AsyncQueueSource_io_async_safe_sink_reset_n = auto_in_d_safe_sink_reset_n; // @[AsyncCrossing.scala 58:12:freechips.rocketchip.system.TinyConfig.fir@98146.4] endmodule module ResetCatchAndSync_d3( // @[:freechips.rocketchip.system.TinyConfig.fir@98297.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@98298.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@98299.4] output io_sync_reset // @[:freechips.rocketchip.system.TinyConfig.fir@98300.4] ); wire AsyncResetSynchronizerShiftReg_w1_d3_i0_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98306.4] wire AsyncResetSynchronizerShiftReg_w1_d3_i0_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98306.4] wire AsyncResetSynchronizerShiftReg_w1_d3_i0_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98306.4] wire AsyncResetSynchronizerShiftReg_w1_d3_i0_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98306.4] wire _T; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98311.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98313.4] AsyncResetSynchronizerShiftReg_w1_d3_i0 AsyncResetSynchronizerShiftReg_w1_d3_i0 ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98306.4] .clock(AsyncResetSynchronizerShiftReg_w1_d3_i0_clock), .reset(AsyncResetSynchronizerShiftReg_w1_d3_i0_reset), .io_d(AsyncResetSynchronizerShiftReg_w1_d3_i0_io_d), .io_q(AsyncResetSynchronizerShiftReg_w1_d3_i0_io_q) ); assign _T = AsyncResetSynchronizerShiftReg_w1_d3_i0_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98311.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98313.4] assign io_sync_reset = ~ _T; // @[ResetCatchAndSync.scala 28:19:freechips.rocketchip.system.TinyConfig.fir@98316.4] assign AsyncResetSynchronizerShiftReg_w1_d3_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98308.4] assign AsyncResetSynchronizerShiftReg_w1_d3_i0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@98309.4] assign AsyncResetSynchronizerShiftReg_w1_d3_i0_io_d = 1'h1; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@98310.4] endmodule module SynchronizerShiftReg_w14_d1( // @[:freechips.rocketchip.system.TinyConfig.fir@98478.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@98479.4] input [13:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@98481.4] output [13:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@98481.4] ); reg [13:0] sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@98486.4] reg [31:0] _RAND_0; assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@98488.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; sync_0 = _RAND_0[13:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin sync_0 <= io_d; end endmodule module AsyncQueueSink_2( // @[:freechips.rocketchip.system.TinyConfig.fir@98954.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@98955.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@98956.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_deq_bits_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output [9:0] io_deq_bits_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_deq_bits_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_deq_bits_hasel, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_deq_bits_hamask_0, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input io_async_mem_0_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input [9:0] io_async_mem_0_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input io_async_mem_0_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_async_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input io_async_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input io_async_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] input io_async_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] output io_async_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@98957.4] ); wire ridx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] wire ridx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] wire ridx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] wire ridx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] wire ridx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] wire widx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98976.4] wire widx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98976.4] wire widx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98976.4] wire widx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98976.4] wire deq_bits_reg_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98987.4] wire [13:0] deq_bits_reg_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98987.4] wire [13:0] deq_bits_reg_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98987.4] wire valid_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] wire valid_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] wire valid_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] wire valid_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] wire valid_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] wire ridx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] wire ridx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] wire ridx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] wire ridx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] wire ridx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] wire AsyncValidSync_clock; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@99032.4] wire AsyncValidSync_reset; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@99032.4] wire AsyncValidSync_io_out; // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@99032.4] wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@99035.4] wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@99035.4] wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@99035.4] wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@99035.4] wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@99038.4] wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@99038.4] wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@99038.4] wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@99038.4] wire AsyncResetRegVec_w1_i0_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] wire AsyncResetRegVec_w1_i0_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] wire AsyncResetRegVec_w1_i0_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] wire AsyncResetRegVec_w1_i0_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] wire AsyncResetRegVec_w1_i0_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] wire source_ready; // @[:freechips.rocketchip.system.TinyConfig.fir@98959.4 :freechips.rocketchip.system.TinyConfig.fir@98960.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@99053.4] wire _T_1; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@98962.4] wire _T_4; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@98971.4] wire ridx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@98972.4] wire widx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98981.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98983.4] wire _T_7; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@98984.4] wire valid; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@98985.4] wire deq_bits_nxt_resumereq; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] wire [9:0] deq_bits_nxt_hartsel; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] wire deq_bits_nxt_ackhavereset; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] wire deq_bits_nxt_hasel; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] wire deq_bits_nxt_hamask_0; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] wire [1:0] _T_8; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@98991.4] wire [11:0] _T_10; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@98993.4] wire [13:0] _T_13; // @[:freechips.rocketchip.system.TinyConfig.fir@98998.4 :freechips.rocketchip.system.TinyConfig.fir@99000.4] wire valid_reg_1; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@99022.4] wire _T_21; // @[AsyncQueue.scala 157:44:freechips.rocketchip.system.TinyConfig.fir@99042.4] AsyncResetRegVec_w1_i0 ridx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@98964.4] .clock(ridx_bin_clock), .reset(ridx_bin_reset), .io_d(ridx_bin_io_d), .io_q(ridx_bin_io_q), .io_en(ridx_bin_io_en) ); AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98976.4] .clock(widx_gray_clock), .reset(widx_gray_reset), .io_d(widx_gray_io_d), .io_q(widx_gray_io_q) ); SynchronizerShiftReg_w14_d1 deq_bits_reg ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@98987.4] .clock(deq_bits_reg_clock), .io_d(deq_bits_reg_io_d), .io_q(deq_bits_reg_io_q) ); AsyncResetRegVec_w1_i0 valid_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99016.4] .clock(valid_reg_clock), .reset(valid_reg_reset), .io_d(valid_reg_io_d), .io_q(valid_reg_io_q), .io_en(valid_reg_io_en) ); AsyncResetRegVec_w1_i0 ridx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99025.4] .clock(ridx_gray_clock), .reset(ridx_gray_reset), .io_d(ridx_gray_io_d), .io_q(ridx_gray_io_q), .io_en(ridx_gray_io_en) ); AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 154:31:freechips.rocketchip.system.TinyConfig.fir@99032.4] .clock(AsyncValidSync_clock), .reset(AsyncValidSync_reset), .io_out(AsyncValidSync_io_out) ); AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@99035.4] .clock(AsyncValidSync_1_clock), .reset(AsyncValidSync_1_reset), .io_in(AsyncValidSync_1_io_in), .io_out(AsyncValidSync_1_io_out) ); AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@99038.4] .clock(AsyncValidSync_2_clock), .reset(AsyncValidSync_2_reset), .io_in(AsyncValidSync_2_io_in), .io_out(AsyncValidSync_2_io_out) ); AsyncResetRegVec_w1_i0 AsyncResetRegVec_w1_i0 ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@99067.4] .clock(AsyncResetRegVec_w1_i0_clock), .reset(AsyncResetRegVec_w1_i0_reset), .io_d(AsyncResetRegVec_w1_i0_io_d), .io_q(AsyncResetRegVec_w1_i0_io_q), .io_en(AsyncResetRegVec_w1_i0_io_en) ); assign source_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.TinyConfig.fir@98959.4 :freechips.rocketchip.system.TinyConfig.fir@98960.4 AsyncQueue.scala 164:18:freechips.rocketchip.system.TinyConfig.fir@99053.4] assign _T_1 = source_ready == 1'h0; // @[AsyncQueue.scala 130:49:freechips.rocketchip.system.TinyConfig.fir@98962.4] assign _T_4 = ridx_bin_io_q + io_deq_valid; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.TinyConfig.fir@98971.4] assign ridx = _T_1 ? 1'h0 : _T_4; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.TinyConfig.fir@98972.4] assign widx = widx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98981.4 ShiftReg.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@98983.4] assign _T_7 = ridx != widx; // @[AsyncQueue.scala 132:36:freechips.rocketchip.system.TinyConfig.fir@98984.4] assign valid = source_ready & _T_7; // @[AsyncQueue.scala 132:28:freechips.rocketchip.system.TinyConfig.fir@98985.4] assign deq_bits_nxt_resumereq = valid ? io_async_mem_0_resumereq : io_deq_bits_resumereq; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] assign deq_bits_nxt_hartsel = valid ? io_async_mem_0_hartsel : io_deq_bits_hartsel; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] assign deq_bits_nxt_ackhavereset = valid ? io_async_mem_0_ackhavereset : io_deq_bits_ackhavereset; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] assign deq_bits_nxt_hasel = valid ? 1'h0 : io_deq_bits_hasel; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] assign deq_bits_nxt_hamask_0 = valid ? 1'h0 : io_deq_bits_hamask_0; // @[AsyncQueue.scala 144:25:freechips.rocketchip.system.TinyConfig.fir@98986.4] assign _T_8 = {deq_bits_nxt_hasel,deq_bits_nxt_hamask_0}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@98991.4] assign _T_10 = {deq_bits_nxt_resumereq,deq_bits_nxt_hartsel,deq_bits_nxt_ackhavereset}; // @[ShiftReg.scala 49:22:freechips.rocketchip.system.TinyConfig.fir@98993.4] assign _T_13 = deq_bits_reg_io_q; // @[:freechips.rocketchip.system.TinyConfig.fir@98998.4 :freechips.rocketchip.system.TinyConfig.fir@99000.4] assign valid_reg_1 = valid_reg_io_q; // @[AsyncQueue.scala 147:59:freechips.rocketchip.system.TinyConfig.fir@99022.4] assign _T_21 = io_async_safe_source_reset_n == 1'h0; // @[AsyncQueue.scala 157:44:freechips.rocketchip.system.TinyConfig.fir@99042.4] assign io_deq_valid = valid_reg_1 & source_ready; // @[AsyncQueue.scala 148:16:freechips.rocketchip.system.TinyConfig.fir@99024.4] assign io_deq_bits_resumereq = _T_13[13]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@99015.4] assign io_deq_bits_hartsel = _T_13[12:3]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@99014.4] assign io_deq_bits_ackhavereset = _T_13[2]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@99013.4] assign io_deq_bits_hasel = _T_13[1]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@99012.4] assign io_deq_bits_hamask_0 = _T_13[0]; // @[AsyncQueue.scala 145:15:freechips.rocketchip.system.TinyConfig.fir@99011.4] assign io_async_ridx = ridx_gray_io_q; // @[AsyncQueue.scala 151:17:freechips.rocketchip.system.TinyConfig.fir@99031.4] assign io_async_safe_ridx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 161:20:freechips.rocketchip.system.TinyConfig.fir@99050.4] assign io_async_safe_sink_reset_n = reset == 1'h0; // @[AsyncQueue.scala 165:22:freechips.rocketchip.system.TinyConfig.fir@99056.4] assign ridx_bin_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98966.4] assign ridx_bin_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@98967.4] assign ridx_bin_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@98968.4] assign ridx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@98969.4] assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98978.4] assign widx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@98979.4] assign widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@98980.4] assign deq_bits_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@98989.4] assign deq_bits_reg_io_d = {_T_10,_T_8}; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@98995.4] assign valid_reg_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99018.4] assign valid_reg_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99019.4] assign valid_reg_io_d = source_ready & _T_7; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@99020.4] assign valid_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@99021.4] assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99027.4] assign ridx_gray_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99028.4] assign ridx_gray_io_d = _T_1 ? 1'h0 : _T_4; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@99029.4] assign ridx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@99030.4] assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99033.4] assign AsyncValidSync_reset = reset | _T_21; // @[:freechips.rocketchip.system.TinyConfig.fir@99034.4 AsyncQueue.scala 157:25:freechips.rocketchip.system.TinyConfig.fir@99044.4] assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99036.4] assign AsyncValidSync_1_reset = reset | _T_21; // @[:freechips.rocketchip.system.TinyConfig.fir@99037.4 AsyncQueue.scala 158:25:freechips.rocketchip.system.TinyConfig.fir@99048.4] assign AsyncValidSync_1_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 162:25:freechips.rocketchip.system.TinyConfig.fir@99051.4] assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99039.4] assign AsyncValidSync_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99040.4] assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 163:24:freechips.rocketchip.system.TinyConfig.fir@99052.4] assign AsyncResetRegVec_w1_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99069.4] assign AsyncResetRegVec_w1_i0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99070.4] assign AsyncResetRegVec_w1_i0_io_d = io_async_widx == io_async_ridx; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@99071.4] assign AsyncResetRegVec_w1_i0_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@99072.4] endmodule module TLDebugModuleInnerAsync( // @[:freechips.rocketchip.system.TinyConfig.fir@99074.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@99075.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@99076.4] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [3:0] auto_dmiXing_in_a_mem_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmiXing_in_a_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_a_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmiXing_in_a_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_a_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_a_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmiXing_in_d_mem_0_source, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_d_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmiXing_in_d_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_d_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmiXing_in_d_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmiXing_in_d_safe_sink_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmInner_tl_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmInner_tl_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [9:0] auto_dmInner_tl_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [3:0] auto_dmInner_tl_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input [31:0] auto_dmInner_tl_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmInner_tl_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input auto_dmInner_tl_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output auto_dmInner_tl_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [9:0] auto_dmInner_tl_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] output [31:0] auto_dmInner_tl_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99077.4] input io_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input io_innerCtrl_mem_0_resumereq, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input [9:0] io_innerCtrl_mem_0_hartsel, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input io_innerCtrl_mem_0_ackhavereset, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] output io_innerCtrl_ridx, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input io_innerCtrl_widx, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] output io_innerCtrl_safe_ridx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input io_innerCtrl_safe_widx_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] input io_innerCtrl_safe_source_reset_n, // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] output io_innerCtrl_safe_sink_reset_n // @[:freechips.rocketchip.system.TinyConfig.fir@99078.4] ); wire dmInner_clock; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_reset; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_tl_in_a_ready; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_tl_in_a_valid; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_tl_in_a_bits_opcode; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_tl_in_a_bits_param; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [1:0] dmInner_auto_tl_in_a_bits_size; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [9:0] dmInner_auto_tl_in_a_bits_source; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [11:0] dmInner_auto_tl_in_a_bits_address; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [3:0] dmInner_auto_tl_in_a_bits_mask; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [31:0] dmInner_auto_tl_in_a_bits_data; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_tl_in_a_bits_corrupt; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_tl_in_d_ready; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_tl_in_d_valid; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_tl_in_d_bits_opcode; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [1:0] dmInner_auto_tl_in_d_bits_size; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [9:0] dmInner_auto_tl_in_d_bits_source; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [31:0] dmInner_auto_tl_in_d_bits_data; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_a_ready; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_a_valid; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_dmi_in_a_bits_opcode; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_dmi_in_a_bits_param; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [1:0] dmInner_auto_dmi_in_a_bits_size; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_a_bits_source; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [8:0] dmInner_auto_dmi_in_a_bits_address; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [3:0] dmInner_auto_dmi_in_a_bits_mask; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [31:0] dmInner_auto_dmi_in_a_bits_data; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_a_bits_corrupt; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_d_ready; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_d_valid; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [2:0] dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [1:0] dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [31:0] dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_io_dmactive; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_io_innerCtrl_ready; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_io_innerCtrl_valid; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_io_innerCtrl_bits_resumereq; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire [9:0] dmInner_io_innerCtrl_bits_hartsel; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmInner_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] wire dmiXing_clock; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [2:0] dmiXing_auto_in_a_mem_0_opcode; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [8:0] dmiXing_auto_in_a_mem_0_address; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [3:0] dmiXing_auto_in_a_mem_0_mask; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [31:0] dmiXing_auto_in_a_mem_0_data; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_a_ridx; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_a_widx; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_a_safe_ridx_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_a_safe_widx_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_a_safe_source_reset_n; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [2:0] dmiXing_auto_in_d_mem_0_opcode; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [1:0] dmiXing_auto_in_d_mem_0_size; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_mem_0_source; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [31:0] dmiXing_auto_in_d_mem_0_data; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_ridx; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_widx; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_safe_ridx_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_safe_widx_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_in_d_safe_sink_reset_n; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_a_ready; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_a_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [2:0] dmiXing_auto_out_a_bits_opcode; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [2:0] dmiXing_auto_out_a_bits_param; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [1:0] dmiXing_auto_out_a_bits_size; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_a_bits_source; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [8:0] dmiXing_auto_out_a_bits_address; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [3:0] dmiXing_auto_out_a_bits_mask; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [31:0] dmiXing_auto_out_a_bits_data; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_d_ready; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_d_valid; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [2:0] dmiXing_auto_out_d_bits_opcode; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [1:0] dmiXing_auto_out_d_bits_size; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmiXing_auto_out_d_bits_source; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire [31:0] dmiXing_auto_out_d_bits_data; // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] wire dmactiveSync_clock; // @[ResetCatchAndSync.scala 39:28:freechips.rocketchip.system.TinyConfig.fir@99102.4] wire dmactiveSync_reset; // @[ResetCatchAndSync.scala 39:28:freechips.rocketchip.system.TinyConfig.fir@99102.4] wire dmactiveSync_io_sync_reset; // @[ResetCatchAndSync.scala 39:28:freechips.rocketchip.system.TinyConfig.fir@99102.4] wire debug_clock_gate_in; // @[ClockGate.scala 23:20:freechips.rocketchip.system.TinyConfig.fir@99112.4] wire debug_clock_gate_en; // @[ClockGate.scala 23:20:freechips.rocketchip.system.TinyConfig.fir@99112.4] wire debug_clock_gate_out; // @[ClockGate.scala 23:20:freechips.rocketchip.system.TinyConfig.fir@99112.4] wire AsyncQueueSink_clock; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_reset; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_deq_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_deq_bits_resumereq; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire [9:0] AsyncQueueSink_io_deq_bits_hartsel; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_deq_bits_hasel; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_deq_bits_hamask_0; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_mem_0_resumereq; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire [9:0] AsyncQueueSink_io_async_mem_0_hartsel; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_ridx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_widx; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_safe_widx_valid; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire AsyncQueueSink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] wire dmactive_synced; // @[Debug.scala 1415:27:freechips.rocketchip.system.TinyConfig.fir@99107.4] reg clock_en; // @[Debug.scala 1419:27:freechips.rocketchip.system.TinyConfig.fir@99110.4] reg [31:0] _RAND_0; TLDebugModuleInner dmInner ( // @[Debug.scala 1389:27:freechips.rocketchip.system.TinyConfig.fir@99084.4] .clock(dmInner_clock), .reset(dmInner_reset), .auto_tl_in_a_ready(dmInner_auto_tl_in_a_ready), .auto_tl_in_a_valid(dmInner_auto_tl_in_a_valid), .auto_tl_in_a_bits_opcode(dmInner_auto_tl_in_a_bits_opcode), .auto_tl_in_a_bits_param(dmInner_auto_tl_in_a_bits_param), .auto_tl_in_a_bits_size(dmInner_auto_tl_in_a_bits_size), .auto_tl_in_a_bits_source(dmInner_auto_tl_in_a_bits_source), .auto_tl_in_a_bits_address(dmInner_auto_tl_in_a_bits_address), .auto_tl_in_a_bits_mask(dmInner_auto_tl_in_a_bits_mask), .auto_tl_in_a_bits_data(dmInner_auto_tl_in_a_bits_data), .auto_tl_in_a_bits_corrupt(dmInner_auto_tl_in_a_bits_corrupt), .auto_tl_in_d_ready(dmInner_auto_tl_in_d_ready), .auto_tl_in_d_valid(dmInner_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode(dmInner_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size(dmInner_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source(dmInner_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data(dmInner_auto_tl_in_d_bits_data), .auto_dmi_in_a_ready(dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid(dmInner_auto_dmi_in_a_valid), .auto_dmi_in_a_bits_opcode(dmInner_auto_dmi_in_a_bits_opcode), .auto_dmi_in_a_bits_param(dmInner_auto_dmi_in_a_bits_param), .auto_dmi_in_a_bits_size(dmInner_auto_dmi_in_a_bits_size), .auto_dmi_in_a_bits_source(dmInner_auto_dmi_in_a_bits_source), .auto_dmi_in_a_bits_address(dmInner_auto_dmi_in_a_bits_address), .auto_dmi_in_a_bits_mask(dmInner_auto_dmi_in_a_bits_mask), .auto_dmi_in_a_bits_data(dmInner_auto_dmi_in_a_bits_data), .auto_dmi_in_a_bits_corrupt(dmInner_auto_dmi_in_a_bits_corrupt), .auto_dmi_in_d_ready(dmInner_auto_dmi_in_d_ready), .auto_dmi_in_d_valid(dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode(dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size(dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source(dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data(dmInner_auto_dmi_in_d_bits_data), .io_dmactive(dmInner_io_dmactive), .io_innerCtrl_ready(dmInner_io_innerCtrl_ready), .io_innerCtrl_valid(dmInner_io_innerCtrl_valid), .io_innerCtrl_bits_resumereq(dmInner_io_innerCtrl_bits_resumereq), .io_innerCtrl_bits_hartsel(dmInner_io_innerCtrl_bits_hartsel), .io_innerCtrl_bits_ackhavereset(dmInner_io_innerCtrl_bits_ackhavereset) ); TLAsyncCrossingSink dmiXing ( // @[Debug.scala 1390:27:freechips.rocketchip.system.TinyConfig.fir@99091.4] .clock(dmiXing_clock), .auto_in_a_mem_0_opcode(dmiXing_auto_in_a_mem_0_opcode), .auto_in_a_mem_0_address(dmiXing_auto_in_a_mem_0_address), .auto_in_a_mem_0_mask(dmiXing_auto_in_a_mem_0_mask), .auto_in_a_mem_0_data(dmiXing_auto_in_a_mem_0_data), .auto_in_a_ridx(dmiXing_auto_in_a_ridx), .auto_in_a_widx(dmiXing_auto_in_a_widx), .auto_in_a_safe_ridx_valid(dmiXing_auto_in_a_safe_ridx_valid), .auto_in_a_safe_widx_valid(dmiXing_auto_in_a_safe_widx_valid), .auto_in_a_safe_source_reset_n(dmiXing_auto_in_a_safe_source_reset_n), .auto_in_d_mem_0_opcode(dmiXing_auto_in_d_mem_0_opcode), .auto_in_d_mem_0_size(dmiXing_auto_in_d_mem_0_size), .auto_in_d_mem_0_source(dmiXing_auto_in_d_mem_0_source), .auto_in_d_mem_0_data(dmiXing_auto_in_d_mem_0_data), .auto_in_d_ridx(dmiXing_auto_in_d_ridx), .auto_in_d_widx(dmiXing_auto_in_d_widx), .auto_in_d_safe_ridx_valid(dmiXing_auto_in_d_safe_ridx_valid), .auto_in_d_safe_widx_valid(dmiXing_auto_in_d_safe_widx_valid), .auto_in_d_safe_sink_reset_n(dmiXing_auto_in_d_safe_sink_reset_n), .auto_out_a_ready(dmiXing_auto_out_a_ready), .auto_out_a_valid(dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode(dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param(dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size(dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source(dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address(dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask(dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data(dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt(dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready(dmiXing_auto_out_d_ready), .auto_out_d_valid(dmiXing_auto_out_d_valid), .auto_out_d_bits_opcode(dmiXing_auto_out_d_bits_opcode), .auto_out_d_bits_size(dmiXing_auto_out_d_bits_size), .auto_out_d_bits_source(dmiXing_auto_out_d_bits_source), .auto_out_d_bits_data(dmiXing_auto_out_d_bits_data) ); ResetCatchAndSync_d3 dmactiveSync ( // @[ResetCatchAndSync.scala 39:28:freechips.rocketchip.system.TinyConfig.fir@99102.4] .clock(dmactiveSync_clock), .reset(dmactiveSync_reset), .io_sync_reset(dmactiveSync_io_sync_reset) ); EICG_wrapper debug_clock_gate ( // @[ClockGate.scala 23:20:freechips.rocketchip.system.TinyConfig.fir@99112.4] .in(debug_clock_gate_in), .en(debug_clock_gate_en), .out(debug_clock_gate_out) ); AsyncQueueSink_2 AsyncQueueSink ( // @[AsyncQueue.scala 183:22:freechips.rocketchip.system.TinyConfig.fir@99121.4] .clock(AsyncQueueSink_clock), .reset(AsyncQueueSink_reset), .io_deq_valid(AsyncQueueSink_io_deq_valid), .io_deq_bits_resumereq(AsyncQueueSink_io_deq_bits_resumereq), .io_deq_bits_hartsel(AsyncQueueSink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset(AsyncQueueSink_io_deq_bits_ackhavereset), .io_deq_bits_hasel(AsyncQueueSink_io_deq_bits_hasel), .io_deq_bits_hamask_0(AsyncQueueSink_io_deq_bits_hamask_0), .io_async_mem_0_resumereq(AsyncQueueSink_io_async_mem_0_resumereq), .io_async_mem_0_hartsel(AsyncQueueSink_io_async_mem_0_hartsel), .io_async_mem_0_ackhavereset(AsyncQueueSink_io_async_mem_0_ackhavereset), .io_async_ridx(AsyncQueueSink_io_async_ridx), .io_async_widx(AsyncQueueSink_io_async_widx), .io_async_safe_ridx_valid(AsyncQueueSink_io_async_safe_ridx_valid), .io_async_safe_widx_valid(AsyncQueueSink_io_async_safe_widx_valid), .io_async_safe_source_reset_n(AsyncQueueSink_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n(AsyncQueueSink_io_async_safe_sink_reset_n) ); assign dmactive_synced = ~ dmactiveSync_io_sync_reset; // @[Debug.scala 1415:27:freechips.rocketchip.system.TinyConfig.fir@99107.4] assign auto_dmiXing_in_a_ridx = dmiXing_auto_in_a_ridx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_a_safe_ridx_valid = dmiXing_auto_in_a_safe_ridx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_mem_0_opcode = dmiXing_auto_in_d_mem_0_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_mem_0_size = dmiXing_auto_in_d_mem_0_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_mem_0_source = dmiXing_auto_in_d_mem_0_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_mem_0_data = dmiXing_auto_in_d_mem_0_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_widx = dmiXing_auto_in_d_widx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmiXing_in_d_safe_widx_valid = dmiXing_auto_in_d_safe_widx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign auto_dmInner_tl_in_a_ready = dmInner_auto_tl_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign auto_dmInner_tl_in_d_valid = dmInner_auto_tl_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign auto_dmInner_tl_in_d_bits_opcode = dmInner_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign auto_dmInner_tl_in_d_bits_size = dmInner_auto_tl_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign auto_dmInner_tl_in_d_bits_source = dmInner_auto_tl_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign auto_dmInner_tl_in_d_bits_data = dmInner_auto_tl_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign io_innerCtrl_ridx = AsyncQueueSink_io_async_ridx; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99129.4] assign io_innerCtrl_safe_ridx_valid = AsyncQueueSink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99127.4] assign io_innerCtrl_safe_sink_reset_n = AsyncQueueSink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99124.4] assign dmInner_clock = debug_clock_gate_out; // @[:freechips.rocketchip.system.TinyConfig.fir@99089.4 Debug.scala 1427:28:freechips.rocketchip.system.TinyConfig.fir@99118.4] assign dmInner_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99090.4] assign dmInner_auto_tl_in_a_valid = auto_dmInner_tl_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_opcode = auto_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_param = auto_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_size = auto_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_source = auto_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_address = auto_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_mask = auto_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_data = auto_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_a_bits_corrupt = auto_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_tl_in_d_ready = auto_dmInner_tl_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99098.4] assign dmInner_auto_dmi_in_a_valid = dmiXing_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_opcode = dmiXing_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_param = dmiXing_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_size = dmiXing_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_source = dmiXing_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_address = dmiXing_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_mask = dmiXing_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_data = dmiXing_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_a_bits_corrupt = dmiXing_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_auto_dmi_in_d_ready = dmiXing_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmInner_io_dmactive = ~ dmactiveSync_io_sync_reset; // @[Debug.scala 1428:34:freechips.rocketchip.system.TinyConfig.fir@99119.4] assign dmInner_io_innerCtrl_valid = AsyncQueueSink_io_deq_valid; // @[Debug.scala 1430:37:freechips.rocketchip.system.TinyConfig.fir@99131.4] assign dmInner_io_innerCtrl_bits_resumereq = AsyncQueueSink_io_deq_bits_resumereq; // @[Debug.scala 1430:37:freechips.rocketchip.system.TinyConfig.fir@99131.4] assign dmInner_io_innerCtrl_bits_hartsel = AsyncQueueSink_io_deq_bits_hartsel; // @[Debug.scala 1430:37:freechips.rocketchip.system.TinyConfig.fir@99131.4] assign dmInner_io_innerCtrl_bits_ackhavereset = AsyncQueueSink_io_deq_bits_ackhavereset; // @[Debug.scala 1430:37:freechips.rocketchip.system.TinyConfig.fir@99131.4] assign dmiXing_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99095.4] assign dmiXing_auto_in_a_mem_0_opcode = auto_dmiXing_in_a_mem_0_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_mem_0_address = auto_dmiXing_in_a_mem_0_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_mem_0_mask = auto_dmiXing_in_a_mem_0_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_mem_0_data = auto_dmiXing_in_a_mem_0_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_widx = auto_dmiXing_in_a_widx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_safe_widx_valid = auto_dmiXing_in_a_safe_widx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_a_safe_source_reset_n = auto_dmiXing_in_a_safe_source_reset_n; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_d_ridx = auto_dmiXing_in_d_ridx; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_d_safe_ridx_valid = auto_dmiXing_in_d_safe_ridx_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_in_d_safe_sink_reset_n = auto_dmiXing_in_d_safe_sink_reset_n; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99100.4] assign dmiXing_auto_out_a_ready = dmInner_auto_dmi_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmiXing_auto_out_d_valid = dmInner_auto_dmi_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmiXing_auto_out_d_bits_opcode = dmInner_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmiXing_auto_out_d_bits_size = dmInner_auto_dmi_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmiXing_auto_out_d_bits_source = dmInner_auto_dmi_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmiXing_auto_out_d_bits_data = dmInner_auto_dmi_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@99097.4] assign dmactiveSync_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99104.4] assign dmactiveSync_reset = ~ io_dmactive; // @[:freechips.rocketchip.system.TinyConfig.fir@99105.4] assign debug_clock_gate_in = clock; // @[ClockGate.scala 25:14:freechips.rocketchip.system.TinyConfig.fir@99116.4] assign debug_clock_gate_en = clock_en; // @[ClockGate.scala 26:14:freechips.rocketchip.system.TinyConfig.fir@99117.4] assign AsyncQueueSink_clock = debug_clock_gate_out; // @[:freechips.rocketchip.system.TinyConfig.fir@99122.4] assign AsyncQueueSink_reset = ~ dmactive_synced; // @[:freechips.rocketchip.system.TinyConfig.fir@99123.4] assign AsyncQueueSink_io_async_mem_0_resumereq = io_innerCtrl_mem_0_resumereq; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99130.4] assign AsyncQueueSink_io_async_mem_0_hartsel = io_innerCtrl_mem_0_hartsel; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99130.4] assign AsyncQueueSink_io_async_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99130.4] assign AsyncQueueSink_io_async_widx = io_innerCtrl_widx; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99128.4] assign AsyncQueueSink_io_async_safe_widx_valid = io_innerCtrl_safe_widx_valid; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99126.4] assign AsyncQueueSink_io_async_safe_source_reset_n = io_innerCtrl_safe_source_reset_n; // @[AsyncQueue.scala 184:19:freechips.rocketchip.system.TinyConfig.fir@99125.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; clock_en = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin clock_en <= dmactive_synced | reset; end endmodule module TLDebugModule( // @[:freechips.rocketchip.system.TinyConfig.fir@99136.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@99137.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@99138.4] output auto_dmInner_dmInner_tl_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input auto_dmInner_dmInner_tl_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [2:0] auto_dmInner_dmInner_tl_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [1:0] auto_dmInner_dmInner_tl_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [9:0] auto_dmInner_dmInner_tl_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [11:0] auto_dmInner_dmInner_tl_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [3:0] auto_dmInner_dmInner_tl_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input [31:0] auto_dmInner_dmInner_tl_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input auto_dmInner_dmInner_tl_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] input auto_dmInner_dmInner_tl_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output auto_dmInner_dmInner_tl_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output [1:0] auto_dmInner_dmInner_tl_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output [9:0] auto_dmInner_dmInner_tl_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output [31:0] auto_dmInner_dmInner_tl_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output auto_dmOuter_intsource_out_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@99139.4] output io_ctrl_ndreset, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] output io_ctrl_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] output io_dmi_dmi_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input io_dmi_dmi_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input [6:0] io_dmi_dmi_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input [31:0] io_dmi_dmi_req_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input [1:0] io_dmi_dmi_req_bits_op, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input io_dmi_dmi_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] output io_dmi_dmi_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] output [31:0] io_dmi_dmi_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] output [1:0] io_dmi_dmi_resp_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input io_dmi_dmiClock, // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] input io_dmi_dmiReset // @[:freechips.rocketchip.system.TinyConfig.fir@99140.4] ); wire dmOuter_clock; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_reset; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [2:0] dmOuter_auto_asource_out_a_mem_0_opcode; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [8:0] dmOuter_auto_asource_out_a_mem_0_address; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [3:0] dmOuter_auto_asource_out_a_mem_0_mask; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [31:0] dmOuter_auto_asource_out_a_mem_0_data; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_a_ridx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_a_widx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_a_safe_ridx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_a_safe_widx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_a_safe_source_reset_n; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [2:0] dmOuter_auto_asource_out_d_mem_0_opcode; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [1:0] dmOuter_auto_asource_out_d_mem_0_size; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_mem_0_source; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [31:0] dmOuter_auto_asource_out_d_mem_0_data; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_ridx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_widx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_safe_ridx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_safe_widx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_auto_intsource_out_sync_0; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_dmi_req_ready; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_dmi_req_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [6:0] dmOuter_io_dmi_req_bits_addr; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [31:0] dmOuter_io_dmi_req_bits_data; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [1:0] dmOuter_io_dmi_req_bits_op; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_dmi_resp_ready; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_dmi_resp_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [31:0] dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [1:0] dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_ctrl_ndreset; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_ctrl_dmactive; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire [9:0] dmOuter_io_innerCtrl_mem_0_hartsel; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_ridx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_widx; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmOuter_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] wire dmInner_clock; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_reset; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [2:0] dmInner_auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [8:0] dmInner_auto_dmiXing_in_a_mem_0_address; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [3:0] dmInner_auto_dmiXing_in_a_mem_0_mask; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [31:0] dmInner_auto_dmiXing_in_a_mem_0_data; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_a_ridx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_a_widx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [2:0] dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [1:0] dmInner_auto_dmiXing_in_d_mem_0_size; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_mem_0_source; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [31:0] dmInner_auto_dmiXing_in_d_mem_0_data; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_ridx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_widx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmInner_tl_in_a_ready; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmInner_tl_in_a_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_param; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [1:0] dmInner_auto_dmInner_tl_in_a_bits_size; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [9:0] dmInner_auto_dmInner_tl_in_a_bits_source; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [11:0] dmInner_auto_dmInner_tl_in_a_bits_address; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [3:0] dmInner_auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [31:0] dmInner_auto_dmInner_tl_in_a_bits_data; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmInner_tl_in_d_ready; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_auto_dmInner_tl_in_d_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [2:0] dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [1:0] dmInner_auto_dmInner_tl_in_d_bits_size; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [9:0] dmInner_auto_dmInner_tl_in_d_bits_source; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [31:0] dmInner_auto_dmInner_tl_in_d_bits_data; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_dmactive; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire [9:0] dmInner_io_innerCtrl_mem_0_hartsel; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_ridx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_widx; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] wire dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] TLDebugModuleOuterAsync dmOuter ( // @[Debug.scala 1451:53:freechips.rocketchip.system.TinyConfig.fir@99146.4] .clock(dmOuter_clock), .reset(dmOuter_reset), .auto_asource_out_a_mem_0_opcode(dmOuter_auto_asource_out_a_mem_0_opcode), .auto_asource_out_a_mem_0_address(dmOuter_auto_asource_out_a_mem_0_address), .auto_asource_out_a_mem_0_mask(dmOuter_auto_asource_out_a_mem_0_mask), .auto_asource_out_a_mem_0_data(dmOuter_auto_asource_out_a_mem_0_data), .auto_asource_out_a_ridx(dmOuter_auto_asource_out_a_ridx), .auto_asource_out_a_widx(dmOuter_auto_asource_out_a_widx), .auto_asource_out_a_safe_ridx_valid(dmOuter_auto_asource_out_a_safe_ridx_valid), .auto_asource_out_a_safe_widx_valid(dmOuter_auto_asource_out_a_safe_widx_valid), .auto_asource_out_a_safe_source_reset_n(dmOuter_auto_asource_out_a_safe_source_reset_n), .auto_asource_out_d_mem_0_opcode(dmOuter_auto_asource_out_d_mem_0_opcode), .auto_asource_out_d_mem_0_size(dmOuter_auto_asource_out_d_mem_0_size), .auto_asource_out_d_mem_0_source(dmOuter_auto_asource_out_d_mem_0_source), .auto_asource_out_d_mem_0_data(dmOuter_auto_asource_out_d_mem_0_data), .auto_asource_out_d_ridx(dmOuter_auto_asource_out_d_ridx), .auto_asource_out_d_widx(dmOuter_auto_asource_out_d_widx), .auto_asource_out_d_safe_ridx_valid(dmOuter_auto_asource_out_d_safe_ridx_valid), .auto_asource_out_d_safe_widx_valid(dmOuter_auto_asource_out_d_safe_widx_valid), .auto_asource_out_d_safe_sink_reset_n(dmOuter_auto_asource_out_d_safe_sink_reset_n), .auto_intsource_out_sync_0(dmOuter_auto_intsource_out_sync_0), .io_dmi_req_ready(dmOuter_io_dmi_req_ready), .io_dmi_req_valid(dmOuter_io_dmi_req_valid), .io_dmi_req_bits_addr(dmOuter_io_dmi_req_bits_addr), .io_dmi_req_bits_data(dmOuter_io_dmi_req_bits_data), .io_dmi_req_bits_op(dmOuter_io_dmi_req_bits_op), .io_dmi_resp_ready(dmOuter_io_dmi_resp_ready), .io_dmi_resp_valid(dmOuter_io_dmi_resp_valid), .io_dmi_resp_bits_data(dmOuter_io_dmi_resp_bits_data), .io_dmi_resp_bits_resp(dmOuter_io_dmi_resp_bits_resp), .io_ctrl_ndreset(dmOuter_io_ctrl_ndreset), .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive), .io_innerCtrl_mem_0_resumereq(dmOuter_io_innerCtrl_mem_0_resumereq), .io_innerCtrl_mem_0_hartsel(dmOuter_io_innerCtrl_mem_0_hartsel), .io_innerCtrl_mem_0_ackhavereset(dmOuter_io_innerCtrl_mem_0_ackhavereset), .io_innerCtrl_ridx(dmOuter_io_innerCtrl_ridx), .io_innerCtrl_widx(dmOuter_io_innerCtrl_widx), .io_innerCtrl_safe_ridx_valid(dmOuter_io_innerCtrl_safe_ridx_valid), .io_innerCtrl_safe_widx_valid(dmOuter_io_innerCtrl_safe_widx_valid), .io_innerCtrl_safe_source_reset_n(dmOuter_io_innerCtrl_safe_source_reset_n), .io_innerCtrl_safe_sink_reset_n(dmOuter_io_innerCtrl_safe_sink_reset_n) ); TLDebugModuleInnerAsync dmInner ( // @[Debug.scala 1452:53:freechips.rocketchip.system.TinyConfig.fir@99153.4] .clock(dmInner_clock), .reset(dmInner_reset), .auto_dmiXing_in_a_mem_0_opcode(dmInner_auto_dmiXing_in_a_mem_0_opcode), .auto_dmiXing_in_a_mem_0_address(dmInner_auto_dmiXing_in_a_mem_0_address), .auto_dmiXing_in_a_mem_0_mask(dmInner_auto_dmiXing_in_a_mem_0_mask), .auto_dmiXing_in_a_mem_0_data(dmInner_auto_dmiXing_in_a_mem_0_data), .auto_dmiXing_in_a_ridx(dmInner_auto_dmiXing_in_a_ridx), .auto_dmiXing_in_a_widx(dmInner_auto_dmiXing_in_a_widx), .auto_dmiXing_in_a_safe_ridx_valid(dmInner_auto_dmiXing_in_a_safe_ridx_valid), .auto_dmiXing_in_a_safe_widx_valid(dmInner_auto_dmiXing_in_a_safe_widx_valid), .auto_dmiXing_in_a_safe_source_reset_n(dmInner_auto_dmiXing_in_a_safe_source_reset_n), .auto_dmiXing_in_d_mem_0_opcode(dmInner_auto_dmiXing_in_d_mem_0_opcode), .auto_dmiXing_in_d_mem_0_size(dmInner_auto_dmiXing_in_d_mem_0_size), .auto_dmiXing_in_d_mem_0_source(dmInner_auto_dmiXing_in_d_mem_0_source), .auto_dmiXing_in_d_mem_0_data(dmInner_auto_dmiXing_in_d_mem_0_data), .auto_dmiXing_in_d_ridx(dmInner_auto_dmiXing_in_d_ridx), .auto_dmiXing_in_d_widx(dmInner_auto_dmiXing_in_d_widx), .auto_dmiXing_in_d_safe_ridx_valid(dmInner_auto_dmiXing_in_d_safe_ridx_valid), .auto_dmiXing_in_d_safe_widx_valid(dmInner_auto_dmiXing_in_d_safe_widx_valid), .auto_dmiXing_in_d_safe_sink_reset_n(dmInner_auto_dmiXing_in_d_safe_sink_reset_n), .auto_dmInner_tl_in_a_ready(dmInner_auto_dmInner_tl_in_a_ready), .auto_dmInner_tl_in_a_valid(dmInner_auto_dmInner_tl_in_a_valid), .auto_dmInner_tl_in_a_bits_opcode(dmInner_auto_dmInner_tl_in_a_bits_opcode), .auto_dmInner_tl_in_a_bits_param(dmInner_auto_dmInner_tl_in_a_bits_param), .auto_dmInner_tl_in_a_bits_size(dmInner_auto_dmInner_tl_in_a_bits_size), .auto_dmInner_tl_in_a_bits_source(dmInner_auto_dmInner_tl_in_a_bits_source), .auto_dmInner_tl_in_a_bits_address(dmInner_auto_dmInner_tl_in_a_bits_address), .auto_dmInner_tl_in_a_bits_mask(dmInner_auto_dmInner_tl_in_a_bits_mask), .auto_dmInner_tl_in_a_bits_data(dmInner_auto_dmInner_tl_in_a_bits_data), .auto_dmInner_tl_in_a_bits_corrupt(dmInner_auto_dmInner_tl_in_a_bits_corrupt), .auto_dmInner_tl_in_d_ready(dmInner_auto_dmInner_tl_in_d_ready), .auto_dmInner_tl_in_d_valid(dmInner_auto_dmInner_tl_in_d_valid), .auto_dmInner_tl_in_d_bits_opcode(dmInner_auto_dmInner_tl_in_d_bits_opcode), .auto_dmInner_tl_in_d_bits_size(dmInner_auto_dmInner_tl_in_d_bits_size), .auto_dmInner_tl_in_d_bits_source(dmInner_auto_dmInner_tl_in_d_bits_source), .auto_dmInner_tl_in_d_bits_data(dmInner_auto_dmInner_tl_in_d_bits_data), .io_dmactive(dmInner_io_dmactive), .io_innerCtrl_mem_0_resumereq(dmInner_io_innerCtrl_mem_0_resumereq), .io_innerCtrl_mem_0_hartsel(dmInner_io_innerCtrl_mem_0_hartsel), .io_innerCtrl_mem_0_ackhavereset(dmInner_io_innerCtrl_mem_0_ackhavereset), .io_innerCtrl_ridx(dmInner_io_innerCtrl_ridx), .io_innerCtrl_widx(dmInner_io_innerCtrl_widx), .io_innerCtrl_safe_ridx_valid(dmInner_io_innerCtrl_safe_ridx_valid), .io_innerCtrl_safe_widx_valid(dmInner_io_innerCtrl_safe_widx_valid), .io_innerCtrl_safe_source_reset_n(dmInner_io_innerCtrl_safe_source_reset_n), .io_innerCtrl_safe_sink_reset_n(dmInner_io_innerCtrl_safe_sink_reset_n) ); assign auto_dmInner_dmInner_tl_in_a_ready = dmInner_auto_dmInner_tl_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmInner_dmInner_tl_in_d_valid = dmInner_auto_dmInner_tl_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmInner_dmInner_tl_in_d_bits_opcode = dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmInner_dmInner_tl_in_d_bits_size = dmInner_auto_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmInner_dmInner_tl_in_d_bits_source = dmInner_auto_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmInner_dmInner_tl_in_d_bits_data = dmInner_auto_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign auto_dmOuter_intsource_out_sync_0 = dmOuter_auto_intsource_out_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@99161.4] assign io_ctrl_ndreset = dmOuter_io_ctrl_ndreset; // @[Debug.scala 1490:13:freechips.rocketchip.system.TinyConfig.fir@99172.4] assign io_ctrl_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 1490:13:freechips.rocketchip.system.TinyConfig.fir@99172.4] assign io_dmi_dmi_req_ready = dmOuter_io_dmi_req_ready; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign io_dmi_dmi_resp_valid = dmOuter_io_dmi_resp_valid; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign io_dmi_dmi_resp_bits_data = dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign io_dmi_dmi_resp_bits_resp = dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_clock = io_dmi_dmiClock; // @[:freechips.rocketchip.system.TinyConfig.fir@99151.4 Debug.scala 1475:28:freechips.rocketchip.system.TinyConfig.fir@99166.4] assign dmOuter_reset = io_dmi_dmiReset; // @[:freechips.rocketchip.system.TinyConfig.fir@99152.4 Debug.scala 1474:28:freechips.rocketchip.system.TinyConfig.fir@99165.4] assign dmOuter_auto_asource_out_a_ridx = dmInner_auto_dmiXing_in_a_ridx; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_a_safe_ridx_valid = dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_mem_0_opcode = dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_mem_0_size = dmInner_auto_dmiXing_in_d_mem_0_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_mem_0_source = dmInner_auto_dmiXing_in_d_mem_0_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_mem_0_data = dmInner_auto_dmiXing_in_d_mem_0_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_widx = dmInner_auto_dmiXing_in_d_widx; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_auto_asource_out_d_safe_widx_valid = dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmOuter_io_dmi_req_valid = io_dmi_dmi_req_valid; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_io_dmi_req_bits_addr = io_dmi_dmi_req_bits_addr; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_io_dmi_req_bits_data = io_dmi_dmi_req_bits_data; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_io_dmi_req_bits_op = io_dmi_dmi_req_bits_op; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_io_dmi_resp_ready = io_dmi_dmi_resp_ready; // @[Debug.scala 1473:18:freechips.rocketchip.system.TinyConfig.fir@99164.4] assign dmOuter_io_innerCtrl_ridx = dmInner_io_innerCtrl_ridx; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmOuter_io_innerCtrl_safe_ridx_valid = dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmOuter_io_innerCtrl_safe_sink_reset_n = dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@99158.4] assign dmInner_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@99159.4] assign dmInner_auto_dmiXing_in_a_mem_0_opcode = dmOuter_auto_asource_out_a_mem_0_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_mem_0_address = dmOuter_auto_asource_out_a_mem_0_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_mem_0_mask = dmOuter_auto_asource_out_a_mem_0_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_mem_0_data = dmOuter_auto_asource_out_a_mem_0_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_widx = dmOuter_auto_asource_out_a_widx; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_safe_widx_valid = dmOuter_auto_asource_out_a_safe_widx_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_a_safe_source_reset_n = dmOuter_auto_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_d_ridx = dmOuter_auto_asource_out_d_ridx; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_d_safe_ridx_valid = dmOuter_auto_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmiXing_in_d_safe_sink_reset_n = dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@99160.4] assign dmInner_auto_dmInner_tl_in_a_valid = auto_dmInner_dmInner_tl_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_opcode = auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_param = auto_dmInner_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_size = auto_dmInner_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_source = auto_dmInner_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_address = auto_dmInner_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_mask = auto_dmInner_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_data = auto_dmInner_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_a_bits_corrupt = auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_auto_dmInner_tl_in_d_ready = auto_dmInner_dmInner_tl_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@99162.4] assign dmInner_io_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 1484:36:freechips.rocketchip.system.TinyConfig.fir@99168.4] assign dmInner_io_innerCtrl_mem_0_resumereq = dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_io_innerCtrl_mem_0_hartsel = dmOuter_io_innerCtrl_mem_0_hartsel; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_io_innerCtrl_mem_0_ackhavereset = dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_io_innerCtrl_widx = dmOuter_io_innerCtrl_widx; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_io_innerCtrl_safe_widx_valid = dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] assign dmInner_io_innerCtrl_safe_source_reset_n = dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1483:36:freechips.rocketchip.system.TinyConfig.fir@99167.4] endmodule module TLMonitor_35( // @[:freechips.rocketchip.system.TinyConfig.fir@99196.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@99197.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@99198.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@99199.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@100644.4] wire [26:0] _T_8; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@99219.6] wire [11:0] _T_9; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@99220.6] wire [11:0] _T_10; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@99221.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@99222.6] wire [31:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@99222.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@99223.6] wire _T_14; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@99225.6] wire [1:0] _T_15; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@99226.6] wire [1:0] _T_17; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@99228.6] wire _T_18; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@99229.6] wire _T_19; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@99230.6] wire _T_20; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@99231.6] wire _T_21; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@99232.6] wire _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99234.6] wire _T_24; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99235.6] wire _T_26; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99237.6] wire _T_27; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99238.6] wire _T_28; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@99239.6] wire _T_29; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@99240.6] wire _T_30; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@99241.6] wire _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99242.6] wire _T_32; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99243.6] wire _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99244.6] wire _T_34; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99245.6] wire _T_35; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99246.6] wire _T_36; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99247.6] wire _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99248.6] wire _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99249.6] wire _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99250.6] wire _T_40; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99251.6] wire _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99252.6] wire _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99253.6] wire [3:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@99256.6] wire [32:0] _T_49; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99260.6] wire _T_57; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@99272.6] wire [31:0] _T_59; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99275.8] wire [32:0] _T_60; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99276.8] wire [32:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99277.8] wire [32:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99278.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99279.8] wire [31:0] _T_64; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99280.8] wire [32:0] _T_65; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99281.8] wire [32:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99282.8] wire [32:0] _T_67; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99283.8] wire _T_68; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99284.8] wire [31:0] _T_69; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99285.8] wire [32:0] _T_70; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99286.8] wire [32:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99287.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99288.8] wire _T_73; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99289.8] wire [32:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99292.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99293.8] wire _T_78; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99294.8] wire [31:0] _T_79; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99295.8] wire [32:0] _T_80; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99296.8] wire [32:0] _T_81; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99297.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99298.8] wire _T_83; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99299.8] wire [31:0] _T_84; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99300.8] wire [32:0] _T_85; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99301.8] wire [32:0] _T_86; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99302.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99303.8] wire _T_88; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99304.8] wire [31:0] _T_89; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99305.8] wire [32:0] _T_90; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99306.8] wire [32:0] _T_91; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99307.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99308.8] wire _T_93; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99309.8] wire _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99310.8] wire _T_95; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99311.8] wire _T_96; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99312.8] wire _T_97; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99313.8] wire _T_104; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99320.8] wire _T_113; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99341.8] wire _T_114; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99342.8] wire _T_116; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99348.8] wire _T_117; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99349.8] wire _T_118; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@99354.8] wire _T_120; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99356.8] wire _T_121; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99357.8] wire [3:0] _T_122; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@99362.8] wire _T_123; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@99363.8] wire _T_125; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99365.8] wire _T_126; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99366.8] wire _T_131; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@99380.6] wire _T_196; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@99470.8] wire _T_198; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99472.8] wire _T_199; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99473.8] wire _T_209; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@99496.6] wire _T_211; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99499.8] wire _T_219; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99507.8] wire _T_221; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99509.8] wire _T_254; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99542.8] wire _T_255; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99543.8] wire _T_256; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99544.8] wire _T_257; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99545.8] wire _T_258; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99546.8] wire _T_259; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99547.8] wire _T_261; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99549.8] wire _T_263; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99551.8] wire _T_264; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99552.8] wire _T_271; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@99571.8] wire _T_273; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99573.8] wire _T_274; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99574.8] wire _T_275; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@99579.8] wire _T_277; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99581.8] wire _T_278; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99582.8] wire _T_283; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@99596.6] wire _T_321; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99635.8] wire _T_330; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99644.8] wire _T_338; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99652.8] wire _T_340; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99654.8] wire _T_342; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99656.8] wire _T_344; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99658.8] wire _T_345; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99659.8] wire _T_360; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@99695.6] wire [3:0] _T_433; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@99785.8] wire [3:0] _T_434; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@99786.8] wire _T_435; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@99787.8] wire _T_437; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99789.8] wire _T_438; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99790.8] wire _T_439; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@99796.6] wire _T_441; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99799.8] wire _T_473; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99831.8] wire _T_490; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99848.8] wire _T_491; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99849.8] wire _T_498; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@99868.8] wire _T_500; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99870.8] wire _T_501; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99871.8] wire _T_506; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@99885.6] wire _T_565; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@99957.8] wire _T_567; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99959.8] wire _T_568; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99960.8] wire _T_573; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@99974.6] wire _T_624; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100026.8] wire _T_625; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100027.8] wire _T_640; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@100065.6] wire _T_642; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100067.6] wire _T_643; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100068.6] wire _T_647; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@100078.6] wire _T_651; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@100087.8] wire _T_653; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100089.8] wire _T_654; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100090.8] wire _T_655; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@100095.8] wire _T_657; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100097.8] wire _T_658; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100098.8] wire _T_659; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@100103.8] wire _T_661; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100105.8] wire _T_662; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100106.8] wire _T_663; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@100111.8] wire _T_665; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100113.8] wire _T_666; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100114.8] wire _T_667; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@100120.6] wire _T_678; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@100144.8] wire _T_680; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100146.8] wire _T_681; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100147.8] wire _T_682; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@100152.8] wire _T_684; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100154.8] wire _T_685; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100155.8] wire _T_695; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@100178.6] wire _T_715; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@100219.8] wire _T_717; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100221.8] wire _T_718; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100222.8] wire _T_724; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@100237.6] wire _T_741; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@100272.6] wire _T_759; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@100308.6] wire _T_788; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@100368.4] wire [9:0] _T_793; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@100373.4] wire _T_794; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@100374.4] wire _T_795; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@100375.4] reg [9:0] _T_797; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@100377.4] reg [31:0] _RAND_0; wire [9:0] _T_799; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100379.4] wire _T_800; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100380.4] reg [2:0] _T_808; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@100391.4] reg [31:0] _RAND_1; reg [2:0] _T_809; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@100392.4] reg [31:0] _RAND_2; reg [3:0] _T_810; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@100393.4] reg [31:0] _RAND_3; reg [31:0] _T_812; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@100395.4] reg [31:0] _RAND_4; wire _T_813; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@100396.4] wire _T_814; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@100397.4] wire _T_815; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@100399.6] wire _T_817; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100401.6] wire _T_818; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100402.6] wire _T_819; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@100407.6] wire _T_821; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100409.6] wire _T_822; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100410.6] wire _T_823; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@100415.6] wire _T_825; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100417.6] wire _T_826; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100418.6] wire _T_831; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@100431.6] wire _T_833; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100433.6] wire _T_834; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100434.6] wire _T_836; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@100441.4] wire _T_837; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@100449.4] wire [26:0] _T_839; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@100451.4] wire [11:0] _T_840; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@100452.4] wire [11:0] _T_841; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@100453.4] wire [9:0] _T_842; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@100454.4] wire _T_843; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@100455.4] reg [9:0] _T_845; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@100457.4] reg [31:0] _RAND_5; wire [9:0] _T_847; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100459.4] wire _T_848; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100460.4] reg [2:0] _T_856; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@100471.4] reg [31:0] _RAND_6; reg [1:0] _T_857; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@100472.4] reg [31:0] _RAND_7; reg [3:0] _T_858; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@100473.4] reg [31:0] _RAND_8; reg _T_860; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@100475.4] reg [31:0] _RAND_9; reg _T_861; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@100476.4] reg [31:0] _RAND_10; wire _T_862; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@100477.4] wire _T_863; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@100478.4] wire _T_864; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@100480.6] wire _T_866; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100482.6] wire _T_867; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100483.6] wire _T_868; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@100488.6] wire _T_870; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100490.6] wire _T_871; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100491.6] wire _T_872; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@100496.6] wire _T_874; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100498.6] wire _T_875; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100499.6] wire _T_880; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@100512.6] wire _T_882; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100514.6] wire _T_883; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100515.6] wire _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@100520.6] wire _T_886; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100522.6] wire _T_887; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100523.6] wire _T_889; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@100530.4] reg _T_890; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@100539.4] reg [31:0] _RAND_11; reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@100549.4] reg [31:0] _RAND_12; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100551.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100552.4] reg [9:0] _T_919; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@100571.4] reg [31:0] _RAND_13; wire [9:0] _T_921; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100573.4] wire _T_922; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100574.4] wire _T_932; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@100589.4] wire _T_937; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@100596.6] wire _T_939; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100598.6] wire _T_940; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100599.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@100591.4] wire _T_944; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@100610.4] wire _T_946; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@100612.4] wire _T_947; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@100613.4] wire _T_930; // @[:freechips.rocketchip.system.TinyConfig.fir@100585.4 :freechips.rocketchip.system.TinyConfig.fir@100587.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@100593.6] wire _T_949; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@100617.6] wire _T_953; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100621.6] wire _T_954; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100622.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@100614.4] wire _T_941; // @[:freechips.rocketchip.system.TinyConfig.fir@100605.4 :freechips.rocketchip.system.TinyConfig.fir@100607.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@100616.6] wire _T_955; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@100628.4] wire _T_957; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@100630.4] wire _T_958; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@100631.4] wire _T_960; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100633.4] wire _T_961; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100634.4] wire _T_962; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@100639.4] wire _T_963; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@100640.4] wire _T_964; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@100641.4] reg [31:0] _T_965; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@100643.4] reg [31:0] _RAND_14; wire _T_968; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@100648.4] wire _T_969; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@100649.4] wire _T_970; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@100650.4] wire _T_971; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@100651.4] wire _T_973; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100653.4] wire _T_974; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100654.4] wire [31:0] _T_976; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@100660.4] wire _T_979; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@100664.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99322.10] wire _GEN_31; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@99430.10] wire _GEN_45; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99554.10] wire _GEN_53; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99661.10] wire _GEN_61; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@99760.10] wire _GEN_69; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99851.10] wire _GEN_77; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@99940.10] wire _GEN_85; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100029.10] wire _GEN_91; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100092.10] wire _GEN_99; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@100133.10] wire _GEN_109; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@100191.10] wire _GEN_119; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@100251.10] wire _GEN_123; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@100286.10] wire _GEN_127; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@100322.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@100644.4] .out(plusarg_reader_out) ); assign _T_8 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@99219.6] assign _T_9 = _T_8[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@99220.6] assign _T_10 = ~ _T_9; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@99221.6] assign _GEN_18 = {{20'd0}, _T_10}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@99222.6] assign _T_11 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@99222.6] assign _T_12 = _T_11 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@99223.6] assign _T_14 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@99225.6] assign _T_15 = 2'h1 << _T_14; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@99226.6] assign _T_17 = _T_15 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@99228.6] assign _T_18 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@99229.6] assign _T_19 = _T_17[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@99230.6] assign _T_20 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@99231.6] assign _T_21 = _T_20 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@99232.6] assign _T_23 = _T_19 & _T_21; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99234.6] assign _T_24 = _T_18 | _T_23; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99235.6] assign _T_26 = _T_19 & _T_20; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99237.6] assign _T_27 = _T_18 | _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99238.6] assign _T_28 = _T_17[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@99239.6] assign _T_29 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@99240.6] assign _T_30 = _T_29 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@99241.6] assign _T_31 = _T_21 & _T_30; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99242.6] assign _T_32 = _T_28 & _T_31; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99243.6] assign _T_33 = _T_24 | _T_32; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99244.6] assign _T_34 = _T_21 & _T_29; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99245.6] assign _T_35 = _T_28 & _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99246.6] assign _T_36 = _T_24 | _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99247.6] assign _T_37 = _T_20 & _T_30; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99248.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99249.6] assign _T_39 = _T_27 | _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99250.6] assign _T_40 = _T_20 & _T_29; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@99251.6] assign _T_41 = _T_28 & _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@99252.6] assign _T_42 = _T_27 | _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@99253.6] assign _T_45 = {_T_42,_T_39,_T_36,_T_33}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@99256.6] assign _T_49 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99260.6] assign _T_57 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@99272.6] assign _T_59 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99275.8] assign _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99276.8] assign _T_61 = $signed(_T_60) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99277.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99278.8] assign _T_63 = $signed(_T_62) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99279.8] assign _T_64 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99280.8] assign _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99281.8] assign _T_66 = $signed(_T_65) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99282.8] assign _T_67 = $signed(_T_66); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99283.8] assign _T_68 = $signed(_T_67) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99284.8] assign _T_69 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99285.8] assign _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99286.8] assign _T_71 = $signed(_T_70) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99287.8] assign _T_72 = $signed(_T_71); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99288.8] assign _T_73 = $signed(_T_72) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99289.8] assign _T_76 = $signed(_T_49) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99292.8] assign _T_77 = $signed(_T_76); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99293.8] assign _T_78 = $signed(_T_77) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99294.8] assign _T_79 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99295.8] assign _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99296.8] assign _T_81 = $signed(_T_80) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99297.8] assign _T_82 = $signed(_T_81); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99298.8] assign _T_83 = $signed(_T_82) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99299.8] assign _T_84 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99300.8] assign _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99301.8] assign _T_86 = $signed(_T_85) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99302.8] assign _T_87 = $signed(_T_86); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99303.8] assign _T_88 = $signed(_T_87) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99304.8] assign _T_89 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@99305.8] assign _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@99306.8] assign _T_91 = $signed(_T_90) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99307.8] assign _T_92 = $signed(_T_91); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@99308.8] assign _T_93 = $signed(_T_92) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@99309.8] assign _T_94 = _T_63 | _T_68; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99310.8] assign _T_95 = _T_94 | _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99311.8] assign _T_96 = _T_95 | _T_78; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99312.8] assign _T_97 = _T_96 | _T_83; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99313.8] assign _T_104 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99320.8] assign _T_113 = _T_18 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99341.8] assign _T_114 = _T_113 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99342.8] assign _T_116 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99348.8] assign _T_117 = _T_116 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99349.8] assign _T_118 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@99354.8] assign _T_120 = _T_118 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99356.8] assign _T_121 = _T_120 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99357.8] assign _T_122 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@99362.8] assign _T_123 = _T_122 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@99363.8] assign _T_125 = _T_123 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99365.8] assign _T_126 = _T_125 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99366.8] assign _T_131 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@99380.6] assign _T_196 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@99470.8] assign _T_198 = _T_196 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99472.8] assign _T_199 = _T_198 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99473.8] assign _T_209 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@99496.6] assign _T_211 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99499.8] assign _T_219 = _T_211 & _T_63; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99507.8] assign _T_221 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99509.8] assign _T_254 = _T_68 | _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99542.8] assign _T_255 = _T_254 | _T_78; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99543.8] assign _T_256 = _T_255 | _T_83; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99544.8] assign _T_257 = _T_256 | _T_88; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99545.8] assign _T_258 = _T_257 | _T_93; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@99546.8] assign _T_259 = _T_221 & _T_258; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99547.8] assign _T_261 = _T_219 | _T_259; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99549.8] assign _T_263 = _T_261 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99551.8] assign _T_264 = _T_263 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99552.8] assign _T_271 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@99571.8] assign _T_273 = _T_271 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99573.8] assign _T_274 = _T_273 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99574.8] assign _T_275 = io_in_a_bits_mask == _T_45; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@99579.8] assign _T_277 = _T_275 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99581.8] assign _T_278 = _T_277 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99582.8] assign _T_283 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@99596.6] assign _T_321 = _T_221 & _T_256; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99635.8] assign _T_330 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99644.8] assign _T_338 = _T_330 & _T_93; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99652.8] assign _T_340 = _T_219 | _T_321; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99654.8] assign _T_342 = _T_340 | _T_338; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@99656.8] assign _T_344 = _T_342 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99658.8] assign _T_345 = _T_344 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99659.8] assign _T_360 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@99695.6] assign _T_433 = ~ _T_45; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@99785.8] assign _T_434 = io_in_a_bits_mask & _T_433; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@99786.8] assign _T_435 = _T_434 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@99787.8] assign _T_437 = _T_435 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99789.8] assign _T_438 = _T_437 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99790.8] assign _T_439 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@99796.6] assign _T_441 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@99799.8] assign _T_473 = _T_441 & _T_97; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@99831.8] assign _T_490 = _T_473 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99848.8] assign _T_491 = _T_490 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99849.8] assign _T_498 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@99868.8] assign _T_500 = _T_498 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99870.8] assign _T_501 = _T_500 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99871.8] assign _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@99885.6] assign _T_565 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@99957.8] assign _T_567 = _T_565 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99959.8] assign _T_568 = _T_567 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99960.8] assign _T_573 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@99974.6] assign _T_624 = _T_219 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100026.8] assign _T_625 = _T_624 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100027.8] assign _T_640 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@100065.6] assign _T_642 = _T_640 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100067.6] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100068.6] assign _T_647 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@100078.6] assign _T_651 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@100087.8] assign _T_653 = _T_651 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100089.8] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100090.8] assign _T_655 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@100095.8] assign _T_657 = _T_655 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100097.8] assign _T_658 = _T_657 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100098.8] assign _T_659 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@100103.8] assign _T_661 = _T_659 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100105.8] assign _T_662 = _T_661 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100106.8] assign _T_663 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@100111.8] assign _T_665 = _T_663 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100113.8] assign _T_666 = _T_665 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100114.8] assign _T_667 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@100120.6] assign _T_678 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@100144.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100146.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100147.8] assign _T_682 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@100152.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100154.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100155.8] assign _T_695 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@100178.6] assign _T_715 = _T_663 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@100219.8] assign _T_717 = _T_715 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100221.8] assign _T_718 = _T_717 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100222.8] assign _T_724 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@100237.6] assign _T_741 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@100272.6] assign _T_759 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@100308.6] assign _T_788 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@100368.4] assign _T_793 = _T_10[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@100373.4] assign _T_794 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@100374.4] assign _T_795 = _T_794 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@100375.4] assign _T_799 = _T_797 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100379.4] assign _T_800 = _T_797 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100380.4] assign _T_813 = _T_800 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@100396.4] assign _T_814 = io_in_a_valid & _T_813; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@100397.4] assign _T_815 = io_in_a_bits_opcode == _T_808; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@100399.6] assign _T_817 = _T_815 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100401.6] assign _T_818 = _T_817 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100402.6] assign _T_819 = io_in_a_bits_param == _T_809; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@100407.6] assign _T_821 = _T_819 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100409.6] assign _T_822 = _T_821 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100410.6] assign _T_823 = io_in_a_bits_size == _T_810; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@100415.6] assign _T_825 = _T_823 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100417.6] assign _T_826 = _T_825 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100418.6] assign _T_831 = io_in_a_bits_address == _T_812; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@100431.6] assign _T_833 = _T_831 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100433.6] assign _T_834 = _T_833 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100434.6] assign _T_836 = _T_788 & _T_800; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@100441.4] assign _T_837 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@100449.4] assign _T_839 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@100451.4] assign _T_840 = _T_839[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@100452.4] assign _T_841 = ~ _T_840; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@100453.4] assign _T_842 = _T_841[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@100454.4] assign _T_843 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@100455.4] assign _T_847 = _T_845 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100459.4] assign _T_848 = _T_845 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100460.4] assign _T_862 = _T_848 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@100477.4] assign _T_863 = io_in_d_valid & _T_862; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@100478.4] assign _T_864 = io_in_d_bits_opcode == _T_856; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@100480.6] assign _T_866 = _T_864 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100482.6] assign _T_867 = _T_866 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100483.6] assign _T_868 = io_in_d_bits_param == _T_857; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@100488.6] assign _T_870 = _T_868 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100490.6] assign _T_871 = _T_870 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100491.6] assign _T_872 = io_in_d_bits_size == _T_858; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@100496.6] assign _T_874 = _T_872 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100498.6] assign _T_875 = _T_874 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100499.6] assign _T_880 = io_in_d_bits_sink == _T_860; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@100512.6] assign _T_882 = _T_880 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100514.6] assign _T_883 = _T_882 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100515.6] assign _T_884 = io_in_d_bits_denied == _T_861; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@100520.6] assign _T_886 = _T_884 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100522.6] assign _T_887 = _T_886 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100523.6] assign _T_889 = _T_837 & _T_848; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@100530.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100551.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100552.4] assign _T_921 = _T_919 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@100573.4] assign _T_922 = _T_919 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@100574.4] assign _T_932 = _T_788 & _T_903; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@100589.4] assign _T_937 = _T_890 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@100596.6] assign _T_939 = _T_937 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100598.6] assign _T_940 = _T_939 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100599.6] assign _GEN_15 = _T_932 ? 2'h1 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@100591.4] assign _T_944 = _T_837 & _T_922; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@100610.4] assign _T_946 = _T_647 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@100612.4] assign _T_947 = _T_944 & _T_946; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@100613.4] assign _T_930 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@100585.4 :freechips.rocketchip.system.TinyConfig.fir@100587.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@100593.6] assign _T_949 = _T_930 | _T_890; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@100617.6] assign _T_953 = _T_949 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100621.6] assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100622.6] assign _GEN_16 = _T_947 ? 2'h1 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@100614.4] assign _T_941 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@100605.4 :freechips.rocketchip.system.TinyConfig.fir@100607.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@100616.6] assign _T_955 = _T_930 != _T_941; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@100628.4] assign _T_957 = _T_930 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@100630.4] assign _T_958 = _T_955 | _T_957; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@100631.4] assign _T_960 = _T_958 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100633.4] assign _T_961 = _T_960 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100634.4] assign _T_962 = _T_890 | _T_930; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@100639.4] assign _T_963 = ~ _T_941; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@100640.4] assign _T_964 = _T_962 & _T_963; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@100641.4] assign _T_968 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@100648.4] assign _T_969 = _T_937 | _T_968; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@100649.4] assign _T_970 = _T_965 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@100650.4] assign _T_971 = _T_969 | _T_970; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@100651.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100653.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100654.4] assign _T_976 = _T_965 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@100660.4] assign _T_979 = _T_788 | _T_837; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@100664.4] assign _GEN_19 = io_in_a_valid & _T_57; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99322.10] assign _GEN_31 = io_in_a_valid & _T_131; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@99430.10] assign _GEN_45 = io_in_a_valid & _T_209; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99554.10] assign _GEN_53 = io_in_a_valid & _T_283; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99661.10] assign _GEN_61 = io_in_a_valid & _T_360; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@99760.10] assign _GEN_69 = io_in_a_valid & _T_439; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99851.10] assign _GEN_77 = io_in_a_valid & _T_506; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@99940.10] assign _GEN_85 = io_in_a_valid & _T_573; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100029.10] assign _GEN_91 = io_in_d_valid & _T_647; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100092.10] assign _GEN_99 = io_in_d_valid & _T_667; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@100133.10] assign _GEN_109 = io_in_d_valid & _T_695; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@100191.10] assign _GEN_119 = io_in_d_valid & _T_724; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@100251.10] assign _GEN_123 = io_in_d_valid & _T_741; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@100286.10] assign _GEN_127 = io_in_d_valid & _T_759; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@100322.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_797 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_808 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_809 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_810 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_812 = _RAND_4[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_845 = _RAND_5[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_856 = _RAND_6[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_857 = _RAND_7[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_858 = _RAND_8[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_860 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_861 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_890 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_900 = _RAND_12[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_919 = _RAND_13[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_965 = _RAND_14[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_797 <= 10'h0; end else begin if (_T_788) begin if (_T_800) begin if (_T_795) begin _T_797 <= _T_793; end else begin _T_797 <= 10'h0; end end else begin _T_797 <= _T_799; end end end if (_T_836) begin _T_808 <= io_in_a_bits_opcode; end if (_T_836) begin _T_809 <= io_in_a_bits_param; end if (_T_836) begin _T_810 <= io_in_a_bits_size; end if (_T_836) begin _T_812 <= io_in_a_bits_address; end if (reset) begin _T_845 <= 10'h0; end else begin if (_T_837) begin if (_T_848) begin if (_T_843) begin _T_845 <= _T_842; end else begin _T_845 <= 10'h0; end end else begin _T_845 <= _T_847; end end end if (_T_889) begin _T_856 <= io_in_d_bits_opcode; end if (_T_889) begin _T_857 <= io_in_d_bits_param; end if (_T_889) begin _T_858 <= io_in_d_bits_size; end if (_T_889) begin _T_860 <= io_in_d_bits_sink; end if (_T_889) begin _T_861 <= io_in_d_bits_denied; end if (reset) begin _T_890 <= 1'h0; end else begin _T_890 <= _T_964; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_788) begin if (_T_903) begin if (_T_795) begin _T_900 <= _T_793; end else begin _T_900 <= 10'h0; end end else begin _T_900 <= _T_902; end end end if (reset) begin _T_919 <= 10'h0; end else begin if (_T_837) begin if (_T_922) begin if (_T_843) begin _T_919 <= _T_842; end else begin _T_919 <= 10'h0; end end else begin _T_919 <= _T_921; end end end if (reset) begin _T_965 <= 32'h0; end else begin if (_T_979) begin _T_965 <= 32'h0; end else begin _T_965 <= _T_976; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@99323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at HellaCache.scala:237:21)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@99329.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@99330.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_114) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at HellaCache.scala:237:21)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99344.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_114) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@99345.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99351.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_117) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@99352.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at HellaCache.scala:237:21)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99359.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_121) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@99360.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_126) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99368.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_126) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@99369.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@99430.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_104) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@99431.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at HellaCache.scala:237:21)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@99437.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_104) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@99438.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_114) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at HellaCache.scala:237:21)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@99452.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_114) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@99453.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@99459.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_117) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@99460.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at HellaCache.scala:237:21)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@99467.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_121) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@99468.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_199) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at HellaCache.scala:237:21)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99475.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_199) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@99476.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_31 & _T_126) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@99484.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_31 & _T_126) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@99485.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_45 & _T_264) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99554.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_45 & _T_264) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@99555.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_45 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@99568.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_45 & _T_117) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@99569.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_45 & _T_274) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99576.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_45 & _T_274) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@99577.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_45 & _T_278) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99584.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_45 & _T_278) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@99585.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_345) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99661.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_345) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@99662.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@99675.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_117) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@99676.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_274) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@99683.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_274) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@99684.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_278) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@99691.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_278) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@99692.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_61 & _T_345) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@99760.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_61 & _T_345) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@99761.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_61 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@99774.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_61 & _T_117) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@99775.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_61 & _T_274) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@99782.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_61 & _T_274) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@99783.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_61 & _T_438) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99792.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_61 & _T_438) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@99793.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_69 & _T_491) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99851.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_69 & _T_491) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@99852.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_69 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@99865.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_69 & _T_117) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@99866.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_69 & _T_501) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at HellaCache.scala:237:21)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99873.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_69 & _T_501) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@99874.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_69 & _T_278) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@99881.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_69 & _T_278) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@99882.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_77 & _T_491) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@99940.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_77 & _T_491) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@99941.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_77 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@99954.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_77 & _T_117) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@99955.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_77 & _T_568) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at HellaCache.scala:237:21)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99962.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_77 & _T_568) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@99963.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_77 & _T_278) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@99970.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_77 & _T_278) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@99971.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_625) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at HellaCache.scala:237:21)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_625) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@100030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at HellaCache.scala:237:21)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@100043.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_117) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@100044.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_278) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at HellaCache.scala:237:21)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@100051.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_278) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@100052.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_643) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at HellaCache.scala:237:21)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100070.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_643) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@100071.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_91 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at HellaCache.scala:237:21)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100092.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_91 & _T_654) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@100093.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_91 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100100.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_91 & _T_658) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@100101.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_91 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100108.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_91 & _T_662) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@100109.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_91 & _T_666) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at HellaCache.scala:237:21)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100116.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_91 & _T_666) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@100117.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_99 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at HellaCache.scala:237:21)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@100133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_99 & _T_104) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@100134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_99 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at HellaCache.scala:237:21)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@100141.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_99 & _T_654) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@100142.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_99 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at HellaCache.scala:237:21)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100149.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_99 & _T_681) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@100150.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_99 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at HellaCache.scala:237:21)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100157.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_99 & _T_685) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@100158.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_99 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@100165.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_99 & _T_662) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@100166.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_109 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at HellaCache.scala:237:21)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@100191.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_109 & _T_104) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@100192.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_109 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at HellaCache.scala:237:21)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@100199.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_109 & _T_654) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@100200.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_109 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at HellaCache.scala:237:21)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@100207.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_109 & _T_681) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@100208.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_109 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at HellaCache.scala:237:21)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@100215.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_109 & _T_685) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@100216.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_109 & _T_718) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100224.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_109 & _T_718) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@100225.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@100251.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_658) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@100252.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_119 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@100259.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_119 & _T_662) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@100260.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@100286.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_658) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@100287.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_123 & _T_718) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@100295.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_123 & _T_718) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@100296.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_127 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at HellaCache.scala:237:21)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@100322.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_127 & _T_658) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@100323.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_127 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at HellaCache.scala:237:21)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@100330.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_127 & _T_662) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@100331.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_814 & _T_818) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100404.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_814 & _T_818) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@100405.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_814 & _T_822) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100412.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_814 & _T_822) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@100413.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_814 & _T_826) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100420.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_814 & _T_826) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@100421.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_814 & _T_834) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100436.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_814 & _T_834) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@100437.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_867) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100485.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_867) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@100486.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_871) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100493.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_871) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@100494.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_875) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100501.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_875) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@100502.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_883) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100517.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_883) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@100518.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_887) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at HellaCache.scala:237:21)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100525.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_887) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@100526.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_932 & _T_940) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at HellaCache.scala:237:21)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100601.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_932 & _T_940) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@100602.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_947 & _T_954) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:237:21)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100624.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_947 & _T_954) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@100625.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_961) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at HellaCache.scala:237:21)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100636.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_961) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@100637.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at HellaCache.scala:237:21)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100656.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@100657.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_36( // @[:freechips.rocketchip.system.TinyConfig.fir@100677.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@100678.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@100679.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@100680.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@102125.4] wire [31:0] _T_11; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@100703.6] wire _T_12; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@100704.6] wire [32:0] _T_49; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100741.6] wire [31:0] _T_59; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100756.8] wire [32:0] _T_60; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100757.8] wire [32:0] _T_61; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100758.8] wire [32:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100759.8] wire _T_63; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100760.8] wire [31:0] _T_64; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100761.8] wire [32:0] _T_65; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100762.8] wire [32:0] _T_66; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100763.8] wire [32:0] _T_67; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100764.8] wire _T_68; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100765.8] wire [31:0] _T_69; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100766.8] wire [32:0] _T_70; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100767.8] wire [32:0] _T_71; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100768.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100769.8] wire _T_73; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100770.8] wire [32:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100773.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100774.8] wire _T_78; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100775.8] wire [31:0] _T_79; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100776.8] wire [32:0] _T_80; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100777.8] wire [32:0] _T_81; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100778.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100779.8] wire _T_83; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100780.8] wire [31:0] _T_84; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100781.8] wire [32:0] _T_85; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100782.8] wire [32:0] _T_86; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100783.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100784.8] wire _T_88; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100785.8] wire [31:0] _T_89; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100786.8] wire [32:0] _T_90; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100787.8] wire [32:0] _T_91; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100788.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100789.8] wire _T_93; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100790.8] wire _T_104; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@100801.8] wire _T_116; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@100829.8] wire _T_117; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@100830.8] wire _T_254; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101023.8] wire _T_255; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101024.8] wire _T_256; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101025.8] wire _T_257; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101026.8] wire _T_258; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101027.8] wire _T_261; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@101030.8] wire _T_263; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101032.8] wire _T_264; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101033.8] wire _T_640; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@101546.6] wire _T_642; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101548.6] wire _T_643; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101549.6] wire _T_647; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@101559.6] wire _T_651; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@101568.8] wire _T_653; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101570.8] wire _T_654; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101571.8] wire _T_655; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@101576.8] wire _T_657; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101578.8] wire _T_658; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101579.8] wire _T_659; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@101584.8] wire _T_661; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101586.8] wire _T_662; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101587.8] wire _T_663; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@101592.8] wire _T_665; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101594.8] wire _T_666; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101595.8] wire _T_667; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@101601.6] wire _T_678; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@101625.8] wire _T_680; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101627.8] wire _T_681; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101628.8] wire _T_682; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@101633.8] wire _T_684; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101635.8] wire _T_685; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101636.8] wire _T_695; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@101659.6] wire _T_715; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@101700.8] wire _T_717; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101702.8] wire _T_718; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101703.8] wire _T_724; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@101718.6] wire _T_741; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@101753.6] wire _T_759; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@101789.6] wire _T_788; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@101849.4] reg [9:0] _T_797; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@101858.4] reg [31:0] _RAND_0; wire [9:0] _T_799; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@101860.4] wire _T_800; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@101861.4] reg [31:0] _T_812; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@101876.4] reg [31:0] _RAND_1; wire _T_813; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@101877.4] wire _T_814; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@101878.4] wire _T_831; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@101912.6] wire _T_833; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101914.6] wire _T_834; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101915.6] wire _T_836; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@101922.4] wire [26:0] _T_839; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@101932.4] wire [11:0] _T_840; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@101933.4] wire [11:0] _T_841; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@101934.4] wire [9:0] _T_842; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@101935.4] wire _T_843; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@101936.4] reg [9:0] _T_845; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@101938.4] reg [31:0] _RAND_2; wire [9:0] _T_847; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@101940.4] wire _T_848; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@101941.4] reg [2:0] _T_856; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@101952.4] reg [31:0] _RAND_3; reg [1:0] _T_857; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@101953.4] reg [31:0] _RAND_4; reg [3:0] _T_858; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@101954.4] reg [31:0] _RAND_5; reg _T_860; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@101956.4] reg [31:0] _RAND_6; reg _T_861; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@101957.4] reg [31:0] _RAND_7; wire _T_862; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@101958.4] wire _T_863; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@101959.4] wire _T_864; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@101961.6] wire _T_866; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101963.6] wire _T_867; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101964.6] wire _T_868; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@101969.6] wire _T_870; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101971.6] wire _T_871; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101972.6] wire _T_872; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@101977.6] wire _T_874; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101979.6] wire _T_875; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101980.6] wire _T_880; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@101993.6] wire _T_882; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101995.6] wire _T_883; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101996.6] wire _T_884; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@102001.6] wire _T_886; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102003.6] wire _T_887; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102004.6] wire _T_889; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@102011.4] reg _T_890; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@102020.4] reg [31:0] _RAND_8; reg [9:0] _T_900; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@102030.4] reg [31:0] _RAND_9; wire [9:0] _T_902; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@102032.4] wire _T_903; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@102033.4] reg [9:0] _T_919; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@102052.4] reg [31:0] _RAND_10; wire [9:0] _T_921; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@102054.4] wire _T_922; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@102055.4] wire _T_932; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@102070.4] wire _T_937; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@102077.6] wire _T_939; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102079.6] wire _T_940; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102080.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@102072.4] wire _T_944; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@102091.4] wire _T_946; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@102093.4] wire _T_947; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@102094.4] wire _T_930; // @[:freechips.rocketchip.system.TinyConfig.fir@102066.4 :freechips.rocketchip.system.TinyConfig.fir@102068.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@102074.6] wire _T_949; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@102098.6] wire _T_953; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102102.6] wire _T_954; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102103.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@102095.4] wire _T_941; // @[:freechips.rocketchip.system.TinyConfig.fir@102086.4 :freechips.rocketchip.system.TinyConfig.fir@102088.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@102097.6] wire _T_955; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@102109.4] wire _T_957; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@102111.4] wire _T_958; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@102112.4] wire _T_960; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102114.4] wire _T_961; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102115.4] wire _T_962; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@102120.4] wire _T_963; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@102121.4] wire _T_964; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@102122.4] reg [31:0] _T_965; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@102124.4] reg [31:0] _RAND_11; wire _T_968; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@102129.4] wire _T_969; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@102130.4] wire _T_970; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@102131.4] wire _T_971; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@102132.4] wire _T_973; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102134.4] wire _T_974; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102135.4] wire [31:0] _T_976; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@102141.4] wire _T_979; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@102145.4] wire _GEN_18; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101573.10] wire _GEN_26; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@101614.10] wire _GEN_36; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@101672.10] wire _GEN_46; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@101732.10] wire _GEN_50; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@101767.10] wire _GEN_54; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@101803.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@102125.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_address & 32'h3f; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@100703.6] assign _T_12 = _T_11 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@100704.6] assign _T_49 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100741.6] assign _T_59 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100756.8] assign _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100757.8] assign _T_61 = $signed(_T_60) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100758.8] assign _T_62 = $signed(_T_61); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100759.8] assign _T_63 = $signed(_T_62) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100760.8] assign _T_64 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100761.8] assign _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100762.8] assign _T_66 = $signed(_T_65) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100763.8] assign _T_67 = $signed(_T_66); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100764.8] assign _T_68 = $signed(_T_67) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100765.8] assign _T_69 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100766.8] assign _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100767.8] assign _T_71 = $signed(_T_70) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100768.8] assign _T_72 = $signed(_T_71); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100769.8] assign _T_73 = $signed(_T_72) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100770.8] assign _T_76 = $signed(_T_49) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100773.8] assign _T_77 = $signed(_T_76); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100774.8] assign _T_78 = $signed(_T_77) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100775.8] assign _T_79 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100776.8] assign _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100777.8] assign _T_81 = $signed(_T_80) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100778.8] assign _T_82 = $signed(_T_81); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100779.8] assign _T_83 = $signed(_T_82) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100780.8] assign _T_84 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100781.8] assign _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100782.8] assign _T_86 = $signed(_T_85) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100783.8] assign _T_87 = $signed(_T_86); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100784.8] assign _T_88 = $signed(_T_87) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100785.8] assign _T_89 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@100786.8] assign _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@100787.8] assign _T_91 = $signed(_T_90) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100788.8] assign _T_92 = $signed(_T_91); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@100789.8] assign _T_93 = $signed(_T_92) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@100790.8] assign _T_104 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@100801.8] assign _T_116 = _T_12 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@100829.8] assign _T_117 = _T_116 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@100830.8] assign _T_254 = _T_68 | _T_73; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101023.8] assign _T_255 = _T_254 | _T_78; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101024.8] assign _T_256 = _T_255 | _T_83; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101025.8] assign _T_257 = _T_256 | _T_88; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101026.8] assign _T_258 = _T_257 | _T_93; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@101027.8] assign _T_261 = _T_63 | _T_258; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@101030.8] assign _T_263 = _T_261 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101032.8] assign _T_264 = _T_263 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101033.8] assign _T_640 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@101546.6] assign _T_642 = _T_640 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101548.6] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101549.6] assign _T_647 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@101559.6] assign _T_651 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@101568.8] assign _T_653 = _T_651 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101570.8] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101571.8] assign _T_655 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@101576.8] assign _T_657 = _T_655 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101578.8] assign _T_658 = _T_657 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101579.8] assign _T_659 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@101584.8] assign _T_661 = _T_659 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101586.8] assign _T_662 = _T_661 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101587.8] assign _T_663 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@101592.8] assign _T_665 = _T_663 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101594.8] assign _T_666 = _T_665 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101595.8] assign _T_667 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@101601.6] assign _T_678 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@101625.8] assign _T_680 = _T_678 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101627.8] assign _T_681 = _T_680 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101628.8] assign _T_682 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@101633.8] assign _T_684 = _T_682 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101635.8] assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101636.8] assign _T_695 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@101659.6] assign _T_715 = _T_663 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@101700.8] assign _T_717 = _T_715 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101702.8] assign _T_718 = _T_717 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101703.8] assign _T_724 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@101718.6] assign _T_741 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@101753.6] assign _T_759 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@101789.6] assign _T_788 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@101849.4] assign _T_799 = _T_797 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@101860.4] assign _T_800 = _T_797 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@101861.4] assign _T_813 = _T_800 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@101877.4] assign _T_814 = io_in_a_valid & _T_813; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@101878.4] assign _T_831 = io_in_a_bits_address == _T_812; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@101912.6] assign _T_833 = _T_831 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101914.6] assign _T_834 = _T_833 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101915.6] assign _T_836 = _T_788 & _T_800; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@101922.4] assign _T_839 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@101932.4] assign _T_840 = _T_839[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@101933.4] assign _T_841 = ~ _T_840; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@101934.4] assign _T_842 = _T_841[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@101935.4] assign _T_843 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@101936.4] assign _T_847 = _T_845 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@101940.4] assign _T_848 = _T_845 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@101941.4] assign _T_862 = _T_848 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@101958.4] assign _T_863 = io_in_d_valid & _T_862; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@101959.4] assign _T_864 = io_in_d_bits_opcode == _T_856; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@101961.6] assign _T_866 = _T_864 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101963.6] assign _T_867 = _T_866 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101964.6] assign _T_868 = io_in_d_bits_param == _T_857; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@101969.6] assign _T_870 = _T_868 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101971.6] assign _T_871 = _T_870 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101972.6] assign _T_872 = io_in_d_bits_size == _T_858; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@101977.6] assign _T_874 = _T_872 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101979.6] assign _T_875 = _T_874 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101980.6] assign _T_880 = io_in_d_bits_sink == _T_860; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@101993.6] assign _T_882 = _T_880 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101995.6] assign _T_883 = _T_882 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101996.6] assign _T_884 = io_in_d_bits_denied == _T_861; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@102001.6] assign _T_886 = _T_884 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102003.6] assign _T_887 = _T_886 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102004.6] assign _T_889 = io_in_d_valid & _T_848; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@102011.4] assign _T_902 = _T_900 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@102032.4] assign _T_903 = _T_900 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@102033.4] assign _T_921 = _T_919 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@102054.4] assign _T_922 = _T_919 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@102055.4] assign _T_932 = _T_788 & _T_903; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@102070.4] assign _T_937 = _T_890 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@102077.6] assign _T_939 = _T_937 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102079.6] assign _T_940 = _T_939 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102080.6] assign _GEN_15 = _T_932 ? 2'h1 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@102072.4] assign _T_944 = io_in_d_valid & _T_922; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@102091.4] assign _T_946 = _T_647 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@102093.4] assign _T_947 = _T_944 & _T_946; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@102094.4] assign _T_930 = _GEN_15[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@102066.4 :freechips.rocketchip.system.TinyConfig.fir@102068.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@102074.6] assign _T_949 = _T_930 | _T_890; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@102098.6] assign _T_953 = _T_949 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102102.6] assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102103.6] assign _GEN_16 = _T_947 ? 2'h1 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@102095.4] assign _T_941 = _GEN_16[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@102086.4 :freechips.rocketchip.system.TinyConfig.fir@102088.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@102097.6] assign _T_955 = _T_930 != _T_941; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@102109.4] assign _T_957 = _T_930 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@102111.4] assign _T_958 = _T_955 | _T_957; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@102112.4] assign _T_960 = _T_958 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102114.4] assign _T_961 = _T_960 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102115.4] assign _T_962 = _T_890 | _T_930; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@102120.4] assign _T_963 = ~ _T_941; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@102121.4] assign _T_964 = _T_962 & _T_963; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@102122.4] assign _T_968 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@102129.4] assign _T_969 = _T_937 | _T_968; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@102130.4] assign _T_970 = _T_965 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@102131.4] assign _T_971 = _T_969 | _T_970; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@102132.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102134.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102135.4] assign _T_976 = _T_965 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@102141.4] assign _T_979 = _T_788 | io_in_d_valid; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@102145.4] assign _GEN_18 = io_in_d_valid & _T_647; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101573.10] assign _GEN_26 = io_in_d_valid & _T_667; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@101614.10] assign _GEN_36 = io_in_d_valid & _T_695; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@101672.10] assign _GEN_46 = io_in_d_valid & _T_724; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@101732.10] assign _GEN_50 = io_in_d_valid & _T_741; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@101767.10] assign _GEN_54 = io_in_d_valid & _T_759; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@101803.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_797 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_812 = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_845 = _RAND_2[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_856 = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_857 = _RAND_4[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_858 = _RAND_5[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_860 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_861 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_890 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_900 = _RAND_9[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_919 = _RAND_10[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_965 = _RAND_11[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_797 <= 10'h0; end else begin if (_T_788) begin if (_T_800) begin _T_797 <= 10'h0; end else begin _T_797 <= _T_799; end end end if (_T_836) begin _T_812 <= io_in_a_bits_address; end if (reset) begin _T_845 <= 10'h0; end else begin if (io_in_d_valid) begin if (_T_848) begin if (_T_843) begin _T_845 <= _T_842; end else begin _T_845 <= 10'h0; end end else begin _T_845 <= _T_847; end end end if (_T_889) begin _T_856 <= io_in_d_bits_opcode; end if (_T_889) begin _T_857 <= io_in_d_bits_param; end if (_T_889) begin _T_858 <= io_in_d_bits_size; end if (_T_889) begin _T_860 <= io_in_d_bits_sink; end if (_T_889) begin _T_861 <= io_in_d_bits_denied; end if (reset) begin _T_890 <= 1'h0; end else begin _T_890 <= _T_964; end if (reset) begin _T_900 <= 10'h0; end else begin if (_T_788) begin if (_T_903) begin _T_900 <= 10'h0; end else begin _T_900 <= _T_902; end end end if (reset) begin _T_919 <= 10'h0; end else begin if (io_in_d_valid) begin if (_T_922) begin if (_T_843) begin _T_919 <= _T_842; end else begin _T_919 <= 10'h0; end end else begin _T_919 <= _T_921; end end end if (reset) begin _T_965 <= 32'h0; end else begin if (_T_979) begin _T_965 <= 32'h0; end else begin _T_965 <= _T_976; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_a_valid & _T_264) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Frontend.scala:350:21)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101035.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_a_valid & _T_264) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@101036.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_a_valid & _T_117) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Frontend.scala:350:21)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@101049.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_a_valid & _T_117) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@101050.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_643) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Frontend.scala:350:21)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101551.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_643) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@101552.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Frontend.scala:350:21)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101573.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_654) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@101574.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Frontend.scala:350:21)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101581.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_658) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@101582.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101589.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_662) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@101590.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_18 & _T_666) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Frontend.scala:350:21)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101597.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_18 & _T_666) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@101598.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Frontend.scala:350:21)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@101614.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_104) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@101615.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Frontend.scala:350:21)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@101622.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_654) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@101623.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Frontend.scala:350:21)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101630.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_681) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@101631.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Frontend.scala:350:21)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_685) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@101639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_26 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@101646.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_26 & _T_662) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@101647.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Frontend.scala:350:21)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@101672.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_104) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@101673.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Frontend.scala:350:21)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@101680.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_654) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@101681.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_681) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Frontend.scala:350:21)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@101688.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_681) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@101689.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_685) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Frontend.scala:350:21)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@101696.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_685) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@101697.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_36 & _T_718) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101705.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_36 & _T_718) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@101706.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_46 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Frontend.scala:350:21)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@101732.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_46 & _T_658) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@101733.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_46 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@101740.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_46 & _T_662) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@101741.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_50 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Frontend.scala:350:21)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@101767.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_50 & _T_658) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@101768.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_50 & _T_718) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@101776.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_50 & _T_718) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@101777.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_54 & _T_658) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Frontend.scala:350:21)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@101803.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_54 & _T_658) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@101804.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_54 & _T_662) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Frontend.scala:350:21)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@101811.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_54 & _T_662) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@101812.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_814 & _T_834) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101917.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_814 & _T_834) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@101918.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_867) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101966.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_867) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@101967.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_871) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101974.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_871) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@101975.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_875) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101982.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_875) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@101983.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_883) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101998.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_883) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@101999.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_863 & _T_887) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Frontend.scala:350:21)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102006.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_863 & _T_887) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@102007.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_932 & _T_940) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Frontend.scala:350:21)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102082.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_932 & _T_940) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@102083.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_947 & _T_954) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:350:21)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102105.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_947 & _T_954) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@102106.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_961) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at Frontend.scala:350:21)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102117.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_961) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@102118.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Frontend.scala:350:21)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102137.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@102138.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_8( // @[:freechips.rocketchip.system.TinyConfig.fir@102150.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@102151.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@102152.4] output auto_in_1_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_in_1_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [31:0] auto_in_1_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_in_1_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [2:0] auto_in_1_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [3:0] auto_in_1_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [31:0] auto_in_1_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_in_1_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_in_0_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_in_0_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [2:0] auto_in_0_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [2:0] auto_in_0_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [3:0] auto_in_0_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [31:0] auto_in_0_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [3:0] auto_in_0_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [31:0] auto_in_0_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_in_0_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_in_0_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [2:0] auto_in_0_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [3:0] auto_in_0_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_in_0_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [31:0] auto_in_0_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@102153.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] wire TLMonitor_1_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire [31:0] TLMonitor_1_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire [2:0] TLMonitor_1_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire [1:0] TLMonitor_1_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire [3:0] TLMonitor_1_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire TLMonitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] wire requestDOI_0_1; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@102372.4] wire [26:0] _T_72; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@102378.4] wire [11:0] _T_73; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@102379.4] wire [11:0] _T_74; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@102380.4] wire [9:0] _T_75; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@102381.4] wire _T_76; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@102382.4] wire _T_77; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@102383.4] wire _T_144; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102492.4] reg [9:0] _T_156; // @[Arbiter.scala 53:30:freechips.rocketchip.system.TinyConfig.fir@102516.4] reg [31:0] _RAND_0; wire _T_157; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@102517.4] wire _T_158; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@102518.4] wire [1:0] _T_159; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@102519.4] wire _T_161; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@102521.4] wire _T_163; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102523.4] wire _T_164; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102524.4] reg [1:0] _T_166; // @[Arbiter.scala 20:23:freechips.rocketchip.system.TinyConfig.fir@102530.4] reg [31:0] _RAND_1; wire [1:0] _T_167; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@102531.4] wire [1:0] _T_168; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@102532.4] wire [3:0] _T_169; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@102533.4] wire [2:0] _T_170; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@102534.4] wire [3:0] _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@102535.4] wire [3:0] _T_171; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@102535.4] wire [2:0] _T_173; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@102537.4] wire [3:0] _T_174; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@102538.4] wire [3:0] _GEN_2; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@102539.4] wire [3:0] _T_175; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@102539.4] wire [1:0] _T_176; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@102540.4] wire [1:0] _T_177; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@102541.4] wire [1:0] _T_178; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@102542.4] wire [1:0] _T_179; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@102543.4] wire _T_180; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@102544.4] wire _T_181; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@102545.4] wire [1:0] _T_182; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@102547.6] wire [2:0] _T_183; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@102548.6] wire [1:0] _T_184; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@102549.6] wire [1:0] _T_185; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@102550.6] wire _T_188; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@102555.4] wire _T_189; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@102556.4] wire _T_191; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@102561.4] wire _T_192; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@102562.4] wire _T_195; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@102568.4] wire _T_197; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@102570.4] wire _T_200; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@102573.4] wire _T_201; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@102574.4] wire _T_204; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102577.4] wire _T_205; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102578.4] wire _T_206; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@102583.4] wire _T_207; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@102584.4] wire _T_209; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@102586.4] wire _T_211; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102588.4] wire _T_212; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102589.4] reg _T_221_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@102606.4] reg [31:0] _RAND_2; wire _T_227; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102615.4] reg _T_221_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.TinyConfig.fir@102606.4] reg [31:0] _RAND_3; wire _T_228; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102616.4] wire _T_229; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102617.4] wire out_0_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@102620.4] wire _T_216; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@102597.4] wire [9:0] _GEN_3; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@102598.4] wire [9:0] _T_218; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@102599.4] wire _T_222_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@102607.4] wire _T_222_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@102607.4] wire _T_223_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@102609.4] wire _T_223_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@102609.4] wire [79:0] _T_238; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102628.4] wire [79:0] _T_239; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102629.4] wire [79:0] _T_246; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102636.4] wire [79:0] _T_247; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102637.4] wire [79:0] _T_248; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102638.4] TLMonitor_35 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102162.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); TLMonitor_36 TLMonitor_1 ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@102211.4] .clock(TLMonitor_1_clock), .reset(TLMonitor_1_reset), .io_in_a_ready(TLMonitor_1_io_in_a_ready), .io_in_a_valid(TLMonitor_1_io_in_a_valid), .io_in_a_bits_address(TLMonitor_1_io_in_a_bits_address), .io_in_d_valid(TLMonitor_1_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_1_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_1_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_1_io_in_d_bits_size), .io_in_d_bits_sink(TLMonitor_1_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_1_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_1_io_in_d_bits_corrupt) ); assign requestDOI_0_1 = auto_out_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@102372.4] assign _T_72 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@102378.4] assign _T_73 = _T_72[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@102379.4] assign _T_74 = ~ _T_73; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@102380.4] assign _T_75 = _T_74[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@102381.4] assign _T_76 = auto_in_0_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@102382.4] assign _T_77 = _T_76 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@102383.4] assign _T_144 = auto_out_d_bits_source ? auto_in_0_d_ready : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102492.4] assign _T_157 = _T_156 == 10'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.TinyConfig.fir@102517.4] assign _T_158 = _T_157 & auto_out_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.TinyConfig.fir@102518.4] assign _T_159 = {auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@102519.4] assign _T_161 = _T_159 == _T_159; // @[Arbiter.scala 19:19:freechips.rocketchip.system.TinyConfig.fir@102521.4] assign _T_163 = _T_161 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102523.4] assign _T_164 = _T_163 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102524.4] assign _T_167 = ~ _T_166; // @[Arbiter.scala 21:30:freechips.rocketchip.system.TinyConfig.fir@102531.4] assign _T_168 = _T_159 & _T_167; // @[Arbiter.scala 21:28:freechips.rocketchip.system.TinyConfig.fir@102532.4] assign _T_169 = {_T_168,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@102533.4] assign _T_170 = _T_169[3:1]; // @[package.scala 207:48:freechips.rocketchip.system.TinyConfig.fir@102534.4] assign _GEN_1 = {{1'd0}, _T_170}; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@102535.4] assign _T_171 = _T_169 | _GEN_1; // @[package.scala 207:43:freechips.rocketchip.system.TinyConfig.fir@102535.4] assign _T_173 = _T_171[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.TinyConfig.fir@102537.4] assign _T_174 = {_T_166, 2'h0}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.TinyConfig.fir@102538.4] assign _GEN_2 = {{1'd0}, _T_173}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@102539.4] assign _T_175 = _GEN_2 | _T_174; // @[Arbiter.scala 22:58:freechips.rocketchip.system.TinyConfig.fir@102539.4] assign _T_176 = _T_175[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.TinyConfig.fir@102540.4] assign _T_177 = _T_175[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.TinyConfig.fir@102541.4] assign _T_178 = _T_176 & _T_177; // @[Arbiter.scala 23:39:freechips.rocketchip.system.TinyConfig.fir@102542.4] assign _T_179 = ~ _T_178; // @[Arbiter.scala 23:18:freechips.rocketchip.system.TinyConfig.fir@102543.4] assign _T_180 = _T_159 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.TinyConfig.fir@102544.4] assign _T_181 = _T_158 & _T_180; // @[Arbiter.scala 24:18:freechips.rocketchip.system.TinyConfig.fir@102545.4] assign _T_182 = _T_179 & _T_159; // @[Arbiter.scala 25:29:freechips.rocketchip.system.TinyConfig.fir@102547.6] assign _T_183 = {_T_182, 1'h0}; // @[package.scala 198:48:freechips.rocketchip.system.TinyConfig.fir@102548.6] assign _T_184 = _T_183[1:0]; // @[package.scala 198:53:freechips.rocketchip.system.TinyConfig.fir@102549.6] assign _T_185 = _T_182 | _T_184; // @[package.scala 198:43:freechips.rocketchip.system.TinyConfig.fir@102550.6] assign _T_188 = _T_179[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@102555.4] assign _T_189 = _T_179[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.TinyConfig.fir@102556.4] assign _T_191 = _T_188 & auto_in_0_a_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@102561.4] assign _T_192 = _T_189 & auto_in_1_a_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.TinyConfig.fir@102562.4] assign _T_195 = _T_191 | _T_192; // @[Arbiter.scala 67:52:freechips.rocketchip.system.TinyConfig.fir@102568.4] assign _T_197 = _T_191 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@102570.4] assign _T_200 = _T_192 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.TinyConfig.fir@102573.4] assign _T_201 = _T_197 | _T_200; // @[Arbiter.scala 68:59:freechips.rocketchip.system.TinyConfig.fir@102574.4] assign _T_204 = _T_201 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102577.4] assign _T_205 = _T_204 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102578.4] assign _T_206 = auto_in_0_a_valid | auto_in_1_a_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.TinyConfig.fir@102583.4] assign _T_207 = _T_206 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.TinyConfig.fir@102584.4] assign _T_209 = _T_207 | _T_195; // @[Arbiter.scala 70:36:freechips.rocketchip.system.TinyConfig.fir@102586.4] assign _T_211 = _T_209 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102588.4] assign _T_212 = _T_211 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102589.4] assign _T_227 = _T_221_0 ? auto_in_0_a_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102615.4] assign _T_228 = _T_221_1 ? auto_in_1_a_valid : 1'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102616.4] assign _T_229 = _T_227 | _T_228; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102617.4] assign out_0_a_valid = _T_157 ? _T_206 : _T_229; // @[Arbiter.scala 86:24:freechips.rocketchip.system.TinyConfig.fir@102620.4] assign _T_216 = auto_out_a_ready & out_0_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@102597.4] assign _GEN_3 = {{9'd0}, _T_216}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@102598.4] assign _T_218 = _T_156 - _GEN_3; // @[Arbiter.scala 75:52:freechips.rocketchip.system.TinyConfig.fir@102599.4] assign _T_222_0 = _T_157 ? _T_191 : _T_221_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@102607.4] assign _T_222_1 = _T_157 ? _T_192 : _T_221_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.TinyConfig.fir@102607.4] assign _T_223_0 = _T_157 ? _T_188 : _T_221_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@102609.4] assign _T_223_1 = _T_157 ? _T_189 : _T_221_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@102609.4] assign _T_238 = {auto_in_0_a_bits_opcode,auto_in_0_a_bits_param,auto_in_0_a_bits_size,1'h1,auto_in_0_a_bits_address,auto_in_0_a_bits_mask,auto_in_0_a_bits_data,1'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102628.4] assign _T_239 = _T_222_0 ? _T_238 : 80'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102629.4] assign _T_246 = {11'h40c,auto_in_1_a_bits_address,4'hf,33'h0}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102636.4] assign _T_247 = _T_222_1 ? _T_246 : 80'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102637.4] assign _T_248 = _T_239 | _T_247; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@102638.4] assign auto_in_1_a_ready = auto_out_a_ready & _T_223_1; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_1_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_1_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102264.4] assign auto_in_0_a_ready = auto_out_a_ready & _T_223_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_in_0_d_valid = auto_out_d_valid & auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102263.4] assign auto_out_a_valid = _T_157 ? _T_206 : _T_229; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_opcode = _T_248[79:77]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_param = _T_248[76:74]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_size = _T_248[73:70]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_source = _T_248[69]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_address = _T_248[68:37]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_mask = _T_248[36:33]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_data = _T_248[32:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_a_bits_corrupt = _T_248[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign auto_out_d_ready = _T_144 | requestDOI_0_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102262.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@102164.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@102165.4] assign TLMonitor_io_in_a_ready = auto_out_a_ready & _T_223_0; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_valid = auto_out_d_valid & auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102210.4] assign TLMonitor_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@102213.4] assign TLMonitor_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@102214.4] assign TLMonitor_1_io_in_a_ready = auto_out_a_ready & _T_223_1; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] assign TLMonitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@102259.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_156 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_166 = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_221_0 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_221_1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_156 <= 10'h0; end else begin if (_T_158) begin if (_T_191) begin if (_T_77) begin _T_156 <= _T_75; end else begin _T_156 <= 10'h0; end end else begin _T_156 <= 10'h0; end end else begin _T_156 <= _T_218; end end if (reset) begin _T_166 <= 2'h3; end else begin if (_T_181) begin _T_166 <= _T_185; end end if (reset) begin _T_221_0 <= 1'h0; end else begin if (_T_157) begin _T_221_0 <= _T_191; end end if (reset) begin _T_221_1 <= 1'h0; end else begin if (_T_157) begin _T_221_1 <= _T_192; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_164) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102526.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_164) begin $fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.TinyConfig.fir@102527.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_205) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102580.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_205) begin $fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.TinyConfig.fir@102581.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_212) begin $fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102591.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_212) begin $fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@102592.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLXbar_9( // @[:freechips.rocketchip.system.TinyConfig.fir@102674.2] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@102677.4] ); assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@102687.4] assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102686.4] endmodule module IntXbar_4( // @[:freechips.rocketchip.system.TinyConfig.fir@102861.2] input auto_int_in_2_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] input auto_int_in_1_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] input auto_int_in_1_1, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] input auto_int_in_0_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] output auto_int_out_1, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] output auto_int_out_2, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] output auto_int_out_3 // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4] ); assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4] assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4] assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4] assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4] endmodule module DCacheModuleanon2( // @[:freechips.rocketchip.system.TinyConfig.fir@102989.2] input io_in_2_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input [31:0] io_in_2_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input io_in_3_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input [31:0] io_in_3_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] output io_in_5_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input io_in_5_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] output io_in_7_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input io_in_7_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] input [31:0] io_in_7_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] output io_out_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] output io_out_bits_write, // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] output [31:0] io_out_bits_addr // @[:freechips.rocketchip.system.TinyConfig.fir@102992.4] ); wire [31:0] _GEN_22; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103024.4] wire _T_2; // @[Arbiter.scala 31:68:freechips.rocketchip.system.TinyConfig.fir@103058.4] wire _T_9; // @[Arbiter.scala 31:78:freechips.rocketchip.system.TinyConfig.fir@103065.4] wire _T_21; // @[Arbiter.scala 135:19:freechips.rocketchip.system.TinyConfig.fir@103085.4] assign _GEN_22 = io_in_3_valid ? io_in_3_bits_addr : io_in_7_bits_addr; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103024.4] assign _T_2 = io_in_2_valid | io_in_3_valid; // @[Arbiter.scala 31:68:freechips.rocketchip.system.TinyConfig.fir@103058.4] assign _T_9 = _T_2 == 1'h0; // @[Arbiter.scala 31:78:freechips.rocketchip.system.TinyConfig.fir@103065.4] assign _T_21 = _T_9 == 1'h0; // @[Arbiter.scala 135:19:freechips.rocketchip.system.TinyConfig.fir@103085.4] assign io_in_5_ready = _T_2 == 1'h0; // @[Arbiter.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@103080.4] assign io_in_7_ready = _T_2 == 1'h0; // @[Arbiter.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@103084.4] assign io_out_valid = _T_21 | io_in_7_valid; // @[Arbiter.scala 135:16:freechips.rocketchip.system.TinyConfig.fir@103087.4] assign io_out_bits_write = io_in_2_valid ? 1'h1 : io_in_3_valid; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@102999.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103006.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103014.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103022.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103030.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103038.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103046.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103054.6] assign io_out_bits_addr = io_in_2_valid ? io_in_2_bits_addr : _GEN_22; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@102998.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103005.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103013.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103021.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103029.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103037.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103045.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103053.6] endmodule module DCacheDataArray( // @[:freechips.rocketchip.system.TinyConfig.fir@103089.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@103090.4] input io_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] input [7:0] io_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] input io_req_bits_write, // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] input [31:0] io_req_bits_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] input [3:0] io_req_bits_eccMask, // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] output [31:0] io_resp_0 // @[:freechips.rocketchip.system.TinyConfig.fir@103092.4] ); wire [5:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_en; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_wdata_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_wdata_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_wdata_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_rdata_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_rdata_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire [7:0] data_arrays_0_RW0_rdata_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_wmask_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_wmask_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_wmask_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire data_arrays_0_RW0_wmask_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] wire _T_3; // @[DCache.scala 64:17:freechips.rocketchip.system.TinyConfig.fir@103107.4] wire _T_10; // @[DCache.scala 68:42:freechips.rocketchip.system.TinyConfig.fir@103133.4] wire _T_11; // @[DCache.scala 68:39:freechips.rocketchip.system.TinyConfig.fir@103134.4] wire [15:0] _T_16; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@103144.4] wire [15:0] _T_17; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@103145.4] data_arrays_0 data_arrays_0 ( // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@103103.4] .RW0_addr(data_arrays_0_RW0_addr), .RW0_en(data_arrays_0_RW0_en), .RW0_clk(data_arrays_0_RW0_clk), .RW0_wmode(data_arrays_0_RW0_wmode), .RW0_wdata_0(data_arrays_0_RW0_wdata_0), .RW0_wdata_1(data_arrays_0_RW0_wdata_1), .RW0_wdata_2(data_arrays_0_RW0_wdata_2), .RW0_wdata_3(data_arrays_0_RW0_wdata_3), .RW0_rdata_0(data_arrays_0_RW0_rdata_0), .RW0_rdata_1(data_arrays_0_RW0_rdata_1), .RW0_rdata_2(data_arrays_0_RW0_rdata_2), .RW0_rdata_3(data_arrays_0_RW0_rdata_3), .RW0_wmask_0(data_arrays_0_RW0_wmask_0), .RW0_wmask_1(data_arrays_0_RW0_wmask_1), .RW0_wmask_2(data_arrays_0_RW0_wmask_2), .RW0_wmask_3(data_arrays_0_RW0_wmask_3) ); assign _T_3 = io_req_valid & io_req_bits_write; // @[DCache.scala 64:17:freechips.rocketchip.system.TinyConfig.fir@103107.4] assign _T_10 = io_req_bits_write == 1'h0; // @[DCache.scala 68:42:freechips.rocketchip.system.TinyConfig.fir@103133.4] assign _T_11 = io_req_valid & _T_10; // @[DCache.scala 68:39:freechips.rocketchip.system.TinyConfig.fir@103134.4] assign _T_16 = {data_arrays_0_RW0_rdata_1,data_arrays_0_RW0_rdata_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@103144.4] assign _T_17 = {data_arrays_0_RW0_rdata_3,data_arrays_0_RW0_rdata_2}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@103145.4] assign io_resp_0 = {_T_17,_T_16}; // @[DCache.scala 71:69:freechips.rocketchip.system.TinyConfig.fir@103147.4] assign data_arrays_0_RW0_wdata_0 = io_req_bits_wdata[7:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@103121.8] assign data_arrays_0_RW0_wdata_1 = io_req_bits_wdata[15:8]; // @[:freechips.rocketchip.system.TinyConfig.fir@103124.8] assign data_arrays_0_RW0_wdata_2 = io_req_bits_wdata[23:16]; // @[:freechips.rocketchip.system.TinyConfig.fir@103127.8] assign data_arrays_0_RW0_wdata_3 = io_req_bits_wdata[31:24]; // @[:freechips.rocketchip.system.TinyConfig.fir@103130.8] assign data_arrays_0_RW0_wmask_0 = io_req_bits_eccMask[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@103119.6 :freechips.rocketchip.system.TinyConfig.fir@103121.8] assign data_arrays_0_RW0_wmask_1 = io_req_bits_eccMask[1]; // @[:freechips.rocketchip.system.TinyConfig.fir@103119.6 :freechips.rocketchip.system.TinyConfig.fir@103124.8] assign data_arrays_0_RW0_wmask_2 = io_req_bits_eccMask[2]; // @[:freechips.rocketchip.system.TinyConfig.fir@103119.6 :freechips.rocketchip.system.TinyConfig.fir@103127.8] assign data_arrays_0_RW0_wmask_3 = io_req_bits_eccMask[3]; // @[:freechips.rocketchip.system.TinyConfig.fir@103119.6 :freechips.rocketchip.system.TinyConfig.fir@103130.8] assign data_arrays_0_RW0_wmode = io_req_bits_write; assign data_arrays_0_RW0_clk = clock; assign data_arrays_0_RW0_en = _T_11 | _T_3; assign data_arrays_0_RW0_addr = io_req_bits_addr[7:2]; endmodule module DCacheModuleanon3( // @[:freechips.rocketchip.system.TinyConfig.fir@103149.2] input io_in_0_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [7:0] io_in_0_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input io_in_0_bits_write, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [31:0] io_in_0_bits_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [3:0] io_in_0_bits_eccMask, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output io_in_1_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input io_in_1_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [7:0] io_in_1_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input io_in_1_bits_write, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [31:0] io_in_1_bits_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [3:0] io_in_1_bits_eccMask, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output io_in_3_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input io_in_3_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [7:0] io_in_3_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [31:0] io_in_3_bits_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] input [3:0] io_in_3_bits_eccMask, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output io_out_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output [7:0] io_out_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output io_out_bits_write, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output [31:0] io_out_bits_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] output [3:0] io_out_bits_eccMask // @[:freechips.rocketchip.system.TinyConfig.fir@103152.4] ); wire [3:0] _GEN_9; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] wire [31:0] _GEN_11; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] wire _GEN_12; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] wire [7:0] _GEN_13; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] wire _T; // @[Arbiter.scala 31:68:freechips.rocketchip.system.TinyConfig.fir@103188.4] wire _T_3; // @[Arbiter.scala 31:78:freechips.rocketchip.system.TinyConfig.fir@103191.4] wire _T_9; // @[Arbiter.scala 135:19:freechips.rocketchip.system.TinyConfig.fir@103201.4] assign _GEN_9 = io_in_1_valid ? io_in_1_bits_eccMask : io_in_3_bits_eccMask; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] assign _GEN_11 = io_in_1_valid ? io_in_1_bits_wdata : io_in_3_bits_wdata; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] assign _GEN_12 = io_in_1_valid ? io_in_1_bits_write : 1'h0; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] assign _GEN_13 = io_in_1_valid ? io_in_1_bits_addr : io_in_3_bits_addr; // @[Arbiter.scala 126:27:freechips.rocketchip.system.TinyConfig.fir@103170.4] assign _T = io_in_0_valid | io_in_1_valid; // @[Arbiter.scala 31:68:freechips.rocketchip.system.TinyConfig.fir@103188.4] assign _T_3 = _T == 1'h0; // @[Arbiter.scala 31:78:freechips.rocketchip.system.TinyConfig.fir@103191.4] assign _T_9 = _T_3 == 1'h0; // @[Arbiter.scala 135:19:freechips.rocketchip.system.TinyConfig.fir@103201.4] assign io_in_1_ready = io_in_0_valid == 1'h0; // @[Arbiter.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@103196.4] assign io_in_3_ready = _T == 1'h0; // @[Arbiter.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@103200.4] assign io_out_valid = _T_9 | io_in_3_valid; // @[Arbiter.scala 135:16:freechips.rocketchip.system.TinyConfig.fir@103203.4] assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : _GEN_13; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@103160.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103168.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103177.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103186.6] assign io_out_bits_write = io_in_0_valid ? io_in_0_bits_write : _GEN_12; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@103159.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103167.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103176.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103185.6] assign io_out_bits_wdata = io_in_0_valid ? io_in_0_bits_wdata : _GEN_11; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@103158.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103166.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103175.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103184.6] assign io_out_bits_eccMask = io_in_0_valid ? io_in_0_bits_eccMask : _GEN_9; // @[Arbiter.scala 124:15:freechips.rocketchip.system.TinyConfig.fir@103156.4 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103164.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103173.6 Arbiter.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@103182.6] endmodule module PMPChecker( // @[:freechips.rocketchip.system.TinyConfig.fir@103215.2] input io_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [1:0] io_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input io_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [29:0] io_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_pmp_7_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] input [31:0] io_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] output io_r, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] output io_w, // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] output io_x // @[:freechips.rocketchip.system.TinyConfig.fir@103218.4] ); wire _T_10; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103251.4] wire [31:0] _T_11; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103252.4] wire [31:0] _T_12; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103253.4] wire [31:0] _T_13; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103254.4] wire [31:0] _T_14; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103255.4] wire [31:0] _T_15; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103256.4] wire [31:0] _T_16; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103257.4] wire [31:0] _T_17; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103258.4] wire _T_18; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103259.4] wire _T_19; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103260.4] wire [31:0] _T_24; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103265.4] wire [31:0] _T_25; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103266.4] wire [31:0] _T_26; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103267.4] wire [31:0] _T_27; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103268.4] wire _T_28; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103269.4] wire _T_29; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103270.4] wire _T_34; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103275.4] wire _T_35; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103276.4] wire _T_36; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103277.4] wire _T_37; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103278.4] wire _T_38; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103279.4] wire _T_91; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103334.4] wire _T_93; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103337.4] wire _T_95; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103340.4] wire _T_97_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] wire _T_97_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] wire _T_97_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] wire _T_98; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103344.4] wire [31:0] _T_103; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103349.4] wire [31:0] _T_104; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103350.4] wire [31:0] _T_105; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103351.4] wire _T_106; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103352.4] wire _T_107; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103353.4] wire [31:0] _T_112; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103358.4] wire [31:0] _T_113; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103359.4] wire [31:0] _T_114; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103360.4] wire [31:0] _T_115; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103361.4] wire _T_116; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103362.4] wire _T_117; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103363.4] wire _T_123; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103369.4] wire _T_124; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103370.4] wire _T_125; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103371.4] wire _T_126; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103372.4] wire _T_179; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103427.4] wire _T_181; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103430.4] wire _T_183; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103433.4] wire _T_185_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] wire _T_185_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] wire _T_185_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] wire _T_186; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103437.4] wire [31:0] _T_191; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103442.4] wire [31:0] _T_192; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103443.4] wire [31:0] _T_193; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103444.4] wire _T_194; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103445.4] wire _T_195; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103446.4] wire [31:0] _T_200; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103451.4] wire [31:0] _T_201; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103452.4] wire [31:0] _T_202; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103453.4] wire [31:0] _T_203; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103454.4] wire _T_204; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103455.4] wire _T_205; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103456.4] wire _T_211; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103462.4] wire _T_212; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103463.4] wire _T_213; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103464.4] wire _T_214; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103465.4] wire _T_267; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103520.4] wire _T_269; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103523.4] wire _T_271; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103526.4] wire _T_273_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] wire _T_273_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] wire _T_273_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] wire _T_274; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103530.4] wire [31:0] _T_279; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103535.4] wire [31:0] _T_280; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103536.4] wire [31:0] _T_281; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103537.4] wire _T_282; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103538.4] wire _T_283; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103539.4] wire [31:0] _T_288; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103544.4] wire [31:0] _T_289; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103545.4] wire [31:0] _T_290; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103546.4] wire [31:0] _T_291; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103547.4] wire _T_292; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103548.4] wire _T_293; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103549.4] wire _T_299; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103555.4] wire _T_300; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103556.4] wire _T_301; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103557.4] wire _T_302; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103558.4] wire _T_355; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103613.4] wire _T_357; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103616.4] wire _T_359; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103619.4] wire _T_361_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] wire _T_361_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] wire _T_361_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] wire _T_362; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103623.4] wire [31:0] _T_367; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103628.4] wire [31:0] _T_368; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103629.4] wire [31:0] _T_369; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103630.4] wire _T_370; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103631.4] wire _T_371; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103632.4] wire [31:0] _T_376; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103637.4] wire [31:0] _T_377; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103638.4] wire [31:0] _T_378; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103639.4] wire [31:0] _T_379; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103640.4] wire _T_380; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103641.4] wire _T_381; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103642.4] wire _T_387; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103648.4] wire _T_388; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103649.4] wire _T_389; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103650.4] wire _T_390; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103651.4] wire _T_443; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103706.4] wire _T_445; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103709.4] wire _T_447; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103712.4] wire _T_449_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] wire _T_449_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] wire _T_449_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] wire _T_450; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103716.4] wire [31:0] _T_455; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103721.4] wire [31:0] _T_456; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103722.4] wire [31:0] _T_457; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103723.4] wire _T_458; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103724.4] wire _T_459; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103725.4] wire [31:0] _T_464; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103730.4] wire [31:0] _T_465; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103731.4] wire [31:0] _T_466; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103732.4] wire [31:0] _T_467; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103733.4] wire _T_468; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103734.4] wire _T_469; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103735.4] wire _T_475; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103741.4] wire _T_476; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103742.4] wire _T_477; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103743.4] wire _T_478; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103744.4] wire _T_531; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103799.4] wire _T_533; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103802.4] wire _T_535; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103805.4] wire _T_537_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] wire _T_537_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] wire _T_537_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] wire _T_538; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103809.4] wire [31:0] _T_543; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103814.4] wire [31:0] _T_544; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103815.4] wire [31:0] _T_545; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103816.4] wire _T_546; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103817.4] wire _T_547; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103818.4] wire [31:0] _T_552; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103823.4] wire [31:0] _T_553; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103824.4] wire [31:0] _T_554; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103825.4] wire [31:0] _T_555; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103826.4] wire _T_556; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103827.4] wire _T_557; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103828.4] wire _T_563; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103834.4] wire _T_564; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103835.4] wire _T_565; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103836.4] wire _T_566; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103837.4] wire _T_619; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103892.4] wire _T_621; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103895.4] wire _T_623; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103898.4] wire _T_625_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] wire _T_625_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] wire _T_625_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] wire _T_626; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103902.4] wire [31:0] _T_631; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103907.4] wire [31:0] _T_632; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103908.4] wire [31:0] _T_633; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103909.4] wire _T_634; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103910.4] wire _T_635; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103911.4] wire _T_652; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103928.4] wire _T_653; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103929.4] wire _T_654; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103930.4] wire _T_707; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103985.4] wire _T_709; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103988.4] wire _T_711; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103991.4] assign _T_10 = io_pmp_7_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103251.4] assign _T_11 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103252.4] assign _T_12 = ~ _T_11; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103253.4] assign _T_13 = _T_12 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103254.4] assign _T_14 = ~ _T_13; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103255.4] assign _T_15 = io_addr ^ _T_14; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103256.4] assign _T_16 = ~ io_pmp_7_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103257.4] assign _T_17 = _T_15 & _T_16; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103258.4] assign _T_18 = _T_17 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103259.4] assign _T_19 = io_pmp_7_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103260.4] assign _T_24 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103265.4] assign _T_25 = ~ _T_24; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103266.4] assign _T_26 = _T_25 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103267.4] assign _T_27 = ~ _T_26; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103268.4] assign _T_28 = io_addr < _T_27; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103269.4] assign _T_29 = _T_28 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103270.4] assign _T_34 = io_addr < _T_14; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103275.4] assign _T_35 = _T_29 & _T_34; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103276.4] assign _T_36 = _T_19 & _T_35; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103277.4] assign _T_37 = _T_10 ? _T_18 : _T_36; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103278.4] assign _T_38 = io_pmp_7_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103279.4] assign _T_91 = io_pmp_7_cfg_r | _T_38; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103334.4] assign _T_93 = io_pmp_7_cfg_w | _T_38; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103337.4] assign _T_95 = io_pmp_7_cfg_x | _T_38; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103340.4] assign _T_97_cfg_x = _T_37 ? _T_95 : 1'h1; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] assign _T_97_cfg_w = _T_37 ? _T_93 : 1'h1; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] assign _T_97_cfg_r = _T_37 ? _T_91 : 1'h1; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103343.4] assign _T_98 = io_pmp_6_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103344.4] assign _T_103 = io_addr ^ _T_27; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103349.4] assign _T_104 = ~ io_pmp_6_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103350.4] assign _T_105 = _T_103 & _T_104; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103351.4] assign _T_106 = _T_105 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103352.4] assign _T_107 = io_pmp_6_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103353.4] assign _T_112 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103358.4] assign _T_113 = ~ _T_112; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103359.4] assign _T_114 = _T_113 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103360.4] assign _T_115 = ~ _T_114; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103361.4] assign _T_116 = io_addr < _T_115; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103362.4] assign _T_117 = _T_116 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103363.4] assign _T_123 = _T_117 & _T_28; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103369.4] assign _T_124 = _T_107 & _T_123; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103370.4] assign _T_125 = _T_98 ? _T_106 : _T_124; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103371.4] assign _T_126 = io_pmp_6_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103372.4] assign _T_179 = io_pmp_6_cfg_r | _T_126; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103427.4] assign _T_181 = io_pmp_6_cfg_w | _T_126; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103430.4] assign _T_183 = io_pmp_6_cfg_x | _T_126; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103433.4] assign _T_185_cfg_x = _T_125 ? _T_183 : _T_97_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] assign _T_185_cfg_w = _T_125 ? _T_181 : _T_97_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] assign _T_185_cfg_r = _T_125 ? _T_179 : _T_97_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103436.4] assign _T_186 = io_pmp_5_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103437.4] assign _T_191 = io_addr ^ _T_115; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103442.4] assign _T_192 = ~ io_pmp_5_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103443.4] assign _T_193 = _T_191 & _T_192; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103444.4] assign _T_194 = _T_193 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103445.4] assign _T_195 = io_pmp_5_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103446.4] assign _T_200 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103451.4] assign _T_201 = ~ _T_200; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103452.4] assign _T_202 = _T_201 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103453.4] assign _T_203 = ~ _T_202; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103454.4] assign _T_204 = io_addr < _T_203; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103455.4] assign _T_205 = _T_204 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103456.4] assign _T_211 = _T_205 & _T_116; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103462.4] assign _T_212 = _T_195 & _T_211; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103463.4] assign _T_213 = _T_186 ? _T_194 : _T_212; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103464.4] assign _T_214 = io_pmp_5_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103465.4] assign _T_267 = io_pmp_5_cfg_r | _T_214; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103520.4] assign _T_269 = io_pmp_5_cfg_w | _T_214; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103523.4] assign _T_271 = io_pmp_5_cfg_x | _T_214; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103526.4] assign _T_273_cfg_x = _T_213 ? _T_271 : _T_185_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] assign _T_273_cfg_w = _T_213 ? _T_269 : _T_185_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] assign _T_273_cfg_r = _T_213 ? _T_267 : _T_185_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103529.4] assign _T_274 = io_pmp_4_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103530.4] assign _T_279 = io_addr ^ _T_203; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103535.4] assign _T_280 = ~ io_pmp_4_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103536.4] assign _T_281 = _T_279 & _T_280; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103537.4] assign _T_282 = _T_281 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103538.4] assign _T_283 = io_pmp_4_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103539.4] assign _T_288 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103544.4] assign _T_289 = ~ _T_288; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103545.4] assign _T_290 = _T_289 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103546.4] assign _T_291 = ~ _T_290; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103547.4] assign _T_292 = io_addr < _T_291; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103548.4] assign _T_293 = _T_292 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103549.4] assign _T_299 = _T_293 & _T_204; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103555.4] assign _T_300 = _T_283 & _T_299; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103556.4] assign _T_301 = _T_274 ? _T_282 : _T_300; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103557.4] assign _T_302 = io_pmp_4_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103558.4] assign _T_355 = io_pmp_4_cfg_r | _T_302; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103613.4] assign _T_357 = io_pmp_4_cfg_w | _T_302; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103616.4] assign _T_359 = io_pmp_4_cfg_x | _T_302; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103619.4] assign _T_361_cfg_x = _T_301 ? _T_359 : _T_273_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] assign _T_361_cfg_w = _T_301 ? _T_357 : _T_273_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] assign _T_361_cfg_r = _T_301 ? _T_355 : _T_273_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103622.4] assign _T_362 = io_pmp_3_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103623.4] assign _T_367 = io_addr ^ _T_291; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103628.4] assign _T_368 = ~ io_pmp_3_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103629.4] assign _T_369 = _T_367 & _T_368; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103630.4] assign _T_370 = _T_369 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103631.4] assign _T_371 = io_pmp_3_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103632.4] assign _T_376 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103637.4] assign _T_377 = ~ _T_376; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103638.4] assign _T_378 = _T_377 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103639.4] assign _T_379 = ~ _T_378; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103640.4] assign _T_380 = io_addr < _T_379; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103641.4] assign _T_381 = _T_380 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103642.4] assign _T_387 = _T_381 & _T_292; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103648.4] assign _T_388 = _T_371 & _T_387; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103649.4] assign _T_389 = _T_362 ? _T_370 : _T_388; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103650.4] assign _T_390 = io_pmp_3_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103651.4] assign _T_443 = io_pmp_3_cfg_r | _T_390; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103706.4] assign _T_445 = io_pmp_3_cfg_w | _T_390; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103709.4] assign _T_447 = io_pmp_3_cfg_x | _T_390; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103712.4] assign _T_449_cfg_x = _T_389 ? _T_447 : _T_361_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] assign _T_449_cfg_w = _T_389 ? _T_445 : _T_361_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] assign _T_449_cfg_r = _T_389 ? _T_443 : _T_361_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103715.4] assign _T_450 = io_pmp_2_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103716.4] assign _T_455 = io_addr ^ _T_379; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103721.4] assign _T_456 = ~ io_pmp_2_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103722.4] assign _T_457 = _T_455 & _T_456; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103723.4] assign _T_458 = _T_457 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103724.4] assign _T_459 = io_pmp_2_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103725.4] assign _T_464 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103730.4] assign _T_465 = ~ _T_464; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103731.4] assign _T_466 = _T_465 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103732.4] assign _T_467 = ~ _T_466; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103733.4] assign _T_468 = io_addr < _T_467; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103734.4] assign _T_469 = _T_468 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103735.4] assign _T_475 = _T_469 & _T_380; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103741.4] assign _T_476 = _T_459 & _T_475; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103742.4] assign _T_477 = _T_450 ? _T_458 : _T_476; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103743.4] assign _T_478 = io_pmp_2_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103744.4] assign _T_531 = io_pmp_2_cfg_r | _T_478; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103799.4] assign _T_533 = io_pmp_2_cfg_w | _T_478; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103802.4] assign _T_535 = io_pmp_2_cfg_x | _T_478; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103805.4] assign _T_537_cfg_x = _T_477 ? _T_535 : _T_449_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] assign _T_537_cfg_w = _T_477 ? _T_533 : _T_449_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] assign _T_537_cfg_r = _T_477 ? _T_531 : _T_449_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103808.4] assign _T_538 = io_pmp_1_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103809.4] assign _T_543 = io_addr ^ _T_467; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103814.4] assign _T_544 = ~ io_pmp_1_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103815.4] assign _T_545 = _T_543 & _T_544; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103816.4] assign _T_546 = _T_545 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103817.4] assign _T_547 = io_pmp_1_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103818.4] assign _T_552 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 60:36:freechips.rocketchip.system.TinyConfig.fir@103823.4] assign _T_553 = ~ _T_552; // @[PMP.scala 60:29:freechips.rocketchip.system.TinyConfig.fir@103824.4] assign _T_554 = _T_553 | 32'h3; // @[PMP.scala 60:48:freechips.rocketchip.system.TinyConfig.fir@103825.4] assign _T_555 = ~ _T_554; // @[PMP.scala 60:27:freechips.rocketchip.system.TinyConfig.fir@103826.4] assign _T_556 = io_addr < _T_555; // @[PMP.scala 77:9:freechips.rocketchip.system.TinyConfig.fir@103827.4] assign _T_557 = _T_556 == 1'h0; // @[PMP.scala 88:5:freechips.rocketchip.system.TinyConfig.fir@103828.4] assign _T_563 = _T_557 & _T_468; // @[PMP.scala 94:48:freechips.rocketchip.system.TinyConfig.fir@103834.4] assign _T_564 = _T_547 & _T_563; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103835.4] assign _T_565 = _T_538 ? _T_546 : _T_564; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103836.4] assign _T_566 = io_pmp_1_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103837.4] assign _T_619 = io_pmp_1_cfg_r | _T_566; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103892.4] assign _T_621 = io_pmp_1_cfg_w | _T_566; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103895.4] assign _T_623 = io_pmp_1_cfg_x | _T_566; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103898.4] assign _T_625_cfg_x = _T_565 ? _T_623 : _T_537_cfg_x; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] assign _T_625_cfg_w = _T_565 ? _T_621 : _T_537_cfg_w; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] assign _T_625_cfg_r = _T_565 ? _T_619 : _T_537_cfg_r; // @[PMP.scala 184:8:freechips.rocketchip.system.TinyConfig.fir@103901.4] assign _T_626 = io_pmp_0_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@103902.4] assign _T_631 = io_addr ^ _T_555; // @[PMP.scala 63:47:freechips.rocketchip.system.TinyConfig.fir@103907.4] assign _T_632 = ~ io_pmp_0_mask; // @[PMP.scala 63:54:freechips.rocketchip.system.TinyConfig.fir@103908.4] assign _T_633 = _T_631 & _T_632; // @[PMP.scala 63:52:freechips.rocketchip.system.TinyConfig.fir@103909.4] assign _T_634 = _T_633 == 32'h0; // @[PMP.scala 63:58:freechips.rocketchip.system.TinyConfig.fir@103910.4] assign _T_635 = io_pmp_0_cfg_a[0]; // @[PMP.scala 46:26:freechips.rocketchip.system.TinyConfig.fir@103911.4] assign _T_652 = _T_635 & _T_556; // @[PMP.scala 132:61:freechips.rocketchip.system.TinyConfig.fir@103928.4] assign _T_653 = _T_626 ? _T_634 : _T_652; // @[PMP.scala 132:8:freechips.rocketchip.system.TinyConfig.fir@103929.4] assign _T_654 = io_pmp_0_cfg_l == 1'h0; // @[PMP.scala 163:29:freechips.rocketchip.system.TinyConfig.fir@103930.4] assign _T_707 = io_pmp_0_cfg_r | _T_654; // @[PMP.scala 181:40:freechips.rocketchip.system.TinyConfig.fir@103985.4] assign _T_709 = io_pmp_0_cfg_w | _T_654; // @[PMP.scala 182:40:freechips.rocketchip.system.TinyConfig.fir@103988.4] assign _T_711 = io_pmp_0_cfg_x | _T_654; // @[PMP.scala 183:40:freechips.rocketchip.system.TinyConfig.fir@103991.4] assign io_r = _T_653 ? _T_707 : _T_625_cfg_r; // @[PMP.scala 187:8:freechips.rocketchip.system.TinyConfig.fir@103995.4] assign io_w = _T_653 ? _T_709 : _T_625_cfg_w; // @[PMP.scala 188:8:freechips.rocketchip.system.TinyConfig.fir@103996.4] assign io_x = _T_653 ? _T_711 : _T_625_cfg_x; // @[PMP.scala 189:8:freechips.rocketchip.system.TinyConfig.fir@103997.4] endmodule module TLB( // @[:freechips.rocketchip.system.TinyConfig.fir@104169.2] input io_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_req_bits_vaddr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [4:0] io_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output [31:0] io_resp_paddr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_pf_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_pf_st, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_ae_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_ae_st, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_ma_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] output io_resp_ma_st, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [1:0] io_ptw_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input io_ptw_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [29:0] io_ptw_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] input [31:0] io_ptw_pmp_7_mask // @[:freechips.rocketchip.system.TinyConfig.fir@104172.4] ); wire pmp_io_pmp_0_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_0_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_0_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_0_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_0_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_0_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_1_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_1_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_1_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_1_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_1_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_1_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_2_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_2_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_2_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_2_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_2_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_2_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_3_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_3_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_3_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_3_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_3_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_3_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_4_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_4_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_4_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_4_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_4_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_4_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_5_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_5_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_5_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_5_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_5_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_5_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_6_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_6_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_6_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_6_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_6_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_6_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_7_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_7_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_7_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_pmp_7_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [29:0] pmp_io_pmp_7_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_pmp_7_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [31:0] pmp_io_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire pmp_io_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] wire [19:0] vpn; // @[TLB.scala 180:30:freechips.rocketchip.system.TinyConfig.fir@104193.4] wire [19:0] mpu_ppn; // @[TLB.scala 185:123:freechips.rocketchip.system.TinyConfig.fir@104240.4] wire [11:0] _T_26; // @[TLB.scala 186:52:freechips.rocketchip.system.TinyConfig.fir@104243.4] wire [31:0] mpu_physaddr; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@104244.4] wire [31:0] _T_30; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104263.4] wire [32:0] _T_31; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104264.4] wire [32:0] _T_32; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104265.4] wire [32:0] _T_33; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104266.4] wire _T_34; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104267.4] wire [31:0] _T_35; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104268.4] wire [32:0] _T_36; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104269.4] wire [32:0] _T_37; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104270.4] wire [32:0] _T_38; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104271.4] wire _T_39; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104272.4] wire [31:0] _T_40; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104273.4] wire [32:0] _T_41; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104274.4] wire [32:0] _T_42; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104275.4] wire [32:0] _T_43; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104276.4] wire _T_44; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104277.4] wire [32:0] _T_46; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104279.4] wire [32:0] _T_47; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104280.4] wire [32:0] _T_48; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104281.4] wire _T_49; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104282.4] wire [31:0] _T_50; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104283.4] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104284.4] wire [32:0] _T_52; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104285.4] wire [32:0] _T_53; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104286.4] wire _T_54; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104287.4] wire [31:0] _T_55; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104288.4] wire [32:0] _T_56; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104289.4] wire [32:0] _T_57; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104290.4] wire [32:0] _T_58; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104291.4] wire _T_59; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104292.4] wire [31:0] _T_60; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104293.4] wire [32:0] _T_61; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104294.4] wire [32:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104295.4] wire [32:0] _T_63; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104296.4] wire _T_64; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104297.4] wire _T_66; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104307.4] wire _T_67; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104308.4] wire _T_68; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104309.4] wire _T_69; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104310.4] wire _T_70; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104311.4] wire legal_address; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104312.4] wire [31:0] _T_120; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104364.4] wire [32:0] _T_121; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104365.4] wire [31:0] _T_133; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104377.4] wire [32:0] _T_134; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104378.4] wire prot_r; // @[TLB.scala 197:41:freechips.rocketchip.system.TinyConfig.fir@104409.4] wire [32:0] _T_167; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104412.4] wire [32:0] _T_168; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104413.4] wire _T_169; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104414.4] wire [32:0] _T_172; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104417.4] wire [32:0] _T_173; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104418.4] wire _T_174; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104419.4] wire [32:0] _T_177; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104422.4] wire [32:0] _T_178; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104423.4] wire _T_179; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104424.4] wire _T_180; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104425.4] wire _T_181; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104426.4] wire _T_191; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104437.4] wire prot_w; // @[TLB.scala 198:45:freechips.rocketchip.system.TinyConfig.fir@104438.4] wire prot_al; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104466.4] wire [32:0] _T_295; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104548.4] wire [32:0] _T_296; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104549.4] wire _T_297; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104550.4] wire [32:0] _T_300; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104553.4] wire [32:0] _T_301; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104554.4] wire _T_302; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104555.4] wire _T_308; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104561.4] wire _T_309; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104562.4] wire _T_310; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104563.4] wire prot_eff; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104569.4] wire [1:0] _T_845; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105577.4] wire [6:0] pr_array; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105582.4] wire [1:0] _T_853; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105586.4] wire [6:0] pw_array; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105591.4] wire [1:0] _T_869; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105604.4] wire [6:0] eff_array; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105609.4] wire [1:0] _T_881; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105618.4] wire [6:0] paa_array; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105623.4] wire [3:0] _T_900; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@105642.4] wire [3:0] _T_902; // @[TLB.scala 266:69:freechips.rocketchip.system.TinyConfig.fir@105644.4] wire [31:0] _GEN_144; // @[TLB.scala 266:39:freechips.rocketchip.system.TinyConfig.fir@105645.4] wire [31:0] _T_903; // @[TLB.scala 266:39:freechips.rocketchip.system.TinyConfig.fir@105645.4] wire misaligned; // @[TLB.scala 266:75:freechips.rocketchip.system.TinyConfig.fir@105646.4] wire _T_904; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105647.4] wire _T_905; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105648.4] wire cmd_lrsc; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105649.4] wire _T_907; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105651.4] wire _T_908; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105652.4] wire _T_909; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105653.4] wire _T_910; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105654.4] wire _T_911; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105655.4] wire _T_912; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105656.4] wire cmd_amo_logical; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105657.4] wire _T_914; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105659.4] wire _T_915; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105660.4] wire _T_916; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105661.4] wire _T_917; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105662.4] wire _T_918; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105663.4] wire _T_919; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105664.4] wire _T_920; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105665.4] wire _T_921; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105666.4] wire cmd_amo_arithmetic; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105667.4] wire _T_923; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@105669.4] wire _T_925; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@105671.4] wire _T_927; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@105673.4] wire _T_944; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@105690.4] wire cmd_read; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@105691.4] wire _T_945; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@105692.4] wire _T_946; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@105693.4] wire _T_947; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@105694.4] wire _T_949; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@105696.4] wire cmd_write; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@105714.4] wire [6:0] _T_969; // @[TLB.scala 287:8:freechips.rocketchip.system.TinyConfig.fir@105719.4] wire [6:0] _T_971; // @[TLB.scala 288:8:freechips.rocketchip.system.TinyConfig.fir@105721.4] wire [6:0] ae_array; // @[TLB.scala 287:37:freechips.rocketchip.system.TinyConfig.fir@105722.4] wire [6:0] _T_972; // @[TLB.scala 289:46:freechips.rocketchip.system.TinyConfig.fir@105723.4] wire [6:0] _T_973; // @[TLB.scala 289:44:freechips.rocketchip.system.TinyConfig.fir@105724.4] wire [6:0] ae_ld_array; // @[TLB.scala 289:24:freechips.rocketchip.system.TinyConfig.fir@105725.4] wire [6:0] _T_974; // @[TLB.scala 291:37:freechips.rocketchip.system.TinyConfig.fir@105726.4] wire [6:0] _T_975; // @[TLB.scala 291:35:freechips.rocketchip.system.TinyConfig.fir@105727.4] wire [6:0] _T_976; // @[TLB.scala 291:8:freechips.rocketchip.system.TinyConfig.fir@105728.4] wire [6:0] _T_977; // @[TLB.scala 292:26:freechips.rocketchip.system.TinyConfig.fir@105729.4] wire [6:0] _T_978; // @[TLB.scala 292:8:freechips.rocketchip.system.TinyConfig.fir@105730.4] wire [6:0] _T_979; // @[TLB.scala 291:53:freechips.rocketchip.system.TinyConfig.fir@105731.4] wire [6:0] _T_981; // @[TLB.scala 293:8:freechips.rocketchip.system.TinyConfig.fir@105733.4] wire [6:0] ae_st_array; // @[TLB.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@105734.4] wire _T_989; // @[TLB.scala 298:36:freechips.rocketchip.system.TinyConfig.fir@105743.4] wire [6:0] _T_990; // @[TLB.scala 298:49:freechips.rocketchip.system.TinyConfig.fir@105744.4] wire [6:0] ma_ld_array; // @[TLB.scala 298:24:freechips.rocketchip.system.TinyConfig.fir@105745.4] wire _T_991; // @[TLB.scala 299:36:freechips.rocketchip.system.TinyConfig.fir@105746.4] wire [6:0] ma_st_array; // @[TLB.scala 299:24:freechips.rocketchip.system.TinyConfig.fir@105748.4] wire [6:0] pf_ld_array; // @[TLB.scala 300:24:freechips.rocketchip.system.TinyConfig.fir@105751.4] wire [6:0] pf_st_array; // @[TLB.scala 301:24:freechips.rocketchip.system.TinyConfig.fir@105754.4] wire [6:0] _T_1082; // @[TLB.scala 322:57:freechips.rocketchip.system.TinyConfig.fir@105853.4] wire [6:0] _T_1086; // @[TLB.scala 323:64:freechips.rocketchip.system.TinyConfig.fir@105858.4] wire [6:0] _T_1092; // @[TLB.scala 325:33:freechips.rocketchip.system.TinyConfig.fir@105866.4] wire [6:0] _T_1094; // @[TLB.scala 326:33:freechips.rocketchip.system.TinyConfig.fir@105869.4] wire [6:0] _T_1099; // @[TLB.scala 328:33:freechips.rocketchip.system.TinyConfig.fir@105876.4] wire [6:0] _T_1101; // @[TLB.scala 329:33:freechips.rocketchip.system.TinyConfig.fir@105879.4] PMPChecker pmp ( // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@104245.4] .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l), .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a), .io_pmp_0_cfg_x(pmp_io_pmp_0_cfg_x), .io_pmp_0_cfg_w(pmp_io_pmp_0_cfg_w), .io_pmp_0_cfg_r(pmp_io_pmp_0_cfg_r), .io_pmp_0_addr(pmp_io_pmp_0_addr), .io_pmp_0_mask(pmp_io_pmp_0_mask), .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l), .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a), .io_pmp_1_cfg_x(pmp_io_pmp_1_cfg_x), .io_pmp_1_cfg_w(pmp_io_pmp_1_cfg_w), .io_pmp_1_cfg_r(pmp_io_pmp_1_cfg_r), .io_pmp_1_addr(pmp_io_pmp_1_addr), .io_pmp_1_mask(pmp_io_pmp_1_mask), .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l), .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a), .io_pmp_2_cfg_x(pmp_io_pmp_2_cfg_x), .io_pmp_2_cfg_w(pmp_io_pmp_2_cfg_w), .io_pmp_2_cfg_r(pmp_io_pmp_2_cfg_r), .io_pmp_2_addr(pmp_io_pmp_2_addr), .io_pmp_2_mask(pmp_io_pmp_2_mask), .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l), .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a), .io_pmp_3_cfg_x(pmp_io_pmp_3_cfg_x), .io_pmp_3_cfg_w(pmp_io_pmp_3_cfg_w), .io_pmp_3_cfg_r(pmp_io_pmp_3_cfg_r), .io_pmp_3_addr(pmp_io_pmp_3_addr), .io_pmp_3_mask(pmp_io_pmp_3_mask), .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l), .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a), .io_pmp_4_cfg_x(pmp_io_pmp_4_cfg_x), .io_pmp_4_cfg_w(pmp_io_pmp_4_cfg_w), .io_pmp_4_cfg_r(pmp_io_pmp_4_cfg_r), .io_pmp_4_addr(pmp_io_pmp_4_addr), .io_pmp_4_mask(pmp_io_pmp_4_mask), .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l), .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a), .io_pmp_5_cfg_x(pmp_io_pmp_5_cfg_x), .io_pmp_5_cfg_w(pmp_io_pmp_5_cfg_w), .io_pmp_5_cfg_r(pmp_io_pmp_5_cfg_r), .io_pmp_5_addr(pmp_io_pmp_5_addr), .io_pmp_5_mask(pmp_io_pmp_5_mask), .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l), .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a), .io_pmp_6_cfg_x(pmp_io_pmp_6_cfg_x), .io_pmp_6_cfg_w(pmp_io_pmp_6_cfg_w), .io_pmp_6_cfg_r(pmp_io_pmp_6_cfg_r), .io_pmp_6_addr(pmp_io_pmp_6_addr), .io_pmp_6_mask(pmp_io_pmp_6_mask), .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l), .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a), .io_pmp_7_cfg_x(pmp_io_pmp_7_cfg_x), .io_pmp_7_cfg_w(pmp_io_pmp_7_cfg_w), .io_pmp_7_cfg_r(pmp_io_pmp_7_cfg_r), .io_pmp_7_addr(pmp_io_pmp_7_addr), .io_pmp_7_mask(pmp_io_pmp_7_mask), .io_addr(pmp_io_addr), .io_r(pmp_io_r), .io_w(pmp_io_w), .io_x(pmp_io_x) ); assign vpn = io_req_bits_vaddr[31:12]; // @[TLB.scala 180:30:freechips.rocketchip.system.TinyConfig.fir@104193.4] assign mpu_ppn = io_req_bits_vaddr[31:12]; // @[TLB.scala 185:123:freechips.rocketchip.system.TinyConfig.fir@104240.4] assign _T_26 = io_req_bits_vaddr[11:0]; // @[TLB.scala 186:52:freechips.rocketchip.system.TinyConfig.fir@104243.4] assign mpu_physaddr = {mpu_ppn,_T_26}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@104244.4] assign _T_30 = mpu_physaddr ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104263.4] assign _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104264.4] assign _T_32 = $signed(_T_31) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104265.4] assign _T_33 = $signed(_T_32); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104266.4] assign _T_34 = $signed(_T_33) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104267.4] assign _T_35 = mpu_physaddr ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104268.4] assign _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104269.4] assign _T_37 = $signed(_T_36) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104270.4] assign _T_38 = $signed(_T_37); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104271.4] assign _T_39 = $signed(_T_38) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104272.4] assign _T_40 = mpu_physaddr ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104273.4] assign _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104274.4] assign _T_42 = $signed(_T_41) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104275.4] assign _T_43 = $signed(_T_42); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104276.4] assign _T_44 = $signed(_T_43) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104277.4] assign _T_46 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104279.4] assign _T_47 = $signed(_T_46) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104280.4] assign _T_48 = $signed(_T_47); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104281.4] assign _T_49 = $signed(_T_48) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104282.4] assign _T_50 = mpu_physaddr ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104283.4] assign _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104284.4] assign _T_52 = $signed(_T_51) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104285.4] assign _T_53 = $signed(_T_52); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104286.4] assign _T_54 = $signed(_T_53) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104287.4] assign _T_55 = mpu_physaddr ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104288.4] assign _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104289.4] assign _T_57 = $signed(_T_56) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104290.4] assign _T_58 = $signed(_T_57); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104291.4] assign _T_59 = $signed(_T_58) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104292.4] assign _T_60 = mpu_physaddr ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104293.4] assign _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104294.4] assign _T_62 = $signed(_T_61) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104295.4] assign _T_63 = $signed(_T_62); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104296.4] assign _T_64 = $signed(_T_63) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104297.4] assign _T_66 = _T_34 | _T_39; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104307.4] assign _T_67 = _T_66 | _T_44; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104308.4] assign _T_68 = _T_67 | _T_49; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104309.4] assign _T_69 = _T_68 | _T_54; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104310.4] assign _T_70 = _T_69 | _T_59; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104311.4] assign legal_address = _T_70 | _T_64; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@104312.4] assign _T_120 = mpu_physaddr ^ 32'h8000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104364.4] assign _T_121 = {1'b0,$signed(_T_120)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104365.4] assign _T_133 = mpu_physaddr ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@104377.4] assign _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@104378.4] assign prot_r = legal_address & pmp_io_r; // @[TLB.scala 197:41:freechips.rocketchip.system.TinyConfig.fir@104409.4] assign _T_167 = $signed(_T_46) & $signed(33'sh48010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104412.4] assign _T_168 = $signed(_T_167); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104413.4] assign _T_169 = $signed(_T_168) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104414.4] assign _T_172 = $signed(_T_121) & $signed(33'shc8000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104417.4] assign _T_173 = $signed(_T_172); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104418.4] assign _T_174 = $signed(_T_173) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104419.4] assign _T_177 = $signed(_T_134) & $signed(33'shc0000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104422.4] assign _T_178 = $signed(_T_177); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104423.4] assign _T_179 = $signed(_T_178) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104424.4] assign _T_180 = _T_169 | _T_174; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104425.4] assign _T_181 = _T_180 | _T_179; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104426.4] assign _T_191 = legal_address & _T_181; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104437.4] assign prot_w = _T_191 & pmp_io_w; // @[TLB.scala 198:45:freechips.rocketchip.system.TinyConfig.fir@104438.4] assign prot_al = legal_address & _T_180; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104466.4] assign _T_295 = $signed(_T_41) & $signed(33'shca010000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104548.4] assign _T_296 = $signed(_T_295); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104549.4] assign _T_297 = $signed(_T_296) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104550.4] assign _T_300 = $signed(_T_46) & $signed(33'shca012000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104553.4] assign _T_301 = $signed(_T_300); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@104554.4] assign _T_302 = $signed(_T_301) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@104555.4] assign _T_308 = _T_174 | _T_297; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104561.4] assign _T_309 = _T_308 | _T_302; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104562.4] assign _T_310 = _T_309 | _T_179; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@104563.4] assign prot_eff = legal_address & _T_310; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@104569.4] assign _T_845 = prot_r ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105577.4] assign pr_array = {_T_845,5'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105582.4] assign _T_853 = prot_w ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105586.4] assign pw_array = {_T_853,5'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105591.4] assign _T_869 = prot_eff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105604.4] assign eff_array = {_T_869,5'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105609.4] assign _T_881 = prot_al ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@105618.4] assign paa_array = {_T_881,5'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@105623.4] assign _T_900 = 4'h1 << io_req_bits_size; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@105642.4] assign _T_902 = _T_900 - 4'h1; // @[TLB.scala 266:69:freechips.rocketchip.system.TinyConfig.fir@105644.4] assign _GEN_144 = {{28'd0}, _T_902}; // @[TLB.scala 266:39:freechips.rocketchip.system.TinyConfig.fir@105645.4] assign _T_903 = io_req_bits_vaddr & _GEN_144; // @[TLB.scala 266:39:freechips.rocketchip.system.TinyConfig.fir@105645.4] assign misaligned = _T_903 != 32'h0; // @[TLB.scala 266:75:freechips.rocketchip.system.TinyConfig.fir@105646.4] assign _T_904 = io_req_bits_cmd == 5'h6; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105647.4] assign _T_905 = io_req_bits_cmd == 5'h7; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105648.4] assign cmd_lrsc = _T_904 | _T_905; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105649.4] assign _T_907 = io_req_bits_cmd == 5'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105651.4] assign _T_908 = io_req_bits_cmd == 5'h9; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105652.4] assign _T_909 = io_req_bits_cmd == 5'ha; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105653.4] assign _T_910 = io_req_bits_cmd == 5'hb; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105654.4] assign _T_911 = _T_907 | _T_908; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105655.4] assign _T_912 = _T_911 | _T_909; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105656.4] assign cmd_amo_logical = _T_912 | _T_910; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105657.4] assign _T_914 = io_req_bits_cmd == 5'h8; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105659.4] assign _T_915 = io_req_bits_cmd == 5'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105660.4] assign _T_916 = io_req_bits_cmd == 5'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105661.4] assign _T_917 = io_req_bits_cmd == 5'he; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105662.4] assign _T_918 = io_req_bits_cmd == 5'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@105663.4] assign _T_919 = _T_914 | _T_915; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105664.4] assign _T_920 = _T_919 | _T_916; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105665.4] assign _T_921 = _T_920 | _T_917; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105666.4] assign cmd_amo_arithmetic = _T_921 | _T_918; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@105667.4] assign _T_923 = io_req_bits_cmd == 5'h0; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@105669.4] assign _T_925 = _T_923 | _T_904; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@105671.4] assign _T_927 = _T_925 | _T_905; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@105673.4] assign _T_944 = cmd_amo_logical | cmd_amo_arithmetic; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@105690.4] assign cmd_read = _T_927 | _T_944; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@105691.4] assign _T_945 = io_req_bits_cmd == 5'h1; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@105692.4] assign _T_946 = io_req_bits_cmd == 5'h11; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@105693.4] assign _T_947 = _T_945 | _T_946; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@105694.4] assign _T_949 = _T_947 | _T_905; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@105696.4] assign cmd_write = _T_949 | _T_944; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@105714.4] assign _T_969 = misaligned ? eff_array : 7'h0; // @[TLB.scala 287:8:freechips.rocketchip.system.TinyConfig.fir@105719.4] assign _T_971 = cmd_lrsc ? 7'h7f : 7'h0; // @[TLB.scala 288:8:freechips.rocketchip.system.TinyConfig.fir@105721.4] assign ae_array = _T_969 | _T_971; // @[TLB.scala 287:37:freechips.rocketchip.system.TinyConfig.fir@105722.4] assign _T_972 = ~ pr_array; // @[TLB.scala 289:46:freechips.rocketchip.system.TinyConfig.fir@105723.4] assign _T_973 = ae_array | _T_972; // @[TLB.scala 289:44:freechips.rocketchip.system.TinyConfig.fir@105724.4] assign ae_ld_array = cmd_read ? _T_973 : 7'h0; // @[TLB.scala 289:24:freechips.rocketchip.system.TinyConfig.fir@105725.4] assign _T_974 = ~ pw_array; // @[TLB.scala 291:37:freechips.rocketchip.system.TinyConfig.fir@105726.4] assign _T_975 = ae_array | _T_974; // @[TLB.scala 291:35:freechips.rocketchip.system.TinyConfig.fir@105727.4] assign _T_976 = cmd_write ? _T_975 : 7'h0; // @[TLB.scala 291:8:freechips.rocketchip.system.TinyConfig.fir@105728.4] assign _T_977 = ~ paa_array; // @[TLB.scala 292:26:freechips.rocketchip.system.TinyConfig.fir@105729.4] assign _T_978 = cmd_amo_logical ? _T_977 : 7'h0; // @[TLB.scala 292:8:freechips.rocketchip.system.TinyConfig.fir@105730.4] assign _T_979 = _T_976 | _T_978; // @[TLB.scala 291:53:freechips.rocketchip.system.TinyConfig.fir@105731.4] assign _T_981 = cmd_amo_arithmetic ? _T_977 : 7'h0; // @[TLB.scala 293:8:freechips.rocketchip.system.TinyConfig.fir@105733.4] assign ae_st_array = _T_979 | _T_981; // @[TLB.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@105734.4] assign _T_989 = misaligned & cmd_read; // @[TLB.scala 298:36:freechips.rocketchip.system.TinyConfig.fir@105743.4] assign _T_990 = ~ eff_array; // @[TLB.scala 298:49:freechips.rocketchip.system.TinyConfig.fir@105744.4] assign ma_ld_array = _T_989 ? _T_990 : 7'h0; // @[TLB.scala 298:24:freechips.rocketchip.system.TinyConfig.fir@105745.4] assign _T_991 = misaligned & cmd_write; // @[TLB.scala 299:36:freechips.rocketchip.system.TinyConfig.fir@105746.4] assign ma_st_array = _T_991 ? _T_990 : 7'h0; // @[TLB.scala 299:24:freechips.rocketchip.system.TinyConfig.fir@105748.4] assign pf_ld_array = cmd_read ? 7'h3f : 7'h0; // @[TLB.scala 300:24:freechips.rocketchip.system.TinyConfig.fir@105751.4] assign pf_st_array = cmd_write ? 7'h3f : 7'h0; // @[TLB.scala 301:24:freechips.rocketchip.system.TinyConfig.fir@105754.4] assign _T_1082 = pf_ld_array & 7'h40; // @[TLB.scala 322:57:freechips.rocketchip.system.TinyConfig.fir@105853.4] assign _T_1086 = pf_st_array & 7'h40; // @[TLB.scala 323:64:freechips.rocketchip.system.TinyConfig.fir@105858.4] assign _T_1092 = ae_ld_array & 7'h40; // @[TLB.scala 325:33:freechips.rocketchip.system.TinyConfig.fir@105866.4] assign _T_1094 = ae_st_array & 7'h40; // @[TLB.scala 326:33:freechips.rocketchip.system.TinyConfig.fir@105869.4] assign _T_1099 = ma_ld_array & 7'h40; // @[TLB.scala 328:33:freechips.rocketchip.system.TinyConfig.fir@105876.4] assign _T_1101 = ma_st_array & 7'h40; // @[TLB.scala 329:33:freechips.rocketchip.system.TinyConfig.fir@105879.4] assign io_resp_paddr = {vpn,_T_26}; // @[TLB.scala 335:17:freechips.rocketchip.system.TinyConfig.fir@105898.4] assign io_resp_pf_ld = _T_1082 != 7'h0; // @[TLB.scala 322:17:freechips.rocketchip.system.TinyConfig.fir@105856.4] assign io_resp_pf_st = _T_1086 != 7'h0; // @[TLB.scala 323:17:freechips.rocketchip.system.TinyConfig.fir@105861.4] assign io_resp_ae_ld = _T_1092 != 7'h0; // @[TLB.scala 325:17:freechips.rocketchip.system.TinyConfig.fir@105868.4] assign io_resp_ae_st = _T_1094 != 7'h0; // @[TLB.scala 326:17:freechips.rocketchip.system.TinyConfig.fir@105871.4] assign io_resp_ma_ld = _T_1099 != 7'h0; // @[TLB.scala 328:17:freechips.rocketchip.system.TinyConfig.fir@105878.4] assign io_resp_ma_st = _T_1101 != 7'h0; // @[TLB.scala 329:17:freechips.rocketchip.system.TinyConfig.fir@105881.4] assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104251.4] assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104252.4] assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104253.4] assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104254.4] assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104255.4] assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104256.4] assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104257.4] assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@104258.4] assign pmp_io_addr = {mpu_ppn,_T_26}; // @[TLB.scala 188:15:freechips.rocketchip.system.TinyConfig.fir@104249.4] endmodule module AMOALU( // @[:freechips.rocketchip.system.TinyConfig.fir@105905.2] input [4:0] io_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@105908.4] input [31:0] io_lhs, // @[:freechips.rocketchip.system.TinyConfig.fir@105908.4] input [31:0] io_rhs, // @[:freechips.rocketchip.system.TinyConfig.fir@105908.4] output [31:0] io_out_unmasked // @[:freechips.rocketchip.system.TinyConfig.fir@105908.4] ); wire _T; // @[AMOALU.scala 64:20:freechips.rocketchip.system.TinyConfig.fir@105913.4] wire _T_1; // @[AMOALU.scala 64:43:freechips.rocketchip.system.TinyConfig.fir@105914.4] wire max; // @[AMOALU.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@105915.4] wire _T_2; // @[AMOALU.scala 65:20:freechips.rocketchip.system.TinyConfig.fir@105916.4] wire _T_3; // @[AMOALU.scala 65:43:freechips.rocketchip.system.TinyConfig.fir@105917.4] wire min; // @[AMOALU.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@105918.4] wire add; // @[AMOALU.scala 66:20:freechips.rocketchip.system.TinyConfig.fir@105919.4] wire _T_4; // @[AMOALU.scala 67:26:freechips.rocketchip.system.TinyConfig.fir@105920.4] wire _T_5; // @[AMOALU.scala 67:48:freechips.rocketchip.system.TinyConfig.fir@105921.4] wire logic_and; // @[AMOALU.scala 67:38:freechips.rocketchip.system.TinyConfig.fir@105922.4] wire _T_6; // @[AMOALU.scala 68:26:freechips.rocketchip.system.TinyConfig.fir@105923.4] wire logic_xor; // @[AMOALU.scala 68:39:freechips.rocketchip.system.TinyConfig.fir@105925.4] wire [31:0] adder_out; // @[AMOALU.scala 73:21:freechips.rocketchip.system.TinyConfig.fir@105930.4] wire [4:0] _T_14; // @[AMOALU.scala 86:17:freechips.rocketchip.system.TinyConfig.fir@105933.4] wire _T_16; // @[AMOALU.scala 86:25:freechips.rocketchip.system.TinyConfig.fir@105935.4] wire _T_17; // @[AMOALU.scala 88:12:freechips.rocketchip.system.TinyConfig.fir@105936.4] wire _T_18; // @[AMOALU.scala 88:23:freechips.rocketchip.system.TinyConfig.fir@105937.4] wire _T_19; // @[AMOALU.scala 88:18:freechips.rocketchip.system.TinyConfig.fir@105938.4] wire _T_22; // @[AMOALU.scala 79:35:freechips.rocketchip.system.TinyConfig.fir@105941.4] wire _T_25; // @[AMOALU.scala 88:58:freechips.rocketchip.system.TinyConfig.fir@105944.4] wire less; // @[AMOALU.scala 88:10:freechips.rocketchip.system.TinyConfig.fir@105945.4] wire _T_26; // @[AMOALU.scala 94:23:freechips.rocketchip.system.TinyConfig.fir@105946.4] wire [31:0] minmax; // @[AMOALU.scala 94:19:freechips.rocketchip.system.TinyConfig.fir@105947.4] wire [31:0] _T_27; // @[AMOALU.scala 96:27:freechips.rocketchip.system.TinyConfig.fir@105948.4] wire [31:0] _T_28; // @[AMOALU.scala 96:8:freechips.rocketchip.system.TinyConfig.fir@105949.4] wire [31:0] _T_29; // @[AMOALU.scala 97:27:freechips.rocketchip.system.TinyConfig.fir@105950.4] wire [31:0] _T_30; // @[AMOALU.scala 97:8:freechips.rocketchip.system.TinyConfig.fir@105951.4] wire [31:0] logic_; // @[AMOALU.scala 96:42:freechips.rocketchip.system.TinyConfig.fir@105952.4] wire _T_31; // @[AMOALU.scala 100:19:freechips.rocketchip.system.TinyConfig.fir@105953.4] wire [31:0] _T_32; // @[AMOALU.scala 100:8:freechips.rocketchip.system.TinyConfig.fir@105954.4] assign _T = io_cmd == 5'hd; // @[AMOALU.scala 64:20:freechips.rocketchip.system.TinyConfig.fir@105913.4] assign _T_1 = io_cmd == 5'hf; // @[AMOALU.scala 64:43:freechips.rocketchip.system.TinyConfig.fir@105914.4] assign max = _T | _T_1; // @[AMOALU.scala 64:33:freechips.rocketchip.system.TinyConfig.fir@105915.4] assign _T_2 = io_cmd == 5'hc; // @[AMOALU.scala 65:20:freechips.rocketchip.system.TinyConfig.fir@105916.4] assign _T_3 = io_cmd == 5'he; // @[AMOALU.scala 65:43:freechips.rocketchip.system.TinyConfig.fir@105917.4] assign min = _T_2 | _T_3; // @[AMOALU.scala 65:33:freechips.rocketchip.system.TinyConfig.fir@105918.4] assign add = io_cmd == 5'h8; // @[AMOALU.scala 66:20:freechips.rocketchip.system.TinyConfig.fir@105919.4] assign _T_4 = io_cmd == 5'ha; // @[AMOALU.scala 67:26:freechips.rocketchip.system.TinyConfig.fir@105920.4] assign _T_5 = io_cmd == 5'hb; // @[AMOALU.scala 67:48:freechips.rocketchip.system.TinyConfig.fir@105921.4] assign logic_and = _T_4 | _T_5; // @[AMOALU.scala 67:38:freechips.rocketchip.system.TinyConfig.fir@105922.4] assign _T_6 = io_cmd == 5'h9; // @[AMOALU.scala 68:26:freechips.rocketchip.system.TinyConfig.fir@105923.4] assign logic_xor = _T_6 | _T_4; // @[AMOALU.scala 68:39:freechips.rocketchip.system.TinyConfig.fir@105925.4] assign adder_out = io_lhs + io_rhs; // @[AMOALU.scala 73:21:freechips.rocketchip.system.TinyConfig.fir@105930.4] assign _T_14 = io_cmd & 5'h2; // @[AMOALU.scala 86:17:freechips.rocketchip.system.TinyConfig.fir@105933.4] assign _T_16 = _T_14 == 5'h0; // @[AMOALU.scala 86:25:freechips.rocketchip.system.TinyConfig.fir@105935.4] assign _T_17 = io_lhs[31]; // @[AMOALU.scala 88:12:freechips.rocketchip.system.TinyConfig.fir@105936.4] assign _T_18 = io_rhs[31]; // @[AMOALU.scala 88:23:freechips.rocketchip.system.TinyConfig.fir@105937.4] assign _T_19 = _T_17 == _T_18; // @[AMOALU.scala 88:18:freechips.rocketchip.system.TinyConfig.fir@105938.4] assign _T_22 = io_lhs < io_rhs; // @[AMOALU.scala 79:35:freechips.rocketchip.system.TinyConfig.fir@105941.4] assign _T_25 = _T_16 ? _T_17 : _T_18; // @[AMOALU.scala 88:58:freechips.rocketchip.system.TinyConfig.fir@105944.4] assign less = _T_19 ? _T_22 : _T_25; // @[AMOALU.scala 88:10:freechips.rocketchip.system.TinyConfig.fir@105945.4] assign _T_26 = less ? min : max; // @[AMOALU.scala 94:23:freechips.rocketchip.system.TinyConfig.fir@105946.4] assign minmax = _T_26 ? io_lhs : io_rhs; // @[AMOALU.scala 94:19:freechips.rocketchip.system.TinyConfig.fir@105947.4] assign _T_27 = io_lhs & io_rhs; // @[AMOALU.scala 96:27:freechips.rocketchip.system.TinyConfig.fir@105948.4] assign _T_28 = logic_and ? _T_27 : 32'h0; // @[AMOALU.scala 96:8:freechips.rocketchip.system.TinyConfig.fir@105949.4] assign _T_29 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27:freechips.rocketchip.system.TinyConfig.fir@105950.4] assign _T_30 = logic_xor ? _T_29 : 32'h0; // @[AMOALU.scala 97:8:freechips.rocketchip.system.TinyConfig.fir@105951.4] assign logic_ = _T_28 | _T_30; // @[AMOALU.scala 96:42:freechips.rocketchip.system.TinyConfig.fir@105952.4] assign _T_31 = logic_and | logic_xor; // @[AMOALU.scala 100:19:freechips.rocketchip.system.TinyConfig.fir@105953.4] assign _T_32 = _T_31 ? logic_ : minmax; // @[AMOALU.scala 100:8:freechips.rocketchip.system.TinyConfig.fir@105954.4] assign io_out_unmasked = add ? adder_out : _T_32; // @[AMOALU.scala 105:19:freechips.rocketchip.system.TinyConfig.fir@105976.4] endmodule module DCache( // @[:freechips.rocketchip.system.TinyConfig.fir@105978.2] input gated_clock, // @[:freechips.rocketchip.system.TinyConfig.fir@105979.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@105980.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105981.4] output io_cpu_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_cpu_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_cpu_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [6:0] io_cpu_req_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [4:0] io_cpu_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_cpu_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_cpu_req_bits_signed, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_cpu_req_bits_phys, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_cpu_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_cpu_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [3:0] io_cpu_s1_data_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [31:0] io_cpu_resp_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [6:0] io_cpu_resp_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [4:0] io_cpu_resp_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [1:0] io_cpu_resp_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_resp_bits_signed, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [31:0] io_cpu_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_resp_bits_has_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [31:0] io_cpu_resp_bits_data_word_bypass, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [31:0] io_cpu_resp_bits_data_raw, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output [31:0] io_cpu_resp_bits_store_data, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_replay_next, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_ma_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_ma_st, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_pf_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_pf_st, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_ae_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_s2_xcpt_ae_st, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_ordered, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] output io_cpu_perf_grant, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [1:0] io_ptw_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input io_ptw_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [29:0] io_ptw_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] input [31:0] io_ptw_pmp_7_mask // @[:freechips.rocketchip.system.TinyConfig.fir@105982.4] ); wire metaArb_io_in_2_valid; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire [31:0] metaArb_io_in_2_bits_addr; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_in_3_valid; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire [31:0] metaArb_io_in_3_bits_addr; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_in_5_ready; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_in_5_valid; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_in_7_ready; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_in_7_valid; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire [31:0] metaArb_io_in_7_bits_addr; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_out_valid; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire metaArb_io_out_bits_write; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire [31:0] metaArb_io_out_bits_addr; // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] wire data_clock; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire data_io_req_valid; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire [7:0] data_io_req_bits_addr; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire data_io_req_bits_write; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire [31:0] data_io_req_bits_wdata; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire [3:0] data_io_req_bits_eccMask; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire [31:0] data_io_resp_0; // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] wire dataArb_io_in_0_valid; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [7:0] dataArb_io_in_0_bits_addr; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_0_bits_write; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [31:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [3:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_1_ready; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_1_valid; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [7:0] dataArb_io_in_1_bits_addr; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_1_bits_write; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [31:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [3:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_3_ready; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_in_3_valid; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [7:0] dataArb_io_in_3_bits_addr; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [31:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [3:0] dataArb_io_in_3_bits_eccMask; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_out_valid; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [7:0] dataArb_io_out_bits_addr; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire dataArb_io_out_bits_write; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [31:0] dataArb_io_out_bits_wdata; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire [3:0] dataArb_io_out_bits_eccMask; // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] wire tlb_io_req_valid; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_req_bits_vaddr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_req_bits_size; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [4:0] tlb_io_req_bits_cmd; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_resp_paddr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_pf_ld; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_pf_st; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_ae_ld; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_ae_st; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_ma_ld; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_resp_ma_st; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_0_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_0_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_0_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_0_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_0_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_0_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_1_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_1_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_1_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_1_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_1_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_1_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_2_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_2_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_2_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_2_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_2_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_2_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_3_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_3_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_3_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_3_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_3_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_3_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_4_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_4_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_4_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_4_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_4_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_4_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_5_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_5_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_5_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_5_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_5_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_5_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_6_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_6_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_6_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_6_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_6_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_6_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_7_cfg_l; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_7_cfg_x; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_7_cfg_w; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire tlb_io_ptw_pmp_7_cfg_r; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [29:0] tlb_io_ptw_pmp_7_addr; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [31:0] tlb_io_ptw_pmp_7_mask; // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] wire [4:0] amoalu_io_cmd; // @[DCache.scala 804:24:freechips.rocketchip.system.TinyConfig.fir@109087.4] wire [31:0] amoalu_io_lhs; // @[DCache.scala 804:24:freechips.rocketchip.system.TinyConfig.fir@109087.4] wire [31:0] amoalu_io_rhs; // @[DCache.scala 804:24:freechips.rocketchip.system.TinyConfig.fir@109087.4] wire [31:0] amoalu_io_out_unmasked; // @[DCache.scala 804:24:freechips.rocketchip.system.TinyConfig.fir@109087.4] wire _T_48; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@106115.4] reg s1_valid; // @[DCache.scala 144:21:freechips.rocketchip.system.TinyConfig.fir@106116.4] reg [31:0] _RAND_0; wire _T_49_ready; wire _T_54; // @[DCache.scala 148:37:freechips.rocketchip.system.TinyConfig.fir@106142.4] wire s1_valid_masked; // @[DCache.scala 148:34:freechips.rocketchip.system.TinyConfig.fir@106143.4] reg [4:0] s1_req_cmd; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_1; wire _T_61; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106160.4] wire _T_62; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@106161.4] wire _T_63; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106162.4] wire _T_64; // @[Consts.scala 81:65:freechips.rocketchip.system.TinyConfig.fir@106163.4] wire _T_65; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106164.4] wire _T_66; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106165.4] wire _T_67; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106166.4] wire _T_70; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106169.4] wire _T_68; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106167.4] wire _T_71; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106170.4] wire _T_69; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106168.4] wire _T_72; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106171.4] wire _T_73; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106172.4] wire _T_74; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106173.4] wire _T_78; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106177.4] wire _T_75; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106174.4] wire _T_79; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106178.4] wire _T_76; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106175.4] wire _T_80; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106179.4] wire _T_77; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106176.4] wire _T_81; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106180.4] wire _T_82; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106181.4] wire s1_read; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106182.4] reg s2_valid; // @[DCache.scala 254:21:freechips.rocketchip.system.TinyConfig.fir@106527.4] reg [31:0] _RAND_2; reg [4:0] s2_req_cmd; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_3; wire _T_365; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@106599.4] wire _T_366; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106600.4] wire _T_367; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106601.4] wire _T_368; // @[Consts.scala 82:66:freechips.rocketchip.system.TinyConfig.fir@106602.4] wire _T_369; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106603.4] wire _T_370; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106604.4] wire _T_371; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106605.4] wire _T_374; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106608.4] wire _T_372; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106606.4] wire _T_375; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106609.4] wire _T_373; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106607.4] wire _T_376; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106610.4] wire _T_377; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106611.4] wire _T_378; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106612.4] wire _T_382; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106616.4] wire _T_379; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106613.4] wire _T_383; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106617.4] wire _T_380; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106614.4] wire _T_384; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106618.4] wire _T_381; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106615.4] wire _T_385; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106619.4] wire _T_386; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106620.4] wire s2_write; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106621.4] wire _T_890; // @[DCache.scala 400:39:freechips.rocketchip.system.TinyConfig.fir@107318.4] reg pstore1_held; // @[DCache.scala 399:25:freechips.rocketchip.system.TinyConfig.fir@107317.4] reg [31:0] _RAND_4; wire pstore1_valid_likely; // @[DCache.scala 400:51:freechips.rocketchip.system.TinyConfig.fir@107319.4] reg [31:0] pstore1_addr; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107155.4] reg [31:0] _RAND_5; wire [5:0] _T_1005; // @[DCache.scala 452:9:freechips.rocketchip.system.TinyConfig.fir@107481.4] reg [31:0] s1_req_addr; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_6; wire [5:0] _T_1006; // @[DCache.scala 452:46:freechips.rocketchip.system.TinyConfig.fir@107482.4] wire _T_1007; // @[DCache.scala 452:31:freechips.rocketchip.system.TinyConfig.fir@107483.4] wire _T_83; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@106183.4] wire _T_84; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106184.4] wire _T_85; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106185.4] wire _T_87; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106187.4] wire s1_write; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106205.4] reg [3:0] pstore1_mask; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107170.4] reg [31:0] _RAND_7; wire _T_1011; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107487.4] wire _T_1010; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107486.4] wire _T_1009; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107485.4] wire _T_1008; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107484.4] wire [3:0] _T_1018; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107494.4] wire _T_1022; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107498.4] wire _T_1021; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107497.4] wire _T_1020; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107496.4] wire _T_1019; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107495.4] wire [3:0] _T_1025; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107501.4] wire _T_298; // @[AMOALU.scala 17:27:freechips.rocketchip.system.TinyConfig.fir@106501.4] wire _T_290; // @[AMOALU.scala 17:27:freechips.rocketchip.system.TinyConfig.fir@106493.4] reg [1:0] s1_req_size; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_8; wire _T_292; // @[AMOALU.scala 17:57:freechips.rocketchip.system.TinyConfig.fir@106495.4] wire _T_294; // @[AMOALU.scala 17:46:freechips.rocketchip.system.TinyConfig.fir@106497.4] wire _T_296; // @[AMOALU.scala 18:22:freechips.rocketchip.system.TinyConfig.fir@106499.4] wire [1:0] _T_297; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106500.4] wire [1:0] _T_299; // @[AMOALU.scala 17:22:freechips.rocketchip.system.TinyConfig.fir@106502.4] wire _T_300; // @[AMOALU.scala 17:57:freechips.rocketchip.system.TinyConfig.fir@106503.4] wire [1:0] _T_301; // @[AMOALU.scala 17:51:freechips.rocketchip.system.TinyConfig.fir@106504.4] wire [1:0] _T_302; // @[AMOALU.scala 17:46:freechips.rocketchip.system.TinyConfig.fir@106505.4] wire [1:0] _T_304; // @[AMOALU.scala 18:22:freechips.rocketchip.system.TinyConfig.fir@106507.4] wire [3:0] s1_mask_xwr; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106508.4] wire _T_1029; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107505.4] wire _T_1028; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107504.4] wire _T_1027; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107503.4] wire _T_1026; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107502.4] wire [3:0] _T_1036; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107512.4] wire _T_1040; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107516.4] wire _T_1039; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107515.4] wire _T_1038; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107514.4] wire _T_1037; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107513.4] wire [3:0] _T_1043; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107519.4] wire [3:0] _T_1044; // @[DCache.scala 453:38:freechips.rocketchip.system.TinyConfig.fir@107520.4] wire _T_1045; // @[DCache.scala 453:66:freechips.rocketchip.system.TinyConfig.fir@107521.4] wire [3:0] _T_1046; // @[DCache.scala 453:77:freechips.rocketchip.system.TinyConfig.fir@107522.4] wire _T_1047; // @[DCache.scala 453:92:freechips.rocketchip.system.TinyConfig.fir@107523.4] wire _T_1048; // @[DCache.scala 453:8:freechips.rocketchip.system.TinyConfig.fir@107524.4] wire _T_1049; // @[DCache.scala 452:68:freechips.rocketchip.system.TinyConfig.fir@107525.4] wire _T_1050; // @[DCache.scala 455:27:freechips.rocketchip.system.TinyConfig.fir@107526.4] reg pstore2_valid; // @[DCache.scala 396:26:freechips.rocketchip.system.TinyConfig.fir@107242.4] reg [31:0] _RAND_9; reg [31:0] pstore2_addr; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107381.4] reg [31:0] _RAND_10; wire [5:0] _T_1051; // @[DCache.scala 452:9:freechips.rocketchip.system.TinyConfig.fir@107527.4] wire _T_1053; // @[DCache.scala 452:31:freechips.rocketchip.system.TinyConfig.fir@107529.4] reg [3:0] mask; // @[DCache.scala 426:19:freechips.rocketchip.system.TinyConfig.fir@107425.4] reg [31:0] _RAND_11; wire _T_1057; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107533.4] wire _T_1056; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107532.4] wire _T_1055; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107531.4] wire _T_1054; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107530.4] wire [3:0] _T_1064; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107540.4] wire _T_1068; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107544.4] wire _T_1067; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107543.4] wire _T_1066; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107542.4] wire _T_1065; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107541.4] wire [3:0] _T_1071; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107547.4] wire [3:0] _T_1090; // @[DCache.scala 453:38:freechips.rocketchip.system.TinyConfig.fir@107566.4] wire _T_1091; // @[DCache.scala 453:66:freechips.rocketchip.system.TinyConfig.fir@107567.4] wire [3:0] _T_1092; // @[DCache.scala 453:77:freechips.rocketchip.system.TinyConfig.fir@107568.4] wire _T_1093; // @[DCache.scala 453:92:freechips.rocketchip.system.TinyConfig.fir@107569.4] wire _T_1094; // @[DCache.scala 453:8:freechips.rocketchip.system.TinyConfig.fir@107570.4] wire _T_1095; // @[DCache.scala 452:68:freechips.rocketchip.system.TinyConfig.fir@107571.4] wire _T_1096; // @[DCache.scala 456:21:freechips.rocketchip.system.TinyConfig.fir@107572.4] wire s1_hazard; // @[DCache.scala 455:69:freechips.rocketchip.system.TinyConfig.fir@107573.4] wire s1_raw_hazard; // @[DCache.scala 457:31:freechips.rocketchip.system.TinyConfig.fir@107574.4] wire _T_1097; // @[DCache.scala 462:18:freechips.rocketchip.system.TinyConfig.fir@107576.4] wire [5:0] _T_322; // @[DCache.scala 255:54:freechips.rocketchip.system.TinyConfig.fir@106533.4] wire _T_323; // @[DCache.scala 255:61:freechips.rocketchip.system.TinyConfig.fir@106534.4] wire _T_324; // @[DCache.scala 255:38:freechips.rocketchip.system.TinyConfig.fir@106535.4] wire s2_valid_no_xcpt; // @[DCache.scala 255:35:freechips.rocketchip.system.TinyConfig.fir@106536.4] reg _T_328; // @[DCache.scala 258:48:freechips.rocketchip.system.TinyConfig.fir@106543.4] reg [31:0] _RAND_12; wire s2_valid_masked; // @[DCache.scala 258:42:freechips.rocketchip.system.TinyConfig.fir@106545.4] wire _T_453; // @[Consts.scala 83:54:freechips.rocketchip.system.TinyConfig.fir@106745.4] wire _T_454; // @[Consts.scala 83:47:freechips.rocketchip.system.TinyConfig.fir@106746.4] wire _T_455; // @[Consts.scala 83:71:freechips.rocketchip.system.TinyConfig.fir@106747.4] wire _T_456; // @[Consts.scala 83:64:freechips.rocketchip.system.TinyConfig.fir@106748.4] reg [1:0] s2_hit_state_state; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@106688.4] reg [31:0] _RAND_13; wire [3:0] _T_458; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106750.4] wire _T_516; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106808.4] wire _T_513; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106805.4] wire _T_510; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106802.4] wire _T_507; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106799.4] wire _T_504; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106796.4] wire _T_501; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106793.4] wire _T_498; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106790.4] wire _T_495; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106787.4] wire _T_492; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106784.4] wire _T_489; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106781.4] wire _T_486; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106778.4] wire _T_483; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106775.4] wire _T_502; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106794.4] wire _T_505; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106797.4] wire _T_508; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106800.4] wire _T_511; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106803.4] wire _T_514; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106806.4] wire s2_hit; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106809.4] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw; // @[DCache.scala 317:89:freechips.rocketchip.system.TinyConfig.fir@106836.4] wire _T_343; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106576.4] wire _T_345; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106578.4] wire _T_347; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106580.4] wire s2_read; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106598.4] wire s2_readwrite; // @[DCache.scala 274:30:freechips.rocketchip.system.TinyConfig.fir@106622.4] wire s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala 318:89:freechips.rocketchip.system.TinyConfig.fir@106837.4] wire [1:0] _T_485; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106777.4] wire [1:0] _T_488; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106780.4] wire [1:0] _T_491; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106783.4] wire [1:0] _T_494; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106786.4] wire [1:0] _T_497; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106789.4] wire [1:0] _T_500; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106792.4] wire [1:0] _T_503; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106795.4] wire [1:0] _T_506; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106798.4] wire [1:0] _T_509; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106801.4] wire [1:0] _T_512; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106804.4] wire [1:0] _T_515; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106807.4] wire [1:0] s2_grow_param; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106810.4] wire _T_690; // @[Metadata.scala 46:46:freechips.rocketchip.system.TinyConfig.fir@107025.4] wire s2_update_meta; // @[Metadata.scala 47:40:freechips.rocketchip.system.TinyConfig.fir@107026.4] wire _T_705; // @[DCache.scala 341:62:freechips.rocketchip.system.TinyConfig.fir@107044.4] wire _T_706; // @[DCache.scala 341:24:freechips.rocketchip.system.TinyConfig.fir@107045.4] wire s1_readwrite; // @[DCache.scala 159:30:freechips.rocketchip.system.TinyConfig.fir@106206.4] wire _T_105; // @[DCache.scala 161:34:freechips.rocketchip.system.TinyConfig.fir@106208.4] wire _T_106; // @[DCache.scala 161:64:freechips.rocketchip.system.TinyConfig.fir@106209.4] wire s1_flush_line; // @[DCache.scala 161:50:freechips.rocketchip.system.TinyConfig.fir@106210.4] wire s1_cmd_uses_tlb; // @[DCache.scala 204:38:freechips.rocketchip.system.TinyConfig.fir@106418.4] wire s1_nack; // @[DCache.scala 462:36:freechips.rocketchip.system.TinyConfig.fir@107577.4] wire _T_55; // @[DCache.scala 149:41:freechips.rocketchip.system.TinyConfig.fir@106144.4] wire s1_valid_not_nacked; // @[DCache.scala 149:38:freechips.rocketchip.system.TinyConfig.fir@106145.4] reg [6:0] s1_req_tag; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_14; reg s1_req_signed; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_15; reg s1_req_phys; // @[DCache.scala 150:19:freechips.rocketchip.system.TinyConfig.fir@106146.4] reg [31:0] _RAND_16; wire _T_56; // @[DCache.scala 151:43:freechips.rocketchip.system.TinyConfig.fir@106147.4] wire s0_clk_en; // @[DCache.scala 151:40:freechips.rocketchip.system.TinyConfig.fir@106148.4] wire [25:0] _T_57; // @[DCache.scala 154:49:freechips.rocketchip.system.TinyConfig.fir@106151.6] wire [5:0] _T_58; // @[DCache.scala 154:86:freechips.rocketchip.system.TinyConfig.fir@106152.6] wire [31:0] _T_59; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106153.6] wire _T_60; // @[DCache.scala 155:11:freechips.rocketchip.system.TinyConfig.fir@106155.6] wire s1_sfence; // @[DCache.scala 160:30:freechips.rocketchip.system.TinyConfig.fir@106207.4] reg s1_flush_valid; // @[DCache.scala 162:27:freechips.rocketchip.system.TinyConfig.fir@106211.4] reg [31:0] _RAND_17; reg uncachedInFlight_0; // @[DCache.scala 180:33:freechips.rocketchip.system.TinyConfig.fir@106238.4] reg [31:0] _RAND_18; reg [31:0] uncachedReqs_0_addr; // @[DCache.scala 181:25:freechips.rocketchip.system.TinyConfig.fir@106239.4] reg [31:0] _RAND_19; reg [6:0] uncachedReqs_0_tag; // @[DCache.scala 181:25:freechips.rocketchip.system.TinyConfig.fir@106239.4] reg [31:0] _RAND_20; reg [1:0] uncachedReqs_0_size; // @[DCache.scala 181:25:freechips.rocketchip.system.TinyConfig.fir@106239.4] reg [31:0] _RAND_21; reg uncachedReqs_0_signed; // @[DCache.scala 181:25:freechips.rocketchip.system.TinyConfig.fir@106239.4] reg [31:0] _RAND_22; wire _T_116; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106243.4] wire _T_117; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@106244.4] wire _T_118; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106245.4] wire _T_119; // @[Consts.scala 81:65:freechips.rocketchip.system.TinyConfig.fir@106246.4] wire _T_120; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106247.4] wire _T_121; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106248.4] wire _T_122; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106249.4] wire _T_123; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106250.4] wire _T_124; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106251.4] wire _T_125; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106252.4] wire _T_126; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106253.4] wire _T_127; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106254.4] wire _T_128; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106255.4] wire _T_129; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106256.4] wire _T_130; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106257.4] wire _T_131; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106258.4] wire _T_132; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106259.4] wire _T_133; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106260.4] wire _T_134; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106261.4] wire _T_135; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106262.4] wire _T_136; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106263.4] wire _T_137; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106264.4] wire s0_read; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106265.4] wire _T_138; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106266.4] wire _T_139; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106267.4] wire _T_140; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106268.4] wire res; // @[DCache.scala 988:15:freechips.rocketchip.system.TinyConfig.fir@106269.4] wire _T_167; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106296.4] wire _T_168; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106297.4] wire _T_170; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106299.4] wire _T_188; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106317.4] wire _T_192; // @[DCache.scala 994:23:freechips.rocketchip.system.TinyConfig.fir@106321.4] wire _T_193; // @[DCache.scala 993:21:freechips.rocketchip.system.TinyConfig.fir@106322.4] wire _T_194; // @[DCache.scala 989:12:freechips.rocketchip.system.TinyConfig.fir@106323.4] wire _T_195; // @[DCache.scala 989:28:freechips.rocketchip.system.TinyConfig.fir@106324.4] wire _T_197; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106326.4] wire _T_198; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106327.4] wire _T_199; // @[DCache.scala 186:46:freechips.rocketchip.system.TinyConfig.fir@106332.4] wire _T_202; // @[DCache.scala 192:9:freechips.rocketchip.system.TinyConfig.fir@106341.4] wire _T_203; // @[DCache.scala 192:33:freechips.rocketchip.system.TinyConfig.fir@106342.4] wire _GEN_17; // @[DCache.scala 192:45:freechips.rocketchip.system.TinyConfig.fir@106343.4] wire _T_255; // @[DCache.scala 193:75:freechips.rocketchip.system.TinyConfig.fir@106397.4] wire _T_256; // @[DCache.scala 193:54:freechips.rocketchip.system.TinyConfig.fir@106398.4] reg s1_did_read; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@106399.4] reg [31:0] _RAND_23; wire _GEN_19; // @[DCache.scala 200:34:freechips.rocketchip.system.TinyConfig.fir@106411.4] wire _T_275; // @[DCache.scala 226:35:freechips.rocketchip.system.TinyConfig.fir@106456.4] wire _T_278; // @[DCache.scala 226:59:freechips.rocketchip.system.TinyConfig.fir@106459.4] wire inScratchpad; // @[DCache.scala 226:47:freechips.rocketchip.system.TinyConfig.fir@106460.4] wire [7:0] _T_282; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106479.4] wire [7:0] _T_283; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106480.4] wire [7:0] _T_284; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106481.4] wire [7:0] _T_285; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106482.4] wire [31:0] _T_288; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106485.4] wire _T_307; // @[DCache.scala 252:28:freechips.rocketchip.system.TinyConfig.fir@106512.4] wire _T_308; // @[DCache.scala 252:10:freechips.rocketchip.system.TinyConfig.fir@106513.4] wire [3:0] _T_309; // @[DCache.scala 252:71:freechips.rocketchip.system.TinyConfig.fir@106514.4] wire [3:0] _T_310; // @[DCache.scala 252:69:freechips.rocketchip.system.TinyConfig.fir@106515.4] wire _T_311; // @[DCache.scala 252:93:freechips.rocketchip.system.TinyConfig.fir@106516.4] wire _T_312; // @[DCache.scala 252:53:freechips.rocketchip.system.TinyConfig.fir@106517.4] wire _T_314; // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106519.4] wire _T_315; // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106520.4] wire _T_316; // @[DCache.scala 254:46:freechips.rocketchip.system.TinyConfig.fir@106525.4] wire _T_317; // @[DCache.scala 254:43:freechips.rocketchip.system.TinyConfig.fir@106526.4] reg [31:0] s2_req_addr; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_24; reg [6:0] s2_req_tag; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_25; reg [1:0] s2_req_size; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_26; reg s2_req_signed; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_27; reg s2_req_phys; // @[DCache.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@106548.4] reg [31:0] _RAND_28; wire _T_331; // @[DCache.scala 261:68:freechips.rocketchip.system.TinyConfig.fir@106550.4] reg s2_tlb_resp_pf_ld; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_29; reg s2_tlb_resp_pf_st; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_30; reg s2_tlb_resp_ae_ld; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_31; reg s2_tlb_resp_ae_st; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_32; reg s2_tlb_resp_ma_ld; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_33; reg s2_tlb_resp_ma_st; // @[DCache.scala 263:24:freechips.rocketchip.system.TinyConfig.fir@106556.4] reg [31:0] _RAND_34; reg [31:0] s2_uncached_resp_addr; // @[DCache.scala 265:34:freechips.rocketchip.system.TinyConfig.fir@106561.4] reg [31:0] _RAND_35; wire _T_338; // @[DCache.scala 266:29:freechips.rocketchip.system.TinyConfig.fir@106562.4] reg [31:0] _T_340; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@106569.4] reg [31:0] _RAND_36; wire [19:0] _T_341; // @[DCache.scala 271:84:freechips.rocketchip.system.TinyConfig.fir@106573.4] wire [11:0] _T_342; // @[DCache.scala 271:109:freechips.rocketchip.system.TinyConfig.fir@106574.4] wire [31:0] s2_vaddr; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106575.4] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala 275:43:freechips.rocketchip.system.TinyConfig.fir@106623.4] reg [31:0] _RAND_37; wire en; // @[DCache.scala 286:38:freechips.rocketchip.system.TinyConfig.fir@106654.4] wire _T_395; // @[DCache.scala 287:64:freechips.rocketchip.system.TinyConfig.fir@106655.4] wire word_en; // @[DCache.scala 287:63:freechips.rocketchip.system.TinyConfig.fir@106656.4] wire [31:0] s1_all_data_ways_0; // @[DCache.scala 248:29:freechips.rocketchip.system.TinyConfig.fir@106488.4 DCache.scala 248:29:freechips.rocketchip.system.TinyConfig.fir@106490.4] wire _T_397; // @[DCache.scala 297:28:freechips.rocketchip.system.TinyConfig.fir@106660.4] wire s1_word_en; // @[DCache.scala 297:27:freechips.rocketchip.system.TinyConfig.fir@106661.4] wire [1:0] opc; // @[DCache.scala 520:26:freechips.rocketchip.system.TinyConfig.fir@108530.4] wire [1:0] _T_1916; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@108531.4] wire data_1; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@108532.4] reg blockUncachedGrant; // @[DCache.scala 614:33:freechips.rocketchip.system.TinyConfig.fir@108759.4] reg [31:0] _RAND_38; wire _T_2057; // @[DCache.scala 616:54:freechips.rocketchip.system.TinyConfig.fir@108761.4] wire _T_2058; // @[DCache.scala 616:31:freechips.rocketchip.system.TinyConfig.fir@108762.4] wire [2:0] _GEN_183; // @[DCache.scala 530:29:freechips.rocketchip.system.TinyConfig.fir@108549.4] wire grantIsRefill; // @[DCache.scala 530:29:freechips.rocketchip.system.TinyConfig.fir@108549.4] wire _T_1975; // @[DCache.scala 586:26:freechips.rocketchip.system.TinyConfig.fir@108660.4] wire _T_1976; // @[DCache.scala 586:23:freechips.rocketchip.system.TinyConfig.fir@108661.4] wire _T_1928; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108545.4] wire grantIsCached; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108547.4] reg [9:0] _T_1898; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@108501.4] reg [31:0] _RAND_39; wire d_first; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@108504.4] wire _T_1936; // @[DCache.scala 535:41:freechips.rocketchip.system.TinyConfig.fir@108562.4] wire _T_1940; // @[DCache.scala 535:24:freechips.rocketchip.system.TinyConfig.fir@108567.4] wire _GEN_157; // @[DCache.scala 586:51:freechips.rocketchip.system.TinyConfig.fir@108662.4] wire tl_out__d_ready; // @[DCache.scala 616:68:freechips.rocketchip.system.TinyConfig.fir@108763.4] wire _T_1942; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@108572.4] wire [1:0] _GEN_114; // @[DCache.scala 555:34:freechips.rocketchip.system.TinyConfig.fir@108604.10] wire [1:0] _GEN_136; // @[DCache.scala 539:26:freechips.rocketchip.system.TinyConfig.fir@108574.6] wire [1:0] s1_data_way; // @[DCache.scala 538:26:freechips.rocketchip.system.TinyConfig.fir@108573.4] wire [1:0] _T_399; // @[DCache.scala 299:28:freechips.rocketchip.system.TinyConfig.fir@106663.4] wire _T_400; // @[Mux.scala 30:36:freechips.rocketchip.system.TinyConfig.fir@106664.4] wire _T_401; // @[Mux.scala 30:36:freechips.rocketchip.system.TinyConfig.fir@106665.4] wire [31:0] _T_402; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106666.4] wire [31:0] _T_403; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106667.4] wire [31:0] _T_404; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106668.4] reg [31:0] s2_data; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@106671.4] reg [31:0] _RAND_40; wire s2_hit_valid; // @[Metadata.scala 50:45:freechips.rocketchip.system.TinyConfig.fir@106698.4] wire [7:0] _T_517; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106814.4] wire [7:0] _T_518; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106815.4] wire [7:0] _T_519; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106816.4] wire [7:0] _T_520; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106817.4] wire [15:0] _T_529; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106828.4] wire [15:0] _T_530; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106829.4] wire [31:0] s2_data_corrected; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106830.4] wire _T_540; // @[DCache.scala 323:39:freechips.rocketchip.system.TinyConfig.fir@106847.4] wire _T_543; // @[DCache.scala 323:76:freechips.rocketchip.system.TinyConfig.fir@106850.4] wire s2_valid_miss; // @[DCache.scala 323:73:freechips.rocketchip.system.TinyConfig.fir@106851.4] wire _T_548; // @[DCache.scala 324:63:freechips.rocketchip.system.TinyConfig.fir@106856.4] wire s2_valid_cached_miss; // @[DCache.scala 324:60:freechips.rocketchip.system.TinyConfig.fir@106857.4] wire _T_552; // @[DCache.scala 327:29:freechips.rocketchip.system.TinyConfig.fir@106862.4] wire s2_valid_uncached_pending; // @[DCache.scala 329:64:freechips.rocketchip.system.TinyConfig.fir@106869.4] wire [1:0] s2_victim_state_state; // @[DCache.scala 332:28:freechips.rocketchip.system.TinyConfig.fir@106890.4] wire [3:0] _T_631; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106961.4] wire _T_656; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106986.4] wire _T_660; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106990.4] wire _T_661; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106991.4] wire _T_664; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106994.4] wire _T_665; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106995.4] wire _T_668; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106998.4] wire _T_669; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106999.4] wire _T_672; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107002.4] wire _T_673; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107003.4] wire _T_676; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107006.4] wire _T_677; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107007.4] wire _T_680; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107010.4] wire _T_681; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107011.4] wire _T_684; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107014.4] wire _T_685; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107015.4] wire _T_688; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107018.4] wire s2_victim_dirty; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107019.4] wire s2_dont_nack_uncached; // @[DCache.scala 338:57:freechips.rocketchip.system.TinyConfig.fir@107027.4] wire _T_699; // @[DCache.scala 340:41:freechips.rocketchip.system.TinyConfig.fir@107037.4] wire _T_700; // @[DCache.scala 340:38:freechips.rocketchip.system.TinyConfig.fir@107038.4] wire _T_703; // @[DCache.scala 340:90:freechips.rocketchip.system.TinyConfig.fir@107041.4] wire [23:0] _T_718; // @[DCache.scala 349:58:freechips.rocketchip.system.TinyConfig.fir@107064.4] wire [7:0] _T_729; // @[DCache.scala 361:80:freechips.rocketchip.system.TinyConfig.fir@107089.4] wire _T_760; // @[DCache.scala 387:63:freechips.rocketchip.system.TinyConfig.fir@107149.4] reg [4:0] pstore1_cmd; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107150.4] reg [31:0] _RAND_41; reg [31:0] pstore1_data; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107160.4] reg [31:0] _RAND_42; wire _T_814; // @[DCache.scala 994:23:freechips.rocketchip.system.TinyConfig.fir@107226.4] wire _T_815; // @[DCache.scala 993:21:freechips.rocketchip.system.TinyConfig.fir@107227.4] reg pstore1_rmw; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107229.4] reg [31:0] _RAND_43; wire _T_819; // @[DCache.scala 385:46:freechips.rocketchip.system.TinyConfig.fir@107236.4] wire pstore_drain_opportunistic; // @[DCache.scala 397:36:freechips.rocketchip.system.TinyConfig.fir@107310.4] reg pstore_drain_on_miss; // @[DCache.scala 398:56:freechips.rocketchip.system.TinyConfig.fir@107314.4] reg [31:0] _RAND_44; wire pstore1_valid; // @[DCache.scala 402:38:freechips.rocketchip.system.TinyConfig.fir@107325.4] wire _T_897; // @[DCache.scala 404:54:freechips.rocketchip.system.TinyConfig.fir@107328.4] wire _T_898; // @[DCache.scala 404:85:freechips.rocketchip.system.TinyConfig.fir@107329.4] wire _T_899; // @[DCache.scala 404:98:freechips.rocketchip.system.TinyConfig.fir@107330.4] wire pstore_drain_structural; // @[DCache.scala 404:71:freechips.rocketchip.system.TinyConfig.fir@107331.4] wire _T_904; // @[DCache.scala 405:63:freechips.rocketchip.system.TinyConfig.fir@107336.4] wire _T_905; // @[DCache.scala 405:22:freechips.rocketchip.system.TinyConfig.fir@107337.4] wire _T_907; // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107339.4] wire _T_908; // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107340.4] wire _T_917; // @[DCache.scala 413:44:freechips.rocketchip.system.TinyConfig.fir@107354.4] wire _T_918; // @[DCache.scala 413:41:freechips.rocketchip.system.TinyConfig.fir@107355.4] wire _T_919; // @[DCache.scala 413:58:freechips.rocketchip.system.TinyConfig.fir@107356.4] wire _T_920; // @[DCache.scala 413:107:freechips.rocketchip.system.TinyConfig.fir@107357.4] wire _T_921; // @[DCache.scala 413:76:freechips.rocketchip.system.TinyConfig.fir@107358.4] wire pstore_drain; // @[DCache.scala 412:48:freechips.rocketchip.system.TinyConfig.fir@107359.4] wire _T_931; // @[DCache.scala 416:71:freechips.rocketchip.system.TinyConfig.fir@107369.4] wire _T_932; // @[DCache.scala 416:91:freechips.rocketchip.system.TinyConfig.fir@107370.4] wire _T_935; // @[DCache.scala 417:79:freechips.rocketchip.system.TinyConfig.fir@107374.4] wire advance_pstore1; // @[DCache.scala 417:61:freechips.rocketchip.system.TinyConfig.fir@107375.4] wire _T_937; // @[DCache.scala 418:34:freechips.rocketchip.system.TinyConfig.fir@107377.4] wire [7:0] _T_2235; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109107.4] wire [7:0] _T_2233; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109105.4] wire [7:0] _T_2231; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109103.4] wire [7:0] _T_2229; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109101.4] wire [31:0] mask_1; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109110.4] wire [31:0] _T_2238; // @[DCache.scala 811:30:freechips.rocketchip.system.TinyConfig.fir@109111.4] wire [31:0] _T_2239; // @[DCache.scala 811:64:freechips.rocketchip.system.TinyConfig.fir@109112.4] wire [31:0] _T_2240; // @[DCache.scala 811:62:freechips.rocketchip.system.TinyConfig.fir@109113.4] wire [31:0] pstore1_storegen_data; // @[DCache.scala 811:37:freechips.rocketchip.system.TinyConfig.fir@109114.4] wire [7:0] _T_941; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107390.4] reg [7:0] _T_945; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107394.4] reg [31:0] _RAND_45; wire [7:0] _T_946; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107398.4] reg [7:0] _T_950; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107402.4] reg [31:0] _RAND_46; wire [7:0] _T_951; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107406.4] reg [7:0] _T_955; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107410.4] reg [31:0] _RAND_47; wire [7:0] _T_956; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107414.4] reg [7:0] _T_960; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@107418.4] reg [31:0] _RAND_48; wire [31:0] pstore2_storegen_data; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107424.4] wire [3:0] _T_965; // @[DCache.scala 429:37:freechips.rocketchip.system.TinyConfig.fir@107430.6] wire [3:0] _T_967; // @[DCache.scala 429:15:freechips.rocketchip.system.TinyConfig.fir@107432.6] wire [31:0] _T_981; // @[DCache.scala 444:36:freechips.rocketchip.system.TinyConfig.fir@107452.4] wire [31:0] _T_983; // @[DCache.scala 446:63:freechips.rocketchip.system.TinyConfig.fir@107456.4] wire [7:0] _T_984; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107457.4] wire [7:0] _T_985; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107458.4] wire [7:0] _T_986; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107459.4] wire [7:0] _T_987; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107460.4] wire [15:0] _T_988; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107461.4] wire [15:0] _T_989; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107462.4] wire [3:0] _T_993; // @[DCache.scala 448:47:freechips.rocketchip.system.TinyConfig.fir@107468.4] wire _T_994; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107469.4] wire _T_995; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107470.4] wire _T_996; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107471.4] wire _T_997; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107472.4] wire [1:0] _T_1002; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107477.4] wire [1:0] _T_1003; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107478.4] wire [1:0] _T_1155; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@107647.4] wire [1:0] _T_1157; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@107649.4] wire _T_1158; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@107650.4] wire _T_1159; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@107651.4] wire _T_1160; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@107652.4] wire _T_1161; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@107653.4] wire _T_1163; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107655.4] wire _T_1164; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107656.4] wire _T_1166; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107658.4] wire _T_1167; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107659.4] wire _T_1168; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@107660.4] wire _T_1169; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@107661.4] wire _T_1170; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@107662.4] wire _T_1171; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107663.4] wire _T_1172; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107664.4] wire _T_1173; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107665.4] wire _T_1174; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107666.4] wire _T_1175; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107667.4] wire _T_1176; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107668.4] wire _T_1177; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107669.4] wire _T_1178; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107670.4] wire _T_1179; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107671.4] wire _T_1180; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107672.4] wire _T_1181; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107673.4] wire _T_1182; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107674.4] wire [3:0] get_mask; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107677.4] wire _T_1858; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108445.4] wire [2:0] _T_1859_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire [2:0] _T_1859_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire [3:0] _T_1824_size; // @[Edges.scala 487:17:freechips.rocketchip.system.TinyConfig.fir@108402.4 Edges.scala 490:15:freechips.rocketchip.system.TinyConfig.fir@108406.4] wire [3:0] _T_1859_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire [31:0] _T_1859_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire [3:0] _T_1859_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire [31:0] _T_1859_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] wire _T_1860; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108447.4] wire [2:0] _T_1861_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire [2:0] _T_1861_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire [3:0] _T_1861_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire [31:0] _T_1861_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire [3:0] _T_1861_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire [31:0] _T_1861_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] wire _T_1862; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108449.4] wire [2:0] _T_1863_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire [2:0] _T_1863_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire [3:0] _T_1863_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire [31:0] _T_1863_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire [3:0] _T_1863_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire [31:0] _T_1863_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] wire _T_1864; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108451.4] wire [2:0] _T_1865_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire [2:0] _T_1865_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire [3:0] _T_1865_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire [31:0] _T_1865_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire [3:0] _T_1865_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire [31:0] _T_1865_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] wire _T_1866; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108453.4] wire [2:0] _T_1867_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire [2:0] _T_1867_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire [3:0] _T_1867_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire [31:0] _T_1867_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire [3:0] _T_1867_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire [31:0] _T_1867_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] wire _T_1868; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108455.4] wire [2:0] _T_1869_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire [2:0] _T_1869_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire [3:0] _T_1869_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire [31:0] _T_1869_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire [3:0] _T_1869_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire [31:0] _T_1869_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] wire _T_1870; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108457.4] wire [2:0] _T_1871_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire [2:0] _T_1871_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire [3:0] _T_1871_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire [31:0] _T_1871_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire [3:0] _T_1871_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire [31:0] _T_1871_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] wire _T_1872; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108459.4] wire [2:0] _T_1873_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire [2:0] _T_1873_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire [3:0] _T_1873_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire [31:0] _T_1873_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire [3:0] _T_1873_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire [31:0] _T_1873_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] wire _T_1874; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108461.4] wire [2:0] atomics_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire [2:0] atomics_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire [3:0] atomics_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire [31:0] atomics_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire [3:0] atomics_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire [31:0] atomics_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] wire _T_1876; // @[DCache.scala 492:109:freechips.rocketchip.system.TinyConfig.fir@108464.4] wire _T_1878; // @[DCache.scala 492:63:freechips.rocketchip.system.TinyConfig.fir@108466.4] wire tl_out_a_valid; // @[DCache.scala 492:128:freechips.rocketchip.system.TinyConfig.fir@108467.4] wire _T_1883; // @[DCache.scala 493:89:freechips.rocketchip.system.TinyConfig.fir@108473.4] wire _T_1884; // @[DCache.scala 493:109:freechips.rocketchip.system.TinyConfig.fir@108474.4] wire [2:0] _T_1885_opcode; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire [2:0] _T_1885_param; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire [3:0] _T_1885_size; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire [31:0] _T_1885_address; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire [3:0] _T_1885_mask; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire [31:0] _T_1885_data; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] wire _T_1888; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@108480.4] wire [26:0] _T_1892; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@108495.4] wire [11:0] _T_1893; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@108496.4] wire [11:0] _T_1894; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@108497.4] wire [9:0] _T_1895; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@108498.4] wire _T_1896; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@108499.4] wire [9:0] _T_1897; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@108500.4] wire [9:0] _T_1900; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@108503.4] wire _T_1901; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@108505.4] wire _T_1902; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@108506.4] wire d_last; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@108507.4] wire d_done; // @[Edges.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@108508.4] wire _T_1906; // @[DCache.scala 518:14:freechips.rocketchip.system.TinyConfig.fir@108516.4] wire _T_1907; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108517.4] wire _T_1908; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108518.4] wire _T_1909; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108519.4] wire _T_1910; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108520.4] wire _T_1911; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108521.4] wire _T_1912; // @[DCache.scala 518:30:freechips.rocketchip.system.TinyConfig.fir@108522.4] wire _T_1914; // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108524.4] wire _T_1915; // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108525.4] wire _T_1945; // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108578.8] wire _T_1949; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108596.12] wire _T_1950; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108597.12] wire [29:0] _T_1952; // @[DCache.scala 565:41:freechips.rocketchip.system.TinyConfig.fir@108611.12] wire [31:0] dontCareBits; // @[DCache.scala 565:55:freechips.rocketchip.system.TinyConfig.fir@108612.12] wire [1:0] _T_1953; // @[DCache.scala 566:45:freechips.rocketchip.system.TinyConfig.fir@108613.12] wire [31:0] _GEN_187; // @[DCache.scala 566:26:freechips.rocketchip.system.TinyConfig.fir@108614.12] wire [31:0] _T_1954; // @[DCache.scala 566:26:freechips.rocketchip.system.TinyConfig.fir@108614.12] wire _T_1967; // @[DCache.scala 580:47:freechips.rocketchip.system.TinyConfig.fir@108647.4] wire _T_1968; // @[DCache.scala 580:58:freechips.rocketchip.system.TinyConfig.fir@108648.4] wire _T_1969; // @[DCache.scala 580:26:freechips.rocketchip.system.TinyConfig.fir@108649.4] wire _T_1971; // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108651.4] wire _T_1972; // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108652.4] wire _T_1973; // @[DCache.scala 585:44:freechips.rocketchip.system.TinyConfig.fir@108657.4] wire _T_1978; // @[DCache.scala 605:43:freechips.rocketchip.system.TinyConfig.fir@108669.4] wire _T_1979; // @[DCache.scala 605:56:freechips.rocketchip.system.TinyConfig.fir@108670.4] wire _GEN_158; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] wire _GEN_159; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] wire _GEN_160; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] wire _T_2130; // @[DCache.scala 748:35:freechips.rocketchip.system.TinyConfig.fir@108929.4] wire _T_2131; // @[DCache.scala 748:32:freechips.rocketchip.system.TinyConfig.fir@108930.4] wire _T_2132; // @[DCache.scala 748:72:freechips.rocketchip.system.TinyConfig.fir@108931.4] wire _T_2133; // @[DCache.scala 748:69:freechips.rocketchip.system.TinyConfig.fir@108932.4] wire _T_2134; // @[DCache.scala 748:57:freechips.rocketchip.system.TinyConfig.fir@108933.4] wire _T_2137; // @[DCache.scala 748:115:freechips.rocketchip.system.TinyConfig.fir@108936.4] reg _T_2140; // @[DCache.scala 751:32:freechips.rocketchip.system.TinyConfig.fir@108941.4] reg [31:0] _RAND_49; wire _T_2157_pf_ld; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2157_pf_st; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2157_ae_ld; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2157_ae_st; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2157_ma_ld; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2157_ma_st; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] wire _T_2158; // @[DCache.scala 756:14:freechips.rocketchip.system.TinyConfig.fir@108979.6] wire _T_2159; // @[DCache.scala 756:24:freechips.rocketchip.system.TinyConfig.fir@108980.6] wire _T_2161; // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108982.6] wire _T_2162; // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108983.6] wire _T_2173; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@109009.4] wire _T_2174; // @[DCache.scala 759:30:freechips.rocketchip.system.TinyConfig.fir@109010.4] wire _T_2175; // @[DCache.scala 759:12:freechips.rocketchip.system.TinyConfig.fir@109011.4] wire _T_2177; // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109013.4] wire _T_2178; // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109014.4] reg doUncachedResp; // @[DCache.scala 771:27:freechips.rocketchip.system.TinyConfig.fir@109024.4] reg [31:0] _RAND_50; wire _T_2187; // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109037.6] wire _T_2188; // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109038.6] wire [15:0] _T_2193; // @[AMOALU.scala 39:37:freechips.rocketchip.system.TinyConfig.fir@109053.4] wire [15:0] _T_2194; // @[AMOALU.scala 39:55:freechips.rocketchip.system.TinyConfig.fir@109054.4] wire [15:0] _T_2195; // @[AMOALU.scala 39:24:freechips.rocketchip.system.TinyConfig.fir@109055.4] wire _T_2198; // @[AMOALU.scala 42:26:freechips.rocketchip.system.TinyConfig.fir@109058.4] wire _T_2200; // @[AMOALU.scala 42:85:freechips.rocketchip.system.TinyConfig.fir@109060.4] wire _T_2201; // @[AMOALU.scala 42:76:freechips.rocketchip.system.TinyConfig.fir@109061.4] wire [15:0] _T_2203; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109063.4] wire [15:0] _T_2205; // @[AMOALU.scala 42:20:freechips.rocketchip.system.TinyConfig.fir@109065.4] wire [31:0] _T_2206; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109066.4] wire [7:0] _T_2208; // @[AMOALU.scala 39:37:freechips.rocketchip.system.TinyConfig.fir@109068.4] wire [7:0] _T_2209; // @[AMOALU.scala 39:55:freechips.rocketchip.system.TinyConfig.fir@109069.4] wire [7:0] _T_2210; // @[AMOALU.scala 39:24:freechips.rocketchip.system.TinyConfig.fir@109070.4] wire _T_2213; // @[AMOALU.scala 42:26:freechips.rocketchip.system.TinyConfig.fir@109073.4] wire _T_2215; // @[AMOALU.scala 42:85:freechips.rocketchip.system.TinyConfig.fir@109075.4] wire _T_2216; // @[AMOALU.scala 42:76:freechips.rocketchip.system.TinyConfig.fir@109076.4] wire [23:0] _T_2218; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109078.4] wire [23:0] _T_2219; // @[AMOALU.scala 42:98:freechips.rocketchip.system.TinyConfig.fir@109079.4] wire [23:0] _T_2220; // @[AMOALU.scala 42:20:freechips.rocketchip.system.TinyConfig.fir@109080.4] wire _T_2247; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109126.4] wire _T_2248; // @[DCache.scala 827:48:freechips.rocketchip.system.TinyConfig.fir@109127.4] wire _T_2249; // @[DCache.scala 827:45:freechips.rocketchip.system.TinyConfig.fir@109128.4] wire _T_2436; // @[DCache.scala 937:35:freechips.rocketchip.system.TinyConfig.fir@109358.4] wire _GEN_189; // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108580.10] wire _GEN_192; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108599.14] wire _GEN_193; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108599.14] DCacheModuleanon2 metaArb ( // @[DCache.scala 105:23:freechips.rocketchip.system.TinyConfig.fir@106080.4] .io_in_2_valid(metaArb_io_in_2_valid), .io_in_2_bits_addr(metaArb_io_in_2_bits_addr), .io_in_3_valid(metaArb_io_in_3_valid), .io_in_3_bits_addr(metaArb_io_in_3_bits_addr), .io_in_5_ready(metaArb_io_in_5_ready), .io_in_5_valid(metaArb_io_in_5_valid), .io_in_7_ready(metaArb_io_in_7_ready), .io_in_7_valid(metaArb_io_in_7_valid), .io_in_7_bits_addr(metaArb_io_in_7_bits_addr), .io_out_valid(metaArb_io_out_valid), .io_out_bits_write(metaArb_io_out_bits_write), .io_out_bits_addr(metaArb_io_out_bits_addr) ); DCacheDataArray data ( // @[DCache.scala 115:20:freechips.rocketchip.system.TinyConfig.fir@106085.4] .clock(data_clock), .io_req_valid(data_io_req_valid), .io_req_bits_addr(data_io_req_bits_addr), .io_req_bits_write(data_io_req_bits_write), .io_req_bits_wdata(data_io_req_bits_wdata), .io_req_bits_eccMask(data_io_req_bits_eccMask), .io_resp_0(data_io_resp_0) ); DCacheModuleanon3 dataArb ( // @[DCache.scala 116:23:freechips.rocketchip.system.TinyConfig.fir@106089.4] .io_in_0_valid(dataArb_io_in_0_valid), .io_in_0_bits_addr(dataArb_io_in_0_bits_addr), .io_in_0_bits_write(dataArb_io_in_0_bits_write), .io_in_0_bits_wdata(dataArb_io_in_0_bits_wdata), .io_in_0_bits_eccMask(dataArb_io_in_0_bits_eccMask), .io_in_1_ready(dataArb_io_in_1_ready), .io_in_1_valid(dataArb_io_in_1_valid), .io_in_1_bits_addr(dataArb_io_in_1_bits_addr), .io_in_1_bits_write(dataArb_io_in_1_bits_write), .io_in_1_bits_wdata(dataArb_io_in_1_bits_wdata), .io_in_1_bits_eccMask(dataArb_io_in_1_bits_eccMask), .io_in_3_ready(dataArb_io_in_3_ready), .io_in_3_valid(dataArb_io_in_3_valid), .io_in_3_bits_addr(dataArb_io_in_3_bits_addr), .io_in_3_bits_wdata(dataArb_io_in_3_bits_wdata), .io_in_3_bits_eccMask(dataArb_io_in_3_bits_eccMask), .io_out_valid(dataArb_io_out_valid), .io_out_bits_addr(dataArb_io_out_bits_addr), .io_out_bits_write(dataArb_io_out_bits_write), .io_out_bits_wdata(dataArb_io_out_bits_wdata), .io_out_bits_eccMask(dataArb_io_out_bits_eccMask) ); TLB tlb ( // @[DCache.scala 203:19:freechips.rocketchip.system.TinyConfig.fir@106414.4] .io_req_valid(tlb_io_req_valid), .io_req_bits_vaddr(tlb_io_req_bits_vaddr), .io_req_bits_size(tlb_io_req_bits_size), .io_req_bits_cmd(tlb_io_req_bits_cmd), .io_resp_paddr(tlb_io_resp_paddr), .io_resp_pf_ld(tlb_io_resp_pf_ld), .io_resp_pf_st(tlb_io_resp_pf_st), .io_resp_ae_ld(tlb_io_resp_ae_ld), .io_resp_ae_st(tlb_io_resp_ae_st), .io_resp_ma_ld(tlb_io_resp_ma_ld), .io_resp_ma_st(tlb_io_resp_ma_st), .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x(tlb_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w(tlb_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r(tlb_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x(tlb_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w(tlb_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r(tlb_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x(tlb_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w(tlb_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r(tlb_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x(tlb_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w(tlb_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r(tlb_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x(tlb_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w(tlb_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r(tlb_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x(tlb_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w(tlb_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r(tlb_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x(tlb_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w(tlb_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r(tlb_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x(tlb_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w(tlb_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r(tlb_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask) ); AMOALU amoalu ( // @[DCache.scala 804:24:freechips.rocketchip.system.TinyConfig.fir@109087.4] .io_cmd(amoalu_io_cmd), .io_lhs(amoalu_io_lhs), .io_rhs(amoalu_io_rhs), .io_out_unmasked(amoalu_io_out_unmasked) ); assign _T_48 = io_cpu_req_ready & io_cpu_req_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@106115.4] assign _T_49_ready = 1'h0; assign _T_54 = io_cpu_s1_kill == 1'h0; // @[DCache.scala 148:37:freechips.rocketchip.system.TinyConfig.fir@106142.4] assign s1_valid_masked = s1_valid & _T_54; // @[DCache.scala 148:34:freechips.rocketchip.system.TinyConfig.fir@106143.4] assign _T_61 = s1_req_cmd == 5'h0; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106160.4] assign _T_62 = s1_req_cmd == 5'h6; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@106161.4] assign _T_63 = _T_61 | _T_62; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106162.4] assign _T_64 = s1_req_cmd == 5'h7; // @[Consts.scala 81:65:freechips.rocketchip.system.TinyConfig.fir@106163.4] assign _T_65 = _T_63 | _T_64; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106164.4] assign _T_66 = s1_req_cmd == 5'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106165.4] assign _T_67 = s1_req_cmd == 5'h9; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106166.4] assign _T_70 = _T_66 | _T_67; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106169.4] assign _T_68 = s1_req_cmd == 5'ha; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106167.4] assign _T_71 = _T_70 | _T_68; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106170.4] assign _T_69 = s1_req_cmd == 5'hb; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106168.4] assign _T_72 = _T_71 | _T_69; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106171.4] assign _T_73 = s1_req_cmd == 5'h8; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106172.4] assign _T_74 = s1_req_cmd == 5'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106173.4] assign _T_78 = _T_73 | _T_74; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106177.4] assign _T_75 = s1_req_cmd == 5'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106174.4] assign _T_79 = _T_78 | _T_75; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106178.4] assign _T_76 = s1_req_cmd == 5'he; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106175.4] assign _T_80 = _T_79 | _T_76; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106179.4] assign _T_77 = s1_req_cmd == 5'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106176.4] assign _T_81 = _T_80 | _T_77; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106180.4] assign _T_82 = _T_72 | _T_81; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106181.4] assign s1_read = _T_65 | _T_82; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106182.4] assign _T_365 = s2_req_cmd == 5'h1; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@106599.4] assign _T_366 = s2_req_cmd == 5'h11; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106600.4] assign _T_367 = _T_365 | _T_366; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106601.4] assign _T_368 = s2_req_cmd == 5'h7; // @[Consts.scala 82:66:freechips.rocketchip.system.TinyConfig.fir@106602.4] assign _T_369 = _T_367 | _T_368; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106603.4] assign _T_370 = s2_req_cmd == 5'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106604.4] assign _T_371 = s2_req_cmd == 5'h9; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106605.4] assign _T_374 = _T_370 | _T_371; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106608.4] assign _T_372 = s2_req_cmd == 5'ha; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106606.4] assign _T_375 = _T_374 | _T_372; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106609.4] assign _T_373 = s2_req_cmd == 5'hb; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106607.4] assign _T_376 = _T_375 | _T_373; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106610.4] assign _T_377 = s2_req_cmd == 5'h8; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106611.4] assign _T_378 = s2_req_cmd == 5'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106612.4] assign _T_382 = _T_377 | _T_378; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106616.4] assign _T_379 = s2_req_cmd == 5'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106613.4] assign _T_383 = _T_382 | _T_379; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106617.4] assign _T_380 = s2_req_cmd == 5'he; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106614.4] assign _T_384 = _T_383 | _T_380; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106618.4] assign _T_381 = s2_req_cmd == 5'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106615.4] assign _T_385 = _T_384 | _T_381; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106619.4] assign _T_386 = _T_376 | _T_385; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106620.4] assign s2_write = _T_369 | _T_386; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106621.4] assign _T_890 = s2_valid & s2_write; // @[DCache.scala 400:39:freechips.rocketchip.system.TinyConfig.fir@107318.4] assign pstore1_valid_likely = _T_890 | pstore1_held; // @[DCache.scala 400:51:freechips.rocketchip.system.TinyConfig.fir@107319.4] assign _T_1005 = pstore1_addr[7:2]; // @[DCache.scala 452:9:freechips.rocketchip.system.TinyConfig.fir@107481.4] assign _T_1006 = s1_req_addr[7:2]; // @[DCache.scala 452:46:freechips.rocketchip.system.TinyConfig.fir@107482.4] assign _T_1007 = _T_1005 == _T_1006; // @[DCache.scala 452:31:freechips.rocketchip.system.TinyConfig.fir@107483.4] assign _T_83 = s1_req_cmd == 5'h1; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@106183.4] assign _T_84 = s1_req_cmd == 5'h11; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106184.4] assign _T_85 = _T_83 | _T_84; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106185.4] assign _T_87 = _T_85 | _T_64; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106187.4] assign s1_write = _T_87 | _T_82; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106205.4] assign _T_1011 = pstore1_mask[3]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107487.4] assign _T_1010 = pstore1_mask[2]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107486.4] assign _T_1009 = pstore1_mask[1]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107485.4] assign _T_1008 = pstore1_mask[0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107484.4] assign _T_1018 = {_T_1011,_T_1010,_T_1009,_T_1008}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107494.4] assign _T_1022 = _T_1018[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107498.4] assign _T_1021 = _T_1018[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107497.4] assign _T_1020 = _T_1018[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107496.4] assign _T_1019 = _T_1018[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107495.4] assign _T_1025 = {_T_1022,_T_1021,_T_1020,_T_1019}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107501.4] assign _T_298 = s1_req_addr[1]; // @[AMOALU.scala 17:27:freechips.rocketchip.system.TinyConfig.fir@106501.4] assign _T_290 = s1_req_addr[0]; // @[AMOALU.scala 17:27:freechips.rocketchip.system.TinyConfig.fir@106493.4] assign _T_292 = s1_req_size >= 2'h1; // @[AMOALU.scala 17:57:freechips.rocketchip.system.TinyConfig.fir@106495.4] assign _T_294 = _T_290 | _T_292; // @[AMOALU.scala 17:46:freechips.rocketchip.system.TinyConfig.fir@106497.4] assign _T_296 = _T_290 ? 1'h0 : 1'h1; // @[AMOALU.scala 18:22:freechips.rocketchip.system.TinyConfig.fir@106499.4] assign _T_297 = {_T_294,_T_296}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106500.4] assign _T_299 = _T_298 ? _T_297 : 2'h0; // @[AMOALU.scala 17:22:freechips.rocketchip.system.TinyConfig.fir@106502.4] assign _T_300 = s1_req_size >= 2'h2; // @[AMOALU.scala 17:57:freechips.rocketchip.system.TinyConfig.fir@106503.4] assign _T_301 = _T_300 ? 2'h3 : 2'h0; // @[AMOALU.scala 17:51:freechips.rocketchip.system.TinyConfig.fir@106504.4] assign _T_302 = _T_299 | _T_301; // @[AMOALU.scala 17:46:freechips.rocketchip.system.TinyConfig.fir@106505.4] assign _T_304 = _T_298 ? 2'h0 : _T_297; // @[AMOALU.scala 18:22:freechips.rocketchip.system.TinyConfig.fir@106507.4] assign s1_mask_xwr = {_T_302,_T_304}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106508.4] assign _T_1029 = s1_mask_xwr[3]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107505.4] assign _T_1028 = s1_mask_xwr[2]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107504.4] assign _T_1027 = s1_mask_xwr[1]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107503.4] assign _T_1026 = s1_mask_xwr[0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107502.4] assign _T_1036 = {_T_1029,_T_1028,_T_1027,_T_1026}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107512.4] assign _T_1040 = _T_1036[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107516.4] assign _T_1039 = _T_1036[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107515.4] assign _T_1038 = _T_1036[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107514.4] assign _T_1037 = _T_1036[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107513.4] assign _T_1043 = {_T_1040,_T_1039,_T_1038,_T_1037}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107519.4] assign _T_1044 = _T_1025 & _T_1043; // @[DCache.scala 453:38:freechips.rocketchip.system.TinyConfig.fir@107520.4] assign _T_1045 = _T_1044 != 4'h0; // @[DCache.scala 453:66:freechips.rocketchip.system.TinyConfig.fir@107521.4] assign _T_1046 = pstore1_mask & s1_mask_xwr; // @[DCache.scala 453:77:freechips.rocketchip.system.TinyConfig.fir@107522.4] assign _T_1047 = _T_1046 != 4'h0; // @[DCache.scala 453:92:freechips.rocketchip.system.TinyConfig.fir@107523.4] assign _T_1048 = s1_write ? _T_1045 : _T_1047; // @[DCache.scala 453:8:freechips.rocketchip.system.TinyConfig.fir@107524.4] assign _T_1049 = _T_1007 & _T_1048; // @[DCache.scala 452:68:freechips.rocketchip.system.TinyConfig.fir@107525.4] assign _T_1050 = pstore1_valid_likely & _T_1049; // @[DCache.scala 455:27:freechips.rocketchip.system.TinyConfig.fir@107526.4] assign _T_1051 = pstore2_addr[7:2]; // @[DCache.scala 452:9:freechips.rocketchip.system.TinyConfig.fir@107527.4] assign _T_1053 = _T_1051 == _T_1006; // @[DCache.scala 452:31:freechips.rocketchip.system.TinyConfig.fir@107529.4] assign _T_1057 = mask[3]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107533.4] assign _T_1056 = mask[2]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107532.4] assign _T_1055 = mask[1]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107531.4] assign _T_1054 = mask[0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107530.4] assign _T_1064 = {_T_1057,_T_1056,_T_1055,_T_1054}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107540.4] assign _T_1068 = _T_1064[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107544.4] assign _T_1067 = _T_1064[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107543.4] assign _T_1066 = _T_1064[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107542.4] assign _T_1065 = _T_1064[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.TinyConfig.fir@107541.4] assign _T_1071 = {_T_1068,_T_1067,_T_1066,_T_1065}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107547.4] assign _T_1090 = _T_1071 & _T_1043; // @[DCache.scala 453:38:freechips.rocketchip.system.TinyConfig.fir@107566.4] assign _T_1091 = _T_1090 != 4'h0; // @[DCache.scala 453:66:freechips.rocketchip.system.TinyConfig.fir@107567.4] assign _T_1092 = mask & s1_mask_xwr; // @[DCache.scala 453:77:freechips.rocketchip.system.TinyConfig.fir@107568.4] assign _T_1093 = _T_1092 != 4'h0; // @[DCache.scala 453:92:freechips.rocketchip.system.TinyConfig.fir@107569.4] assign _T_1094 = s1_write ? _T_1091 : _T_1093; // @[DCache.scala 453:8:freechips.rocketchip.system.TinyConfig.fir@107570.4] assign _T_1095 = _T_1053 & _T_1094; // @[DCache.scala 452:68:freechips.rocketchip.system.TinyConfig.fir@107571.4] assign _T_1096 = pstore2_valid & _T_1095; // @[DCache.scala 456:21:freechips.rocketchip.system.TinyConfig.fir@107572.4] assign s1_hazard = _T_1050 | _T_1096; // @[DCache.scala 455:69:freechips.rocketchip.system.TinyConfig.fir@107573.4] assign s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala 457:31:freechips.rocketchip.system.TinyConfig.fir@107574.4] assign _T_1097 = s1_valid & s1_raw_hazard; // @[DCache.scala 462:18:freechips.rocketchip.system.TinyConfig.fir@107576.4] assign _T_322 = {io_cpu_s2_xcpt_ma_ld,io_cpu_s2_xcpt_ma_st,io_cpu_s2_xcpt_pf_ld,io_cpu_s2_xcpt_pf_st,io_cpu_s2_xcpt_ae_ld,io_cpu_s2_xcpt_ae_st}; // @[DCache.scala 255:54:freechips.rocketchip.system.TinyConfig.fir@106533.4] assign _T_323 = _T_322 != 6'h0; // @[DCache.scala 255:61:freechips.rocketchip.system.TinyConfig.fir@106534.4] assign _T_324 = _T_323 == 1'h0; // @[DCache.scala 255:38:freechips.rocketchip.system.TinyConfig.fir@106535.4] assign s2_valid_no_xcpt = s2_valid & _T_324; // @[DCache.scala 255:35:freechips.rocketchip.system.TinyConfig.fir@106536.4] assign s2_valid_masked = s2_valid_no_xcpt & _T_328; // @[DCache.scala 258:42:freechips.rocketchip.system.TinyConfig.fir@106545.4] assign _T_453 = s2_req_cmd == 5'h3; // @[Consts.scala 83:54:freechips.rocketchip.system.TinyConfig.fir@106745.4] assign _T_454 = s2_write | _T_453; // @[Consts.scala 83:47:freechips.rocketchip.system.TinyConfig.fir@106746.4] assign _T_455 = s2_req_cmd == 5'h6; // @[Consts.scala 83:71:freechips.rocketchip.system.TinyConfig.fir@106747.4] assign _T_456 = _T_454 | _T_455; // @[Consts.scala 83:64:freechips.rocketchip.system.TinyConfig.fir@106748.4] assign _T_458 = {s2_write,_T_456,s2_hit_state_state}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106750.4] assign _T_516 = 4'h3 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106808.4] assign _T_513 = 4'h2 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106805.4] assign _T_510 = 4'h1 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106802.4] assign _T_507 = 4'h7 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106799.4] assign _T_504 = 4'h6 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106796.4] assign _T_501 = 4'hf == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106793.4] assign _T_498 = 4'he == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106790.4] assign _T_495 = 4'h0 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106787.4] assign _T_492 = 4'h5 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106784.4] assign _T_489 = 4'h4 == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106781.4] assign _T_486 = 4'hd == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106778.4] assign _T_483 = 4'hc == _T_458; // @[Misc.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@106775.4] assign _T_502 = _T_501 ? 1'h1 : _T_498; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106794.4] assign _T_505 = _T_504 ? 1'h1 : _T_502; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106797.4] assign _T_508 = _T_507 ? 1'h1 : _T_505; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106800.4] assign _T_511 = _T_510 ? 1'h1 : _T_508; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106803.4] assign _T_514 = _T_513 ? 1'h1 : _T_511; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106806.4] assign s2_hit = _T_516 ? 1'h1 : _T_514; // @[Misc.scala 33:9:freechips.rocketchip.system.TinyConfig.fir@106809.4] assign s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked & s2_hit; // @[DCache.scala 317:89:freechips.rocketchip.system.TinyConfig.fir@106836.4] assign _T_343 = s2_req_cmd == 5'h0; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106576.4] assign _T_345 = _T_343 | _T_455; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106578.4] assign _T_347 = _T_345 | _T_368; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106580.4] assign s2_read = _T_347 | _T_386; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106598.4] assign s2_readwrite = s2_read | s2_write; // @[DCache.scala 274:30:freechips.rocketchip.system.TinyConfig.fir@106622.4] assign s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala 318:89:freechips.rocketchip.system.TinyConfig.fir@106837.4] assign _T_485 = _T_483 ? 2'h1 : 2'h0; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106777.4] assign _T_488 = _T_486 ? 2'h2 : _T_485; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106780.4] assign _T_491 = _T_489 ? 2'h1 : _T_488; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106783.4] assign _T_494 = _T_492 ? 2'h2 : _T_491; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106786.4] assign _T_497 = _T_495 ? 2'h0 : _T_494; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106789.4] assign _T_500 = _T_498 ? 2'h3 : _T_497; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106792.4] assign _T_503 = _T_501 ? 2'h3 : _T_500; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106795.4] assign _T_506 = _T_504 ? 2'h2 : _T_503; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106798.4] assign _T_509 = _T_507 ? 2'h3 : _T_506; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106801.4] assign _T_512 = _T_510 ? 2'h1 : _T_509; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106804.4] assign _T_515 = _T_513 ? 2'h2 : _T_512; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106807.4] assign s2_grow_param = _T_516 ? 2'h3 : _T_515; // @[Misc.scala 33:36:freechips.rocketchip.system.TinyConfig.fir@106810.4] assign _T_690 = s2_hit_state_state == s2_grow_param; // @[Metadata.scala 46:46:freechips.rocketchip.system.TinyConfig.fir@107025.4] assign s2_update_meta = _T_690 == 1'h0; // @[Metadata.scala 47:40:freechips.rocketchip.system.TinyConfig.fir@107026.4] assign _T_705 = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 341:62:freechips.rocketchip.system.TinyConfig.fir@107044.4] assign _T_706 = io_cpu_s2_nack | _T_705; // @[DCache.scala 341:24:freechips.rocketchip.system.TinyConfig.fir@107045.4] assign s1_readwrite = s1_read | s1_write; // @[DCache.scala 159:30:freechips.rocketchip.system.TinyConfig.fir@106206.4] assign _T_105 = s1_req_cmd == 5'h5; // @[DCache.scala 161:34:freechips.rocketchip.system.TinyConfig.fir@106208.4] assign _T_106 = s1_req_size[0]; // @[DCache.scala 161:64:freechips.rocketchip.system.TinyConfig.fir@106209.4] assign s1_flush_line = _T_105 & _T_106; // @[DCache.scala 161:50:freechips.rocketchip.system.TinyConfig.fir@106210.4] assign s1_cmd_uses_tlb = s1_readwrite | s1_flush_line; // @[DCache.scala 204:38:freechips.rocketchip.system.TinyConfig.fir@106418.4] assign s1_nack = _T_1097 ? 1'h1 : _T_706; // @[DCache.scala 462:36:freechips.rocketchip.system.TinyConfig.fir@107577.4] assign _T_55 = s1_nack == 1'h0; // @[DCache.scala 149:41:freechips.rocketchip.system.TinyConfig.fir@106144.4] assign s1_valid_not_nacked = s1_valid & _T_55; // @[DCache.scala 149:38:freechips.rocketchip.system.TinyConfig.fir@106145.4] assign _T_56 = metaArb_io_out_bits_write == 1'h0; // @[DCache.scala 151:43:freechips.rocketchip.system.TinyConfig.fir@106147.4] assign s0_clk_en = metaArb_io_out_valid & _T_56; // @[DCache.scala 151:40:freechips.rocketchip.system.TinyConfig.fir@106148.4] assign _T_57 = metaArb_io_out_bits_addr[31:6]; // @[DCache.scala 154:49:freechips.rocketchip.system.TinyConfig.fir@106151.6] assign _T_58 = io_cpu_req_bits_addr[5:0]; // @[DCache.scala 154:86:freechips.rocketchip.system.TinyConfig.fir@106152.6] assign _T_59 = {_T_57,_T_58}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106153.6] assign _T_60 = metaArb_io_in_7_ready == 1'h0; // @[DCache.scala 155:11:freechips.rocketchip.system.TinyConfig.fir@106155.6] assign s1_sfence = s1_req_cmd == 5'h14; // @[DCache.scala 160:30:freechips.rocketchip.system.TinyConfig.fir@106207.4] assign _T_116 = io_cpu_req_bits_cmd == 5'h0; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@106243.4] assign _T_117 = io_cpu_req_bits_cmd == 5'h6; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@106244.4] assign _T_118 = _T_116 | _T_117; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@106245.4] assign _T_119 = io_cpu_req_bits_cmd == 5'h7; // @[Consts.scala 81:65:freechips.rocketchip.system.TinyConfig.fir@106246.4] assign _T_120 = _T_118 | _T_119; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@106247.4] assign _T_121 = io_cpu_req_bits_cmd == 5'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106248.4] assign _T_122 = io_cpu_req_bits_cmd == 5'h9; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106249.4] assign _T_123 = io_cpu_req_bits_cmd == 5'ha; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106250.4] assign _T_124 = io_cpu_req_bits_cmd == 5'hb; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106251.4] assign _T_125 = _T_121 | _T_122; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106252.4] assign _T_126 = _T_125 | _T_123; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106253.4] assign _T_127 = _T_126 | _T_124; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106254.4] assign _T_128 = io_cpu_req_bits_cmd == 5'h8; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106255.4] assign _T_129 = io_cpu_req_bits_cmd == 5'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106256.4] assign _T_130 = io_cpu_req_bits_cmd == 5'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106257.4] assign _T_131 = io_cpu_req_bits_cmd == 5'he; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106258.4] assign _T_132 = io_cpu_req_bits_cmd == 5'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106259.4] assign _T_133 = _T_128 | _T_129; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106260.4] assign _T_134 = _T_133 | _T_130; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106261.4] assign _T_135 = _T_134 | _T_131; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106262.4] assign _T_136 = _T_135 | _T_132; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106263.4] assign _T_137 = _T_127 | _T_136; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@106264.4] assign s0_read = _T_120 | _T_137; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@106265.4] assign _T_138 = io_cpu_req_bits_cmd == 5'h1; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106266.4] assign _T_139 = io_cpu_req_bits_cmd == 5'h3; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@106267.4] assign _T_140 = _T_138 | _T_139; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@106268.4] assign res = _T_140 == 1'h0; // @[DCache.scala 988:15:freechips.rocketchip.system.TinyConfig.fir@106269.4] assign _T_167 = io_cpu_req_bits_cmd == 5'h11; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@106296.4] assign _T_168 = _T_138 | _T_167; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@106297.4] assign _T_170 = _T_168 | _T_119; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@106299.4] assign _T_188 = _T_170 | _T_137; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@106317.4] assign _T_192 = _T_188 & _T_167; // @[DCache.scala 994:23:freechips.rocketchip.system.TinyConfig.fir@106321.4] assign _T_193 = s0_read | _T_192; // @[DCache.scala 993:21:freechips.rocketchip.system.TinyConfig.fir@106322.4] assign _T_194 = _T_193 == 1'h0; // @[DCache.scala 989:12:freechips.rocketchip.system.TinyConfig.fir@106323.4] assign _T_195 = _T_194 | res; // @[DCache.scala 989:28:freechips.rocketchip.system.TinyConfig.fir@106324.4] assign _T_197 = _T_195 | reset; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106326.4] assign _T_198 = _T_197 == 1'h0; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106327.4] assign _T_199 = io_cpu_req_valid & res; // @[DCache.scala 186:46:freechips.rocketchip.system.TinyConfig.fir@106332.4] assign _T_202 = dataArb_io_in_3_ready == 1'h0; // @[DCache.scala 192:9:freechips.rocketchip.system.TinyConfig.fir@106341.4] assign _T_203 = _T_202 & s0_read; // @[DCache.scala 192:33:freechips.rocketchip.system.TinyConfig.fir@106342.4] assign _GEN_17 = _T_203 ? 1'h0 : _T_55; // @[DCache.scala 192:45:freechips.rocketchip.system.TinyConfig.fir@106343.4] assign _T_255 = io_cpu_req_valid & _T_193; // @[DCache.scala 193:75:freechips.rocketchip.system.TinyConfig.fir@106397.4] assign _T_256 = dataArb_io_in_3_ready & _T_255; // @[DCache.scala 193:54:freechips.rocketchip.system.TinyConfig.fir@106398.4] assign _GEN_19 = _T_60 ? 1'h0 : _GEN_17; // @[DCache.scala 200:34:freechips.rocketchip.system.TinyConfig.fir@106411.4] assign _T_275 = tlb_io_resp_paddr >= 32'h80000000; // @[DCache.scala 226:35:freechips.rocketchip.system.TinyConfig.fir@106456.4] assign _T_278 = tlb_io_resp_paddr < 32'h80000100; // @[DCache.scala 226:59:freechips.rocketchip.system.TinyConfig.fir@106459.4] assign inScratchpad = _T_275 & _T_278; // @[DCache.scala 226:47:freechips.rocketchip.system.TinyConfig.fir@106460.4] assign _T_282 = auto_out_d_bits_data[7:0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106479.4] assign _T_283 = auto_out_d_bits_data[15:8]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106480.4] assign _T_284 = auto_out_d_bits_data[23:16]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106481.4] assign _T_285 = auto_out_d_bits_data[31:24]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106482.4] assign _T_288 = {_T_285,_T_284,_T_283,_T_282}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106485.4] assign _T_307 = s1_valid_masked & _T_84; // @[DCache.scala 252:28:freechips.rocketchip.system.TinyConfig.fir@106512.4] assign _T_308 = _T_307 == 1'h0; // @[DCache.scala 252:10:freechips.rocketchip.system.TinyConfig.fir@106513.4] assign _T_309 = ~ io_cpu_s1_data_mask; // @[DCache.scala 252:71:freechips.rocketchip.system.TinyConfig.fir@106514.4] assign _T_310 = s1_mask_xwr | _T_309; // @[DCache.scala 252:69:freechips.rocketchip.system.TinyConfig.fir@106515.4] assign _T_311 = _T_310 == 4'hf; // @[DCache.scala 252:93:freechips.rocketchip.system.TinyConfig.fir@106516.4] assign _T_312 = _T_308 | _T_311; // @[DCache.scala 252:53:freechips.rocketchip.system.TinyConfig.fir@106517.4] assign _T_314 = _T_312 | reset; // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106519.4] assign _T_315 = _T_314 == 1'h0; // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106520.4] assign _T_316 = s1_sfence == 1'h0; // @[DCache.scala 254:46:freechips.rocketchip.system.TinyConfig.fir@106525.4] assign _T_317 = s1_valid_masked & _T_316; // @[DCache.scala 254:43:freechips.rocketchip.system.TinyConfig.fir@106526.4] assign _T_331 = s2_req_size[0]; // @[DCache.scala 261:68:freechips.rocketchip.system.TinyConfig.fir@106550.4] assign _T_338 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala 266:29:freechips.rocketchip.system.TinyConfig.fir@106562.4] assign _T_341 = _T_340[31:12]; // @[DCache.scala 271:84:freechips.rocketchip.system.TinyConfig.fir@106573.4] assign _T_342 = s2_req_addr[11:0]; // @[DCache.scala 271:109:freechips.rocketchip.system.TinyConfig.fir@106574.4] assign s2_vaddr = {_T_341,_T_342}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106575.4] assign en = s1_valid | io_cpu_replay_next; // @[DCache.scala 286:38:freechips.rocketchip.system.TinyConfig.fir@106654.4] assign _T_395 = s1_did_read == 1'h0; // @[DCache.scala 287:64:freechips.rocketchip.system.TinyConfig.fir@106655.4] assign word_en = _T_395 ? 1'h0 : 1'h1; // @[DCache.scala 287:63:freechips.rocketchip.system.TinyConfig.fir@106656.4] assign s1_all_data_ways_0 = data_io_resp_0; // @[DCache.scala 248:29:freechips.rocketchip.system.TinyConfig.fir@106488.4 DCache.scala 248:29:freechips.rocketchip.system.TinyConfig.fir@106490.4] assign _T_397 = io_cpu_replay_next == 1'h0; // @[DCache.scala 297:28:freechips.rocketchip.system.TinyConfig.fir@106660.4] assign s1_word_en = _T_397 ? word_en : 1'h1; // @[DCache.scala 297:27:freechips.rocketchip.system.TinyConfig.fir@106661.4] assign opc = auto_out_d_bits_opcode[1:0]; // @[DCache.scala 520:26:freechips.rocketchip.system.TinyConfig.fir@108530.4] assign _T_1916 = opc & 2'h1; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@108531.4] assign data_1 = _T_1916 == 2'h1; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@108532.4] assign _T_2057 = blockUncachedGrant | s1_valid; // @[DCache.scala 616:54:freechips.rocketchip.system.TinyConfig.fir@108761.4] assign _T_2058 = data_1 & _T_2057; // @[DCache.scala 616:31:freechips.rocketchip.system.TinyConfig.fir@108762.4] assign _GEN_183 = {{1'd0}, opc}; // @[DCache.scala 530:29:freechips.rocketchip.system.TinyConfig.fir@108549.4] assign grantIsRefill = _GEN_183 == 3'h5; // @[DCache.scala 530:29:freechips.rocketchip.system.TinyConfig.fir@108549.4] assign _T_1975 = dataArb_io_in_1_ready == 1'h0; // @[DCache.scala 586:26:freechips.rocketchip.system.TinyConfig.fir@108660.4] assign _T_1976 = grantIsRefill & _T_1975; // @[DCache.scala 586:23:freechips.rocketchip.system.TinyConfig.fir@108661.4] assign _T_1928 = _GEN_183 == 3'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108545.4] assign grantIsCached = _T_1928 | grantIsRefill; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108547.4] assign d_first = _T_1898 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@108504.4] assign _T_1936 = d_first == 1'h0; // @[DCache.scala 535:41:freechips.rocketchip.system.TinyConfig.fir@108562.4] assign _T_1940 = grantIsCached ? _T_1936 : 1'h1; // @[DCache.scala 535:24:freechips.rocketchip.system.TinyConfig.fir@108567.4] assign _GEN_157 = _T_1976 ? 1'h0 : _T_1940; // @[DCache.scala 586:51:freechips.rocketchip.system.TinyConfig.fir@108662.4] assign tl_out__d_ready = _T_2058 ? 1'h0 : _GEN_157; // @[DCache.scala 616:68:freechips.rocketchip.system.TinyConfig.fir@108763.4] assign _T_1942 = tl_out__d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@108572.4] assign _GEN_114 = data_1 ? 2'h2 : 2'h1; // @[DCache.scala 555:34:freechips.rocketchip.system.TinyConfig.fir@108604.10] assign _GEN_136 = grantIsCached ? 2'h1 : _GEN_114; // @[DCache.scala 539:26:freechips.rocketchip.system.TinyConfig.fir@108574.6] assign s1_data_way = _T_1942 ? _GEN_136 : 2'h1; // @[DCache.scala 538:26:freechips.rocketchip.system.TinyConfig.fir@108573.4] assign _T_399 = s1_word_en ? s1_data_way : 2'h0; // @[DCache.scala 299:28:freechips.rocketchip.system.TinyConfig.fir@106663.4] assign _T_400 = _T_399[0]; // @[Mux.scala 30:36:freechips.rocketchip.system.TinyConfig.fir@106664.4] assign _T_401 = _T_399[1]; // @[Mux.scala 30:36:freechips.rocketchip.system.TinyConfig.fir@106665.4] assign _T_402 = _T_400 ? s1_all_data_ways_0 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106666.4] assign _T_403 = _T_401 ? _T_288 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106667.4] assign _T_404 = _T_402 | _T_403; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@106668.4] assign s2_hit_valid = s2_hit_state_state > 2'h0; // @[Metadata.scala 50:45:freechips.rocketchip.system.TinyConfig.fir@106698.4] assign _T_517 = s2_data[7:0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106814.4] assign _T_518 = s2_data[15:8]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106815.4] assign _T_519 = s2_data[23:16]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106816.4] assign _T_520 = s2_data[31:24]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@106817.4] assign _T_529 = {_T_518,_T_517}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106828.4] assign _T_530 = {_T_520,_T_519}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106829.4] assign s2_data_corrected = {_T_520,_T_519,_T_518,_T_517}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106830.4] assign _T_540 = s2_valid_masked & s2_readwrite; // @[DCache.scala 323:39:freechips.rocketchip.system.TinyConfig.fir@106847.4] assign _T_543 = s2_hit == 1'h0; // @[DCache.scala 323:76:freechips.rocketchip.system.TinyConfig.fir@106850.4] assign s2_valid_miss = _T_540 & _T_543; // @[DCache.scala 323:73:freechips.rocketchip.system.TinyConfig.fir@106851.4] assign _T_548 = uncachedInFlight_0 == 1'h0; // @[DCache.scala 324:63:freechips.rocketchip.system.TinyConfig.fir@106856.4] assign s2_valid_cached_miss = 1'h0; // @[DCache.scala 324:60:freechips.rocketchip.system.TinyConfig.fir@106857.4] assign _T_552 = s2_flush_valid_pre_tag_ecc == 1'h0; // @[DCache.scala 327:29:freechips.rocketchip.system.TinyConfig.fir@106862.4] assign s2_valid_uncached_pending = s2_valid_miss & _T_548; // @[DCache.scala 329:64:freechips.rocketchip.system.TinyConfig.fir@106869.4] assign s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[DCache.scala 332:28:freechips.rocketchip.system.TinyConfig.fir@106890.4] assign _T_631 = {2'h2,s2_victim_state_state}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@106961.4] assign _T_656 = 4'hb == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106986.4] assign _T_660 = 4'h4 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106990.4] assign _T_661 = _T_660 ? 1'h0 : _T_656; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106991.4] assign _T_664 = 4'h5 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106994.4] assign _T_665 = _T_664 ? 1'h0 : _T_661; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106995.4] assign _T_668 = 4'h6 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@106998.4] assign _T_669 = _T_668 ? 1'h0 : _T_665; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@106999.4] assign _T_672 = 4'h7 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107002.4] assign _T_673 = _T_672 ? 1'h1 : _T_669; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107003.4] assign _T_676 = 4'h0 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107006.4] assign _T_677 = _T_676 ? 1'h0 : _T_673; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107007.4] assign _T_680 = 4'h1 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107010.4] assign _T_681 = _T_680 ? 1'h0 : _T_677; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107011.4] assign _T_684 = 4'h2 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107014.4] assign _T_685 = _T_684 ? 1'h0 : _T_681; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107015.4] assign _T_688 = 4'h3 == _T_631; // @[Misc.scala 54:20:freechips.rocketchip.system.TinyConfig.fir@107018.4] assign s2_victim_dirty = _T_688 ? 1'h1 : _T_685; // @[Misc.scala 36:9:freechips.rocketchip.system.TinyConfig.fir@107019.4] assign s2_dont_nack_uncached = s2_valid_uncached_pending & auto_out_a_ready; // @[DCache.scala 338:57:freechips.rocketchip.system.TinyConfig.fir@107027.4] assign _T_699 = s2_dont_nack_uncached == 1'h0; // @[DCache.scala 340:41:freechips.rocketchip.system.TinyConfig.fir@107037.4] assign _T_700 = s2_valid_no_xcpt & _T_699; // @[DCache.scala 340:38:freechips.rocketchip.system.TinyConfig.fir@107038.4] assign _T_703 = s2_valid_hit_pre_data_ecc_and_waw == 1'h0; // @[DCache.scala 340:90:freechips.rocketchip.system.TinyConfig.fir@107041.4] assign _T_718 = io_cpu_req_bits_addr[31:8]; // @[DCache.scala 349:58:freechips.rocketchip.system.TinyConfig.fir@107064.4] assign _T_729 = s2_vaddr[7:0]; // @[DCache.scala 361:80:freechips.rocketchip.system.TinyConfig.fir@107089.4] assign _T_760 = s1_valid_not_nacked & s1_write; // @[DCache.scala 387:63:freechips.rocketchip.system.TinyConfig.fir@107149.4] assign _T_814 = s1_write & _T_84; // @[DCache.scala 994:23:freechips.rocketchip.system.TinyConfig.fir@107226.4] assign _T_815 = s1_read | _T_814; // @[DCache.scala 993:21:freechips.rocketchip.system.TinyConfig.fir@107227.4] assign _T_819 = s2_valid_hit_pre_data_ecc_and_waw & s2_write; // @[DCache.scala 385:46:freechips.rocketchip.system.TinyConfig.fir@107236.4] assign pstore_drain_opportunistic = _T_199 == 1'h0; // @[DCache.scala 397:36:freechips.rocketchip.system.TinyConfig.fir@107310.4] assign pstore1_valid = _T_819 | pstore1_held; // @[DCache.scala 402:38:freechips.rocketchip.system.TinyConfig.fir@107325.4] assign _T_897 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala 404:54:freechips.rocketchip.system.TinyConfig.fir@107328.4] assign _T_898 = s1_valid & s1_write; // @[DCache.scala 404:85:freechips.rocketchip.system.TinyConfig.fir@107329.4] assign _T_899 = _T_898 | pstore1_rmw; // @[DCache.scala 404:98:freechips.rocketchip.system.TinyConfig.fir@107330.4] assign pstore_drain_structural = _T_897 & _T_899; // @[DCache.scala 404:71:freechips.rocketchip.system.TinyConfig.fir@107331.4] assign _T_904 = pstore1_valid == pstore1_valid; // @[DCache.scala 405:63:freechips.rocketchip.system.TinyConfig.fir@107336.4] assign _T_905 = pstore1_rmw | _T_904; // @[DCache.scala 405:22:freechips.rocketchip.system.TinyConfig.fir@107337.4] assign _T_907 = _T_905 | reset; // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107339.4] assign _T_908 = _T_907 == 1'h0; // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107340.4] assign _T_917 = pstore1_rmw == 1'h0; // @[DCache.scala 413:44:freechips.rocketchip.system.TinyConfig.fir@107354.4] assign _T_918 = pstore1_valid & _T_917; // @[DCache.scala 413:41:freechips.rocketchip.system.TinyConfig.fir@107355.4] assign _T_919 = _T_918 | pstore2_valid; // @[DCache.scala 413:58:freechips.rocketchip.system.TinyConfig.fir@107356.4] assign _T_920 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala 413:107:freechips.rocketchip.system.TinyConfig.fir@107357.4] assign _T_921 = _T_919 & _T_920; // @[DCache.scala 413:76:freechips.rocketchip.system.TinyConfig.fir@107358.4] assign pstore_drain = pstore_drain_structural | _T_921; // @[DCache.scala 412:48:freechips.rocketchip.system.TinyConfig.fir@107359.4] assign _T_931 = pstore1_valid & pstore2_valid; // @[DCache.scala 416:71:freechips.rocketchip.system.TinyConfig.fir@107369.4] assign _T_932 = pstore_drain == 1'h0; // @[DCache.scala 416:91:freechips.rocketchip.system.TinyConfig.fir@107370.4] assign _T_935 = pstore2_valid == pstore_drain; // @[DCache.scala 417:79:freechips.rocketchip.system.TinyConfig.fir@107374.4] assign advance_pstore1 = pstore1_valid & _T_935; // @[DCache.scala 417:61:freechips.rocketchip.system.TinyConfig.fir@107375.4] assign _T_937 = pstore2_valid & _T_932; // @[DCache.scala 418:34:freechips.rocketchip.system.TinyConfig.fir@107377.4] assign _T_2235 = _T_1011 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109107.4] assign _T_2233 = _T_1010 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109105.4] assign _T_2231 = _T_1009 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109103.4] assign _T_2229 = _T_1008 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109101.4] assign mask_1 = {_T_2235,_T_2233,_T_2231,_T_2229}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109110.4] assign _T_2238 = amoalu_io_out_unmasked & mask_1; // @[DCache.scala 811:30:freechips.rocketchip.system.TinyConfig.fir@109111.4] assign _T_2239 = ~ mask_1; // @[DCache.scala 811:64:freechips.rocketchip.system.TinyConfig.fir@109112.4] assign _T_2240 = s2_data_corrected & _T_2239; // @[DCache.scala 811:62:freechips.rocketchip.system.TinyConfig.fir@109113.4] assign pstore1_storegen_data = _T_2238 | _T_2240; // @[DCache.scala 811:37:freechips.rocketchip.system.TinyConfig.fir@109114.4] assign _T_941 = pstore1_storegen_data[7:0]; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107390.4] assign _T_946 = pstore1_storegen_data[15:8]; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107398.4] assign _T_951 = pstore1_storegen_data[23:16]; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107406.4] assign _T_956 = pstore1_storegen_data[31:24]; // @[DCache.scala 423:44:freechips.rocketchip.system.TinyConfig.fir@107414.4] assign pstore2_storegen_data = {_T_960,_T_955,_T_950,_T_945}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107424.4] assign _T_965 = ~ pstore1_mask; // @[DCache.scala 429:37:freechips.rocketchip.system.TinyConfig.fir@107430.6] assign _T_967 = ~ _T_965; // @[DCache.scala 429:15:freechips.rocketchip.system.TinyConfig.fir@107432.6] assign _T_981 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala 444:36:freechips.rocketchip.system.TinyConfig.fir@107452.4] assign _T_983 = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[DCache.scala 446:63:freechips.rocketchip.system.TinyConfig.fir@107456.4] assign _T_984 = _T_983[7:0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107457.4] assign _T_985 = _T_983[15:8]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107458.4] assign _T_986 = _T_983[23:16]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107459.4] assign _T_987 = _T_983[31:24]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107460.4] assign _T_988 = {_T_985,_T_984}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107461.4] assign _T_989 = {_T_987,_T_986}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107462.4] assign _T_993 = pstore2_valid ? mask : pstore1_mask; // @[DCache.scala 448:47:freechips.rocketchip.system.TinyConfig.fir@107468.4] assign _T_994 = _T_993[0]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107469.4] assign _T_995 = _T_993[1]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107470.4] assign _T_996 = _T_993[2]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107471.4] assign _T_997 = _T_993[3]; // @[package.scala 160:50:freechips.rocketchip.system.TinyConfig.fir@107472.4] assign _T_1002 = {_T_995,_T_994}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107477.4] assign _T_1003 = {_T_997,_T_996}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107478.4] assign _T_1155 = 2'h1 << _T_331; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@107647.4] assign _T_1157 = _T_1155 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@107649.4] assign _T_1158 = s2_req_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@107650.4] assign _T_1159 = _T_1157[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@107651.4] assign _T_1160 = s2_req_addr[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@107652.4] assign _T_1161 = _T_1160 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@107653.4] assign _T_1163 = _T_1159 & _T_1161; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107655.4] assign _T_1164 = _T_1158 | _T_1163; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107656.4] assign _T_1166 = _T_1159 & _T_1160; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107658.4] assign _T_1167 = _T_1158 | _T_1166; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107659.4] assign _T_1168 = _T_1157[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@107660.4] assign _T_1169 = s2_req_addr[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@107661.4] assign _T_1170 = _T_1169 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@107662.4] assign _T_1171 = _T_1161 & _T_1170; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107663.4] assign _T_1172 = _T_1168 & _T_1171; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107664.4] assign _T_1173 = _T_1164 | _T_1172; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107665.4] assign _T_1174 = _T_1161 & _T_1169; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107666.4] assign _T_1175 = _T_1168 & _T_1174; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107667.4] assign _T_1176 = _T_1164 | _T_1175; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107668.4] assign _T_1177 = _T_1160 & _T_1170; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107669.4] assign _T_1178 = _T_1168 & _T_1177; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107670.4] assign _T_1179 = _T_1167 | _T_1178; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107671.4] assign _T_1180 = _T_1160 & _T_1169; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@107672.4] assign _T_1181 = _T_1168 & _T_1180; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@107673.4] assign _T_1182 = _T_1167 | _T_1181; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@107674.4] assign get_mask = {_T_1182,_T_1179,_T_1176,_T_1173}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@107677.4] assign _T_1858 = 5'hf == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108445.4] assign _T_1859_opcode = _T_1858 ? 3'h2 : 3'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1859_param = _T_1858 ? 3'h3 : 3'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1824_size = {{2'd0}, s2_req_size}; // @[Edges.scala 487:17:freechips.rocketchip.system.TinyConfig.fir@108402.4 Edges.scala 490:15:freechips.rocketchip.system.TinyConfig.fir@108406.4] assign _T_1859_size = _T_1858 ? _T_1824_size : 4'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1859_address = _T_1858 ? s2_req_addr : 32'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1859_mask = _T_1858 ? get_mask : 4'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1859_data = _T_1858 ? pstore1_data : 32'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108446.4] assign _T_1860 = 5'he == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108447.4] assign _T_1861_opcode = _T_1860 ? 3'h2 : _T_1859_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1861_param = _T_1860 ? 3'h2 : _T_1859_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1861_size = _T_1860 ? _T_1824_size : _T_1859_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1861_address = _T_1860 ? s2_req_addr : _T_1859_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1861_mask = _T_1860 ? get_mask : _T_1859_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1861_data = _T_1860 ? pstore1_data : _T_1859_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108448.4] assign _T_1862 = 5'hd == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108449.4] assign _T_1863_opcode = _T_1862 ? 3'h2 : _T_1861_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1863_param = _T_1862 ? 3'h1 : _T_1861_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1863_size = _T_1862 ? _T_1824_size : _T_1861_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1863_address = _T_1862 ? s2_req_addr : _T_1861_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1863_mask = _T_1862 ? get_mask : _T_1861_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1863_data = _T_1862 ? pstore1_data : _T_1861_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108450.4] assign _T_1864 = 5'hc == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108451.4] assign _T_1865_opcode = _T_1864 ? 3'h2 : _T_1863_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1865_param = _T_1864 ? 3'h0 : _T_1863_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1865_size = _T_1864 ? _T_1824_size : _T_1863_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1865_address = _T_1864 ? s2_req_addr : _T_1863_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1865_mask = _T_1864 ? get_mask : _T_1863_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1865_data = _T_1864 ? pstore1_data : _T_1863_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108452.4] assign _T_1866 = 5'h8 == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108453.4] assign _T_1867_opcode = _T_1866 ? 3'h2 : _T_1865_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1867_param = _T_1866 ? 3'h4 : _T_1865_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1867_size = _T_1866 ? _T_1824_size : _T_1865_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1867_address = _T_1866 ? s2_req_addr : _T_1865_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1867_mask = _T_1866 ? get_mask : _T_1865_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1867_data = _T_1866 ? pstore1_data : _T_1865_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108454.4] assign _T_1868 = 5'hb == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108455.4] assign _T_1869_opcode = _T_1868 ? 3'h3 : _T_1867_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1869_param = _T_1868 ? 3'h2 : _T_1867_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1869_size = _T_1868 ? _T_1824_size : _T_1867_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1869_address = _T_1868 ? s2_req_addr : _T_1867_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1869_mask = _T_1868 ? get_mask : _T_1867_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1869_data = _T_1868 ? pstore1_data : _T_1867_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108456.4] assign _T_1870 = 5'ha == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108457.4] assign _T_1871_opcode = _T_1870 ? 3'h3 : _T_1869_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1871_param = _T_1870 ? 3'h1 : _T_1869_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1871_size = _T_1870 ? _T_1824_size : _T_1869_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1871_address = _T_1870 ? s2_req_addr : _T_1869_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1871_mask = _T_1870 ? get_mask : _T_1869_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1871_data = _T_1870 ? pstore1_data : _T_1869_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108458.4] assign _T_1872 = 5'h9 == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108459.4] assign _T_1873_opcode = _T_1872 ? 3'h3 : _T_1871_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1873_param = _T_1872 ? 3'h0 : _T_1871_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1873_size = _T_1872 ? _T_1824_size : _T_1871_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1873_address = _T_1872 ? s2_req_addr : _T_1871_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1873_mask = _T_1872 ? get_mask : _T_1871_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1873_data = _T_1872 ? pstore1_data : _T_1871_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108460.4] assign _T_1874 = 5'h4 == s2_req_cmd; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@108461.4] assign atomics_opcode = _T_1874 ? 3'h3 : _T_1873_opcode; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign atomics_param = _T_1874 ? 3'h3 : _T_1873_param; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign atomics_size = _T_1874 ? _T_1824_size : _T_1873_size; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign atomics_address = _T_1874 ? s2_req_addr : _T_1873_address; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign atomics_mask = _T_1874 ? get_mask : _T_1873_mask; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign atomics_data = _T_1874 ? pstore1_data : _T_1873_data; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@108462.4] assign _T_1876 = s2_victim_dirty == 1'h0; // @[DCache.scala 492:109:freechips.rocketchip.system.TinyConfig.fir@108464.4] assign _T_1878 = _T_49_ready & _T_1876; // @[DCache.scala 492:63:freechips.rocketchip.system.TinyConfig.fir@108466.4] assign tl_out_a_valid = _T_1878 | s2_valid_uncached_pending; // @[DCache.scala 492:128:freechips.rocketchip.system.TinyConfig.fir@108467.4] assign _T_1883 = s2_write == 1'h0; // @[DCache.scala 493:89:freechips.rocketchip.system.TinyConfig.fir@108473.4] assign _T_1884 = s2_read == 1'h0; // @[DCache.scala 493:109:freechips.rocketchip.system.TinyConfig.fir@108474.4] assign _T_1885_opcode = _T_1884 ? 3'h0 : atomics_opcode; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1885_param = _T_1884 ? 3'h0 : atomics_param; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1885_size = _T_1884 ? _T_1824_size : atomics_size; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1885_address = _T_1884 ? s2_req_addr : atomics_address; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1885_mask = _T_1884 ? get_mask : atomics_mask; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1885_data = _T_1884 ? pstore1_data : atomics_data; // @[DCache.scala 493:108:freechips.rocketchip.system.TinyConfig.fir@108475.4] assign _T_1888 = auto_out_a_ready & tl_out_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@108480.4] assign _T_1892 = 27'hfff << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@108495.4] assign _T_1893 = _T_1892[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@108496.4] assign _T_1894 = ~ _T_1893; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@108497.4] assign _T_1895 = _T_1894[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@108498.4] assign _T_1896 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@108499.4] assign _T_1897 = _T_1896 ? _T_1895 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@108500.4] assign _T_1900 = _T_1898 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@108503.4] assign _T_1901 = _T_1898 == 10'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@108505.4] assign _T_1902 = _T_1897 == 10'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@108506.4] assign d_last = _T_1901 | _T_1902; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@108507.4] assign d_done = d_last & _T_1942; // @[Edges.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@108508.4] assign _T_1906 = auto_out_d_valid == 1'h0; // @[DCache.scala 518:14:freechips.rocketchip.system.TinyConfig.fir@108516.4] assign _T_1907 = auto_out_d_bits_opcode == 3'h1; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108517.4] assign _T_1908 = auto_out_d_bits_opcode == 3'h0; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108518.4] assign _T_1909 = auto_out_d_bits_opcode == 3'h2; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@108519.4] assign _T_1910 = _T_1907 | _T_1908; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108520.4] assign _T_1911 = _T_1910 | _T_1909; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@108521.4] assign _T_1912 = _T_1906 | _T_1911; // @[DCache.scala 518:30:freechips.rocketchip.system.TinyConfig.fir@108522.4] assign _T_1914 = _T_1912 | reset; // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108524.4] assign _T_1915 = _T_1914 == 1'h0; // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108525.4] assign _T_1945 = reset == 1'h0; // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108578.8] assign _T_1949 = uncachedInFlight_0 | reset; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108596.12] assign _T_1950 = _T_1949 == 1'h0; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108597.12] assign _T_1952 = tlb_io_resp_paddr[31:2]; // @[DCache.scala 565:41:freechips.rocketchip.system.TinyConfig.fir@108611.12] assign dontCareBits = {_T_1952, 2'h0}; // @[DCache.scala 565:55:freechips.rocketchip.system.TinyConfig.fir@108612.12] assign _T_1953 = uncachedReqs_0_addr[1:0]; // @[DCache.scala 566:45:freechips.rocketchip.system.TinyConfig.fir@108613.12] assign _GEN_187 = {{30'd0}, _T_1953}; // @[DCache.scala 566:26:freechips.rocketchip.system.TinyConfig.fir@108614.12] assign _T_1954 = dontCareBits | _GEN_187; // @[DCache.scala 566:26:freechips.rocketchip.system.TinyConfig.fir@108614.12] assign _T_1967 = _T_1942 & d_first; // @[DCache.scala 580:47:freechips.rocketchip.system.TinyConfig.fir@108647.4] assign _T_1968 = _T_1967 & grantIsCached; // @[DCache.scala 580:58:freechips.rocketchip.system.TinyConfig.fir@108648.4] assign _T_1969 = 1'h0 == _T_1968; // @[DCache.scala 580:26:freechips.rocketchip.system.TinyConfig.fir@108649.4] assign _T_1971 = _T_1969 | reset; // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108651.4] assign _T_1972 = _T_1971 == 1'h0; // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108652.4] assign _T_1973 = auto_out_d_valid & grantIsRefill; // @[DCache.scala 585:44:freechips.rocketchip.system.TinyConfig.fir@108657.4] assign _T_1978 = grantIsCached & d_done; // @[DCache.scala 605:43:freechips.rocketchip.system.TinyConfig.fir@108669.4] assign _T_1979 = auto_out_d_bits_denied == 1'h0; // @[DCache.scala 605:56:freechips.rocketchip.system.TinyConfig.fir@108670.4] assign _GEN_158 = auto_out_d_valid ? 1'h0 : _GEN_19; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] assign _GEN_159 = auto_out_d_valid ? 1'h1 : _T_1973; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] assign _GEN_160 = auto_out_d_valid ? 1'h0 : dataArb_io_in_0_bits_write; // @[DCache.scala 619:29:freechips.rocketchip.system.TinyConfig.fir@108765.6] assign _T_2130 = s1_req_phys == 1'h0; // @[DCache.scala 748:35:freechips.rocketchip.system.TinyConfig.fir@108929.4] assign _T_2131 = s1_valid & _T_2130; // @[DCache.scala 748:32:freechips.rocketchip.system.TinyConfig.fir@108930.4] assign _T_2132 = s2_req_phys == 1'h0; // @[DCache.scala 748:72:freechips.rocketchip.system.TinyConfig.fir@108931.4] assign _T_2133 = s2_valid & _T_2132; // @[DCache.scala 748:69:freechips.rocketchip.system.TinyConfig.fir@108932.4] assign _T_2134 = _T_2131 | _T_2133; // @[DCache.scala 748:57:freechips.rocketchip.system.TinyConfig.fir@108933.4] assign _T_2137 = _T_2134 | uncachedInFlight_0; // @[DCache.scala 748:115:freechips.rocketchip.system.TinyConfig.fir@108936.4] assign _T_2157_pf_ld = _T_2140 ? s2_tlb_resp_pf_ld : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2157_pf_st = _T_2140 ? s2_tlb_resp_pf_st : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2157_ae_ld = _T_2140 ? s2_tlb_resp_ae_ld : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2157_ae_st = _T_2140 ? s2_tlb_resp_ae_st : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2157_ma_ld = _T_2140 ? s2_tlb_resp_ma_ld : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2157_ma_st = _T_2140 ? s2_tlb_resp_ma_st : 1'h0; // @[DCache.scala 751:24:freechips.rocketchip.system.TinyConfig.fir@108976.4] assign _T_2158 = s2_valid == 1'h0; // @[DCache.scala 756:14:freechips.rocketchip.system.TinyConfig.fir@108979.6] assign _T_2159 = _T_2158 | s2_hit_valid; // @[DCache.scala 756:24:freechips.rocketchip.system.TinyConfig.fir@108980.6] assign _T_2161 = _T_2159 | reset; // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108982.6] assign _T_2162 = _T_2161 == 1'h0; // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108983.6] assign _T_2173 = _T_455 | _T_368; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@109009.4] assign _T_2174 = s2_valid_masked & _T_2173; // @[DCache.scala 759:30:freechips.rocketchip.system.TinyConfig.fir@109010.4] assign _T_2175 = _T_2174 == 1'h0; // @[DCache.scala 759:12:freechips.rocketchip.system.TinyConfig.fir@109011.4] assign _T_2177 = _T_2175 | reset; // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109013.4] assign _T_2178 = _T_2177 == 1'h0; // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109014.4] assign _T_2187 = _T_703 | reset; // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109037.6] assign _T_2188 = _T_2187 == 1'h0; // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109038.6] assign _T_2193 = s2_data_corrected[31:16]; // @[AMOALU.scala 39:37:freechips.rocketchip.system.TinyConfig.fir@109053.4] assign _T_2194 = s2_data_corrected[15:0]; // @[AMOALU.scala 39:55:freechips.rocketchip.system.TinyConfig.fir@109054.4] assign _T_2195 = _T_1160 ? _T_2193 : _T_2194; // @[AMOALU.scala 39:24:freechips.rocketchip.system.TinyConfig.fir@109055.4] assign _T_2198 = s2_req_size == 2'h1; // @[AMOALU.scala 42:26:freechips.rocketchip.system.TinyConfig.fir@109058.4] assign _T_2200 = _T_2195[15]; // @[AMOALU.scala 42:85:freechips.rocketchip.system.TinyConfig.fir@109060.4] assign _T_2201 = s2_req_signed & _T_2200; // @[AMOALU.scala 42:76:freechips.rocketchip.system.TinyConfig.fir@109061.4] assign _T_2203 = _T_2201 ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109063.4] assign _T_2205 = _T_2198 ? _T_2203 : _T_2193; // @[AMOALU.scala 42:20:freechips.rocketchip.system.TinyConfig.fir@109065.4] assign _T_2206 = {_T_2205,_T_2195}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109066.4] assign _T_2208 = _T_2206[15:8]; // @[AMOALU.scala 39:37:freechips.rocketchip.system.TinyConfig.fir@109068.4] assign _T_2209 = _T_2206[7:0]; // @[AMOALU.scala 39:55:freechips.rocketchip.system.TinyConfig.fir@109069.4] assign _T_2210 = _T_1169 ? _T_2208 : _T_2209; // @[AMOALU.scala 39:24:freechips.rocketchip.system.TinyConfig.fir@109070.4] assign _T_2213 = s2_req_size == 2'h0; // @[AMOALU.scala 42:26:freechips.rocketchip.system.TinyConfig.fir@109073.4] assign _T_2215 = _T_2210[7]; // @[AMOALU.scala 42:85:freechips.rocketchip.system.TinyConfig.fir@109075.4] assign _T_2216 = s2_req_signed & _T_2215; // @[AMOALU.scala 42:76:freechips.rocketchip.system.TinyConfig.fir@109076.4] assign _T_2218 = _T_2216 ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@109078.4] assign _T_2219 = _T_2206[31:8]; // @[AMOALU.scala 42:98:freechips.rocketchip.system.TinyConfig.fir@109079.4] assign _T_2220 = _T_2213 ? _T_2218 : _T_2219; // @[AMOALU.scala 42:20:freechips.rocketchip.system.TinyConfig.fir@109080.4] assign _T_2247 = metaArb_io_in_5_ready & metaArb_io_in_5_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109126.4] assign _T_2248 = s1_flush_valid == 1'h0; // @[DCache.scala 827:48:freechips.rocketchip.system.TinyConfig.fir@109127.4] assign _T_2249 = _T_2247 & _T_2248; // @[DCache.scala 827:45:freechips.rocketchip.system.TinyConfig.fir@109128.4] assign _T_2436 = grantIsCached == 1'h0; // @[DCache.scala 937:35:freechips.rocketchip.system.TinyConfig.fir@109358.4] assign auto_out_a_valid = _T_1878 | s2_valid_uncached_pending; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_opcode = _T_1883 ? 3'h4 : _T_1885_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_param = _T_1883 ? 3'h0 : _T_1885_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_size = _T_1883 ? _T_1824_size : _T_1885_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_address = _T_1883 ? s2_req_addr : _T_1885_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_mask = _T_1883 ? get_mask : _T_1885_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_a_bits_data = _T_1883 ? 32'h0 : _T_1885_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign auto_out_d_ready = _T_2058 ? 1'h0 : _GEN_157; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@105990.4] assign io_cpu_req_ready = _T_2058 ? _GEN_158 : _GEN_19; // @[DCache.scala 177:20:freechips.rocketchip.system.TinyConfig.fir@106234.4 DCache.scala 192:64:freechips.rocketchip.system.TinyConfig.fir@106344.6 DCache.scala 200:53:freechips.rocketchip.system.TinyConfig.fir@106412.6 DCache.scala 212:98:freechips.rocketchip.system.TinyConfig.fir@106435.6 DCache.scala 620:26:freechips.rocketchip.system.TinyConfig.fir@108766.8] assign io_cpu_s2_nack = _T_700 & _T_703; // @[DCache.scala 340:18:freechips.rocketchip.system.TinyConfig.fir@107043.4] assign io_cpu_resp_valid = s2_valid_hit_pre_data_ecc_and_waw | doUncachedResp; // @[DCache.scala 772:21:freechips.rocketchip.system.TinyConfig.fir@109029.4] assign io_cpu_resp_bits_addr = doUncachedResp ? s2_uncached_resp_addr : s2_req_addr; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4 DCache.scala 777:27:freechips.rocketchip.system.TinyConfig.fir@109044.6] assign io_cpu_resp_bits_tag = s2_req_tag; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4] assign io_cpu_resp_bits_cmd = s2_req_cmd; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4] assign io_cpu_resp_bits_size = s2_req_size; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4] assign io_cpu_resp_bits_signed = s2_req_signed; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4] assign io_cpu_resp_bits_data = {_T_2220,_T_2210}; // @[DCache.scala 738:20:freechips.rocketchip.system.TinyConfig.fir@108920.4 DCache.scala 796:25:freechips.rocketchip.system.TinyConfig.fir@109083.4] assign io_cpu_resp_bits_replay = doUncachedResp; // @[DCache.scala 740:27:freechips.rocketchip.system.TinyConfig.fir@108922.4 DCache.scala 776:29:freechips.rocketchip.system.TinyConfig.fir@109043.6] assign io_cpu_resp_bits_has_data = _T_347 | _T_386; // @[DCache.scala 739:29:freechips.rocketchip.system.TinyConfig.fir@108921.4] assign io_cpu_resp_bits_data_word_bypass = {_T_530,_T_529}; // @[DCache.scala 797:37:freechips.rocketchip.system.TinyConfig.fir@109084.4] assign io_cpu_resp_bits_data_raw = {_T_530,_T_529}; // @[DCache.scala 798:29:freechips.rocketchip.system.TinyConfig.fir@109085.4] assign io_cpu_resp_bits_store_data = pstore1_data; // @[DCache.scala 799:31:freechips.rocketchip.system.TinyConfig.fir@109086.4] assign io_cpu_replay_next = _T_1942 & data_1; // @[DCache.scala 773:22:freechips.rocketchip.system.TinyConfig.fir@109033.4] assign io_cpu_s2_xcpt_ma_ld = s2_req_phys ? 1'h0 : _T_2157_ma_ld; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_s2_xcpt_ma_st = s2_req_phys ? 1'h0 : _T_2157_ma_st; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_s2_xcpt_pf_ld = s2_req_phys ? 1'h0 : _T_2157_pf_ld; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_s2_xcpt_pf_st = s2_req_phys ? 1'h0 : _T_2157_pf_st; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_s2_xcpt_ae_ld = s2_req_phys ? 1'h0 : _T_2157_ae_ld; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_s2_xcpt_ae_st = s2_req_phys ? 1'h0 : _T_2157_ae_st; // @[DCache.scala 751:18:freechips.rocketchip.system.TinyConfig.fir@108977.4 DCache.scala 757:22:freechips.rocketchip.system.TinyConfig.fir@109005.6] assign io_cpu_ordered = _T_2137 == 1'h0; // @[DCache.scala 748:18:freechips.rocketchip.system.TinyConfig.fir@108938.4] assign io_cpu_perf_grant = d_last & _T_1942; // @[DCache.scala 888:21:freechips.rocketchip.system.TinyConfig.fir@109241.4] assign metaArb_io_in_2_valid = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 357:26:freechips.rocketchip.system.TinyConfig.fir@107080.4] assign metaArb_io_in_2_bits_addr = {_T_718,_T_729}; // @[DCache.scala 361:30:freechips.rocketchip.system.TinyConfig.fir@107091.4] assign metaArb_io_in_3_valid = _T_1978 & _T_1979; // @[DCache.scala 605:26:freechips.rocketchip.system.TinyConfig.fir@108672.4] assign metaArb_io_in_3_bits_addr = {_T_718,_T_729}; // @[DCache.scala 609:30:freechips.rocketchip.system.TinyConfig.fir@108680.4] assign metaArb_io_in_5_valid = 1'h0; // @[DCache.scala 828:26:freechips.rocketchip.system.TinyConfig.fir@109138.4] assign metaArb_io_in_7_valid = io_cpu_req_valid; // @[DCache.scala 194:26:freechips.rocketchip.system.TinyConfig.fir@106403.4] assign metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr; // @[DCache.scala 197:30:freechips.rocketchip.system.TinyConfig.fir@106407.4] assign data_clock = gated_clock; // @[:freechips.rocketchip.system.TinyConfig.fir@106087.4] assign data_io_req_valid = dataArb_io_out_valid; // @[DCache.scala 118:15:freechips.rocketchip.system.TinyConfig.fir@106096.4] assign data_io_req_bits_addr = dataArb_io_out_bits_addr; // @[DCache.scala 118:15:freechips.rocketchip.system.TinyConfig.fir@106096.4] assign data_io_req_bits_write = dataArb_io_out_bits_write; // @[DCache.scala 118:15:freechips.rocketchip.system.TinyConfig.fir@106096.4] assign data_io_req_bits_wdata = dataArb_io_out_bits_wdata; // @[DCache.scala 118:15:freechips.rocketchip.system.TinyConfig.fir@106096.4] assign data_io_req_bits_eccMask = dataArb_io_out_bits_eccMask; // @[DCache.scala 118:15:freechips.rocketchip.system.TinyConfig.fir@106096.4] assign dataArb_io_in_0_valid = pstore_drain_structural | _T_921; // @[DCache.scala 442:26:freechips.rocketchip.system.TinyConfig.fir@107450.4] assign dataArb_io_in_0_bits_addr = _T_981[7:0]; // @[DCache.scala 444:30:freechips.rocketchip.system.TinyConfig.fir@107453.4] assign dataArb_io_in_0_bits_write = pstore_drain_structural | _T_921; // @[DCache.scala 443:31:freechips.rocketchip.system.TinyConfig.fir@107451.4] assign dataArb_io_in_0_bits_wdata = {_T_989,_T_988}; // @[DCache.scala 446:31:freechips.rocketchip.system.TinyConfig.fir@107464.4] assign dataArb_io_in_0_bits_eccMask = {_T_1003,_T_1002}; // @[DCache.scala 448:33:freechips.rocketchip.system.TinyConfig.fir@107480.4] assign dataArb_io_in_1_valid = _T_2058 ? _GEN_159 : _T_1973; // @[DCache.scala 585:26:freechips.rocketchip.system.TinyConfig.fir@108659.4 DCache.scala 621:32:freechips.rocketchip.system.TinyConfig.fir@108767.8] assign dataArb_io_in_1_bits_addr = dataArb_io_in_0_bits_addr; // @[DCache.scala 598:27:freechips.rocketchip.system.TinyConfig.fir@108668.4] assign dataArb_io_in_1_bits_write = _T_2058 ? _GEN_160 : dataArb_io_in_0_bits_write; // @[DCache.scala 598:27:freechips.rocketchip.system.TinyConfig.fir@108668.4 DCache.scala 622:37:freechips.rocketchip.system.TinyConfig.fir@108768.8] assign dataArb_io_in_1_bits_wdata = dataArb_io_in_0_bits_wdata; // @[DCache.scala 117:43:freechips.rocketchip.system.TinyConfig.fir@106093.4 DCache.scala 598:27:freechips.rocketchip.system.TinyConfig.fir@108668.4] assign dataArb_io_in_1_bits_eccMask = dataArb_io_in_0_bits_eccMask; // @[DCache.scala 598:27:freechips.rocketchip.system.TinyConfig.fir@108668.4] assign dataArb_io_in_3_valid = io_cpu_req_valid & res; // @[DCache.scala 186:26:freechips.rocketchip.system.TinyConfig.fir@106333.4] assign dataArb_io_in_3_bits_addr = io_cpu_req_bits_addr[7:0]; // @[DCache.scala 187:25:freechips.rocketchip.system.TinyConfig.fir@106334.4 DCache.scala 189:30:freechips.rocketchip.system.TinyConfig.fir@106336.4] assign dataArb_io_in_3_bits_wdata = dataArb_io_in_1_bits_wdata; // @[DCache.scala 117:43:freechips.rocketchip.system.TinyConfig.fir@106095.4 DCache.scala 187:25:freechips.rocketchip.system.TinyConfig.fir@106334.4] assign dataArb_io_in_3_bits_eccMask = dataArb_io_in_1_bits_eccMask; // @[DCache.scala 187:25:freechips.rocketchip.system.TinyConfig.fir@106334.4] assign tlb_io_req_valid = s1_valid_masked & s1_cmd_uses_tlb; // @[DCache.scala 207:20:freechips.rocketchip.system.TinyConfig.fir@106424.4] assign tlb_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala 209:25:freechips.rocketchip.system.TinyConfig.fir@106426.4] assign tlb_io_req_bits_size = s1_req_size; // @[DCache.scala 210:24:freechips.rocketchip.system.TinyConfig.fir@106427.4] assign tlb_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala 211:23:freechips.rocketchip.system.TinyConfig.fir@106428.4] assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[DCache.scala 205:10:freechips.rocketchip.system.TinyConfig.fir@106419.4] assign amoalu_io_cmd = pstore1_cmd; // @[DCache.scala 806:19:freechips.rocketchip.system.TinyConfig.fir@109092.4] assign amoalu_io_lhs = {_T_530,_T_529}; // @[DCache.scala 807:19:freechips.rocketchip.system.TinyConfig.fir@109093.4] assign amoalu_io_rhs = pstore1_data; // @[DCache.scala 808:19:freechips.rocketchip.system.TinyConfig.fir@109094.4] assign _GEN_189 = _T_1942 & grantIsCached; // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108580.10] assign _GEN_192 = _T_1942 & _T_2436; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108599.14] assign _GEN_193 = _GEN_192 & d_last; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108599.14] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; s1_valid = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; s1_req_cmd = _RAND_1[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; s2_valid = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; s2_req_cmd = _RAND_3[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; pstore1_held = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; pstore1_addr = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; s1_req_addr = _RAND_6[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; pstore1_mask = _RAND_7[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; s1_req_size = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; pstore2_valid = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; pstore2_addr = _RAND_10[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; mask = _RAND_11[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_328 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; s2_hit_state_state = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; s1_req_tag = _RAND_14[6:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; s1_req_signed = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; s1_req_phys = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; s1_flush_valid = _RAND_17[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; uncachedInFlight_0 = _RAND_18[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; uncachedReqs_0_addr = _RAND_19[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; uncachedReqs_0_tag = _RAND_20[6:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; uncachedReqs_0_size = _RAND_21[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; uncachedReqs_0_signed = _RAND_22[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; s1_did_read = _RAND_23[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_24 = {1{`RANDOM}}; s2_req_addr = _RAND_24[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_25 = {1{`RANDOM}}; s2_req_tag = _RAND_25[6:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_26 = {1{`RANDOM}}; s2_req_size = _RAND_26[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_27 = {1{`RANDOM}}; s2_req_signed = _RAND_27[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_28 = {1{`RANDOM}}; s2_req_phys = _RAND_28[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_29 = {1{`RANDOM}}; s2_tlb_resp_pf_ld = _RAND_29[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_30 = {1{`RANDOM}}; s2_tlb_resp_pf_st = _RAND_30[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_31 = {1{`RANDOM}}; s2_tlb_resp_ae_ld = _RAND_31[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_32 = {1{`RANDOM}}; s2_tlb_resp_ae_st = _RAND_32[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_33 = {1{`RANDOM}}; s2_tlb_resp_ma_ld = _RAND_33[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_34 = {1{`RANDOM}}; s2_tlb_resp_ma_st = _RAND_34[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_35 = {1{`RANDOM}}; s2_uncached_resp_addr = _RAND_35[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_36 = {1{`RANDOM}}; _T_340 = _RAND_36[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_37 = {1{`RANDOM}}; s2_flush_valid_pre_tag_ecc = _RAND_37[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_38 = {1{`RANDOM}}; blockUncachedGrant = _RAND_38[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_39 = {1{`RANDOM}}; _T_1898 = _RAND_39[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_40 = {1{`RANDOM}}; s2_data = _RAND_40[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_41 = {1{`RANDOM}}; pstore1_cmd = _RAND_41[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_42 = {1{`RANDOM}}; pstore1_data = _RAND_42[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_43 = {1{`RANDOM}}; pstore1_rmw = _RAND_43[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_44 = {1{`RANDOM}}; pstore_drain_on_miss = _RAND_44[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_45 = {1{`RANDOM}}; _T_945 = _RAND_45[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_46 = {1{`RANDOM}}; _T_950 = _RAND_46[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_47 = {1{`RANDOM}}; _T_955 = _RAND_47[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_48 = {1{`RANDOM}}; _T_960 = _RAND_48[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_49 = {1{`RANDOM}}; _T_2140 = _RAND_49[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_50 = {1{`RANDOM}}; doUncachedResp = _RAND_50[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge gated_clock) begin if (reset) begin s1_valid <= 1'h0; end else begin s1_valid <= _T_48; end if (s0_clk_en) begin s1_req_cmd <= io_cpu_req_bits_cmd; end if (reset) begin s2_valid <= 1'h0; end else begin s2_valid <= _T_317; end if (_T_1942) begin if (grantIsCached) begin if (_T_338) begin s2_req_cmd <= s1_req_cmd; end end else begin if (data_1) begin s2_req_cmd <= 5'h0; end else begin if (_T_338) begin s2_req_cmd <= s1_req_cmd; end end end end else begin if (_T_338) begin s2_req_cmd <= s1_req_cmd; end end pstore1_held <= _T_931 & _T_932; if (_T_760) begin pstore1_addr <= s1_req_addr; end if (s0_clk_en) begin s1_req_addr <= _T_59; end if (_T_760) begin if (_T_84) begin pstore1_mask <= io_cpu_s1_data_mask; end else begin pstore1_mask <= s1_mask_xwr; end end if (s0_clk_en) begin s1_req_size <= io_cpu_req_bits_size; end pstore2_valid <= _T_937 | advance_pstore1; if (advance_pstore1) begin pstore2_addr <= pstore1_addr; end if (advance_pstore1) begin mask <= _T_967; end _T_328 <= s1_nack == 1'h0; if (_T_338) begin if (inScratchpad) begin s2_hit_state_state <= 2'h3; end else begin s2_hit_state_state <= 2'h0; end end if (s0_clk_en) begin s1_req_tag <= io_cpu_req_bits_tag; end if (s0_clk_en) begin s1_req_signed <= io_cpu_req_bits_signed; end if (s0_clk_en) begin if (_T_60) begin s1_req_phys <= 1'h1; end else begin s1_req_phys <= io_cpu_req_bits_phys; end end s1_flush_valid <= _T_2249 & _T_552; if (reset) begin uncachedInFlight_0 <= 1'h0; end else begin if (_T_1942) begin if (grantIsCached) begin if (_T_1888) begin uncachedInFlight_0 <= 1'h1; end end else begin if (d_last) begin uncachedInFlight_0 <= 1'h0; end else begin if (_T_1888) begin uncachedInFlight_0 <= 1'h1; end end end end else begin if (_T_1888) begin uncachedInFlight_0 <= 1'h1; end end end if (_T_1888) begin uncachedReqs_0_addr <= s2_req_addr; end if (_T_1888) begin uncachedReqs_0_tag <= s2_req_tag; end if (_T_1888) begin uncachedReqs_0_size <= s2_req_size; end if (_T_1888) begin uncachedReqs_0_signed <= s2_req_signed; end if (s0_clk_en) begin s1_did_read <= _T_256; end if (_T_1942) begin if (grantIsCached) begin if (_T_338) begin s2_req_addr <= tlb_io_resp_paddr; end end else begin if (data_1) begin s2_req_addr <= _T_1954; end else begin if (_T_338) begin s2_req_addr <= tlb_io_resp_paddr; end end end end else begin if (_T_338) begin s2_req_addr <= tlb_io_resp_paddr; end end if (_T_1942) begin if (grantIsCached) begin if (_T_338) begin s2_req_tag <= s1_req_tag; end end else begin if (data_1) begin s2_req_tag <= uncachedReqs_0_tag; end else begin if (_T_338) begin s2_req_tag <= s1_req_tag; end end end end else begin if (_T_338) begin s2_req_tag <= s1_req_tag; end end if (_T_1942) begin if (grantIsCached) begin if (_T_338) begin s2_req_size <= s1_req_size; end end else begin if (data_1) begin s2_req_size <= uncachedReqs_0_size; end else begin if (_T_338) begin s2_req_size <= s1_req_size; end end end end else begin if (_T_338) begin s2_req_size <= s1_req_size; end end if (_T_1942) begin if (grantIsCached) begin if (_T_338) begin s2_req_signed <= s1_req_signed; end end else begin if (data_1) begin s2_req_signed <= uncachedReqs_0_signed; end else begin if (_T_338) begin s2_req_signed <= s1_req_signed; end end end end else begin if (_T_338) begin s2_req_signed <= s1_req_signed; end end if (_T_338) begin s2_req_phys <= s1_req_phys; end if (_T_338) begin s2_tlb_resp_pf_ld <= tlb_io_resp_pf_ld; end if (_T_338) begin s2_tlb_resp_pf_st <= tlb_io_resp_pf_st; end if (_T_338) begin s2_tlb_resp_ae_ld <= tlb_io_resp_ae_ld; end if (_T_338) begin s2_tlb_resp_ae_st <= tlb_io_resp_ae_st; end if (_T_338) begin s2_tlb_resp_ma_ld <= tlb_io_resp_ma_ld; end if (_T_338) begin s2_tlb_resp_ma_st <= tlb_io_resp_ma_st; end if (_T_1942) begin if (!(grantIsCached)) begin if (data_1) begin s2_uncached_resp_addr <= uncachedReqs_0_addr; end end end if (_T_338) begin _T_340 <= s1_req_addr; end s2_flush_valid_pre_tag_ecc <= s1_flush_valid; if (_T_2058) begin if (auto_out_d_valid) begin blockUncachedGrant <= _T_1975; end else begin blockUncachedGrant <= dataArb_io_out_valid; end end else begin blockUncachedGrant <= dataArb_io_out_valid; end if (reset) begin _T_1898 <= 10'h0; end else begin if (_T_1942) begin if (d_first) begin if (_T_1896) begin _T_1898 <= _T_1895; end else begin _T_1898 <= 10'h0; end end else begin _T_1898 <= _T_1900; end end end if (en) begin s2_data <= _T_404; end if (_T_760) begin pstore1_cmd <= s1_req_cmd; end if (_T_760) begin pstore1_data <= io_cpu_s1_data_data; end if (_T_760) begin pstore1_rmw <= _T_815; end pstore_drain_on_miss <= io_cpu_s2_nack; if (advance_pstore1) begin _T_945 <= _T_941; end if (advance_pstore1) begin _T_950 <= _T_946; end if (advance_pstore1) begin _T_955 <= _T_951; end if (advance_pstore1) begin _T_960 <= _T_956; end _T_2140 <= tlb_io_req_valid & _T_55; doUncachedResp <= io_cpu_replay_next; `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_198) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:989 assert(!needsRead(req) || res)\n"); // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106329.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_198) begin $fatal; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@106330.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_315) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:252 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n"); // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106522.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_315) begin $fatal; // @[DCache.scala 252:9:freechips.rocketchip.system.TinyConfig.fir@106523.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_198) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:989 assert(!needsRead(req) || res)\n"); // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@107306.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_198) begin $fatal; // @[DCache.scala 989:11:freechips.rocketchip.system.TinyConfig.fir@107307.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_908) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:405 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n"); // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107342.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_908) begin $fatal; // @[DCache.scala 405:9:freechips.rocketchip.system.TinyConfig.fir@107343.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1915) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:518 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n"); // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108527.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1915) begin $fatal; // @[DCache.scala 518:13:freechips.rocketchip.system.TinyConfig.fir@108528.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_189 & _T_1945) begin $fwrite(32'h80000002,"Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:541 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n"); // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108580.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_189 & _T_1945) begin $fatal; // @[DCache.scala 541:13:freechips.rocketchip.system.TinyConfig.fir@108581.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_193 & _T_1950) begin $fwrite(32'h80000002,"Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:551 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n"); // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108599.14] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_193 & _T_1950) begin $fatal; // @[DCache.scala 551:17:freechips.rocketchip.system.TinyConfig.fir@108600.14] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1972) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:580 assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))\n"); // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108654.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1972) begin $fatal; // @[DCache.scala 580:9:freechips.rocketchip.system.TinyConfig.fir@108655.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (s2_req_phys & _T_2162) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:756 assert(!s2_valid || s2_hit_valid)\n"); // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108985.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (s2_req_phys & _T_2162) begin $fatal; // @[DCache.scala 756:13:freechips.rocketchip.system.TinyConfig.fir@108986.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_2178) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:759 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n"); // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109016.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_2178) begin $fatal; // @[DCache.scala 759:11:freechips.rocketchip.system.TinyConfig.fir@109017.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (doUncachedResp & _T_2188) begin $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:775 assert(!s2_valid_hit)\n"); // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109040.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (doUncachedResp & _T_2188) begin $fatal; // @[DCache.scala 775:11:freechips.rocketchip.system.TinyConfig.fir@109041.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module ICache( // @[:freechips.rocketchip.system.TinyConfig.fir@109372.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@109373.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@109374.4] input auto_master_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] output auto_master_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] output [31:0] auto_master_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] input auto_master_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] input [2:0] auto_master_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] input [3:0] auto_master_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] input [31:0] auto_master_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] input auto_master_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@109375.4] output io_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input io_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input [31:0] io_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input [31:0] io_s1_paddr, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input io_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input io_s2_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] output io_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] output [31:0] io_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] output io_resp_bits_ae, // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] input io_invalidate // @[:freechips.rocketchip.system.TinyConfig.fir@109376.4] ); wire [1:0] tag_array_RW0_addr; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire tag_array_RW0_en; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire tag_array_RW0_clk; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire tag_array_RW0_wmode; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire [24:0] tag_array_RW0_wdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire [24:0] tag_array_RW0_rdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] wire [5:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] wire data_arrays_0_RW0_en; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] wire data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] wire data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] wire [31:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] wire [31:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] reg s1_valid; // @[ICache.scala 139:21:freechips.rocketchip.system.TinyConfig.fir@109392.4] reg [31:0] _RAND_0; reg [3:0] vb_array; // @[ICache.scala 198:21:freechips.rocketchip.system.TinyConfig.fir@109485.4] reg [31:0] _RAND_1; wire [1:0] _T_53; // @[ICache.scala 219:29:freechips.rocketchip.system.TinyConfig.fir@109513.4] wire [2:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109525.4] wire [3:0] _T_66; // @[ICache.scala 225:25:freechips.rocketchip.system.TinyConfig.fir@109526.4] wire _T_67; // @[ICache.scala 225:25:freechips.rocketchip.system.TinyConfig.fir@109527.4] wire [23:0] _T_71; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@109531.4] wire [23:0] _T_54; // @[ICache.scala 220:29:freechips.rocketchip.system.TinyConfig.fir@109514.4] wire _T_72; // @[ICache.scala 228:33:freechips.rocketchip.system.TinyConfig.fir@109532.4] wire s1_tag_hit_0; // @[ICache.scala 228:26:freechips.rocketchip.system.TinyConfig.fir@109533.4] wire _T_78; // @[ICache.scala 231:31:freechips.rocketchip.system.TinyConfig.fir@109540.4] wire s1_hit; // @[ICache.scala 141:40:freechips.rocketchip.system.TinyConfig.fir@109396.4] wire _T_1; // @[ICache.scala 143:38:freechips.rocketchip.system.TinyConfig.fir@109397.4] wire _T_2; // @[ICache.scala 143:35:freechips.rocketchip.system.TinyConfig.fir@109398.4] reg s2_valid; // @[ICache.scala 143:25:freechips.rocketchip.system.TinyConfig.fir@109399.4] reg [31:0] _RAND_2; reg s2_hit; // @[ICache.scala 144:23:freechips.rocketchip.system.TinyConfig.fir@109401.4] reg [31:0] _RAND_3; reg invalidated; // @[ICache.scala 146:24:freechips.rocketchip.system.TinyConfig.fir@109403.4] reg [31:0] _RAND_4; reg refill_valid; // @[ICache.scala 147:29:freechips.rocketchip.system.TinyConfig.fir@109404.4] reg [31:0] _RAND_5; wire _T_5; // @[ICache.scala 151:29:freechips.rocketchip.system.TinyConfig.fir@109410.4] wire _T_6; // @[ICache.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@109411.4] wire _T_7; // @[ICache.scala 151:40:freechips.rocketchip.system.TinyConfig.fir@109412.4] wire s2_miss; // @[ICache.scala 151:37:freechips.rocketchip.system.TinyConfig.fir@109413.4] reg _T_9; // @[ICache.scala 153:45:freechips.rocketchip.system.TinyConfig.fir@109416.4] reg [31:0] _RAND_6; wire s2_request_refill; // @[ICache.scala 153:35:freechips.rocketchip.system.TinyConfig.fir@109418.4] wire refill_fire; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109406.4] wire _T_8; // @[ICache.scala 152:41:freechips.rocketchip.system.TinyConfig.fir@109414.4] wire s1_can_request_refill; // @[ICache.scala 152:31:freechips.rocketchip.system.TinyConfig.fir@109415.4] wire _T_10; // @[ICache.scala 154:53:freechips.rocketchip.system.TinyConfig.fir@109419.4] reg [31:0] refill_addr; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@109420.4] reg [31:0] _RAND_7; wire [23:0] refill_tag; // @[ICache.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@109424.4] wire [1:0] refill_idx; // @[ICache.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@109425.4] wire _T_12; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@109427.4] wire refill_one_beat; // @[ICache.scala 157:41:freechips.rocketchip.system.TinyConfig.fir@109428.4] wire s0_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109433.4] wire [26:0] _T_18; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@109437.4] wire [11:0] _T_19; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@109438.4] wire [11:0] _T_20; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@109439.4] wire [9:0] _T_21; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@109440.4] wire [9:0] _T_23; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@109442.4] reg [9:0] _T_24; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@109443.4] reg [31:0] _RAND_8; wire [9:0] _T_26; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@109445.4] wire _T_27; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@109446.4] wire _T_28; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@109447.4] wire _T_29; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@109448.4] wire _T_30; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@109449.4] wire d_done; // @[Edges.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@109450.4] wire [9:0] _T_31; // @[Edges.scala 235:27:freechips.rocketchip.system.TinyConfig.fir@109451.4] wire [9:0] refill_cnt; // @[Edges.scala 235:25:freechips.rocketchip.system.TinyConfig.fir@109452.4] wire refill_done; // @[ICache.scala 165:37:freechips.rocketchip.system.TinyConfig.fir@109457.4] wire [1:0] _T_34; // @[ICache.scala 188:42:freechips.rocketchip.system.TinyConfig.fir@109461.4] wire _T_35; // @[ICache.scala 188:70:freechips.rocketchip.system.TinyConfig.fir@109462.4] wire _T_36; // @[ICache.scala 188:83:freechips.rocketchip.system.TinyConfig.fir@109463.4] wire [2:0] _T_44; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109487.6] wire _T_45; // @[ICache.scala 201:75:freechips.rocketchip.system.TinyConfig.fir@109488.6] wire _T_46; // @[ICache.scala 201:72:freechips.rocketchip.system.TinyConfig.fir@109489.6] wire [7:0] _T_47; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109490.6] wire [7:0] _GEN_37; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109491.6] wire [7:0] _T_48; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109491.6] wire [3:0] _T_49; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109492.6] wire [7:0] _GEN_38; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109493.6] wire [7:0] _T_50; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109493.6] wire [7:0] _T_51; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109494.6] wire [7:0] _T_52; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109495.6] wire [7:0] _GEN_13; // @[ICache.scala 199:26:freechips.rocketchip.system.TinyConfig.fir@109486.4] wire [7:0] _GEN_14; // @[ICache.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@109501.4] wire _T_70; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@109530.4] wire s1_tl_error_0; // @[ICache.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@109538.4] wire _T_94; // @[ICache.scala 251:32:freechips.rocketchip.system.TinyConfig.fir@109562.4] wire [5:0] _T_98; // @[ICache.scala 252:52:freechips.rocketchip.system.TinyConfig.fir@109566.4] wire [9:0] _GEN_39; // @[ICache.scala 252:79:freechips.rocketchip.system.TinyConfig.fir@109567.4] wire [9:0] _T_99; // @[ICache.scala 252:79:freechips.rocketchip.system.TinyConfig.fir@109567.4] wire [5:0] _T_101; // @[ICache.scala 249:31:freechips.rocketchip.system.TinyConfig.fir@109569.4] wire [9:0] _T_104; // @[ICache.scala 252:22:freechips.rocketchip.system.TinyConfig.fir@109572.4] wire [5:0] _T_110; // @[:freechips.rocketchip.system.TinyConfig.fir@109581.6] wire _T_112; // @[ICache.scala 261:41:freechips.rocketchip.system.TinyConfig.fir@109587.4] wire _T_113; // @[ICache.scala 261:46:freechips.rocketchip.system.TinyConfig.fir@109588.4] wire [31:0] s1_dout_0; // @[ICache.scala 262:71:freechips.rocketchip.system.TinyConfig.fir@109600.4] reg [31:0] s2_dout_0; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@109612.4] reg [31:0] _RAND_9; reg s2_tl_error; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@109622.4] reg [31:0] _RAND_10; wire [25:0] _T_135; // @[ICache.scala 384:46:freechips.rocketchip.system.TinyConfig.fir@109654.4] wire _T_225; // @[ICache.scala 421:9:freechips.rocketchip.system.TinyConfig.fir@109764.4] tag_array tag_array ( // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109460.4] .RW0_addr(tag_array_RW0_addr), .RW0_en(tag_array_RW0_en), .RW0_clk(tag_array_RW0_clk), .RW0_wmode(tag_array_RW0_wmode), .RW0_wdata_0(tag_array_RW0_wdata_0), .RW0_rdata_0(tag_array_RW0_rdata_0) ); data_arrays_0_0 data_arrays_0 ( // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@109555.4] .RW0_addr(data_arrays_0_RW0_addr), .RW0_en(data_arrays_0_RW0_en), .RW0_clk(data_arrays_0_RW0_clk), .RW0_wmode(data_arrays_0_RW0_wmode), .RW0_wdata_0(data_arrays_0_RW0_wdata_0), .RW0_rdata_0(data_arrays_0_RW0_rdata_0) ); assign _T_53 = io_s1_paddr[7:6]; // @[ICache.scala 219:29:freechips.rocketchip.system.TinyConfig.fir@109513.4] assign _T_65 = {1'h0,_T_53}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109525.4] assign _T_66 = vb_array >> _T_65; // @[ICache.scala 225:25:freechips.rocketchip.system.TinyConfig.fir@109526.4] assign _T_67 = _T_66[0]; // @[ICache.scala 225:25:freechips.rocketchip.system.TinyConfig.fir@109527.4] assign _T_71 = tag_array_RW0_rdata_0[23:0]; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@109531.4] assign _T_54 = io_s1_paddr[31:8]; // @[ICache.scala 220:29:freechips.rocketchip.system.TinyConfig.fir@109514.4] assign _T_72 = _T_71 == _T_54; // @[ICache.scala 228:33:freechips.rocketchip.system.TinyConfig.fir@109532.4] assign s1_tag_hit_0 = _T_67 & _T_72; // @[ICache.scala 228:26:freechips.rocketchip.system.TinyConfig.fir@109533.4] assign _T_78 = s1_tag_hit_0; // @[ICache.scala 231:31:freechips.rocketchip.system.TinyConfig.fir@109540.4] assign s1_hit = s1_tag_hit_0; // @[ICache.scala 141:40:freechips.rocketchip.system.TinyConfig.fir@109396.4] assign _T_1 = io_s1_kill == 1'h0; // @[ICache.scala 143:38:freechips.rocketchip.system.TinyConfig.fir@109397.4] assign _T_2 = s1_valid & _T_1; // @[ICache.scala 143:35:freechips.rocketchip.system.TinyConfig.fir@109398.4] assign _T_5 = s2_hit == 1'h0; // @[ICache.scala 151:29:freechips.rocketchip.system.TinyConfig.fir@109410.4] assign _T_6 = s2_valid & _T_5; // @[ICache.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@109411.4] assign _T_7 = io_s2_kill == 1'h0; // @[ICache.scala 151:40:freechips.rocketchip.system.TinyConfig.fir@109412.4] assign s2_miss = _T_6 & _T_7; // @[ICache.scala 151:37:freechips.rocketchip.system.TinyConfig.fir@109413.4] assign s2_request_refill = s2_miss & _T_9; // @[ICache.scala 153:35:freechips.rocketchip.system.TinyConfig.fir@109418.4] assign refill_fire = auto_master_out_a_ready & s2_request_refill; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109406.4] assign _T_8 = s2_miss | refill_valid; // @[ICache.scala 152:41:freechips.rocketchip.system.TinyConfig.fir@109414.4] assign s1_can_request_refill = _T_8 == 1'h0; // @[ICache.scala 152:31:freechips.rocketchip.system.TinyConfig.fir@109415.4] assign _T_10 = s1_valid & s1_can_request_refill; // @[ICache.scala 154:53:freechips.rocketchip.system.TinyConfig.fir@109419.4] assign refill_tag = refill_addr[31:8]; // @[ICache.scala 155:31:freechips.rocketchip.system.TinyConfig.fir@109424.4] assign refill_idx = refill_addr[7:6]; // @[ICache.scala 156:31:freechips.rocketchip.system.TinyConfig.fir@109425.4] assign _T_12 = auto_master_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@109427.4] assign refill_one_beat = auto_master_out_d_valid & _T_12; // @[ICache.scala 157:41:freechips.rocketchip.system.TinyConfig.fir@109428.4] assign s0_valid = io_req_ready & io_req_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109433.4] assign _T_18 = 27'hfff << auto_master_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@109437.4] assign _T_19 = _T_18[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@109438.4] assign _T_20 = ~ _T_19; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@109439.4] assign _T_21 = _T_20[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@109440.4] assign _T_23 = _T_12 ? _T_21 : 10'h0; // @[Edges.scala 222:14:freechips.rocketchip.system.TinyConfig.fir@109442.4] assign _T_26 = _T_24 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@109445.4] assign _T_27 = _T_24 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@109446.4] assign _T_28 = _T_24 == 10'h1; // @[Edges.scala 233:25:freechips.rocketchip.system.TinyConfig.fir@109447.4] assign _T_29 = _T_23 == 10'h0; // @[Edges.scala 233:47:freechips.rocketchip.system.TinyConfig.fir@109448.4] assign _T_30 = _T_28 | _T_29; // @[Edges.scala 233:37:freechips.rocketchip.system.TinyConfig.fir@109449.4] assign d_done = _T_30 & auto_master_out_d_valid; // @[Edges.scala 234:22:freechips.rocketchip.system.TinyConfig.fir@109450.4] assign _T_31 = ~ _T_26; // @[Edges.scala 235:27:freechips.rocketchip.system.TinyConfig.fir@109451.4] assign refill_cnt = _T_23 & _T_31; // @[Edges.scala 235:25:freechips.rocketchip.system.TinyConfig.fir@109452.4] assign refill_done = refill_one_beat & d_done; // @[ICache.scala 165:37:freechips.rocketchip.system.TinyConfig.fir@109457.4] assign _T_34 = io_req_bits_addr[7:6]; // @[ICache.scala 188:42:freechips.rocketchip.system.TinyConfig.fir@109461.4] assign _T_35 = refill_done == 1'h0; // @[ICache.scala 188:70:freechips.rocketchip.system.TinyConfig.fir@109462.4] assign _T_36 = _T_35 & s0_valid; // @[ICache.scala 188:83:freechips.rocketchip.system.TinyConfig.fir@109463.4] assign _T_44 = {1'h0,refill_idx}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@109487.6] assign _T_45 = invalidated == 1'h0; // @[ICache.scala 201:75:freechips.rocketchip.system.TinyConfig.fir@109488.6] assign _T_46 = refill_done & _T_45; // @[ICache.scala 201:72:freechips.rocketchip.system.TinyConfig.fir@109489.6] assign _T_47 = 8'h1 << _T_44; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109490.6] assign _GEN_37 = {{4'd0}, vb_array}; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109491.6] assign _T_48 = _GEN_37 | _T_47; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109491.6] assign _T_49 = ~ vb_array; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109492.6] assign _GEN_38 = {{4'd0}, _T_49}; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109493.6] assign _T_50 = _GEN_38 | _T_47; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109493.6] assign _T_51 = ~ _T_50; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109494.6] assign _T_52 = _T_46 ? _T_48 : _T_51; // @[ICache.scala 201:32:freechips.rocketchip.system.TinyConfig.fir@109495.6] assign _GEN_13 = refill_one_beat ? _T_52 : {{4'd0}, vb_array}; // @[ICache.scala 199:26:freechips.rocketchip.system.TinyConfig.fir@109486.4] assign _GEN_14 = io_invalidate ? 8'h0 : _GEN_13; // @[ICache.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@109501.4] assign _T_70 = tag_array_RW0_rdata_0[24]; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@109530.4] assign s1_tl_error_0 = s1_tag_hit_0 & _T_70; // @[ICache.scala 230:32:freechips.rocketchip.system.TinyConfig.fir@109538.4] assign _T_94 = refill_one_beat & _T_45; // @[ICache.scala 251:32:freechips.rocketchip.system.TinyConfig.fir@109562.4] assign _T_98 = {refill_idx, 4'h0}; // @[ICache.scala 252:52:freechips.rocketchip.system.TinyConfig.fir@109566.4] assign _GEN_39 = {{4'd0}, _T_98}; // @[ICache.scala 252:79:freechips.rocketchip.system.TinyConfig.fir@109567.4] assign _T_99 = _GEN_39 | refill_cnt; // @[ICache.scala 252:79:freechips.rocketchip.system.TinyConfig.fir@109567.4] assign _T_101 = io_req_bits_addr[7:2]; // @[ICache.scala 249:31:freechips.rocketchip.system.TinyConfig.fir@109569.4] assign _T_104 = refill_one_beat ? _T_99 : {{4'd0}, _T_101}; // @[ICache.scala 252:22:freechips.rocketchip.system.TinyConfig.fir@109572.4] assign _T_110 = _T_104[5:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@109581.6] assign _T_112 = _T_94 == 1'h0; // @[ICache.scala 261:41:freechips.rocketchip.system.TinyConfig.fir@109587.4] assign _T_113 = _T_112 & s0_valid; // @[ICache.scala 261:46:freechips.rocketchip.system.TinyConfig.fir@109588.4] assign s1_dout_0 = data_arrays_0_RW0_rdata_0; // @[ICache.scala 262:71:freechips.rocketchip.system.TinyConfig.fir@109600.4] assign _T_135 = refill_addr[31:6]; // @[ICache.scala 384:46:freechips.rocketchip.system.TinyConfig.fir@109654.4] assign _T_225 = refill_valid == 1'h0; // @[ICache.scala 421:9:freechips.rocketchip.system.TinyConfig.fir@109764.4] assign auto_master_out_a_valid = s2_miss & _T_9; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@109384.4] assign auto_master_out_a_bits_address = {_T_135, 6'h0}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@109384.4] assign io_req_ready = refill_one_beat == 1'h0; // @[ICache.scala 159:16:freechips.rocketchip.system.TinyConfig.fir@109432.4] assign io_resp_valid = s2_valid & s2_hit; // @[ICache.scala 302:21:freechips.rocketchip.system.TinyConfig.fir@109652.4] assign io_resp_bits_data = s2_dout_0; // @[ICache.scala 299:25:freechips.rocketchip.system.TinyConfig.fir@109648.4] assign io_resp_bits_ae = s2_tl_error; // @[ICache.scala 300:23:freechips.rocketchip.system.TinyConfig.fir@109649.4] assign tag_array_RW0_wdata_0 = {auto_master_out_d_bits_corrupt,refill_tag}; // @[:freechips.rocketchip.system.TinyConfig.fir@109482.8] assign data_arrays_0_RW0_wdata_0 = auto_master_out_d_bits_data; // @[:freechips.rocketchip.system.TinyConfig.fir@109584.8] assign tag_array_RW0_wmode = refill_one_beat & d_done; assign tag_array_RW0_clk = clock; assign tag_array_RW0_en = _T_36 | refill_done; assign tag_array_RW0_addr = refill_done ? refill_idx : _T_34; assign data_arrays_0_RW0_wmode = refill_one_beat & _T_45; assign data_arrays_0_RW0_clk = clock; assign data_arrays_0_RW0_en = _T_113 | _T_94; assign data_arrays_0_RW0_addr = _T_94 ? _T_110 : _T_110; `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; s1_valid = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; vb_array = _RAND_1[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; s2_valid = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; s2_hit = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; invalidated = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; refill_valid = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_9 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; refill_addr = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_24 = _RAND_8[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; s2_dout_0 = _RAND_9[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; s2_tl_error = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin s1_valid <= 1'h0; end else begin s1_valid <= s0_valid; end if (reset) begin vb_array <= 4'h0; end else begin vb_array <= _GEN_14[3:0]; end if (reset) begin s2_valid <= 1'h0; end else begin s2_valid <= _T_2; end s2_hit <= _T_78; if (_T_225) begin invalidated <= 1'h0; end else begin if (io_invalidate) begin invalidated <= 1'h1; end end if (reset) begin refill_valid <= 1'h0; end else begin if (refill_done) begin refill_valid <= 1'h0; end else begin if (refill_fire) begin refill_valid <= 1'h1; end end end _T_9 <= _T_8 == 1'h0; if (_T_10) begin refill_addr <= io_s1_paddr; end if (reset) begin _T_24 <= 10'h0; end else begin if (auto_master_out_d_valid) begin if (_T_27) begin if (_T_12) begin _T_24 <= _T_21; end else begin _T_24 <= 10'h0; end end else begin _T_24 <= _T_26; end end end if (s1_valid) begin s2_dout_0 <= s1_dout_0; end if (s1_valid) begin s2_tl_error <= s1_tl_error_0; end end endmodule module ShiftQueue( // @[:freechips.rocketchip.system.TinyConfig.fir@109889.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@109890.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@109891.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input [31:0] io_enq_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input io_enq_bits_xcpt_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input io_enq_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output [31:0] io_deq_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output io_deq_bits_xcpt_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output io_deq_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] output [4:0] io_mask // @[:freechips.rocketchip.system.TinyConfig.fir@109892.4] ); reg _T_1_0; // @[ShiftQueue.scala 20:30:freechips.rocketchip.system.TinyConfig.fir@109904.4] reg [31:0] _RAND_0; reg _T_1_1; // @[ShiftQueue.scala 20:30:freechips.rocketchip.system.TinyConfig.fir@109904.4] reg [31:0] _RAND_1; reg _T_1_2; // @[ShiftQueue.scala 20:30:freechips.rocketchip.system.TinyConfig.fir@109904.4] reg [31:0] _RAND_2; reg _T_1_3; // @[ShiftQueue.scala 20:30:freechips.rocketchip.system.TinyConfig.fir@109904.4] reg [31:0] _RAND_3; reg _T_1_4; // @[ShiftQueue.scala 20:30:freechips.rocketchip.system.TinyConfig.fir@109904.4] reg [31:0] _RAND_4; reg [31:0] _T_2_0_pc; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_5; reg [31:0] _T_2_0_data; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_6; reg _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_7; reg _T_2_0_replay; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_8; reg [31:0] _T_2_1_pc; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_9; reg [31:0] _T_2_1_data; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_10; reg _T_2_1_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_11; reg _T_2_1_replay; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_12; reg [31:0] _T_2_2_pc; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_13; reg [31:0] _T_2_2_data; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_14; reg _T_2_2_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_15; reg _T_2_2_replay; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_16; reg [31:0] _T_2_3_pc; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_17; reg [31:0] _T_2_3_data; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_18; reg _T_2_3_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_19; reg _T_2_3_replay; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_20; reg [31:0] _T_2_4_pc; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_21; reg [31:0] _T_2_4_data; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_22; reg _T_2_4_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_23; reg _T_2_4_replay; // @[ShiftQueue.scala 21:25:freechips.rocketchip.system.TinyConfig.fir@109905.4] reg [31:0] _RAND_24; wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109907.4] wire _T_6; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109909.4] wire _T_7; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109910.4] wire _T_10; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109913.4] wire _T_11; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109914.4] wire _T_12; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109915.4] wire _T_19; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109925.4] wire _T_24; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109931.4] wire _T_25; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109932.4] wire _T_28; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109935.4] wire _T_29; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109936.4] wire _T_30; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109937.4] wire _T_37; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109947.4] wire _T_42; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109953.4] wire _T_43; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109954.4] wire _T_46; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109957.4] wire _T_47; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109958.4] wire _T_48; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109959.4] wire _T_55; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109969.4] wire _T_60; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109975.4] wire _T_61; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109976.4] wire _T_64; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109979.4] wire _T_65; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109980.4] wire _T_66; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109981.4] wire _T_73; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109991.4] wire _T_77; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109996.4] wire _T_81; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@110000.4] wire _T_82; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@110001.4] wire _T_83; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@110002.4] wire _T_90; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@110012.4] wire [1:0] _T_94; // @[ShiftQueue.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@110026.4] wire [2:0] _T_96; // @[ShiftQueue.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@110028.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@109907.4] assign _T_6 = _T_4 & _T_1_0; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109909.4] assign _T_7 = _T_1_1 | _T_6; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109910.4] assign _T_10 = _T_1_0 == 1'h0; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109913.4] assign _T_11 = _T_4 & _T_10; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109914.4] assign _T_12 = io_deq_ready ? _T_7 : _T_11; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109915.4] assign _T_19 = _T_4 | _T_1_0; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109925.4] assign _T_24 = _T_4 & _T_1_1; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109931.4] assign _T_25 = _T_1_2 | _T_24; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109932.4] assign _T_28 = _T_1_1 == 1'h0; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109935.4] assign _T_29 = _T_6 & _T_28; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109936.4] assign _T_30 = io_deq_ready ? _T_25 : _T_29; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109937.4] assign _T_37 = _T_6 | _T_1_1; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109947.4] assign _T_42 = _T_4 & _T_1_2; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109953.4] assign _T_43 = _T_1_3 | _T_42; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109954.4] assign _T_46 = _T_1_2 == 1'h0; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109957.4] assign _T_47 = _T_24 & _T_46; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109958.4] assign _T_48 = io_deq_ready ? _T_43 : _T_47; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109959.4] assign _T_55 = _T_24 | _T_1_2; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109969.4] assign _T_60 = _T_4 & _T_1_3; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109975.4] assign _T_61 = _T_1_4 | _T_60; // @[ShiftQueue.scala 29:28:freechips.rocketchip.system.TinyConfig.fir@109976.4] assign _T_64 = _T_1_3 == 1'h0; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@109979.4] assign _T_65 = _T_42 & _T_64; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@109980.4] assign _T_66 = io_deq_ready ? _T_61 : _T_65; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@109981.4] assign _T_73 = _T_42 | _T_1_3; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@109991.4] assign _T_77 = _T_4 & _T_1_4; // @[ShiftQueue.scala 29:45:freechips.rocketchip.system.TinyConfig.fir@109996.4] assign _T_81 = _T_1_4 == 1'h0; // @[ShiftQueue.scala 30:48:freechips.rocketchip.system.TinyConfig.fir@110000.4] assign _T_82 = _T_60 & _T_81; // @[ShiftQueue.scala 30:45:freechips.rocketchip.system.TinyConfig.fir@110001.4] assign _T_83 = io_deq_ready ? _T_77 : _T_82; // @[ShiftQueue.scala 28:10:freechips.rocketchip.system.TinyConfig.fir@110002.4] assign _T_90 = _T_60 | _T_1_4; // @[ShiftQueue.scala 36:45:freechips.rocketchip.system.TinyConfig.fir@110012.4] assign _T_94 = {_T_1_1,_T_1_0}; // @[ShiftQueue.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@110026.4] assign _T_96 = {_T_1_4,_T_1_3,_T_1_2}; // @[ShiftQueue.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@110028.4] assign io_enq_ready = _T_1_4 == 1'h0; // @[ShiftQueue.scala 39:16:freechips.rocketchip.system.TinyConfig.fir@110016.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_1_0; // @[ShiftQueue.scala 40:16:freechips.rocketchip.system.TinyConfig.fir@110017.4 ShiftQueue.scala 44:40:freechips.rocketchip.system.TinyConfig.fir@110020.6] assign io_deq_bits_pc = _T_10 ? io_enq_bits_pc : _T_2_0_pc; // @[ShiftQueue.scala 41:15:freechips.rocketchip.system.TinyConfig.fir@110018.4 ShiftQueue.scala 45:36:freechips.rocketchip.system.TinyConfig.fir@110024.6] assign io_deq_bits_data = _T_10 ? io_enq_bits_data : _T_2_0_data; // @[ShiftQueue.scala 41:15:freechips.rocketchip.system.TinyConfig.fir@110018.4 ShiftQueue.scala 45:36:freechips.rocketchip.system.TinyConfig.fir@110024.6] assign io_deq_bits_xcpt_ae_inst = _T_10 ? io_enq_bits_xcpt_ae_inst : _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 41:15:freechips.rocketchip.system.TinyConfig.fir@110018.4 ShiftQueue.scala 45:36:freechips.rocketchip.system.TinyConfig.fir@110024.6] assign io_deq_bits_replay = _T_10 ? io_enq_bits_replay : _T_2_0_replay; // @[ShiftQueue.scala 41:15:freechips.rocketchip.system.TinyConfig.fir@110018.4 ShiftQueue.scala 45:36:freechips.rocketchip.system.TinyConfig.fir@110024.6] assign io_mask = {_T_96,_T_94}; // @[ShiftQueue.scala 52:11:freechips.rocketchip.system.TinyConfig.fir@110030.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_1_0 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_1_1 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_1_2 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_1_3 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_1_4 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_2_0_pc = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_2_0_data = _RAND_6[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_2_0_xcpt_ae_inst = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_2_0_replay = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_2_1_pc = _RAND_9[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_2_1_data = _RAND_10[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_2_1_xcpt_ae_inst = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_2_1_replay = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_2_2_pc = _RAND_13[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_2_2_data = _RAND_14[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_2_2_xcpt_ae_inst = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_2_2_replay = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; _T_2_3_pc = _RAND_17[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; _T_2_3_data = _RAND_18[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; _T_2_3_xcpt_ae_inst = _RAND_19[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; _T_2_3_replay = _RAND_20[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; _T_2_4_pc = _RAND_21[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; _T_2_4_data = _RAND_22[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; _T_2_4_xcpt_ae_inst = _RAND_23[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_24 = {1{`RANDOM}}; _T_2_4_replay = _RAND_24[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_1_0 <= 1'h0; end else begin if (io_deq_ready) begin _T_1_0 <= _T_7; end else begin _T_1_0 <= _T_19; end end if (reset) begin _T_1_1 <= 1'h0; end else begin if (io_deq_ready) begin _T_1_1 <= _T_25; end else begin _T_1_1 <= _T_37; end end if (reset) begin _T_1_2 <= 1'h0; end else begin if (io_deq_ready) begin _T_1_2 <= _T_43; end else begin _T_1_2 <= _T_55; end end if (reset) begin _T_1_3 <= 1'h0; end else begin if (io_deq_ready) begin _T_1_3 <= _T_61; end else begin _T_1_3 <= _T_73; end end if (reset) begin _T_1_4 <= 1'h0; end else begin if (io_deq_ready) begin _T_1_4 <= _T_77; end else begin _T_1_4 <= _T_90; end end if (_T_12) begin if (_T_1_1) begin _T_2_0_pc <= _T_2_1_pc; end else begin _T_2_0_pc <= io_enq_bits_pc; end end if (_T_12) begin if (_T_1_1) begin _T_2_0_data <= _T_2_1_data; end else begin _T_2_0_data <= io_enq_bits_data; end end if (_T_12) begin if (_T_1_1) begin _T_2_0_xcpt_ae_inst <= _T_2_1_xcpt_ae_inst; end else begin _T_2_0_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; end end if (_T_12) begin if (_T_1_1) begin _T_2_0_replay <= _T_2_1_replay; end else begin _T_2_0_replay <= io_enq_bits_replay; end end if (_T_30) begin if (_T_1_2) begin _T_2_1_pc <= _T_2_2_pc; end else begin _T_2_1_pc <= io_enq_bits_pc; end end if (_T_30) begin if (_T_1_2) begin _T_2_1_data <= _T_2_2_data; end else begin _T_2_1_data <= io_enq_bits_data; end end if (_T_30) begin if (_T_1_2) begin _T_2_1_xcpt_ae_inst <= _T_2_2_xcpt_ae_inst; end else begin _T_2_1_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; end end if (_T_30) begin if (_T_1_2) begin _T_2_1_replay <= _T_2_2_replay; end else begin _T_2_1_replay <= io_enq_bits_replay; end end if (_T_48) begin if (_T_1_3) begin _T_2_2_pc <= _T_2_3_pc; end else begin _T_2_2_pc <= io_enq_bits_pc; end end if (_T_48) begin if (_T_1_3) begin _T_2_2_data <= _T_2_3_data; end else begin _T_2_2_data <= io_enq_bits_data; end end if (_T_48) begin if (_T_1_3) begin _T_2_2_xcpt_ae_inst <= _T_2_3_xcpt_ae_inst; end else begin _T_2_2_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; end end if (_T_48) begin if (_T_1_3) begin _T_2_2_replay <= _T_2_3_replay; end else begin _T_2_2_replay <= io_enq_bits_replay; end end if (_T_66) begin if (_T_1_4) begin _T_2_3_pc <= _T_2_4_pc; end else begin _T_2_3_pc <= io_enq_bits_pc; end end if (_T_66) begin if (_T_1_4) begin _T_2_3_data <= _T_2_4_data; end else begin _T_2_3_data <= io_enq_bits_data; end end if (_T_66) begin if (_T_1_4) begin _T_2_3_xcpt_ae_inst <= _T_2_4_xcpt_ae_inst; end else begin _T_2_3_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; end end if (_T_66) begin if (_T_1_4) begin _T_2_3_replay <= _T_2_4_replay; end else begin _T_2_3_replay <= io_enq_bits_replay; end end if (_T_83) begin _T_2_4_pc <= io_enq_bits_pc; end if (_T_83) begin _T_2_4_data <= io_enq_bits_data; end if (_T_83) begin _T_2_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; end if (_T_83) begin _T_2_4_replay <= io_enq_bits_replay; end end endmodule module TLB_1( // @[:freechips.rocketchip.system.TinyConfig.fir@111010.2] input [31:0] io_req_bits_vaddr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] output [31:0] io_resp_paddr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] output io_resp_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [1:0] io_ptw_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input io_ptw_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [29:0] io_ptw_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] input [31:0] io_ptw_pmp_7_mask // @[:freechips.rocketchip.system.TinyConfig.fir@111013.4] ); wire pmp_io_pmp_0_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_0_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_0_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_0_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_0_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_0_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_1_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_1_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_1_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_1_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_1_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_1_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_2_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_2_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_2_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_2_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_2_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_2_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_3_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_3_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_3_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_3_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_3_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_3_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_4_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_4_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_4_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_4_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_4_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_4_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_5_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_5_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_5_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_5_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_5_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_5_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_6_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_6_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_6_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_6_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_6_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_6_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_7_cfg_l; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_7_cfg_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_7_cfg_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_pmp_7_cfg_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [29:0] pmp_io_pmp_7_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_pmp_7_mask; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [31:0] pmp_io_addr; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_r; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_w; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire pmp_io_x; // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] wire [19:0] vpn; // @[TLB.scala 180:30:freechips.rocketchip.system.TinyConfig.fir@111034.4] wire [19:0] mpu_ppn; // @[TLB.scala 185:123:freechips.rocketchip.system.TinyConfig.fir@111081.4] wire [11:0] _T_26; // @[TLB.scala 186:52:freechips.rocketchip.system.TinyConfig.fir@111084.4] wire [31:0] mpu_physaddr; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@111085.4] wire [31:0] _T_30; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111104.4] wire [32:0] _T_31; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111105.4] wire [32:0] _T_32; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111106.4] wire [32:0] _T_33; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111107.4] wire _T_34; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111108.4] wire [31:0] _T_35; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111109.4] wire [32:0] _T_36; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111110.4] wire [32:0] _T_37; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111111.4] wire [32:0] _T_38; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111112.4] wire _T_39; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111113.4] wire [31:0] _T_40; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111114.4] wire [32:0] _T_41; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111115.4] wire [32:0] _T_42; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111116.4] wire [32:0] _T_43; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111117.4] wire _T_44; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111118.4] wire [32:0] _T_46; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111120.4] wire [32:0] _T_47; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111121.4] wire [32:0] _T_48; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111122.4] wire _T_49; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111123.4] wire [31:0] _T_50; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111124.4] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111125.4] wire [32:0] _T_52; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111126.4] wire [32:0] _T_53; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111127.4] wire _T_54; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111128.4] wire [31:0] _T_55; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111129.4] wire [32:0] _T_56; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111130.4] wire [32:0] _T_57; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111131.4] wire [32:0] _T_58; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111132.4] wire _T_59; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111133.4] wire [31:0] _T_60; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111134.4] wire [32:0] _T_61; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111135.4] wire [32:0] _T_62; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111136.4] wire [32:0] _T_63; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111137.4] wire _T_64; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111138.4] wire _T_66; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111148.4] wire _T_67; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111149.4] wire _T_68; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111150.4] wire _T_69; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111151.4] wire _T_70; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111152.4] wire legal_address; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111153.4] wire [31:0] _T_133; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111218.4] wire [32:0] _T_134; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111219.4] wire [32:0] _T_177; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111263.4] wire [32:0] _T_178; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111264.4] wire _T_179; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111265.4] wire [32:0] _T_246; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111338.4] wire [32:0] _T_247; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111339.4] wire _T_248; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111340.4] wire _T_254; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@111346.4] wire _T_270; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@111363.4] wire prot_x; // @[TLB.scala 201:40:freechips.rocketchip.system.TinyConfig.fir@111364.4] wire [1:0] _T_861; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@112436.4] wire [6:0] px_array; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@112441.4] wire [6:0] _T_1096; // @[TLB.scala 327:23:freechips.rocketchip.system.TinyConfig.fir@112713.4] wire [6:0] _T_1097; // @[TLB.scala 327:33:freechips.rocketchip.system.TinyConfig.fir@112714.4] PMPChecker pmp ( // @[TLB.scala 187:19:freechips.rocketchip.system.TinyConfig.fir@111086.4] .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l), .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a), .io_pmp_0_cfg_x(pmp_io_pmp_0_cfg_x), .io_pmp_0_cfg_w(pmp_io_pmp_0_cfg_w), .io_pmp_0_cfg_r(pmp_io_pmp_0_cfg_r), .io_pmp_0_addr(pmp_io_pmp_0_addr), .io_pmp_0_mask(pmp_io_pmp_0_mask), .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l), .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a), .io_pmp_1_cfg_x(pmp_io_pmp_1_cfg_x), .io_pmp_1_cfg_w(pmp_io_pmp_1_cfg_w), .io_pmp_1_cfg_r(pmp_io_pmp_1_cfg_r), .io_pmp_1_addr(pmp_io_pmp_1_addr), .io_pmp_1_mask(pmp_io_pmp_1_mask), .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l), .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a), .io_pmp_2_cfg_x(pmp_io_pmp_2_cfg_x), .io_pmp_2_cfg_w(pmp_io_pmp_2_cfg_w), .io_pmp_2_cfg_r(pmp_io_pmp_2_cfg_r), .io_pmp_2_addr(pmp_io_pmp_2_addr), .io_pmp_2_mask(pmp_io_pmp_2_mask), .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l), .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a), .io_pmp_3_cfg_x(pmp_io_pmp_3_cfg_x), .io_pmp_3_cfg_w(pmp_io_pmp_3_cfg_w), .io_pmp_3_cfg_r(pmp_io_pmp_3_cfg_r), .io_pmp_3_addr(pmp_io_pmp_3_addr), .io_pmp_3_mask(pmp_io_pmp_3_mask), .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l), .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a), .io_pmp_4_cfg_x(pmp_io_pmp_4_cfg_x), .io_pmp_4_cfg_w(pmp_io_pmp_4_cfg_w), .io_pmp_4_cfg_r(pmp_io_pmp_4_cfg_r), .io_pmp_4_addr(pmp_io_pmp_4_addr), .io_pmp_4_mask(pmp_io_pmp_4_mask), .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l), .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a), .io_pmp_5_cfg_x(pmp_io_pmp_5_cfg_x), .io_pmp_5_cfg_w(pmp_io_pmp_5_cfg_w), .io_pmp_5_cfg_r(pmp_io_pmp_5_cfg_r), .io_pmp_5_addr(pmp_io_pmp_5_addr), .io_pmp_5_mask(pmp_io_pmp_5_mask), .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l), .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a), .io_pmp_6_cfg_x(pmp_io_pmp_6_cfg_x), .io_pmp_6_cfg_w(pmp_io_pmp_6_cfg_w), .io_pmp_6_cfg_r(pmp_io_pmp_6_cfg_r), .io_pmp_6_addr(pmp_io_pmp_6_addr), .io_pmp_6_mask(pmp_io_pmp_6_mask), .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l), .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a), .io_pmp_7_cfg_x(pmp_io_pmp_7_cfg_x), .io_pmp_7_cfg_w(pmp_io_pmp_7_cfg_w), .io_pmp_7_cfg_r(pmp_io_pmp_7_cfg_r), .io_pmp_7_addr(pmp_io_pmp_7_addr), .io_pmp_7_mask(pmp_io_pmp_7_mask), .io_addr(pmp_io_addr), .io_r(pmp_io_r), .io_w(pmp_io_w), .io_x(pmp_io_x) ); assign vpn = io_req_bits_vaddr[31:12]; // @[TLB.scala 180:30:freechips.rocketchip.system.TinyConfig.fir@111034.4] assign mpu_ppn = io_req_bits_vaddr[31:12]; // @[TLB.scala 185:123:freechips.rocketchip.system.TinyConfig.fir@111081.4] assign _T_26 = io_req_bits_vaddr[11:0]; // @[TLB.scala 186:52:freechips.rocketchip.system.TinyConfig.fir@111084.4] assign mpu_physaddr = {mpu_ppn,_T_26}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@111085.4] assign _T_30 = mpu_physaddr ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111104.4] assign _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111105.4] assign _T_32 = $signed(_T_31) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111106.4] assign _T_33 = $signed(_T_32); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111107.4] assign _T_34 = $signed(_T_33) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111108.4] assign _T_35 = mpu_physaddr ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111109.4] assign _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111110.4] assign _T_37 = $signed(_T_36) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111111.4] assign _T_38 = $signed(_T_37); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111112.4] assign _T_39 = $signed(_T_38) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111113.4] assign _T_40 = mpu_physaddr ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111114.4] assign _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111115.4] assign _T_42 = $signed(_T_41) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111116.4] assign _T_43 = $signed(_T_42); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111117.4] assign _T_44 = $signed(_T_43) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111118.4] assign _T_46 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111120.4] assign _T_47 = $signed(_T_46) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111121.4] assign _T_48 = $signed(_T_47); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111122.4] assign _T_49 = $signed(_T_48) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111123.4] assign _T_50 = mpu_physaddr ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111124.4] assign _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111125.4] assign _T_52 = $signed(_T_51) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111126.4] assign _T_53 = $signed(_T_52); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111127.4] assign _T_54 = $signed(_T_53) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111128.4] assign _T_55 = mpu_physaddr ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111129.4] assign _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111130.4] assign _T_57 = $signed(_T_56) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111131.4] assign _T_58 = $signed(_T_57); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111132.4] assign _T_59 = $signed(_T_58) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111133.4] assign _T_60 = mpu_physaddr ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111134.4] assign _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111135.4] assign _T_62 = $signed(_T_61) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111136.4] assign _T_63 = $signed(_T_62); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111137.4] assign _T_64 = $signed(_T_63) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111138.4] assign _T_66 = _T_34 | _T_39; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111148.4] assign _T_67 = _T_66 | _T_44; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111149.4] assign _T_68 = _T_67 | _T_49; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111150.4] assign _T_69 = _T_68 | _T_54; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111151.4] assign _T_70 = _T_69 | _T_59; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111152.4] assign legal_address = _T_70 | _T_64; // @[TLB.scala 192:67:freechips.rocketchip.system.TinyConfig.fir@111153.4] assign _T_133 = mpu_physaddr ^ 32'h40000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@111218.4] assign _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@111219.4] assign _T_177 = $signed(_T_134) & $signed(33'shc0000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111263.4] assign _T_178 = $signed(_T_177); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111264.4] assign _T_179 = $signed(_T_178) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111265.4] assign _T_246 = $signed(_T_46) & $signed(33'sh4a000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111338.4] assign _T_247 = $signed(_T_246); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@111339.4] assign _T_248 = $signed(_T_247) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@111340.4] assign _T_254 = _T_248 | _T_179; // @[Parameters.scala 157:89:freechips.rocketchip.system.TinyConfig.fir@111346.4] assign _T_270 = legal_address & _T_254; // @[TLB.scala 194:19:freechips.rocketchip.system.TinyConfig.fir@111363.4] assign prot_x = _T_270 & pmp_io_x; // @[TLB.scala 201:40:freechips.rocketchip.system.TinyConfig.fir@111364.4] assign _T_861 = prot_x ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@112436.4] assign px_array = {_T_861,5'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@112441.4] assign _T_1096 = ~ px_array; // @[TLB.scala 327:23:freechips.rocketchip.system.TinyConfig.fir@112713.4] assign _T_1097 = _T_1096 & 7'h40; // @[TLB.scala 327:33:freechips.rocketchip.system.TinyConfig.fir@112714.4] assign io_resp_paddr = {vpn,_T_26}; // @[TLB.scala 335:17:freechips.rocketchip.system.TinyConfig.fir@112739.4] assign io_resp_ae_inst = _T_1097 != 7'h0; // @[TLB.scala 327:19:freechips.rocketchip.system.TinyConfig.fir@112716.4] assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111092.4] assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111093.4] assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111094.4] assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111095.4] assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111096.4] assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111097.4] assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111098.4] assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 190:14:freechips.rocketchip.system.TinyConfig.fir@111099.4] assign pmp_io_addr = {mpu_ppn,_T_26}; // @[TLB.scala 188:15:freechips.rocketchip.system.TinyConfig.fir@111090.4] endmodule module Frontend( // @[:freechips.rocketchip.system.TinyConfig.fir@112746.2] input gated_clock, // @[:freechips.rocketchip.system.TinyConfig.fir@112747.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@112748.4] input auto_icache_master_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] output auto_icache_master_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] output [31:0] auto_icache_master_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input auto_icache_master_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input [2:0] auto_icache_master_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input [3:0] auto_icache_master_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input [31:0] auto_icache_master_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input auto_icache_master_out_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@112749.4] input io_cpu_might_request, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_cpu_req_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_req_bits_speculative, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output io_cpu_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output [31:0] io_cpu_resp_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output [31:0] io_cpu_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output io_cpu_resp_bits_xcpt_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output io_cpu_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_btb_update_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_bht_update_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_cpu_flush_icache, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] output [31:0] io_cpu_npc, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [1:0] io_ptw_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input io_ptw_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [29:0] io_ptw_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] input [31:0] io_ptw_pmp_7_mask // @[:freechips.rocketchip.system.TinyConfig.fir@112750.4] ); wire icache_clock; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_reset; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_auto_master_out_a_ready; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_auto_master_out_a_valid; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [31:0] icache_auto_master_out_a_bits_address; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_auto_master_out_d_valid; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [2:0] icache_auto_master_out_d_bits_opcode; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [3:0] icache_auto_master_out_d_bits_size; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [31:0] icache_auto_master_out_d_bits_data; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_auto_master_out_d_bits_corrupt; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_req_ready; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_req_valid; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [31:0] icache_io_req_bits_addr; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [31:0] icache_io_s1_paddr; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_s1_kill; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_s2_kill; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_resp_valid; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire [31:0] icache_io_resp_bits_data; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_resp_bits_ae; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire icache_io_invalidate; // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] wire fq_clock; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_reset; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_enq_ready; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_enq_valid; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [31:0] fq_io_enq_bits_pc; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [31:0] fq_io_enq_bits_data; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_enq_bits_xcpt_ae_inst; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_enq_bits_replay; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_deq_ready; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_deq_valid; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [31:0] fq_io_deq_bits_pc; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [31:0] fq_io_deq_bits_data; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire fq_io_deq_bits_replay; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [4:0] fq_io_mask; // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] wire [31:0] tlb_io_req_bits_vaddr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_resp_paddr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_resp_ae_inst; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_0_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_0_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_0_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_0_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_1_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_1_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_1_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_1_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_2_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_2_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_2_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_2_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_3_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_3_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_3_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_3_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_4_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_4_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_4_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_4_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_5_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_5_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_5_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_5_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_6_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_6_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_6_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_6_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_7_cfg_w; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire tlb_io_ptw_pmp_7_cfg_r; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [29:0] tlb_io_ptw_pmp_7_addr; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire [31:0] tlb_io_ptw_pmp_7_mask; // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] wire _T_3; // @[Frontend.scala 89:52:freechips.rocketchip.system.TinyConfig.fir@112774.4] wire _T_4; // @[Frontend.scala 89:75:freechips.rocketchip.system.TinyConfig.fir@112775.4] wire _T_5; // @[Frontend.scala 89:102:freechips.rocketchip.system.TinyConfig.fir@112776.4] wire _T_6; // @[Frontend.scala 89:10:freechips.rocketchip.system.TinyConfig.fir@112777.4] wire _T_7; // @[Frontend.scala 89:130:freechips.rocketchip.system.TinyConfig.fir@112778.4] wire _T_9; // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112780.4] wire _T_10; // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112781.4] reg s1_valid; // @[Frontend.scala 100:21:freechips.rocketchip.system.TinyConfig.fir@112792.4] reg [31:0] _RAND_0; reg s2_valid; // @[Frontend.scala 101:25:freechips.rocketchip.system.TinyConfig.fir@112793.4] reg [31:0] _RAND_1; wire _T_11; // @[Frontend.scala 103:16:freechips.rocketchip.system.TinyConfig.fir@112794.4] wire _T_12; // @[Frontend.scala 103:5:freechips.rocketchip.system.TinyConfig.fir@112795.4] wire _T_13; // @[Frontend.scala 104:17:freechips.rocketchip.system.TinyConfig.fir@112796.4] wire _T_14; // @[Frontend.scala 104:6:freechips.rocketchip.system.TinyConfig.fir@112797.4] wire _T_15; // @[Frontend.scala 104:45:freechips.rocketchip.system.TinyConfig.fir@112798.4] wire _T_16; // @[Frontend.scala 104:58:freechips.rocketchip.system.TinyConfig.fir@112799.4] wire _T_17; // @[Frontend.scala 104:55:freechips.rocketchip.system.TinyConfig.fir@112800.4] wire _T_18; // @[Frontend.scala 104:41:freechips.rocketchip.system.TinyConfig.fir@112801.4] wire _T_19; // @[Frontend.scala 103:40:freechips.rocketchip.system.TinyConfig.fir@112802.4] wire _T_20; // @[Frontend.scala 105:17:freechips.rocketchip.system.TinyConfig.fir@112803.4] wire _T_21; // @[Frontend.scala 105:6:freechips.rocketchip.system.TinyConfig.fir@112804.4] wire _T_24; // @[Frontend.scala 105:55:freechips.rocketchip.system.TinyConfig.fir@112807.4] wire _T_25; // @[Frontend.scala 105:41:freechips.rocketchip.system.TinyConfig.fir@112808.4] wire s0_fq_has_space; // @[Frontend.scala 104:70:freechips.rocketchip.system.TinyConfig.fir@112809.4] wire s0_valid; // @[Frontend.scala 106:35:freechips.rocketchip.system.TinyConfig.fir@112810.4] reg [31:0] s1_pc; // @[Frontend.scala 108:18:freechips.rocketchip.system.TinyConfig.fir@112812.4] reg [31:0] _RAND_2; reg s1_speculative; // @[Frontend.scala 109:27:freechips.rocketchip.system.TinyConfig.fir@112813.4] reg [31:0] _RAND_3; reg [31:0] s2_pc; // @[Frontend.scala 110:22:freechips.rocketchip.system.TinyConfig.fir@112817.4] reg [31:0] _RAND_4; reg s2_tlb_resp_ae_inst; // @[Frontend.scala 114:24:freechips.rocketchip.system.TinyConfig.fir@112820.4] reg [31:0] _RAND_5; reg s2_speculative; // @[Frontend.scala 116:27:freechips.rocketchip.system.TinyConfig.fir@112822.4] reg [31:0] _RAND_6; wire [31:0] _T_29; // @[Frontend.scala 121:22:freechips.rocketchip.system.TinyConfig.fir@112826.4] wire [31:0] _T_30; // @[Frontend.scala 121:29:freechips.rocketchip.system.TinyConfig.fir@112827.4] wire [31:0] s1_base_pc; // @[Frontend.scala 121:20:freechips.rocketchip.system.TinyConfig.fir@112828.4] wire [31:0] ntpc; // @[Frontend.scala 122:25:freechips.rocketchip.system.TinyConfig.fir@112830.4] wire _T_32; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112839.4] wire _T_33; // @[Frontend.scala 127:29:freechips.rocketchip.system.TinyConfig.fir@112840.4] wire _T_34; // @[Frontend.scala 127:26:freechips.rocketchip.system.TinyConfig.fir@112841.4] wire _T_35; // @[Frontend.scala 127:72:freechips.rocketchip.system.TinyConfig.fir@112842.4] reg _T_37; // @[Frontend.scala 127:58:freechips.rocketchip.system.TinyConfig.fir@112844.4] reg [31:0] _RAND_7; wire s2_replay; // @[Frontend.scala 127:48:freechips.rocketchip.system.TinyConfig.fir@112846.4] wire _T_36; // @[Frontend.scala 127:69:freechips.rocketchip.system.TinyConfig.fir@112843.4] wire [31:0] npc; // @[Frontend.scala 128:16:freechips.rocketchip.system.TinyConfig.fir@112848.4] wire _T_39; // @[Frontend.scala 134:56:freechips.rocketchip.system.TinyConfig.fir@112850.4] wire _T_40; // @[Frontend.scala 134:53:freechips.rocketchip.system.TinyConfig.fir@112851.4] wire s0_speculative; // @[Frontend.scala 134:41:freechips.rocketchip.system.TinyConfig.fir@112852.4] wire _T_44; // @[Frontend.scala 140:9:freechips.rocketchip.system.TinyConfig.fir@112861.4] wire _T_45; // @[Frontend.scala 141:17:freechips.rocketchip.system.TinyConfig.fir@112863.6] reg _T_54; // @[Frontend.scala 165:29:freechips.rocketchip.system.TinyConfig.fir@112893.4] reg [31:0] _RAND_8; wire _T_55; // @[Frontend.scala 165:40:freechips.rocketchip.system.TinyConfig.fir@112895.4] wire _T_57; // @[Frontend.scala 165:98:freechips.rocketchip.system.TinyConfig.fir@112897.4] wire _T_58; // @[Frontend.scala 165:77:freechips.rocketchip.system.TinyConfig.fir@112898.4] wire [31:0] _T_60; // @[Frontend.scala 167:28:freechips.rocketchip.system.TinyConfig.fir@112902.4] wire [31:0] _T_61; // @[Frontend.scala 340:29:freechips.rocketchip.system.TinyConfig.fir@112903.4] wire [31:0] _T_62; // @[Frontend.scala 340:33:freechips.rocketchip.system.TinyConfig.fir@112904.4] wire _T_66; // @[Frontend.scala 171:79:freechips.rocketchip.system.TinyConfig.fir@112911.4] wire _T_67; // @[Frontend.scala 171:76:freechips.rocketchip.system.TinyConfig.fir@112912.4] wire _T_68; // @[Frontend.scala 171:104:freechips.rocketchip.system.TinyConfig.fir@112913.4] wire _T_71; // @[Frontend.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@112920.4] ICache icache ( // @[Frontend.scala 63:26:freechips.rocketchip.system.TinyConfig.fir@112756.4] .clock(icache_clock), .reset(icache_reset), .auto_master_out_a_ready(icache_auto_master_out_a_ready), .auto_master_out_a_valid(icache_auto_master_out_a_valid), .auto_master_out_a_bits_address(icache_auto_master_out_a_bits_address), .auto_master_out_d_valid(icache_auto_master_out_d_valid), .auto_master_out_d_bits_opcode(icache_auto_master_out_d_bits_opcode), .auto_master_out_d_bits_size(icache_auto_master_out_d_bits_size), .auto_master_out_d_bits_data(icache_auto_master_out_d_bits_data), .auto_master_out_d_bits_corrupt(icache_auto_master_out_d_bits_corrupt), .io_req_ready(icache_io_req_ready), .io_req_valid(icache_io_req_valid), .io_req_bits_addr(icache_io_req_bits_addr), .io_s1_paddr(icache_io_s1_paddr), .io_s1_kill(icache_io_s1_kill), .io_s2_kill(icache_io_s2_kill), .io_resp_valid(icache_io_resp_valid), .io_resp_bits_data(icache_io_resp_bits_data), .io_resp_bits_ae(icache_io_resp_bits_ae), .io_invalidate(icache_io_invalidate) ); ShiftQueue fq ( // @[Frontend.scala 84:57:freechips.rocketchip.system.TinyConfig.fir@112766.4] .clock(fq_clock), .reset(fq_reset), .io_enq_ready(fq_io_enq_ready), .io_enq_valid(fq_io_enq_valid), .io_enq_bits_pc(fq_io_enq_bits_pc), .io_enq_bits_data(fq_io_enq_bits_data), .io_enq_bits_xcpt_ae_inst(fq_io_enq_bits_xcpt_ae_inst), .io_enq_bits_replay(fq_io_enq_bits_replay), .io_deq_ready(fq_io_deq_ready), .io_deq_valid(fq_io_deq_valid), .io_deq_bits_pc(fq_io_deq_bits_pc), .io_deq_bits_data(fq_io_deq_bits_data), .io_deq_bits_xcpt_ae_inst(fq_io_deq_bits_xcpt_ae_inst), .io_deq_bits_replay(fq_io_deq_bits_replay), .io_mask(fq_io_mask) ); TLB_1 tlb ( // @[Frontend.scala 98:19:freechips.rocketchip.system.TinyConfig.fir@112788.4] .io_req_bits_vaddr(tlb_io_req_bits_vaddr), .io_resp_paddr(tlb_io_resp_paddr), .io_resp_ae_inst(tlb_io_resp_ae_inst), .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x(tlb_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w(tlb_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r(tlb_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x(tlb_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w(tlb_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r(tlb_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x(tlb_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w(tlb_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r(tlb_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x(tlb_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w(tlb_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r(tlb_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x(tlb_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w(tlb_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r(tlb_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x(tlb_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w(tlb_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r(tlb_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x(tlb_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w(tlb_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r(tlb_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x(tlb_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w(tlb_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r(tlb_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask) ); assign _T_3 = io_cpu_req_valid | io_cpu_flush_icache; // @[Frontend.scala 89:52:freechips.rocketchip.system.TinyConfig.fir@112774.4] assign _T_4 = _T_3 | io_cpu_bht_update_valid; // @[Frontend.scala 89:75:freechips.rocketchip.system.TinyConfig.fir@112775.4] assign _T_5 = _T_4 | io_cpu_btb_update_valid; // @[Frontend.scala 89:102:freechips.rocketchip.system.TinyConfig.fir@112776.4] assign _T_6 = _T_5 == 1'h0; // @[Frontend.scala 89:10:freechips.rocketchip.system.TinyConfig.fir@112777.4] assign _T_7 = _T_6 | io_cpu_might_request; // @[Frontend.scala 89:130:freechips.rocketchip.system.TinyConfig.fir@112778.4] assign _T_9 = _T_7 | reset; // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112780.4] assign _T_10 = _T_9 == 1'h0; // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112781.4] assign _T_11 = fq_io_mask[2]; // @[Frontend.scala 103:16:freechips.rocketchip.system.TinyConfig.fir@112794.4] assign _T_12 = _T_11 == 1'h0; // @[Frontend.scala 103:5:freechips.rocketchip.system.TinyConfig.fir@112795.4] assign _T_13 = fq_io_mask[3]; // @[Frontend.scala 104:17:freechips.rocketchip.system.TinyConfig.fir@112796.4] assign _T_14 = _T_13 == 1'h0; // @[Frontend.scala 104:6:freechips.rocketchip.system.TinyConfig.fir@112797.4] assign _T_15 = s1_valid == 1'h0; // @[Frontend.scala 104:45:freechips.rocketchip.system.TinyConfig.fir@112798.4] assign _T_16 = s2_valid == 1'h0; // @[Frontend.scala 104:58:freechips.rocketchip.system.TinyConfig.fir@112799.4] assign _T_17 = _T_15 | _T_16; // @[Frontend.scala 104:55:freechips.rocketchip.system.TinyConfig.fir@112800.4] assign _T_18 = _T_14 & _T_17; // @[Frontend.scala 104:41:freechips.rocketchip.system.TinyConfig.fir@112801.4] assign _T_19 = _T_12 | _T_18; // @[Frontend.scala 103:40:freechips.rocketchip.system.TinyConfig.fir@112802.4] assign _T_20 = fq_io_mask[4]; // @[Frontend.scala 105:17:freechips.rocketchip.system.TinyConfig.fir@112803.4] assign _T_21 = _T_20 == 1'h0; // @[Frontend.scala 105:6:freechips.rocketchip.system.TinyConfig.fir@112804.4] assign _T_24 = _T_15 & _T_16; // @[Frontend.scala 105:55:freechips.rocketchip.system.TinyConfig.fir@112807.4] assign _T_25 = _T_21 & _T_24; // @[Frontend.scala 105:41:freechips.rocketchip.system.TinyConfig.fir@112808.4] assign s0_fq_has_space = _T_19 | _T_25; // @[Frontend.scala 104:70:freechips.rocketchip.system.TinyConfig.fir@112809.4] assign s0_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 106:35:freechips.rocketchip.system.TinyConfig.fir@112810.4] assign _T_29 = ~ s1_pc; // @[Frontend.scala 121:22:freechips.rocketchip.system.TinyConfig.fir@112826.4] assign _T_30 = _T_29 | 32'h3; // @[Frontend.scala 121:29:freechips.rocketchip.system.TinyConfig.fir@112827.4] assign s1_base_pc = ~ _T_30; // @[Frontend.scala 121:20:freechips.rocketchip.system.TinyConfig.fir@112828.4] assign ntpc = s1_base_pc + 32'h4; // @[Frontend.scala 122:25:freechips.rocketchip.system.TinyConfig.fir@112830.4] assign _T_32 = fq_io_enq_ready & fq_io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112839.4] assign _T_33 = _T_32 == 1'h0; // @[Frontend.scala 127:29:freechips.rocketchip.system.TinyConfig.fir@112840.4] assign _T_34 = s2_valid & _T_33; // @[Frontend.scala 127:26:freechips.rocketchip.system.TinyConfig.fir@112841.4] assign _T_35 = s0_valid == 1'h0; // @[Frontend.scala 127:72:freechips.rocketchip.system.TinyConfig.fir@112842.4] assign s2_replay = _T_34 | _T_37; // @[Frontend.scala 127:48:freechips.rocketchip.system.TinyConfig.fir@112846.4] assign _T_36 = s2_replay & _T_35; // @[Frontend.scala 127:69:freechips.rocketchip.system.TinyConfig.fir@112843.4] assign npc = s2_replay ? s2_pc : ntpc; // @[Frontend.scala 128:16:freechips.rocketchip.system.TinyConfig.fir@112848.4] assign _T_39 = s2_speculative == 1'h0; // @[Frontend.scala 134:56:freechips.rocketchip.system.TinyConfig.fir@112850.4] assign _T_40 = s2_valid & _T_39; // @[Frontend.scala 134:53:freechips.rocketchip.system.TinyConfig.fir@112851.4] assign s0_speculative = s1_speculative | _T_40; // @[Frontend.scala 134:41:freechips.rocketchip.system.TinyConfig.fir@112852.4] assign _T_44 = s2_replay == 1'h0; // @[Frontend.scala 140:9:freechips.rocketchip.system.TinyConfig.fir@112861.4] assign _T_45 = io_cpu_req_valid == 1'h0; // @[Frontend.scala 141:17:freechips.rocketchip.system.TinyConfig.fir@112863.6] assign _T_55 = _T_54 & s2_valid; // @[Frontend.scala 165:40:freechips.rocketchip.system.TinyConfig.fir@112895.4] assign _T_57 = icache_io_s2_kill; // @[Frontend.scala 165:98:freechips.rocketchip.system.TinyConfig.fir@112897.4] assign _T_58 = icache_io_resp_valid | _T_57; // @[Frontend.scala 165:77:freechips.rocketchip.system.TinyConfig.fir@112898.4] assign _T_60 = io_cpu_req_valid ? io_cpu_req_bits_pc : npc; // @[Frontend.scala 167:28:freechips.rocketchip.system.TinyConfig.fir@112902.4] assign _T_61 = ~ _T_60; // @[Frontend.scala 340:29:freechips.rocketchip.system.TinyConfig.fir@112903.4] assign _T_62 = _T_61 | 32'h1; // @[Frontend.scala 340:33:freechips.rocketchip.system.TinyConfig.fir@112904.4] assign _T_66 = icache_io_resp_valid == 1'h0; // @[Frontend.scala 171:79:freechips.rocketchip.system.TinyConfig.fir@112911.4] assign _T_67 = icache_io_s2_kill & _T_66; // @[Frontend.scala 171:76:freechips.rocketchip.system.TinyConfig.fir@112912.4] assign _T_68 = s2_tlb_resp_ae_inst == 1'h0; // @[Frontend.scala 171:104:freechips.rocketchip.system.TinyConfig.fir@112913.4] assign _T_71 = icache_io_resp_valid & icache_io_resp_bits_ae; // @[Frontend.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@112920.4] assign auto_icache_master_out_a_valid = icache_auto_master_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign auto_icache_master_out_a_bits_address = icache_auto_master_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign io_cpu_resp_valid = fq_io_deq_valid; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign io_cpu_resp_bits_pc = fq_io_deq_bits_pc; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign io_cpu_resp_bits_data = fq_io_deq_bits_data; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign io_cpu_resp_bits_xcpt_ae_inst = fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign io_cpu_resp_bits_replay = fq_io_deq_bits_replay; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign io_cpu_npc = ~ _T_62; // @[Frontend.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@112906.4] assign icache_clock = gated_clock; // @[:freechips.rocketchip.system.TinyConfig.fir@112761.4 Frontend.scala 94:16:freechips.rocketchip.system.TinyConfig.fir@112786.4] assign icache_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@112762.4] assign icache_auto_master_out_a_ready = auto_icache_master_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_auto_master_out_d_valid = auto_icache_master_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_auto_master_out_d_bits_opcode = auto_icache_master_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_auto_master_out_d_bits_size = auto_icache_master_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_auto_master_out_d_bits_data = auto_icache_master_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_auto_master_out_d_bits_corrupt = auto_icache_master_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@112763.4] assign icache_io_req_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 156:23:freechips.rocketchip.system.TinyConfig.fir@112880.4] assign icache_io_req_bits_addr = io_cpu_npc; // @[Frontend.scala 157:27:freechips.rocketchip.system.TinyConfig.fir@112881.4] assign icache_io_s1_paddr = tlb_io_resp_paddr; // @[Frontend.scala 159:22:freechips.rocketchip.system.TinyConfig.fir@112883.4] assign icache_io_s1_kill = io_cpu_req_valid | s2_replay; // @[Frontend.scala 161:21:freechips.rocketchip.system.TinyConfig.fir@112887.4] assign icache_io_s2_kill = s2_speculative | s2_tlb_resp_ae_inst; // @[Frontend.scala 162:21:freechips.rocketchip.system.TinyConfig.fir@112891.4] assign icache_io_invalidate = io_cpu_flush_icache; // @[Frontend.scala 158:24:freechips.rocketchip.system.TinyConfig.fir@112882.4] assign fq_clock = gated_clock; // @[:freechips.rocketchip.system.TinyConfig.fir@112768.4] assign fq_reset = reset | io_cpu_req_valid; // @[:freechips.rocketchip.system.TinyConfig.fir@112769.4] assign fq_io_enq_valid = _T_55 & _T_58; // @[Frontend.scala 165:19:freechips.rocketchip.system.TinyConfig.fir@112900.4] assign fq_io_enq_bits_pc = s2_pc; // @[Frontend.scala 166:21:freechips.rocketchip.system.TinyConfig.fir@112901.4] assign fq_io_enq_bits_data = icache_io_resp_bits_data; // @[Frontend.scala 169:23:freechips.rocketchip.system.TinyConfig.fir@112907.4] assign fq_io_enq_bits_xcpt_ae_inst = _T_71 ? 1'h1 : s2_tlb_resp_ae_inst; // @[Frontend.scala 174:23:freechips.rocketchip.system.TinyConfig.fir@112919.4 Frontend.scala 175:87:freechips.rocketchip.system.TinyConfig.fir@112922.6] assign fq_io_enq_bits_replay = _T_67 & _T_68; // @[Frontend.scala 171:25:freechips.rocketchip.system.TinyConfig.fir@112916.4] assign fq_io_deq_ready = io_cpu_resp_ready; // @[Frontend.scala 324:15:freechips.rocketchip.system.TinyConfig.fir@112924.4] assign tlb_io_req_bits_vaddr = s1_pc; // @[Frontend.scala 149:25:freechips.rocketchip.system.TinyConfig.fir@112873.4] assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[Frontend.scala 147:10:freechips.rocketchip.system.TinyConfig.fir@112869.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; s1_valid = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; s2_valid = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; s1_pc = _RAND_2[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; s1_speculative = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; s2_pc = _RAND_4[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; s2_tlb_resp_ae_inst = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; s2_speculative = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_37 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_54 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge gated_clock) begin s1_valid <= io_cpu_req_valid | s0_fq_has_space; if (reset) begin s2_valid <= 1'h0; end else begin if (_T_44) begin s2_valid <= _T_45; end else begin s2_valid <= 1'h0; end end s1_pc <= io_cpu_npc; if (io_cpu_req_valid) begin s1_speculative <= io_cpu_req_bits_speculative; end else begin if (s2_replay) begin s1_speculative <= s2_speculative; end else begin s1_speculative <= s0_speculative; end end if (reset) begin s2_pc <= 32'h10040; end else begin if (_T_44) begin s2_pc <= s1_pc; end end if (_T_44) begin s2_tlb_resp_ae_inst <= tlb_io_resp_ae_inst; end if (reset) begin s2_speculative <= 1'h0; end else begin if (_T_44) begin s2_speculative <= s1_speculative; end end if (reset) begin _T_37 <= 1'h1; end else begin _T_37 <= _T_36; end _T_54 <= s1_valid; `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_10) begin $fwrite(32'h80000002,"Assertion failed\n at Frontend.scala:89 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n"); // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112783.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_10) begin $fatal; // @[Frontend.scala 89:9:freechips.rocketchip.system.TinyConfig.fir@112784.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module ScratchpadSlavePort( // @[:freechips.rocketchip.system.TinyConfig.fir@112949.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@112950.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@112951.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [10:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] output [10:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@112952.4] input io_dmem_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output io_dmem_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output [31:0] io_dmem_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output [4:0] io_dmem_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output [1:0] io_dmem_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output io_dmem_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output [31:0] io_dmem_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] output [3:0] io_dmem_s1_data_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] input io_dmem_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] input io_dmem_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] input [31:0] io_dmem_resp_bits_data_raw // @[:freechips.rocketchip.system.TinyConfig.fir@112953.4] ); reg [2:0] state; // @[ScratchpadSlavePort.scala 46:20:freechips.rocketchip.system.TinyConfig.fir@112962.4] reg [31:0] _RAND_0; wire _T; // @[ScratchpadSlavePort.scala 48:17:freechips.rocketchip.system.TinyConfig.fir@112965.4] wire _T_51; // @[ScratchpadSlavePort.scala 98:50:freechips.rocketchip.system.TinyConfig.fir@113056.4] wire tl_in_d_valid; // @[ScratchpadSlavePort.scala 98:41:freechips.rocketchip.system.TinyConfig.fir@113057.4] wire _T_1; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112972.4] wire _T_6; // @[ScratchpadSlavePort.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@112991.4] wire _T_7; // @[ScratchpadSlavePort.scala 86:44:freechips.rocketchip.system.TinyConfig.fir@112992.4] wire _T_8; // @[ScratchpadSlavePort.scala 86:56:freechips.rocketchip.system.TinyConfig.fir@112993.4] wire _T_9; // @[ScratchpadSlavePort.scala 86:78:freechips.rocketchip.system.TinyConfig.fir@112994.4] wire ready; // @[ScratchpadSlavePort.scala 86:35:freechips.rocketchip.system.TinyConfig.fir@112995.4] wire _T_10; // @[ScratchpadSlavePort.scala 87:38:freechips.rocketchip.system.TinyConfig.fir@112996.4] wire _T_11; // @[ScratchpadSlavePort.scala 87:57:freechips.rocketchip.system.TinyConfig.fir@112997.4] wire dmem_req_valid; // @[ScratchpadSlavePort.scala 87:48:freechips.rocketchip.system.TinyConfig.fir@112998.4] wire _T_2; // @[ScratchpadSlavePort.scala 52:26:freechips.rocketchip.system.TinyConfig.fir@112979.4] reg [2:0] acq_opcode; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_1; reg [2:0] acq_param; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_2; reg [1:0] acq_size; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_3; reg [10:0] acq_source; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_4; reg [31:0] acq_address; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_5; reg [3:0] acq_mask; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_6; reg [31:0] acq_data; // @[ScratchpadSlavePort.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@112983.4] reg [31:0] _RAND_7; wire tl_in_a_ready; // @[ScratchpadSlavePort.scala 91:40:freechips.rocketchip.system.TinyConfig.fir@113004.4] wire _T_3; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112984.4] wire ready_likely; // @[ScratchpadSlavePort.scala 85:42:freechips.rocketchip.system.TinyConfig.fir@112990.4] wire _T_13; // @[ScratchpadSlavePort.scala 88:48:freechips.rocketchip.system.TinyConfig.fir@113000.4] wire [2:0] _T_17_opcode; // @[ScratchpadSlavePort.scala 92:41:freechips.rocketchip.system.TinyConfig.fir@113007.4] wire [2:0] _T_17_param; // @[ScratchpadSlavePort.scala 92:41:freechips.rocketchip.system.TinyConfig.fir@113007.4] wire _T_21; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113014.4] wire [3:0] _T_22; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113015.4] wire _T_23; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113016.4] wire [3:0] _T_24; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113017.4] wire _T_25; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113018.4] wire [3:0] _T_26; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113019.4] wire _T_27; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113020.4] wire [3:0] _T_28; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113021.4] wire _T_29; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113022.4] wire [3:0] _T_30; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113023.4] wire [2:0] _T_33; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113027.4] wire [3:0] _T_35; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113029.4] wire [3:0] _T_37; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113031.4] wire [3:0] _T_39; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113033.4] wire _T_42; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113036.4] wire [3:0] _T_43; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113037.4] wire _T_44; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113038.4] wire [3:0] _T_45; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113039.4] wire _T_46; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113040.4] wire [4:0] _T_47; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113041.4] wire _T_48; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113042.4] wire _T_53; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@113059.4] wire _T_54; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@113060.4] wire _T_55; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@113061.4] reg [31:0] _T_60; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@113085.4] reg [31:0] _RAND_8; assign _T = state == 3'h1; // @[ScratchpadSlavePort.scala 48:17:freechips.rocketchip.system.TinyConfig.fir@112965.4] assign _T_51 = state == 3'h4; // @[ScratchpadSlavePort.scala 98:50:freechips.rocketchip.system.TinyConfig.fir@113056.4] assign tl_in_d_valid = io_dmem_resp_valid | _T_51; // @[ScratchpadSlavePort.scala 98:41:freechips.rocketchip.system.TinyConfig.fir@113057.4] assign _T_1 = auto_in_d_ready & tl_in_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112972.4] assign _T_6 = state == 3'h0; // @[ScratchpadSlavePort.scala 86:23:freechips.rocketchip.system.TinyConfig.fir@112991.4] assign _T_7 = state == 3'h2; // @[ScratchpadSlavePort.scala 86:44:freechips.rocketchip.system.TinyConfig.fir@112992.4] assign _T_8 = _T_7 & io_dmem_resp_valid; // @[ScratchpadSlavePort.scala 86:56:freechips.rocketchip.system.TinyConfig.fir@112993.4] assign _T_9 = _T_8 & auto_in_d_ready; // @[ScratchpadSlavePort.scala 86:78:freechips.rocketchip.system.TinyConfig.fir@112994.4] assign ready = _T_6 | _T_9; // @[ScratchpadSlavePort.scala 86:35:freechips.rocketchip.system.TinyConfig.fir@112995.4] assign _T_10 = auto_in_a_valid & ready; // @[ScratchpadSlavePort.scala 87:38:freechips.rocketchip.system.TinyConfig.fir@112996.4] assign _T_11 = state == 3'h3; // @[ScratchpadSlavePort.scala 87:57:freechips.rocketchip.system.TinyConfig.fir@112997.4] assign dmem_req_valid = _T_10 | _T_11; // @[ScratchpadSlavePort.scala 87:48:freechips.rocketchip.system.TinyConfig.fir@112998.4] assign _T_2 = dmem_req_valid & io_dmem_req_ready; // @[ScratchpadSlavePort.scala 52:26:freechips.rocketchip.system.TinyConfig.fir@112979.4] assign tl_in_a_ready = io_dmem_req_ready & ready; // @[ScratchpadSlavePort.scala 91:40:freechips.rocketchip.system.TinyConfig.fir@113004.4] assign _T_3 = tl_in_a_ready & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@112984.4] assign ready_likely = _T_6 | _T_7; // @[ScratchpadSlavePort.scala 85:42:freechips.rocketchip.system.TinyConfig.fir@112990.4] assign _T_13 = auto_in_a_valid & ready_likely; // @[ScratchpadSlavePort.scala 88:48:freechips.rocketchip.system.TinyConfig.fir@113000.4] assign _T_17_opcode = _T_11 ? acq_opcode : auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala 92:41:freechips.rocketchip.system.TinyConfig.fir@113007.4] assign _T_17_param = _T_11 ? acq_param : auto_in_a_bits_param; // @[ScratchpadSlavePort.scala 92:41:freechips.rocketchip.system.TinyConfig.fir@113007.4] assign _T_21 = 3'h4 == _T_17_param; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113014.4] assign _T_22 = _T_21 ? 4'h8 : 4'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113015.4] assign _T_23 = 3'h3 == _T_17_param; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113016.4] assign _T_24 = _T_23 ? 4'hf : _T_22; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113017.4] assign _T_25 = 3'h2 == _T_17_param; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113018.4] assign _T_26 = _T_25 ? 4'he : _T_24; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113019.4] assign _T_27 = 3'h1 == _T_17_param; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113020.4] assign _T_28 = _T_27 ? 4'hd : _T_26; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113021.4] assign _T_29 = 3'h0 == _T_17_param; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113022.4] assign _T_30 = _T_29 ? 4'hc : _T_28; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113023.4] assign _T_33 = _T_23 ? 3'h4 : 3'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113027.4] assign _T_35 = _T_25 ? 4'hb : {{1'd0}, _T_33}; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113029.4] assign _T_37 = _T_27 ? 4'ha : _T_35; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113031.4] assign _T_39 = _T_29 ? 4'h9 : _T_37; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113033.4] assign _T_42 = 3'h3 == _T_17_opcode; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113036.4] assign _T_43 = _T_42 ? _T_39 : 4'h0; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113037.4] assign _T_44 = 3'h2 == _T_17_opcode; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113038.4] assign _T_45 = _T_44 ? _T_30 : _T_43; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113039.4] assign _T_46 = 3'h1 == _T_17_opcode; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113040.4] assign _T_47 = _T_46 ? 5'h11 : {{1'd0}, _T_45}; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@113041.4] assign _T_48 = 3'h0 == _T_17_opcode; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@113042.4] assign _T_53 = acq_opcode == 3'h0; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@113059.4] assign _T_54 = acq_opcode == 3'h1; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@113060.4] assign _T_55 = _T_53 | _T_54; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@113061.4] assign auto_in_a_ready = io_dmem_req_ready & ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign auto_in_d_valid = io_dmem_resp_valid | _T_51; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign auto_in_d_bits_opcode = _T_55 ? 3'h0 : 3'h1; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign auto_in_d_bits_size = acq_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign auto_in_d_bits_source = acq_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign auto_in_d_bits_data = _T_7 ? io_dmem_resp_bits_data_raw : _T_60; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@112961.4] assign io_dmem_req_valid = _T_13 | _T_11; // @[ScratchpadSlavePort.scala 90:23:freechips.rocketchip.system.TinyConfig.fir@113003.4] assign io_dmem_req_bits_addr = _T_11 ? acq_address : auto_in_a_bits_address; // @[ScratchpadSlavePort.scala 92:22:freechips.rocketchip.system.TinyConfig.fir@113050.4] assign io_dmem_req_bits_cmd = _T_48 ? 5'h1 : _T_47; // @[ScratchpadSlavePort.scala 92:22:freechips.rocketchip.system.TinyConfig.fir@113050.4] assign io_dmem_req_bits_size = _T_11 ? acq_size : auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 92:22:freechips.rocketchip.system.TinyConfig.fir@113050.4] assign io_dmem_s1_kill = state != 3'h1; // @[ScratchpadSlavePort.scala 95:21:freechips.rocketchip.system.TinyConfig.fir@113054.4] assign io_dmem_s1_data_data = acq_data; // @[ScratchpadSlavePort.scala 93:26:freechips.rocketchip.system.TinyConfig.fir@113051.4] assign io_dmem_s1_data_mask = acq_mask; // @[ScratchpadSlavePort.scala 94:26:freechips.rocketchip.system.TinyConfig.fir@113052.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; state = _RAND_0[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; acq_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; acq_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; acq_size = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; acq_source = _RAND_4[10:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; acq_address = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; acq_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; acq_data = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_60 = _RAND_8[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin state <= 3'h0; end else begin if (_T_2) begin state <= 3'h1; end else begin if (io_dmem_s2_nack) begin state <= 3'h3; end else begin if (_T_1) begin state <= 3'h0; end else begin if (io_dmem_resp_valid) begin state <= 3'h4; end else begin if (_T) begin state <= 3'h2; end end end end end end if (_T_3) begin acq_opcode <= auto_in_a_bits_opcode; end if (_T_3) begin acq_param <= auto_in_a_bits_param; end if (_T_3) begin acq_size <= auto_in_a_bits_size; end if (_T_3) begin acq_source <= auto_in_a_bits_source; end if (_T_3) begin acq_address <= auto_in_a_bits_address; end if (_T_3) begin acq_mask <= auto_in_a_bits_mask; end if (_T_3) begin acq_data <= auto_in_a_bits_data; end if (_T_7) begin _T_60 <= io_dmem_resp_bits_data_raw; end end endmodule module Repeater_5( // @[:freechips.rocketchip.system.TinyConfig.fir@113101.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@113102.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@113103.4] input io_repeat, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output io_full, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] output [3:0] io_deq_bits_mask // @[:freechips.rocketchip.system.TinyConfig.fir@113104.4] ); reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.TinyConfig.fir@113109.4] reg [31:0] _RAND_0; reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_1; reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_2; reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_3; reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_4; reg [31:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_5; reg [3:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.TinyConfig.fir@113110.4] reg [31:0] _RAND_6; wire _T_1; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@113113.4] wire _T_4; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113119.4] wire _T_5; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@113120.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113125.4] wire _T_7; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@113126.4] wire _T_8; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@113127.4] assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.TinyConfig.fir@113113.4] assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113119.4] assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.TinyConfig.fir@113120.4] assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113125.4] assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.TinyConfig.fir@113126.4] assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:freechips.rocketchip.system.TinyConfig.fir@113127.4] assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.TinyConfig.fir@113118.4] assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:freechips.rocketchip.system.TinyConfig.fir@113115.4] assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@113112.4] assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.TinyConfig.fir@113117.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; saved_opcode = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; saved_param = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; saved_size = _RAND_3[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; saved_source = _RAND_4[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; saved_address = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; saved_mask = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin full <= 1'h0; end else begin if (_T_8) begin full <= 1'h0; end else begin if (_T_5) begin full <= 1'h1; end end end if (_T_5) begin saved_opcode <= io_enq_bits_opcode; end if (_T_5) begin saved_param <= io_enq_bits_param; end if (_T_5) begin saved_size <= io_enq_bits_size; end if (_T_5) begin saved_source <= io_enq_bits_source; end if (_T_5) begin saved_address <= io_enq_bits_address; end if (_T_5) begin saved_mask <= io_enq_bits_mask; end end endmodule module TLFragmenter_5( // @[:freechips.rocketchip.system.TinyConfig.fir@113132.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@113133.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@113134.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [10:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [10:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@113135.4] ); wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [31:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [3:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [31:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] wire [3:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] reg [3:0] _T_2; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.TinyConfig.fir@113146.4] reg [31:0] _RAND_0; reg [2:0] _T_3; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.TinyConfig.fir@113147.4] reg [31:0] _RAND_1; reg _T_4; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.TinyConfig.fir@113148.4] reg [31:0] _RAND_2; wire [3:0] _T_5; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@113149.4] wire _T_6; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@113150.4] wire _T_7; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@113151.4] wire [3:0] _T_9; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@113153.4] wire [2:0] _T_10; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@113154.4] wire [4:0] _T_12; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113156.4] wire [1:0] _T_13; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113157.4] wire [1:0] _T_14; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113158.4] wire _T_15; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@113159.4] wire _T_27; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@113175.4] wire _T_28; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@113176.4] wire [5:0] _T_29; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@113177.4] wire [5:0] _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@113178.4] wire [5:0] _T_30; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@113178.4] wire [6:0] _T_31; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@113179.4] wire [6:0] _T_32; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@113180.4] wire [6:0] _T_33; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113181.4] wire [6:0] _T_34; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@113182.4] wire [6:0] _T_35; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@113183.4] wire [2:0] _T_36; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@113184.4] wire [3:0] _T_37; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@113185.4] wire _T_38; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@113186.4] wire [3:0] _GEN_8; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113187.4] wire [3:0] _T_39; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113187.4] wire [1:0] _T_40; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@113188.4] wire [1:0] _T_41; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@113189.4] wire _T_42; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@113190.4] wire [1:0] _T_43; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113191.4] wire _T_44; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@113192.4] wire [2:0] _T_46; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113194.4] wire _T_53; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@113208.4] wire _T_52; // @[Fragmenter.scala 200:54:freechips.rocketchip.system.TinyConfig.fir@113207.4] wire _T_54; // @[Fragmenter.scala 203:37:freechips.rocketchip.system.TinyConfig.fir@113209.4] wire _T_55; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@113210.4] wire _T_56; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@113211.4] wire _T_57; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@113212.4] wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113195.4] wire [3:0] _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@113197.6] wire [3:0] _T_49; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@113198.6] wire _T_51; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@113203.8] wire _T_58; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@113214.4] wire _T_80; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@113247.4] wire [2:0] _T_81; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@113248.4] wire [12:0] _T_83; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113250.4] wire [5:0] _T_84; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113251.4] wire [5:0] _T_85; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113252.4] wire [8:0] _T_87; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113254.4] wire [1:0] _T_88; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113255.4] wire [1:0] _T_89; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113256.4] wire _T_90; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@113257.4] wire _T_91; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@113258.4] reg [3:0] _T_93; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.TinyConfig.fir@113260.4] reg [31:0] _RAND_3; wire _T_94; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@113261.4] wire [3:0] _T_95; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@113262.4] wire [3:0] _T_97; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@113264.4] wire [3:0] _T_98; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@113265.4] wire [3:0] _T_99; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@113266.4] wire [3:0] _T_102; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@113269.4] reg _T_109; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@113276.4] reg [31:0] _RAND_4; wire _GEN_5; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@113277.4] wire _T_111; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@113281.4] wire _T_112; // @[Fragmenter.scala 278:78:freechips.rocketchip.system.TinyConfig.fir@113282.4] wire _T_1_a_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@113142.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@113291.4] wire _T_113; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113283.4] wire _T_114; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@113287.4] wire _T_115; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@113288.4] wire [5:0] _T_117; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@113292.4] wire [5:0] _T_118; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@113293.4] wire [5:0] _T_119; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@113294.4] wire [5:0] _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@113295.4] wire [5:0] _T_120; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@113295.4] wire [5:0] _T_121; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@113296.4] wire [5:0] _T_122; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@113297.4] wire [31:0] _GEN_11; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@113298.4] wire [4:0] _T_124; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113300.4] wire [5:0] _T_125; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113301.4] wire _T_127; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@113305.4] wire _T_129; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@113307.4] wire _T_131; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113309.4] wire _T_132; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113310.4] wire _T_134; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@113317.4] wire _T_135; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@113318.4] wire _T_137; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113320.4] wire _T_138; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113321.4] Repeater_5 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.TinyConfig.fir@113222.4] .clock(Repeater_clock), .reset(Repeater_reset), .io_repeat(Repeater_io_repeat), .io_full(Repeater_io_full), .io_enq_ready(Repeater_io_enq_ready), .io_enq_valid(Repeater_io_enq_valid), .io_enq_bits_opcode(Repeater_io_enq_bits_opcode), .io_enq_bits_param(Repeater_io_enq_bits_param), .io_enq_bits_size(Repeater_io_enq_bits_size), .io_enq_bits_source(Repeater_io_enq_bits_source), .io_enq_bits_address(Repeater_io_enq_bits_address), .io_enq_bits_mask(Repeater_io_enq_bits_mask), .io_deq_ready(Repeater_io_deq_ready), .io_deq_valid(Repeater_io_deq_valid), .io_deq_bits_opcode(Repeater_io_deq_bits_opcode), .io_deq_bits_param(Repeater_io_deq_bits_param), .io_deq_bits_size(Repeater_io_deq_bits_size), .io_deq_bits_source(Repeater_io_deq_bits_source), .io_deq_bits_address(Repeater_io_deq_bits_address), .io_deq_bits_mask(Repeater_io_deq_bits_mask) ); assign _T_5 = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.TinyConfig.fir@113149.4] assign _T_6 = _T_2 == 4'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.TinyConfig.fir@113150.4] assign _T_7 = _T_5 == 4'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.TinyConfig.fir@113151.4] assign _T_9 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@113153.4] assign _T_10 = _T_9[2:0]; // @[OneHot.scala 65:27:freechips.rocketchip.system.TinyConfig.fir@113154.4] assign _T_12 = 5'h3 << auto_out_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113156.4] assign _T_13 = _T_12[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113157.4] assign _T_14 = ~ _T_13; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113158.4] assign _T_15 = auto_out_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@113159.4] assign _T_27 = _T_10[2:2]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.TinyConfig.fir@113175.4] assign _T_28 = _T_15 ? 1'h1 : _T_27; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.TinyConfig.fir@113176.4] assign _T_29 = {_T_5, 2'h0}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.TinyConfig.fir@113177.4] assign _GEN_7 = {{4'd0}, _T_14}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@113178.4] assign _T_30 = _T_29 | _GEN_7; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.TinyConfig.fir@113178.4] assign _T_31 = {_T_30, 1'h0}; // @[package.scala 187:35:freechips.rocketchip.system.TinyConfig.fir@113179.4] assign _T_32 = _T_31 | 7'h1; // @[package.scala 187:40:freechips.rocketchip.system.TinyConfig.fir@113180.4] assign _T_33 = {1'h0,_T_30}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113181.4] assign _T_34 = ~ _T_33; // @[package.scala 187:53:freechips.rocketchip.system.TinyConfig.fir@113182.4] assign _T_35 = _T_32 & _T_34; // @[package.scala 187:51:freechips.rocketchip.system.TinyConfig.fir@113183.4] assign _T_36 = _T_35[6:4]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@113184.4] assign _T_37 = _T_35[3:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@113185.4] assign _T_38 = _T_36 != 3'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@113186.4] assign _GEN_8 = {{1'd0}, _T_36}; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113187.4] assign _T_39 = _GEN_8 | _T_37; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113187.4] assign _T_40 = _T_39[3:2]; // @[OneHot.scala 30:18:freechips.rocketchip.system.TinyConfig.fir@113188.4] assign _T_41 = _T_39[1:0]; // @[OneHot.scala 31:18:freechips.rocketchip.system.TinyConfig.fir@113189.4] assign _T_42 = _T_40 != 2'h0; // @[OneHot.scala 32:14:freechips.rocketchip.system.TinyConfig.fir@113190.4] assign _T_43 = _T_40 | _T_41; // @[OneHot.scala 32:28:freechips.rocketchip.system.TinyConfig.fir@113191.4] assign _T_44 = _T_43[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.TinyConfig.fir@113192.4] assign _T_46 = {_T_38,_T_42,_T_44}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113194.4] assign _T_53 = _T_15 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.TinyConfig.fir@113208.4] assign _T_52 = auto_out_d_bits_source[5]; // @[Fragmenter.scala 200:54:freechips.rocketchip.system.TinyConfig.fir@113207.4] assign _T_54 = _T_52 ? _T_6 : _T_7; // @[Fragmenter.scala 203:37:freechips.rocketchip.system.TinyConfig.fir@113209.4] assign _T_55 = _T_54 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.TinyConfig.fir@113210.4] assign _T_56 = _T_53 & _T_55; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.TinyConfig.fir@113211.4] assign _T_57 = auto_in_d_ready | _T_56; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.TinyConfig.fir@113212.4] assign _T_47 = _T_57 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113195.4] assign _GEN_9 = {{3'd0}, _T_28}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@113197.6] assign _T_49 = _T_2 - _GEN_9; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.TinyConfig.fir@113198.6] assign _T_51 = auto_out_d_bits_source[4]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@113203.8] assign _T_58 = _T_56 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.TinyConfig.fir@113214.4] assign _T_80 = Repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@113247.4] assign _T_81 = _T_80 ? 3'h2 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.TinyConfig.fir@113248.4] assign _T_83 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113250.4] assign _T_84 = _T_83[5:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113251.4] assign _T_85 = ~ _T_84; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113252.4] assign _T_87 = 9'h3 << _T_81; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113254.4] assign _T_88 = _T_87[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113255.4] assign _T_89 = ~ _T_88; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113256.4] assign _T_90 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@113257.4] assign _T_91 = _T_90 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@113258.4] assign _T_94 = _T_93 == 4'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.TinyConfig.fir@113261.4] assign _T_95 = _T_85[5:2]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.TinyConfig.fir@113262.4] assign _T_97 = _T_93 - 4'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.TinyConfig.fir@113264.4] assign _T_98 = _T_94 ? _T_95 : _T_97; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.TinyConfig.fir@113265.4] assign _T_99 = ~ _T_98; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.TinyConfig.fir@113266.4] assign _T_102 = ~ _T_99; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.TinyConfig.fir@113269.4] assign _GEN_5 = _T_94 ? _T_4 : _T_109; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@113277.4] assign _T_111 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.TinyConfig.fir@113281.4] assign _T_112 = Repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala 278:78:freechips.rocketchip.system.TinyConfig.fir@113282.4] assign _T_1_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 352:76:freechips.rocketchip.system.TinyConfig.fir@113142.4 Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@113291.4] assign _T_113 = auto_out_a_ready & _T_1_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@113283.4] assign _T_114 = _T_91 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.TinyConfig.fir@113287.4] assign _T_115 = _T_102 != 4'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.TinyConfig.fir@113288.4] assign _T_117 = {_T_98, 2'h0}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.TinyConfig.fir@113292.4] assign _T_118 = ~ _T_85; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.TinyConfig.fir@113293.4] assign _T_119 = _T_117 | _T_118; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.TinyConfig.fir@113294.4] assign _GEN_10 = {{4'd0}, _T_89}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@113295.4] assign _T_120 = _T_119 | _GEN_10; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.TinyConfig.fir@113295.4] assign _T_121 = _T_120 | 6'h3; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.TinyConfig.fir@113296.4] assign _T_122 = ~ _T_121; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.TinyConfig.fir@113297.4] assign _GEN_11 = {{26'd0}, _T_122}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.TinyConfig.fir@113298.4] assign _T_124 = {_T_111,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113300.4] assign _T_125 = {Repeater_io_deq_bits_source,_T_112}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113301.4] assign _T_127 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.TinyConfig.fir@113305.4] assign _T_129 = _T_127 | _T_114; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.TinyConfig.fir@113307.4] assign _T_131 = _T_129 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113309.4] assign _T_132 = _T_131 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113310.4] assign _T_134 = Repeater_io_deq_bits_mask == 4'hf; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.TinyConfig.fir@113317.4] assign _T_135 = _T_127 | _T_134; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.TinyConfig.fir@113318.4] assign _T_137 = _T_135 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113320.4] assign _T_138 = _T_137 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113321.4] assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_in_d_valid = auto_out_d_valid & _T_58; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_in_d_bits_size = _T_6 ? _T_46 : _T_3; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_in_d_bits_source = auto_out_d_bits_source[10:6]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@113145.4] assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_size = _T_81[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_source = {_T_125,_T_124}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_11; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_mask = Repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign auto_out_d_ready = auto_in_d_ready | _T_56; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@113144.4] assign Repeater_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@113224.4] assign Repeater_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@113225.4] assign Repeater_io_repeat = _T_114 & _T_115; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.TinyConfig.fir@113290.4] assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.TinyConfig.fir@113226.4] assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.TinyConfig.fir@113291.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_2 = _RAND_0[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_3 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_4 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_93 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_109 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_2 <= 4'h0; end else begin if (_T_47) begin if (_T_6) begin _T_2 <= _T_5; end else begin _T_2 <= _T_49; end end end if (_T_47) begin if (_T_6) begin _T_3 <= _T_46; end end if (reset) begin _T_4 <= 1'h0; end else begin if (_T_47) begin if (_T_6) begin _T_4 <= _T_51; end end end if (reset) begin _T_93 <= 4'h0; end else begin if (_T_113) begin _T_93 <= _T_102; end end if (_T_94) begin _T_109 <= _T_4; end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_132) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113312.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_132) begin $fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.TinyConfig.fir@113313.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_138) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113323.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_138) begin $fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.TinyConfig.fir@113324.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLMonitor_37( // @[:freechips.rocketchip.system.TinyConfig.fir@113355.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@113356.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@113357.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@113358.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@114818.4] wire _T_6; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@113374.6] wire _T_8; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@113379.6] wire [26:0] _T_10; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113381.6] wire [11:0] _T_11; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113382.6] wire [11:0] _T_12; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113383.6] wire [31:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@113384.6] wire [31:0] _T_13; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@113384.6] wire _T_14; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@113385.6] wire _T_16; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@113387.6] wire [1:0] _T_17; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@113388.6] wire [1:0] _T_19; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@113390.6] wire _T_20; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@113391.6] wire _T_21; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@113392.6] wire _T_22; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@113393.6] wire _T_23; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@113394.6] wire _T_25; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113396.6] wire _T_26; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113397.6] wire _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113399.6] wire _T_29; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113400.6] wire _T_30; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@113401.6] wire _T_31; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@113402.6] wire _T_32; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@113403.6] wire _T_33; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113404.6] wire _T_34; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113405.6] wire _T_35; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113406.6] wire _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113407.6] wire _T_37; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113408.6] wire _T_38; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113409.6] wire _T_39; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113410.6] wire _T_40; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113411.6] wire _T_41; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113412.6] wire _T_42; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113413.6] wire _T_43; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113414.6] wire _T_44; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113415.6] wire [3:0] _T_47; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113418.6] wire [32:0] _T_51; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113422.6] wire _T_68; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@113443.6] wire [31:0] _T_70; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113446.8] wire [32:0] _T_71; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113447.8] wire [32:0] _T_72; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113448.8] wire [32:0] _T_73; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113449.8] wire _T_74; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113450.8] wire [31:0] _T_75; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113451.8] wire [32:0] _T_76; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113452.8] wire [32:0] _T_77; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113453.8] wire [32:0] _T_78; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113454.8] wire _T_79; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113455.8] wire [31:0] _T_80; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113456.8] wire [32:0] _T_81; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113457.8] wire [32:0] _T_82; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113458.8] wire [32:0] _T_83; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113459.8] wire _T_84; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113460.8] wire [32:0] _T_87; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113463.8] wire [32:0] _T_88; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113464.8] wire _T_89; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113465.8] wire [31:0] _T_90; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113466.8] wire [32:0] _T_91; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113467.8] wire [32:0] _T_92; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113468.8] wire [32:0] _T_93; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113469.8] wire _T_94; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113470.8] wire [31:0] _T_95; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113471.8] wire [32:0] _T_96; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113472.8] wire [32:0] _T_97; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113473.8] wire [32:0] _T_98; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113474.8] wire _T_99; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113475.8] wire [31:0] _T_100; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113476.8] wire [32:0] _T_101; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113477.8] wire [32:0] _T_102; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113478.8] wire [32:0] _T_103; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113479.8] wire _T_104; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113480.8] wire _T_105; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113481.8] wire _T_106; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113482.8] wire _T_107; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113483.8] wire _T_108; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113484.8] wire _T_115; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113491.8] wire _T_120; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113504.8] wire _T_121; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113505.8] wire _T_124; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113512.8] wire _T_125; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113513.8] wire _T_127; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113519.8] wire _T_128; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113520.8] wire _T_129; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@113525.8] wire _T_131; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113527.8] wire _T_132; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113528.8] wire [3:0] _T_133; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@113533.8] wire _T_134; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@113534.8] wire _T_136; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113536.8] wire _T_137; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113537.8] wire _T_138; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@113542.8] wire _T_140; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113544.8] wire _T_141; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113545.8] wire _T_142; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@113551.6] wire _T_207; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@113641.8] wire _T_209; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113643.8] wire _T_210; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113644.8] wire _T_220; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@113667.6] wire _T_222; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113670.8] wire _T_230; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113678.8] wire _T_232; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113680.8] wire _T_265; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113713.8] wire _T_266; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113714.8] wire _T_267; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113715.8] wire _T_268; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113716.8] wire _T_269; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113717.8] wire _T_270; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113718.8] wire _T_272; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113720.8] wire _T_274; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113722.8] wire _T_275; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113723.8] wire _T_282; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@113742.8] wire _T_284; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113744.8] wire _T_285; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113745.8] wire _T_286; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@113750.8] wire _T_288; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113752.8] wire _T_289; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113753.8] wire _T_294; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@113767.6] wire _T_332; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113806.8] wire _T_341; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113815.8] wire _T_349; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113823.8] wire _T_351; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113825.8] wire _T_353; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113827.8] wire _T_355; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113829.8] wire _T_356; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113830.8] wire _T_371; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@113866.6] wire [3:0] _T_444; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@113956.8] wire [3:0] _T_445; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@113957.8] wire _T_446; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@113958.8] wire _T_448; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113960.8] wire _T_449; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113961.8] wire _T_450; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@113967.6] wire _T_452; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113970.8] wire _T_484; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@114002.8] wire _T_501; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114019.8] wire _T_502; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114020.8] wire _T_509; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@114039.8] wire _T_511; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114041.8] wire _T_512; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114042.8] wire _T_517; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@114056.6] wire _T_576; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@114128.8] wire _T_578; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114130.8] wire _T_579; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114131.8] wire _T_584; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@114145.6] wire _T_635; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114197.8] wire _T_636; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114198.8] wire _T_651; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@114236.6] wire _T_653; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114238.6] wire _T_654; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114239.6] wire _T_656; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@114245.6] wire _T_658; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@114250.6] wire _T_660; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@114252.6] wire _T_662; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114255.8] wire _T_663; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114256.8] wire _T_664; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@114261.8] wire _T_666; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114263.8] wire _T_667; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114264.8] wire _T_668; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@114269.8] wire _T_670; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114271.8] wire _T_671; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114272.8] wire _T_672; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@114277.8] wire _T_674; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114279.8] wire _T_675; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114280.8] wire _T_676; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@114285.8] wire _T_678; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114287.8] wire _T_679; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114288.8] wire _T_680; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@114294.6] wire _T_691; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@114318.8] wire _T_693; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114320.8] wire _T_694; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114321.8] wire _T_695; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@114326.8] wire _T_697; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114328.8] wire _T_698; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114329.8] wire _T_708; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@114352.6] wire _T_728; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@114393.8] wire _T_730; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114395.8] wire _T_731; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114396.8] wire _T_737; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@114411.6] wire _T_754; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@114446.6] wire _T_772; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@114482.6] wire _T_801; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@114542.4] wire [9:0] _T_806; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@114547.4] wire _T_807; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@114548.4] wire _T_808; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@114549.4] reg [9:0] _T_810; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@114551.4] reg [31:0] _RAND_0; wire [9:0] _T_812; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114553.4] wire _T_813; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114554.4] reg [2:0] _T_821; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@114565.4] reg [31:0] _RAND_1; reg [2:0] _T_822; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@114566.4] reg [31:0] _RAND_2; reg [3:0] _T_823; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@114567.4] reg [31:0] _RAND_3; reg _T_824; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@114568.4] reg [31:0] _RAND_4; reg [31:0] _T_825; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@114569.4] reg [31:0] _RAND_5; wire _T_826; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@114570.4] wire _T_827; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@114571.4] wire _T_828; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@114573.6] wire _T_830; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114575.6] wire _T_831; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114576.6] wire _T_832; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@114581.6] wire _T_834; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114583.6] wire _T_835; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114584.6] wire _T_836; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@114589.6] wire _T_838; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114591.6] wire _T_839; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114592.6] wire _T_840; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@114597.6] wire _T_842; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114599.6] wire _T_843; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114600.6] wire _T_844; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@114605.6] wire _T_846; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114607.6] wire _T_847; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114608.6] wire _T_849; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@114615.4] wire _T_850; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@114623.4] wire [26:0] _T_852; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@114625.4] wire [11:0] _T_853; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@114626.4] wire [11:0] _T_854; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@114627.4] wire [9:0] _T_855; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@114628.4] wire _T_856; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@114629.4] reg [9:0] _T_858; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@114631.4] reg [31:0] _RAND_6; wire [9:0] _T_860; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114633.4] wire _T_861; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114634.4] reg [2:0] _T_869; // @[Monitor.scala 418:22:freechips.rocketchip.system.TinyConfig.fir@114645.4] reg [31:0] _RAND_7; reg [1:0] _T_870; // @[Monitor.scala 419:22:freechips.rocketchip.system.TinyConfig.fir@114646.4] reg [31:0] _RAND_8; reg [3:0] _T_871; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@114647.4] reg [31:0] _RAND_9; reg _T_872; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@114648.4] reg [31:0] _RAND_10; reg _T_873; // @[Monitor.scala 422:22:freechips.rocketchip.system.TinyConfig.fir@114649.4] reg [31:0] _RAND_11; reg _T_874; // @[Monitor.scala 423:22:freechips.rocketchip.system.TinyConfig.fir@114650.4] reg [31:0] _RAND_12; wire _T_875; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@114651.4] wire _T_876; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@114652.4] wire _T_877; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@114654.6] wire _T_879; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114656.6] wire _T_880; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114657.6] wire _T_881; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@114662.6] wire _T_883; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114664.6] wire _T_884; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114665.6] wire _T_885; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@114670.6] wire _T_887; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114672.6] wire _T_888; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114673.6] wire _T_889; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@114678.6] wire _T_891; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114680.6] wire _T_892; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114681.6] wire _T_893; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@114686.6] wire _T_895; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114688.6] wire _T_896; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114689.6] wire _T_897; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@114694.6] wire _T_899; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114696.6] wire _T_900; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114697.6] wire _T_902; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@114704.4] reg [1:0] _T_903; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@114713.4] reg [31:0] _RAND_13; reg [9:0] _T_913; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@114723.4] reg [31:0] _RAND_14; wire [9:0] _T_915; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114725.4] wire _T_916; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114726.4] reg [9:0] _T_932; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@114745.4] reg [31:0] _RAND_15; wire [9:0] _T_934; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114747.4] wire _T_935; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114748.4] wire _T_945; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@114763.4] wire [1:0] _T_947; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@114766.6] wire [1:0] _T_948; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@114768.6] wire _T_949; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@114769.6] wire _T_950; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@114770.6] wire _T_952; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114772.6] wire _T_953; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114773.6] wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@114765.4] wire _T_957; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@114784.4] wire _T_959; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@114786.4] wire _T_960; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@114787.4] wire [1:0] _T_961; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@114789.6] wire [1:0] _T_962; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@114791.6] wire [1:0] _T_963; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@114792.6] wire _T_964; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@114793.6] wire _T_966; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114795.6] wire _T_967; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114796.6] wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@114788.4] wire _T_968; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@114802.4] wire _T_969; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@114803.4] wire _T_970; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@114804.4] wire _T_971; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@114805.4] wire _T_973; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114807.4] wire _T_974; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114808.4] wire [1:0] _T_975; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@114813.4] wire [1:0] _T_976; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@114814.4] wire [1:0] _T_977; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@114815.4] reg [31:0] _T_978; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@114817.4] reg [31:0] _RAND_16; wire _T_979; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@114820.4] wire _T_980; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@114821.4] wire _T_981; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@114822.4] wire _T_982; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@114823.4] wire _T_983; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@114824.4] wire _T_984; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@114825.4] wire _T_986; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114827.4] wire _T_987; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114828.4] wire [31:0] _T_989; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@114834.4] wire _T_992; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@114838.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113493.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@113601.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113725.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113832.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@113931.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114022.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@114111.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114200.10] wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114258.10] wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@114300.10] wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@114358.10] wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@114417.10] wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@114452.10] wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@114488.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@114818.4] .out(plusarg_reader_out) ); assign _T_6 = io_in_a_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@113374.6] assign _T_8 = io_in_a_bits_source | _T_6; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@113379.6] assign _T_10 = 27'hfff << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@113381.6] assign _T_11 = _T_10[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@113382.6] assign _T_12 = ~ _T_11; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@113383.6] assign _GEN_18 = {{20'd0}, _T_12}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@113384.6] assign _T_13 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@113384.6] assign _T_14 = _T_13 == 32'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@113385.6] assign _T_16 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@113387.6] assign _T_17 = 2'h1 << _T_16; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@113388.6] assign _T_19 = _T_17 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@113390.6] assign _T_20 = io_in_a_bits_size >= 4'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@113391.6] assign _T_21 = _T_19[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@113392.6] assign _T_22 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@113393.6] assign _T_23 = _T_22 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@113394.6] assign _T_25 = _T_21 & _T_23; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113396.6] assign _T_26 = _T_20 | _T_25; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113397.6] assign _T_28 = _T_21 & _T_22; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113399.6] assign _T_29 = _T_20 | _T_28; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113400.6] assign _T_30 = _T_19[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@113401.6] assign _T_31 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@113402.6] assign _T_32 = _T_31 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@113403.6] assign _T_33 = _T_23 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113404.6] assign _T_34 = _T_30 & _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113405.6] assign _T_35 = _T_26 | _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113406.6] assign _T_36 = _T_23 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113407.6] assign _T_37 = _T_30 & _T_36; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113408.6] assign _T_38 = _T_26 | _T_37; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113409.6] assign _T_39 = _T_22 & _T_32; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113410.6] assign _T_40 = _T_30 & _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113411.6] assign _T_41 = _T_29 | _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113412.6] assign _T_42 = _T_22 & _T_31; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@113413.6] assign _T_43 = _T_30 & _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@113414.6] assign _T_44 = _T_29 | _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@113415.6] assign _T_47 = {_T_44,_T_41,_T_38,_T_35}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@113418.6] assign _T_51 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113422.6] assign _T_68 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@113443.6] assign _T_70 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113446.8] assign _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113447.8] assign _T_72 = $signed(_T_71) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113448.8] assign _T_73 = $signed(_T_72); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113449.8] assign _T_74 = $signed(_T_73) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113450.8] assign _T_75 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113451.8] assign _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113452.8] assign _T_77 = $signed(_T_76) & $signed(-33'sh4000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113453.8] assign _T_78 = $signed(_T_77); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113454.8] assign _T_79 = $signed(_T_78) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113455.8] assign _T_80 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113456.8] assign _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113457.8] assign _T_82 = $signed(_T_81) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113458.8] assign _T_83 = $signed(_T_82); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113459.8] assign _T_84 = $signed(_T_83) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113460.8] assign _T_87 = $signed(_T_51) & $signed(-33'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113463.8] assign _T_88 = $signed(_T_87); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113464.8] assign _T_89 = $signed(_T_88) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113465.8] assign _T_90 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113466.8] assign _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113467.8] assign _T_92 = $signed(_T_91) & $signed(-33'sh100); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113468.8] assign _T_93 = $signed(_T_92); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113469.8] assign _T_94 = $signed(_T_93) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113470.8] assign _T_95 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113471.8] assign _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113472.8] assign _T_97 = $signed(_T_96) & $signed(-33'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113473.8] assign _T_98 = $signed(_T_97); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113474.8] assign _T_99 = $signed(_T_98) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113475.8] assign _T_100 = io_in_a_bits_address ^ 32'h60000000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@113476.8] assign _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@113477.8] assign _T_102 = $signed(_T_101) & $signed(-33'sh20000000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113478.8] assign _T_103 = $signed(_T_102); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@113479.8] assign _T_104 = $signed(_T_103) == $signed(33'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@113480.8] assign _T_105 = _T_74 | _T_79; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113481.8] assign _T_106 = _T_105 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113482.8] assign _T_107 = _T_106 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113483.8] assign _T_108 = _T_107 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113484.8] assign _T_115 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113491.8] assign _T_120 = _T_8 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113504.8] assign _T_121 = _T_120 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113505.8] assign _T_124 = _T_20 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113512.8] assign _T_125 = _T_124 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113513.8] assign _T_127 = _T_14 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113519.8] assign _T_128 = _T_127 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113520.8] assign _T_129 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@113525.8] assign _T_131 = _T_129 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113527.8] assign _T_132 = _T_131 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113528.8] assign _T_133 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@113533.8] assign _T_134 = _T_133 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@113534.8] assign _T_136 = _T_134 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113536.8] assign _T_137 = _T_136 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113537.8] assign _T_138 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@113542.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113544.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113545.8] assign _T_142 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@113551.6] assign _T_207 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@113641.8] assign _T_209 = _T_207 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113643.8] assign _T_210 = _T_209 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113644.8] assign _T_220 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@113667.6] assign _T_222 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113670.8] assign _T_230 = _T_222 & _T_74; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113678.8] assign _T_232 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113680.8] assign _T_265 = _T_79 | _T_84; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113713.8] assign _T_266 = _T_265 | _T_89; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113714.8] assign _T_267 = _T_266 | _T_94; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113715.8] assign _T_268 = _T_267 | _T_99; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113716.8] assign _T_269 = _T_268 | _T_104; // @[Parameters.scala 181:42:freechips.rocketchip.system.TinyConfig.fir@113717.8] assign _T_270 = _T_232 & _T_269; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113718.8] assign _T_272 = _T_230 | _T_270; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113720.8] assign _T_274 = _T_272 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113722.8] assign _T_275 = _T_274 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113723.8] assign _T_282 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@113742.8] assign _T_284 = _T_282 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113744.8] assign _T_285 = _T_284 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113745.8] assign _T_286 = io_in_a_bits_mask == _T_47; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@113750.8] assign _T_288 = _T_286 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113752.8] assign _T_289 = _T_288 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113753.8] assign _T_294 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@113767.6] assign _T_332 = _T_232 & _T_267; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113806.8] assign _T_341 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113815.8] assign _T_349 = _T_341 & _T_104; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@113823.8] assign _T_351 = _T_230 | _T_332; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113825.8] assign _T_353 = _T_351 | _T_349; // @[Parameters.scala 182:30:freechips.rocketchip.system.TinyConfig.fir@113827.8] assign _T_355 = _T_353 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113829.8] assign _T_356 = _T_355 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113830.8] assign _T_371 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@113866.6] assign _T_444 = ~ _T_47; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@113956.8] assign _T_445 = io_in_a_bits_mask & _T_444; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@113957.8] assign _T_446 = _T_445 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@113958.8] assign _T_448 = _T_446 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113960.8] assign _T_449 = _T_448 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113961.8] assign _T_450 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@113967.6] assign _T_452 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@113970.8] assign _T_484 = _T_452 & _T_108; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@114002.8] assign _T_501 = _T_484 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114019.8] assign _T_502 = _T_501 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114020.8] assign _T_509 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@114039.8] assign _T_511 = _T_509 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114041.8] assign _T_512 = _T_511 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114042.8] assign _T_517 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@114056.6] assign _T_576 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@114128.8] assign _T_578 = _T_576 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114130.8] assign _T_579 = _T_578 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114131.8] assign _T_584 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@114145.6] assign _T_635 = _T_230 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114197.8] assign _T_636 = _T_635 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114198.8] assign _T_651 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 44:24:freechips.rocketchip.system.TinyConfig.fir@114236.6] assign _T_653 = _T_651 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114238.6] assign _T_654 = _T_653 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114239.6] assign _T_656 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 46:9:freechips.rocketchip.system.TinyConfig.fir@114245.6] assign _T_658 = io_in_d_bits_source | _T_656; // @[Parameters.scala 310:46:freechips.rocketchip.system.TinyConfig.fir@114250.6] assign _T_660 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.TinyConfig.fir@114252.6] assign _T_662 = _T_658 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114255.8] assign _T_663 = _T_662 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114256.8] assign _T_664 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.TinyConfig.fir@114261.8] assign _T_666 = _T_664 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114263.8] assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114264.8] assign _T_668 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.TinyConfig.fir@114269.8] assign _T_670 = _T_668 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114271.8] assign _T_671 = _T_670 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114272.8] assign _T_672 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.TinyConfig.fir@114277.8] assign _T_674 = _T_672 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114279.8] assign _T_675 = _T_674 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114280.8] assign _T_676 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.TinyConfig.fir@114285.8] assign _T_678 = _T_676 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114287.8] assign _T_679 = _T_678 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114288.8] assign _T_680 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.TinyConfig.fir@114294.6] assign _T_691 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 104:26:freechips.rocketchip.system.TinyConfig.fir@114318.8] assign _T_693 = _T_691 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114320.8] assign _T_694 = _T_693 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114321.8] assign _T_695 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.TinyConfig.fir@114326.8] assign _T_697 = _T_695 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114328.8] assign _T_698 = _T_697 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114329.8] assign _T_708 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.TinyConfig.fir@114352.6] assign _T_728 = _T_676 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.TinyConfig.fir@114393.8] assign _T_730 = _T_728 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114395.8] assign _T_731 = _T_730 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114396.8] assign _T_737 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.TinyConfig.fir@114411.6] assign _T_754 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.TinyConfig.fir@114446.6] assign _T_772 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.TinyConfig.fir@114482.6] assign _T_801 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@114542.4] assign _T_806 = _T_12[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@114547.4] assign _T_807 = io_in_a_bits_opcode[2]; // @[Edges.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@114548.4] assign _T_808 = _T_807 == 1'h0; // @[Edges.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@114549.4] assign _T_812 = _T_810 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114553.4] assign _T_813 = _T_810 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114554.4] assign _T_826 = _T_813 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@114570.4] assign _T_827 = io_in_a_valid & _T_826; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@114571.4] assign _T_828 = io_in_a_bits_opcode == _T_821; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@114573.6] assign _T_830 = _T_828 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114575.6] assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114576.6] assign _T_832 = io_in_a_bits_param == _T_822; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@114581.6] assign _T_834 = _T_832 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114583.6] assign _T_835 = _T_834 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114584.6] assign _T_836 = io_in_a_bits_size == _T_823; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@114589.6] assign _T_838 = _T_836 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114591.6] assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114592.6] assign _T_840 = io_in_a_bits_source == _T_824; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@114597.6] assign _T_842 = _T_840 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114599.6] assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114600.6] assign _T_844 = io_in_a_bits_address == _T_825; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@114605.6] assign _T_846 = _T_844 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114607.6] assign _T_847 = _T_846 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114608.6] assign _T_849 = _T_801 & _T_813; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@114615.4] assign _T_850 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@114623.4] assign _T_852 = 27'hfff << io_in_d_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@114625.4] assign _T_853 = _T_852[11:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@114626.4] assign _T_854 = ~ _T_853; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@114627.4] assign _T_855 = _T_854[11:2]; // @[Edges.scala 221:59:freechips.rocketchip.system.TinyConfig.fir@114628.4] assign _T_856 = io_in_d_bits_opcode[0]; // @[Edges.scala 107:36:freechips.rocketchip.system.TinyConfig.fir@114629.4] assign _T_860 = _T_858 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114633.4] assign _T_861 = _T_858 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114634.4] assign _T_875 = _T_861 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@114651.4] assign _T_876 = io_in_d_valid & _T_875; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@114652.4] assign _T_877 = io_in_d_bits_opcode == _T_869; // @[Monitor.scala 425:29:freechips.rocketchip.system.TinyConfig.fir@114654.6] assign _T_879 = _T_877 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114656.6] assign _T_880 = _T_879 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114657.6] assign _T_881 = io_in_d_bits_param == _T_870; // @[Monitor.scala 426:29:freechips.rocketchip.system.TinyConfig.fir@114662.6] assign _T_883 = _T_881 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114664.6] assign _T_884 = _T_883 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114665.6] assign _T_885 = io_in_d_bits_size == _T_871; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@114670.6] assign _T_887 = _T_885 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114672.6] assign _T_888 = _T_887 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114673.6] assign _T_889 = io_in_d_bits_source == _T_872; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@114678.6] assign _T_891 = _T_889 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114680.6] assign _T_892 = _T_891 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114681.6] assign _T_893 = io_in_d_bits_sink == _T_873; // @[Monitor.scala 429:29:freechips.rocketchip.system.TinyConfig.fir@114686.6] assign _T_895 = _T_893 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114688.6] assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114689.6] assign _T_897 = io_in_d_bits_denied == _T_874; // @[Monitor.scala 430:29:freechips.rocketchip.system.TinyConfig.fir@114694.6] assign _T_899 = _T_897 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114696.6] assign _T_900 = _T_899 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114697.6] assign _T_902 = _T_850 & _T_861; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@114704.4] assign _T_915 = _T_913 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114725.4] assign _T_916 = _T_913 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114726.4] assign _T_934 = _T_932 - 10'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@114747.4] assign _T_935 = _T_932 == 10'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@114748.4] assign _T_945 = _T_801 & _T_916; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@114763.4] assign _T_947 = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@114766.6] assign _T_948 = _T_903 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@114768.6] assign _T_949 = _T_948[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@114769.6] assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@114770.6] assign _T_952 = _T_950 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114772.6] assign _T_953 = _T_952 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114773.6] assign _GEN_15 = _T_945 ? _T_947 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@114765.4] assign _T_957 = _T_850 & _T_935; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@114784.4] assign _T_959 = _T_660 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.TinyConfig.fir@114786.4] assign _T_960 = _T_957 & _T_959; // @[Monitor.scala 465:72:freechips.rocketchip.system.TinyConfig.fir@114787.4] assign _T_961 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@114789.6] assign _T_962 = _GEN_15 | _T_903; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@114791.6] assign _T_963 = _T_962 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@114792.6] assign _T_964 = _T_963[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@114793.6] assign _T_966 = _T_964 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114795.6] assign _T_967 = _T_966 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114796.6] assign _GEN_16 = _T_960 ? _T_961 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@114788.4] assign _T_968 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.TinyConfig.fir@114802.4] assign _T_969 = _GEN_15 != 2'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.TinyConfig.fir@114803.4] assign _T_970 = _T_969 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.TinyConfig.fir@114804.4] assign _T_971 = _T_968 | _T_970; // @[Monitor.scala 471:30:freechips.rocketchip.system.TinyConfig.fir@114805.4] assign _T_973 = _T_971 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114807.4] assign _T_974 = _T_973 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114808.4] assign _T_975 = _T_903 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@114813.4] assign _T_976 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@114814.4] assign _T_977 = _T_975 & _T_976; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@114815.4] assign _T_979 = _T_903 != 2'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@114820.4] assign _T_980 = _T_979 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@114821.4] assign _T_981 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@114822.4] assign _T_982 = _T_980 | _T_981; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@114823.4] assign _T_983 = _T_978 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@114824.4] assign _T_984 = _T_982 | _T_983; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@114825.4] assign _T_986 = _T_984 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114827.4] assign _T_987 = _T_986 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114828.4] assign _T_989 = _T_978 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@114834.4] assign _T_992 = _T_801 | _T_850; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@114838.4] assign _GEN_19 = io_in_a_valid & _T_68; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113493.10] assign _GEN_35 = io_in_a_valid & _T_142; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@113601.10] assign _GEN_53 = io_in_a_valid & _T_220; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113725.10] assign _GEN_65 = io_in_a_valid & _T_294; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113832.10] assign _GEN_75 = io_in_a_valid & _T_371; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@113931.10] assign _GEN_85 = io_in_a_valid & _T_450; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114022.10] assign _GEN_95 = io_in_a_valid & _T_517; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@114111.10] assign _GEN_105 = io_in_a_valid & _T_584; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114200.10] assign _GEN_115 = io_in_d_valid & _T_660; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114258.10] assign _GEN_125 = io_in_d_valid & _T_680; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@114300.10] assign _GEN_137 = io_in_d_valid & _T_708; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@114358.10] assign _GEN_149 = io_in_d_valid & _T_737; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@114417.10] assign _GEN_155 = io_in_d_valid & _T_754; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@114452.10] assign _GEN_161 = io_in_d_valid & _T_772; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@114488.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_810 = _RAND_0[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_821 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_822 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_823 = _RAND_3[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_824 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_825 = _RAND_5[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_858 = _RAND_6[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_869 = _RAND_7[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_870 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_871 = _RAND_9[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_872 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_873 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_874 = _RAND_12[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_903 = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_913 = _RAND_14[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_932 = _RAND_15[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_978 = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_810 <= 10'h0; end else begin if (_T_801) begin if (_T_813) begin if (_T_808) begin _T_810 <= _T_806; end else begin _T_810 <= 10'h0; end end else begin _T_810 <= _T_812; end end end if (_T_849) begin _T_821 <= io_in_a_bits_opcode; end if (_T_849) begin _T_822 <= io_in_a_bits_param; end if (_T_849) begin _T_823 <= io_in_a_bits_size; end if (_T_849) begin _T_824 <= io_in_a_bits_source; end if (_T_849) begin _T_825 <= io_in_a_bits_address; end if (reset) begin _T_858 <= 10'h0; end else begin if (_T_850) begin if (_T_861) begin if (_T_856) begin _T_858 <= _T_855; end else begin _T_858 <= 10'h0; end end else begin _T_858 <= _T_860; end end end if (_T_902) begin _T_869 <= io_in_d_bits_opcode; end if (_T_902) begin _T_870 <= io_in_d_bits_param; end if (_T_902) begin _T_871 <= io_in_d_bits_size; end if (_T_902) begin _T_872 <= io_in_d_bits_source; end if (_T_902) begin _T_873 <= io_in_d_bits_sink; end if (_T_902) begin _T_874 <= io_in_d_bits_denied; end if (reset) begin _T_903 <= 2'h0; end else begin _T_903 <= _T_977; end if (reset) begin _T_913 <= 10'h0; end else begin if (_T_801) begin if (_T_916) begin if (_T_808) begin _T_913 <= _T_806; end else begin _T_913 <= 10'h0; end end else begin _T_913 <= _T_915; end end end if (reset) begin _T_932 <= 10'h0; end else begin if (_T_850) begin if (_T_935) begin if (_T_856) begin _T_932 <= _T_855; end else begin _T_932 <= 10'h0; end end else begin _T_932 <= _T_934; end end end if (reset) begin _T_978 <= 32'h0; end else begin if (_T_992) begin _T_978 <= 32'h0; end else begin _T_978 <= _T_989; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113493.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@113494.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@113500.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_115) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@113501.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113507.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_121) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@113508.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113515.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_125) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@113516.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113522.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_128) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@113523.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113530.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_132) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@113531.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113539.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_137) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@113540.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113547.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_141) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@113548.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@113601.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@113602.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@113608.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_115) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@113609.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@113615.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_121) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@113616.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_125) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@113623.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_125) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@113624.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@113630.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_128) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@113631.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_132) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@113638.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_132) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@113639.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_210) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113646.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_210) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@113647.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_137) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@113655.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_137) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@113656.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@113663.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@113664.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_275) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113725.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_275) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@113726.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@113732.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_121) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@113733.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@113739.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_128) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@113740.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113747.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_285) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@113748.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113755.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_289) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@113756.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@113763.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_141) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@113764.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113832.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_356) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@113833.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@113839.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_121) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@113840.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@113846.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_128) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@113847.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@113854.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_285) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@113855.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@113862.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_289) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@113863.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_356) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@113931.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_356) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@113932.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@113938.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_121) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@113939.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@113945.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_128) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@113946.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@113953.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_285) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@113954.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_449) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113963.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_449) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@113964.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114022.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_502) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@114023.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@114029.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_121) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@114030.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@114036.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_128) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@114037.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_512) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114044.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_512) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@114045.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@114052.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_289) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@114053.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_502) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@114111.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_502) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@114112.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@114118.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_121) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@114119.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@114125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_128) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@114126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_579) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_579) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@114134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@114141.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_289) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@114142.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_636) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114200.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_636) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@114201.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_121) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@114207.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_121) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@114208.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_128) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@114214.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_128) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@114215.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_289) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@114222.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_289) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@114223.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@114230.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_141) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@114231.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_654) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114241.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_654) begin $fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.TinyConfig.fir@114242.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114258.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_663) begin $fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@114259.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114266.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_667) begin $fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.TinyConfig.fir@114267.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114274.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_671) begin $fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.TinyConfig.fir@114275.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114282.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_675) begin $fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.TinyConfig.fir@114283.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_115 & _T_679) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_115 & _T_679) begin $fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.TinyConfig.fir@114291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@114300.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_663) begin $fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.TinyConfig.fir@114301.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@114307.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_115) begin $fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.TinyConfig.fir@114308.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@114315.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_667) begin $fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.TinyConfig.fir@114316.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114323.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_694) begin $fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.TinyConfig.fir@114324.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114331.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_698) begin $fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.TinyConfig.fir@114332.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_125 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@114339.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_125 & _T_675) begin $fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.TinyConfig.fir@114340.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@114358.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_663) begin $fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.TinyConfig.fir@114359.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_115) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@114365.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_115) begin $fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.TinyConfig.fir@114366.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_667) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@114373.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_667) begin $fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.TinyConfig.fir@114374.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_694) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@114381.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_694) begin $fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.TinyConfig.fir@114382.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_698) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@114389.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_698) begin $fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.TinyConfig.fir@114390.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_137 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114398.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_137 & _T_731) begin $fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.TinyConfig.fir@114399.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@114417.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_663) begin $fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.TinyConfig.fir@114418.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@114425.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_671) begin $fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.TinyConfig.fir@114426.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_149 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@114433.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_149 & _T_675) begin $fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.TinyConfig.fir@114434.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@114452.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_663) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@114453.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@114460.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_671) begin $fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.TinyConfig.fir@114461.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_155 & _T_731) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@114469.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_155 & _T_731) begin $fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.TinyConfig.fir@114470.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_663) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@114488.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_663) begin $fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.TinyConfig.fir@114489.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_671) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@114496.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_671) begin $fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.TinyConfig.fir@114497.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_161 & _T_675) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@114504.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_161 & _T_675) begin $fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.TinyConfig.fir@114505.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_831) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114578.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_831) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@114579.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_835) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114586.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_835) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@114587.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_839) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114594.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_839) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@114595.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_843) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114602.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_843) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@114603.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_827 & _T_847) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114610.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_827 & _T_847) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@114611.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_880) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114659.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_880) begin $fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.TinyConfig.fir@114660.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_884) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114667.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_884) begin $fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.TinyConfig.fir@114668.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_888) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114675.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_888) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@114676.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_892) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114683.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_892) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@114684.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_896) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114691.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_896) begin $fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.TinyConfig.fir@114692.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_876 & _T_900) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114699.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_876 & _T_900) begin $fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.TinyConfig.fir@114700.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_945 & _T_953) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114775.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_945 & _T_953) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@114776.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_960 & _T_967) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114798.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_960 & _T_967) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@114799.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_974) begin $fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114810.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_974) begin $fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.TinyConfig.fir@114811.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_987) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114830.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_987) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@114831.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_38( // @[:freechips.rocketchip.system.TinyConfig.fir@114843.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@114844.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@114845.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@114846.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_1; wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_3; wire _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_4; wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_address__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_5; wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@114849.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@114850.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@114851.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@114852.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@114853.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@114854.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@114855.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114856.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114859.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114874.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114880.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@114883.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_address__T_18_addr = value_1; assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_address__T_10_data = io_enq_bits_address; assign _T_address__T_10_addr = value; assign _T_address__T_10_mask = 1'h1; assign _T_address__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_18_addr = value_1; assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = value; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@114852.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@114853.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@114854.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@114855.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114856.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114859.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114874.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114880.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@114883.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@114890.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@114888.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114899.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114898.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114897.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114896.4] assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114895.4] assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114894.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114893.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114892.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_address[initvar] = _RAND_4[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_mask[initvar] = _RAND_5[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_address__T_10_en & _T_address__T_10_mask) begin _T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114848.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_39( // @[:freechips.rocketchip.system.TinyConfig.fir@114907.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@114908.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@114909.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input [1:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_enq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_enq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output io_deq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output io_deq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@114910.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_1; wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_2; wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_3; wire _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg _T_sink [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_4; wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg _T_denied [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_5; wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@114913.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@114914.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@114915.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@114916.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@114917.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@114918.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@114919.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114920.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114923.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114938.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114944.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@114947.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_sink__T_18_addr = value_1; assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_sink__T_10_data = io_enq_bits_sink; assign _T_sink__T_10_addr = value; assign _T_sink__T_10_mask = 1'h1; assign _T_sink__T_10_en = io_enq_ready & io_enq_valid; assign _T_denied__T_18_addr = value_1; assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_denied__T_10_data = io_enq_bits_denied; assign _T_denied__T_10_addr = value; assign _T_denied__T_10_mask = 1'h1; assign _T_denied__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] assign _T_corrupt__T_10_data = io_enq_bits_corrupt; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@114916.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@114917.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@114918.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@114919.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114920.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@114923.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114938.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@114944.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@114947.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@114954.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@114952.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114963.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114962.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114961.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114960.4] assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114959.4] assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114958.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114957.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@114956.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_sink[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_denied[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_sink__T_10_en & _T_sink__T_10_mask) begin _T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_denied__T_10_en & _T_denied__T_10_mask) begin _T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@114912.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module TLBuffer_10( // @[:freechips.rocketchip.system.TinyConfig.fir@114971.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@114972.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@114973.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@114974.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] TLMonitor_37 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@114981.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode), .io_in_d_bits_param(TLMonitor_io_in_d_bits_param), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source), .io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink), .io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied), .io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt) ); Queue_38 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115034.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_data(Queue_io_enq_bits_data), .io_enq_bits_corrupt(Queue_io_enq_bits_corrupt), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_data(Queue_io_deq_bits_data), .io_deq_bits_corrupt(Queue_io_deq_bits_corrupt) ); Queue_39 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115048.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_param(Queue_1_io_enq_bits_param), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_sink(Queue_1_io_enq_bits_sink), .io_enq_bits_denied(Queue_1_io_enq_bits_denied), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115033.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115032.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@114983.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@114984.4] assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@115029.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@115035.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@115036.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@115037.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115045.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115044.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115043.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115042.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115041.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115040.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115039.4] assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115038.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@115047.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@115049.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@115050.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@115051.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115059.4] assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115058.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115057.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115056.4] assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115055.4] assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115054.4] assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115053.4] assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115052.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@115061.4] endmodule module Queue_40( // @[:freechips.rocketchip.system.TinyConfig.fir@115081.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115082.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@115083.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [3:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] output [31:0] io_deq_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@115084.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_1; wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_2; wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_3; wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_4; wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_address__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_5; wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@115087.4] reg [31:0] _RAND_7; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@115088.4] reg [31:0] _RAND_8; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@115089.4] reg [31:0] _RAND_9; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@115090.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@115091.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@115092.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@115093.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115094.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115097.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115112.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115118.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@115121.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_param__T_10_data = io_enq_bits_param; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_address__T_18_addr = value_1; assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_address__T_10_data = io_enq_bits_address; assign _T_address__T_10_addr = value; assign _T_address__T_10_mask = 1'h1; assign _T_address__T_10_en = io_enq_ready & io_enq_valid; assign _T_mask__T_18_addr = value_1; assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_mask__T_10_data = io_enq_bits_mask; assign _T_mask__T_10_addr = value; assign _T_mask__T_10_mask = 1'h1; assign _T_mask__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@115090.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@115091.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@115092.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@115093.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115094.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115097.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115112.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115118.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@115121.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@115128.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@115126.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115137.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115136.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115135.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115134.4] assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115133.4] assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115132.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115131.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[4:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_address[initvar] = _RAND_4[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_mask[initvar] = _RAND_5[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; value = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value_1 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_address__T_10_en & _T_address__T_10_mask) begin _T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_mask__T_10_en & _T_mask__T_10_mask) begin _T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115086.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_41( // @[:freechips.rocketchip.system.TinyConfig.fir@115145.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115146.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@115147.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output io_deq_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output io_deq_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] output io_deq_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@115148.4] ); reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_0; wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_1; wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_param__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_2; wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_3; wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_source__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg _T_sink [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_4; wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg _T_denied [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_5; wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_6; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg [31:0] _RAND_7; wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@115151.4] reg [31:0] _RAND_8; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@115152.4] reg [31:0] _RAND_9; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@115153.4] reg [31:0] _RAND_10; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@115154.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@115155.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@115156.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@115157.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115158.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115161.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115176.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115182.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@115185.4] assign _T_opcode__T_18_addr = value_1; assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_opcode__T_10_data = io_enq_bits_opcode; assign _T_opcode__T_10_addr = value; assign _T_opcode__T_10_mask = 1'h1; assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid; assign _T_param__T_18_addr = value_1; assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_param__T_10_data = 2'h0; assign _T_param__T_10_addr = value; assign _T_param__T_10_mask = 1'h1; assign _T_param__T_10_en = io_enq_ready & io_enq_valid; assign _T_size__T_18_addr = value_1; assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = value; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = io_enq_ready & io_enq_valid; assign _T_source__T_18_addr = value_1; assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_source__T_10_data = io_enq_bits_source; assign _T_source__T_10_addr = value; assign _T_source__T_10_mask = 1'h1; assign _T_source__T_10_en = io_enq_ready & io_enq_valid; assign _T_sink__T_18_addr = value_1; assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_sink__T_10_data = 1'h0; assign _T_sink__T_10_addr = value; assign _T_sink__T_10_mask = 1'h1; assign _T_sink__T_10_en = io_enq_ready & io_enq_valid; assign _T_denied__T_18_addr = value_1; assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_denied__T_10_data = 1'h0; assign _T_denied__T_10_addr = value; assign _T_denied__T_10_mask = 1'h1; assign _T_denied__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_corrupt__T_18_addr = value_1; assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] assign _T_corrupt__T_10_data = 1'h0; assign _T_corrupt__T_10_addr = value; assign _T_corrupt__T_10_mask = 1'h1; assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@115154.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@115155.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@115156.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@115157.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115158.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@115161.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115176.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@115182.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@115185.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@115192.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@115190.4] assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115201.4] assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115200.4] assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115199.4] assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115198.4] assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115197.4] assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115196.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115195.4] assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@115194.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_opcode[initvar] = _RAND_0[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_param[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_size[initvar] = _RAND_2[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_source[initvar] = _RAND_3[4:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_sink[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_5 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_denied[initvar] = _RAND_5[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_6 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_6[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_7 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_corrupt[initvar] = _RAND_7[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; value = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; value_1 = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_1 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin _T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_param__T_10_en & _T_param__T_10_mask) begin _T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_source__T_10_en & _T_source__T_10_mask) begin _T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_sink__T_10_en & _T_sink__T_10_mask) begin _T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_denied__T_10_en & _T_denied__T_10_mask) begin _T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin _T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@115150.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module TLBuffer_11( // @[:freechips.rocketchip.system.TinyConfig.fir@115209.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115210.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@115211.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input auto_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] output auto_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input auto_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] input [31:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@115212.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [4:0] Queue_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [3:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [4:0] Queue_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [3:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [4:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [4:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] Queue_40 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115223.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_opcode(Queue_io_enq_bits_opcode), .io_enq_bits_param(Queue_io_enq_bits_param), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_source(Queue_io_enq_bits_source), .io_enq_bits_address(Queue_io_enq_bits_address), .io_enq_bits_mask(Queue_io_enq_bits_mask), .io_enq_bits_data(Queue_io_enq_bits_data), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_opcode(Queue_io_deq_bits_opcode), .io_deq_bits_param(Queue_io_deq_bits_param), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_source(Queue_io_deq_bits_source), .io_deq_bits_address(Queue_io_deq_bits_address), .io_deq_bits_mask(Queue_io_deq_bits_mask), .io_deq_bits_data(Queue_io_deq_bits_data) ); Queue_41 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@115237.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_opcode(Queue_1_io_enq_bits_opcode), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_source(Queue_1_io_enq_bits_source), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_opcode(Queue_1_io_deq_bits_opcode), .io_deq_bits_param(Queue_1_io_deq_bits_param), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_source(Queue_1_io_deq_bits_source), .io_deq_bits_sink(Queue_1_io_deq_bits_sink), .io_deq_bits_denied(Queue_1_io_deq_bits_denied), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt) ); assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@115222.4] assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115221.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@115224.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@115225.4] assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@115226.4] assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115234.4] assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115233.4] assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115232.4] assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115231.4] assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115230.4] assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115229.4] assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115228.4] assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.TinyConfig.fir@115236.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@115238.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@115239.4] assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@115240.4] assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115248.4] assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115246.4] assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115245.4] assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@115242.4] assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.TinyConfig.fir@115250.4] endmodule module SynchronizerShiftReg_w1_d3( // @[:freechips.rocketchip.system.TinyConfig.fir@115270.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115271.4] input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4] output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4] ); reg sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115278.4] reg [31:0] _RAND_0; reg sync_1; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115279.4] reg [31:0] _RAND_1; reg sync_2; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115280.4] reg [31:0] _RAND_2; assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@115284.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; sync_0 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; sync_1 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; sync_2 = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin sync_0 <= sync_1; sync_1 <= sync_2; sync_2 <= io_d; end endmodule module IntSyncCrossingSink( // @[:freechips.rocketchip.system.TinyConfig.fir@115286.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115287.4] input auto_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115289.4] output auto_out_0 // @[:freechips.rocketchip.system.TinyConfig.fir@115289.4] ); wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@115300.4] wire SynchronizerShiftReg_w1_d3_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@115300.4] wire SynchronizerShiftReg_w1_d3_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@115300.4] SynchronizerShiftReg_w1_d3 SynchronizerShiftReg_w1_d3 ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@115300.4] .clock(SynchronizerShiftReg_w1_d3_clock), .io_d(SynchronizerShiftReg_w1_d3_io_d), .io_q(SynchronizerShiftReg_w1_d3_io_q) ); assign auto_out_0 = SynchronizerShiftReg_w1_d3_io_q; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115298.4] assign SynchronizerShiftReg_w1_d3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@115302.4] assign SynchronizerShiftReg_w1_d3_io_d = auto_in_sync_0; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@115304.4] endmodule module IntSyncCrossingSink_1( // @[:freechips.rocketchip.system.TinyConfig.fir@115314.2] input auto_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4] input auto_in_sync_1, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4] output auto_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4] output auto_out_1 // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4] ); assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115326.4] assign auto_out_1 = auto_in_sync_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115326.4] endmodule module IntSyncCrossingSink_2( // @[:freechips.rocketchip.system.TinyConfig.fir@115330.2] input auto_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115333.4] output auto_out_0 // @[:freechips.rocketchip.system.TinyConfig.fir@115333.4] ); assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115342.4] endmodule module HellaCacheArbiter( // @[:freechips.rocketchip.system.TinyConfig.fir@115355.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115356.4] output io_requestor_0_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_requestor_0_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_requestor_0_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [6:0] io_requestor_0_req_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [4:0] io_requestor_0_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [1:0] io_requestor_0_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_requestor_0_req_bits_signed, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_requestor_0_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_requestor_0_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [6:0] io_requestor_0_resp_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [31:0] io_requestor_0_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_resp_bits_has_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [31:0] io_requestor_0_resp_bits_data_word_bypass, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_replay_next, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_ma_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_ma_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_pf_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_pf_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_ae_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_s2_xcpt_ae_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_ordered, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_0_perf_grant, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_1_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_requestor_1_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_requestor_1_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [4:0] io_requestor_1_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [1:0] io_requestor_1_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_requestor_1_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_requestor_1_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [3:0] io_requestor_1_s1_data_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_1_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_requestor_1_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [31:0] io_requestor_1_resp_bits_data_raw, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_mem_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [31:0] io_mem_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [6:0] io_mem_req_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [4:0] io_mem_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [1:0] io_mem_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_mem_req_bits_signed, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_mem_req_bits_phys, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output io_mem_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [31:0] io_mem_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] output [3:0] io_mem_s1_data_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [6:0] io_mem_resp_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_mem_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_resp_bits_has_data, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_mem_resp_bits_data_word_bypass, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input [31:0] io_mem_resp_bits_data_raw, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_replay_next, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_ma_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_ma_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_pf_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_pf_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_ae_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_s2_xcpt_ae_st, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_ordered, // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] input io_mem_perf_grant // @[:freechips.rocketchip.system.TinyConfig.fir@115358.4] ); reg _T; // @[HellaCacheArbiter.scala 19:20:freechips.rocketchip.system.TinyConfig.fir@115363.4] reg [31:0] _RAND_0; reg _T_1; // @[HellaCacheArbiter.scala 20:20:freechips.rocketchip.system.TinyConfig.fir@115364.4] reg [31:0] _RAND_1; wire _T_4; // @[HellaCacheArbiter.scala 27:67:freechips.rocketchip.system.TinyConfig.fir@115371.4] wire [7:0] _T_7; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@115383.6] wire [7:0] _GEN_1; // @[HellaCacheArbiter.scala 49:26:freechips.rocketchip.system.TinyConfig.fir@115381.4] wire _T_8; // @[HellaCacheArbiter.scala 50:21:freechips.rocketchip.system.TinyConfig.fir@115387.4] wire _T_9; // @[HellaCacheArbiter.scala 51:21:freechips.rocketchip.system.TinyConfig.fir@115392.4] wire _T_10; // @[HellaCacheArbiter.scala 59:41:freechips.rocketchip.system.TinyConfig.fir@115396.4] wire _T_11; // @[HellaCacheArbiter.scala 59:57:freechips.rocketchip.system.TinyConfig.fir@115397.4] wire [5:0] _T_15; // @[HellaCacheArbiter.scala 70:45:freechips.rocketchip.system.TinyConfig.fir@115411.4] assign _T_4 = io_requestor_0_req_valid == 1'h0; // @[HellaCacheArbiter.scala 27:67:freechips.rocketchip.system.TinyConfig.fir@115371.4] assign _T_7 = {io_requestor_0_req_bits_tag,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@115383.6] assign _GEN_1 = io_requestor_0_req_valid ? _T_7 : 8'h1; // @[HellaCacheArbiter.scala 49:26:freechips.rocketchip.system.TinyConfig.fir@115381.4] assign _T_8 = _T == 1'h0; // @[HellaCacheArbiter.scala 50:21:freechips.rocketchip.system.TinyConfig.fir@115387.4] assign _T_9 = _T_1 == 1'h0; // @[HellaCacheArbiter.scala 51:21:freechips.rocketchip.system.TinyConfig.fir@115392.4] assign _T_10 = io_mem_resp_bits_tag[0]; // @[HellaCacheArbiter.scala 59:41:freechips.rocketchip.system.TinyConfig.fir@115396.4] assign _T_11 = _T_10 == 1'h0; // @[HellaCacheArbiter.scala 59:57:freechips.rocketchip.system.TinyConfig.fir@115397.4] assign _T_15 = io_mem_resp_bits_tag[6:1]; // @[HellaCacheArbiter.scala 70:45:freechips.rocketchip.system.TinyConfig.fir@115411.4] assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 25:31:freechips.rocketchip.system.TinyConfig.fir@115370.4] assign io_requestor_0_s2_nack = io_mem_s2_nack & _T_9; // @[HellaCacheArbiter.scala 64:31:freechips.rocketchip.system.TinyConfig.fir@115405.4] assign io_requestor_0_resp_valid = io_mem_resp_valid & _T_11; // @[HellaCacheArbiter.scala 60:18:freechips.rocketchip.system.TinyConfig.fir@115399.4] assign io_requestor_0_resp_bits_tag = {{1'd0}, _T_15}; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115410.4 HellaCacheArbiter.scala 70:21:freechips.rocketchip.system.TinyConfig.fir@115412.4] assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115410.4] assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115410.4] assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115410.4] assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115410.4] assign io_requestor_0_replay_next = io_mem_replay_next; // @[HellaCacheArbiter.scala 72:35:freechips.rocketchip.system.TinyConfig.fir@115413.4] assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala 61:31:freechips.rocketchip.system.TinyConfig.fir@115400.4] assign io_requestor_0_ordered = io_mem_ordered; // @[HellaCacheArbiter.scala 62:31:freechips.rocketchip.system.TinyConfig.fir@115401.4] assign io_requestor_0_perf_grant = io_mem_perf_grant; // @[HellaCacheArbiter.scala 63:28:freechips.rocketchip.system.TinyConfig.fir@115402.4] assign io_requestor_1_req_ready = io_requestor_0_req_ready & _T_4; // @[HellaCacheArbiter.scala 27:33:freechips.rocketchip.system.TinyConfig.fir@115373.4] assign io_requestor_1_s2_nack = io_mem_s2_nack & _T_1; // @[HellaCacheArbiter.scala 64:31:freechips.rocketchip.system.TinyConfig.fir@115423.4] assign io_requestor_1_resp_valid = io_mem_resp_valid & _T_10; // @[HellaCacheArbiter.scala 60:18:freechips.rocketchip.system.TinyConfig.fir@115417.4] assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala 69:17:freechips.rocketchip.system.TinyConfig.fir@115428.4] assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid; // @[HellaCacheArbiter.scala 24:22:freechips.rocketchip.system.TinyConfig.fir@115369.4] assign io_mem_req_bits_addr = io_requestor_0_req_valid ? io_requestor_0_req_bits_addr : io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6] assign io_mem_req_bits_tag = _GEN_1[6:0]; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 33:29:freechips.rocketchip.system.TinyConfig.fir@115376.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6 HellaCacheArbiter.scala 33:29:freechips.rocketchip.system.TinyConfig.fir@115384.6] assign io_mem_req_bits_cmd = io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6] assign io_mem_req_bits_size = io_requestor_0_req_valid ? io_requestor_0_req_bits_size : io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6] assign io_mem_req_bits_signed = io_requestor_0_req_valid ? io_requestor_0_req_bits_signed : 1'h0; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6] assign io_mem_req_bits_phys = io_requestor_0_req_valid ? 1'h0 : 1'h1; // @[HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115374.4 HellaCacheArbiter.scala 32:25:freechips.rocketchip.system.TinyConfig.fir@115382.6] assign io_mem_s1_kill = _T_8 ? io_requestor_0_s1_kill : io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala 37:24:freechips.rocketchip.system.TinyConfig.fir@115378.4 HellaCacheArbiter.scala 37:24:freechips.rocketchip.system.TinyConfig.fir@115389.6] assign io_mem_s1_data_data = _T_8 ? io_requestor_0_s1_data_data : io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala 38:24:freechips.rocketchip.system.TinyConfig.fir@115379.4 HellaCacheArbiter.scala 38:24:freechips.rocketchip.system.TinyConfig.fir@115390.6] assign io_mem_s1_data_mask = _T_8 ? 4'h0 : io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala 38:24:freechips.rocketchip.system.TinyConfig.fir@115379.4 HellaCacheArbiter.scala 38:24:freechips.rocketchip.system.TinyConfig.fir@115390.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_1 = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (io_requestor_0_req_valid) begin _T <= 1'h0; end else begin _T <= 1'h1; end _T_1 <= _T; end endmodule module PTW( // @[:freechips.rocketchip.system.TinyConfig.fir@115493.2] output io_requestor_0_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_0_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_0_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_0_pmp_7_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output io_requestor_1_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [29:0] io_requestor_1_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] output [31:0] io_requestor_1_pmp_7_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [1:0] io_dpath_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input io_dpath_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [29:0] io_dpath_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] input [31:0] io_dpath_pmp_7_mask // @[:freechips.rocketchip.system.TinyConfig.fir@115496.4] ); assign io_requestor_0_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_0_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116344.4] assign io_requestor_1_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] assign io_requestor_1_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 277:25:freechips.rocketchip.system.TinyConfig.fir@116356.4] endmodule module RVCExpander( // @[:freechips.rocketchip.system.TinyConfig.fir@116562.2] input [31:0] io_in, // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] output [31:0] io_out_bits, // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] output [4:0] io_out_rd, // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] output [4:0] io_out_rs1, // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] output [4:0] io_out_rs2, // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] output io_rvc // @[:freechips.rocketchip.system.TinyConfig.fir@116565.4] ); wire [1:0] _T; // @[RVC.scala 163:20:freechips.rocketchip.system.TinyConfig.fir@116570.4] wire [7:0] _T_2; // @[RVC.scala 53:22:freechips.rocketchip.system.TinyConfig.fir@116573.4] wire _T_3; // @[RVC.scala 53:29:freechips.rocketchip.system.TinyConfig.fir@116574.4] wire [6:0] _T_4; // @[RVC.scala 53:20:freechips.rocketchip.system.TinyConfig.fir@116575.4] wire [3:0] _T_5; // @[RVC.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@116576.4] wire [1:0] _T_6; // @[RVC.scala 34:35:freechips.rocketchip.system.TinyConfig.fir@116577.4] wire _T_7; // @[RVC.scala 34:45:freechips.rocketchip.system.TinyConfig.fir@116578.4] wire _T_8; // @[RVC.scala 34:51:freechips.rocketchip.system.TinyConfig.fir@116579.4] wire [2:0] _T_13; // @[RVC.scala 31:30:freechips.rocketchip.system.TinyConfig.fir@116584.4] wire [4:0] _T_14; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116585.4] wire [29:0] _T_18; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116589.4] wire [1:0] _T_25; // @[RVC.scala 36:20:freechips.rocketchip.system.TinyConfig.fir@116602.4] wire [2:0] _T_26; // @[RVC.scala 36:28:freechips.rocketchip.system.TinyConfig.fir@116603.4] wire [7:0] _T_28; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116605.4] wire [2:0] _T_29; // @[RVC.scala 30:30:freechips.rocketchip.system.TinyConfig.fir@116606.4] wire [4:0] _T_30; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116607.4] wire [27:0] _T_36; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116613.4] wire [6:0] _T_50; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116633.4] wire [26:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116641.4] wire [26:0] _T_80; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116669.4] wire [1:0] _T_95; // @[RVC.scala 63:32:freechips.rocketchip.system.TinyConfig.fir@116690.4] wire [4:0] _T_106; // @[RVC.scala 63:66:freechips.rocketchip.system.TinyConfig.fir@116701.4] wire [26:0] _T_111; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116706.4] wire [2:0] _T_124; // @[RVC.scala 66:30:freechips.rocketchip.system.TinyConfig.fir@116725.4] wire [4:0] _T_133; // @[RVC.scala 66:64:freechips.rocketchip.system.TinyConfig.fir@116734.4] wire [27:0] _T_138; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116739.4] wire [26:0] _T_169; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116776.4] wire [26:0] _T_200; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116813.4] wire _T_209; // @[RVC.scala 43:30:freechips.rocketchip.system.TinyConfig.fir@116828.4] wire [6:0] _T_211; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116830.4] wire [4:0] _T_212; // @[RVC.scala 43:38:freechips.rocketchip.system.TinyConfig.fir@116831.4] wire [11:0] _T_213; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116832.4] wire [4:0] _T_214; // @[RVC.scala 33:13:freechips.rocketchip.system.TinyConfig.fir@116833.4] wire [31:0] _T_219; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116838.4] wire [9:0] _T_228; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116853.4] wire _T_229; // @[RVC.scala 44:36:freechips.rocketchip.system.TinyConfig.fir@116854.4] wire [1:0] _T_230; // @[RVC.scala 44:42:freechips.rocketchip.system.TinyConfig.fir@116855.4] wire _T_232; // @[RVC.scala 44:57:freechips.rocketchip.system.TinyConfig.fir@116857.4] wire _T_233; // @[RVC.scala 44:63:freechips.rocketchip.system.TinyConfig.fir@116858.4] wire _T_234; // @[RVC.scala 44:69:freechips.rocketchip.system.TinyConfig.fir@116859.4] wire [2:0] _T_235; // @[RVC.scala 44:76:freechips.rocketchip.system.TinyConfig.fir@116860.4] wire [20:0] _T_243; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116868.4] wire _T_244; // @[RVC.scala 81:36:freechips.rocketchip.system.TinyConfig.fir@116869.4] wire [9:0] _T_263; // @[RVC.scala 81:46:freechips.rocketchip.system.TinyConfig.fir@116888.4] wire _T_282; // @[RVC.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@116907.4] wire [7:0] _T_301; // @[RVC.scala 81:68:freechips.rocketchip.system.TinyConfig.fir@116926.4] wire [31:0] _T_306; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116931.4] wire [31:0] _T_321; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116952.4] wire _T_332; // @[RVC.scala 90:29:freechips.rocketchip.system.TinyConfig.fir@116969.4] wire [6:0] _T_333; // @[RVC.scala 90:20:freechips.rocketchip.system.TinyConfig.fir@116970.4] wire [14:0] _T_336; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116973.4] wire [31:0] _T_339; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116976.4] wire [19:0] _T_340; // @[RVC.scala 91:31:freechips.rocketchip.system.TinyConfig.fir@116977.4] wire [31:0] _T_343; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116980.4] wire _T_351; // @[RVC.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@116994.4] wire _T_353; // @[RVC.scala 92:27:freechips.rocketchip.system.TinyConfig.fir@116996.4] wire _T_354; // @[RVC.scala 92:21:freechips.rocketchip.system.TinyConfig.fir@116997.4] wire [6:0] _T_361; // @[RVC.scala 86:20:freechips.rocketchip.system.TinyConfig.fir@117004.4] wire [2:0] _T_364; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@117007.4] wire [1:0] _T_365; // @[RVC.scala 42:42:freechips.rocketchip.system.TinyConfig.fir@117008.4] wire [31:0] _T_379; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117022.4] wire [31:0] _T_386_bits; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] wire [4:0] _T_386_rd; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] wire [4:0] _T_386_rs2; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] wire [25:0] _T_397; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117046.4] wire [30:0] _GEN_0; // @[RVC.scala 99:23:freechips.rocketchip.system.TinyConfig.fir@117058.4] wire [30:0] _T_409; // @[RVC.scala 99:23:freechips.rocketchip.system.TinyConfig.fir@117058.4] wire [31:0] _T_422; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117071.4] wire [2:0] _T_425; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117074.4] wire _T_426; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117075.4] wire [2:0] _T_427; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117076.4] wire _T_428; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117077.4] wire [2:0] _T_429; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117078.4] wire _T_430; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117079.4] wire [2:0] _T_431; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117080.4] wire _T_432; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117081.4] wire [2:0] _T_433; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117082.4] wire _T_434; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117083.4] wire [2:0] _T_435; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117084.4] wire _T_436; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117085.4] wire [2:0] _T_437; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117086.4] wire _T_438; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117087.4] wire [2:0] _T_439; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117088.4] wire _T_441; // @[RVC.scala 103:30:freechips.rocketchip.system.TinyConfig.fir@117090.4] wire [30:0] _T_442; // @[RVC.scala 103:22:freechips.rocketchip.system.TinyConfig.fir@117091.4] wire [6:0] _T_444; // @[RVC.scala 104:22:freechips.rocketchip.system.TinyConfig.fir@117093.4] wire [24:0] _T_454; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117103.4] wire [30:0] _GEN_1; // @[RVC.scala 105:43:freechips.rocketchip.system.TinyConfig.fir@117104.4] wire [30:0] _T_455; // @[RVC.scala 105:43:freechips.rocketchip.system.TinyConfig.fir@117104.4] wire [1:0] _T_456; // @[RVC.scala 107:42:freechips.rocketchip.system.TinyConfig.fir@117105.4] wire _T_457; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117106.4] wire [30:0] _T_458; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117107.4] wire _T_459; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117108.4] wire [31:0] _T_460; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117109.4] wire _T_461; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117110.4] wire [31:0] _T_462; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117111.4] wire [31:0] _T_551; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117206.4] wire [4:0] _T_560; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@117221.4] wire [12:0] _T_569; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117230.4] wire _T_570; // @[RVC.scala 95:29:freechips.rocketchip.system.TinyConfig.fir@117231.4] wire [5:0] _T_583; // @[RVC.scala 95:39:freechips.rocketchip.system.TinyConfig.fir@117244.4] wire [3:0] _T_598; // @[RVC.scala 95:72:freechips.rocketchip.system.TinyConfig.fir@117259.4] wire _T_611; // @[RVC.scala 95:83:freechips.rocketchip.system.TinyConfig.fir@117272.4] wire [31:0] _T_618; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117279.4] wire [31:0] _T_685; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117352.4] wire _T_691; // @[RVC.scala 113:27:freechips.rocketchip.system.TinyConfig.fir@117364.4] wire [6:0] _T_692; // @[RVC.scala 113:23:freechips.rocketchip.system.TinyConfig.fir@117365.4] wire [25:0] _T_701; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117374.4] wire [28:0] _T_717; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117396.4] wire [1:0] _T_722; // @[RVC.scala 37:22:freechips.rocketchip.system.TinyConfig.fir@117407.4] wire [2:0] _T_724; // @[RVC.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@117409.4] wire [27:0] _T_732; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117417.4] wire [27:0] _T_747; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117438.4] wire [24:0] _T_757; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117454.4] wire [24:0] _T_768; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117471.4] wire [24:0] _T_779; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117488.4] wire [17:0] _T_780; // @[RVC.scala 133:29:freechips.rocketchip.system.TinyConfig.fir@117489.4] wire [24:0] _T_781; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117490.4] wire [24:0] _T_784; // @[RVC.scala 134:33:freechips.rocketchip.system.TinyConfig.fir@117493.4] wire _T_790; // @[RVC.scala 135:27:freechips.rocketchip.system.TinyConfig.fir@117505.4] wire [31:0] _T_761_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117458.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117460.4] wire [31:0] _T_788_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117497.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117499.4] wire [31:0] _T_791_bits; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] wire [4:0] _T_791_rd; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] wire [4:0] _T_791_rs1; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] wire [4:0] _T_791_rs2; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] wire [24:0] _T_797; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117512.4] wire [24:0] _T_799; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117514.4] wire [24:0] _T_800; // @[RVC.scala 137:47:freechips.rocketchip.system.TinyConfig.fir@117515.4] wire [24:0] _T_803; // @[RVC.scala 138:33:freechips.rocketchip.system.TinyConfig.fir@117518.4] wire [31:0] _T_773_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117476.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117478.4] wire [31:0] _T_807_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117522.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117524.4] wire [31:0] _T_810_bits; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] wire [4:0] _T_810_rd; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] wire [4:0] _T_810_rs1; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] wire [31:0] _T_812_bits; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] wire [4:0] _T_812_rd; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] wire [4:0] _T_812_rs1; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] wire [4:0] _T_812_rs2; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] wire [8:0] _T_816; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117537.4] wire [3:0] _T_817; // @[RVC.scala 124:34:freechips.rocketchip.system.TinyConfig.fir@117538.4] wire [4:0] _T_823; // @[RVC.scala 124:67:freechips.rocketchip.system.TinyConfig.fir@117544.4] wire [28:0] _T_828; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117549.4] wire [1:0] _T_833; // @[RVC.scala 39:22:freechips.rocketchip.system.TinyConfig.fir@117560.4] wire [3:0] _T_834; // @[RVC.scala 39:30:freechips.rocketchip.system.TinyConfig.fir@117561.4] wire [7:0] _T_836; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117563.4] wire [2:0] _T_837; // @[RVC.scala 123:33:freechips.rocketchip.system.TinyConfig.fir@117564.4] wire [4:0] _T_843; // @[RVC.scala 123:66:freechips.rocketchip.system.TinyConfig.fir@117570.4] wire [27:0] _T_848; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117575.4] wire [27:0] _T_868; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117601.4] wire [4:0] _T_874; // @[RVC.scala 20:57:freechips.rocketchip.system.TinyConfig.fir@117613.4] wire [4:0] _T_875; // @[RVC.scala 20:79:freechips.rocketchip.system.TinyConfig.fir@117614.4] wire [2:0] _T_914; // @[RVC.scala 151:20:freechips.rocketchip.system.TinyConfig.fir@117701.4] wire [4:0] _T_915; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117702.4] wire _T_916; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117703.4] wire [31:0] _T_44_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116621.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116623.4] wire [31:0] _T_24_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116595.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116597.4] wire [31:0] _T_917_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] wire [4:0] _T_917_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] wire [4:0] _T_917_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] wire _T_918; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117705.4] wire [31:0] _T_66_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116649.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116651.4] wire [31:0] _T_919_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] wire [4:0] _T_919_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] wire [4:0] _T_919_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] wire _T_920; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117707.4] wire [31:0] _T_88_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116677.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116679.4] wire [31:0] _T_921_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] wire [4:0] _T_921_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] wire [4:0] _T_921_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] wire _T_922; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117709.4] wire [31:0] _T_119_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116714.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116716.4] wire [31:0] _T_923_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] wire [4:0] _T_923_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] wire [4:0] _T_923_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] wire _T_924; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117711.4] wire [31:0] _T_146_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116747.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116749.4] wire [31:0] _T_925_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] wire [4:0] _T_925_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] wire [4:0] _T_925_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] wire _T_926; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117713.4] wire [31:0] _T_177_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116784.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116786.4] wire [31:0] _T_927_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] wire [4:0] _T_927_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] wire [4:0] _T_927_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] wire _T_928; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117715.4] wire [31:0] _T_208_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116821.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116823.4] wire [31:0] _T_929_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] wire [4:0] _T_929_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] wire [4:0] _T_929_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] wire _T_930; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117717.4] wire [31:0] _T_931_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] wire [4:0] _T_931_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] wire [4:0] _T_931_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] wire [4:0] _T_931_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] wire _T_932; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117719.4] wire [31:0] _T_933_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] wire [4:0] _T_933_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] wire [4:0] _T_933_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] wire [4:0] _T_933_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] wire _T_934; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117721.4] wire [31:0] _T_935_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] wire [4:0] _T_935_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] wire [4:0] _T_935_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] wire [4:0] _T_935_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] wire _T_936; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117723.4] wire [31:0] _T_937_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] wire [4:0] _T_937_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] wire [4:0] _T_937_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] wire [4:0] _T_937_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] wire _T_938; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117725.4] wire [31:0] _T_939_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] wire [4:0] _T_939_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] wire [4:0] _T_939_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] wire [4:0] _T_939_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] wire _T_940; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117727.4] wire [31:0] _T_941_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] wire [4:0] _T_941_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] wire [4:0] _T_941_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] wire [4:0] _T_941_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] wire _T_942; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117729.4] wire [31:0] _T_943_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] wire [4:0] _T_943_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] wire [4:0] _T_943_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] wire [4:0] _T_943_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] wire _T_944; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117731.4] wire [31:0] _T_945_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] wire [4:0] _T_945_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] wire [4:0] _T_945_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] wire [4:0] _T_945_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] wire _T_946; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117733.4] wire [31:0] _T_706_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117379.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117381.4] wire [31:0] _T_947_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] wire [4:0] _T_947_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] wire [4:0] _T_947_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] wire [4:0] _T_947_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] wire _T_948; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117735.4] wire [31:0] _T_721_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117400.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117402.4] wire [31:0] _T_949_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] wire [4:0] _T_949_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] wire [4:0] _T_949_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] wire [4:0] _T_949_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] wire _T_950; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117737.4] wire [31:0] _T_736_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117421.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117423.4] wire [31:0] _T_951_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] wire [4:0] _T_951_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] wire [4:0] _T_951_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] wire [4:0] _T_951_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] wire _T_952; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117739.4] wire [31:0] _T_751_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117442.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117444.4] wire [31:0] _T_953_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] wire [4:0] _T_953_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] wire [4:0] _T_953_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] wire [4:0] _T_953_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] wire _T_954; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117741.4] wire [31:0] _T_955_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] wire [4:0] _T_955_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] wire [4:0] _T_955_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] wire [4:0] _T_955_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] wire _T_956; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117743.4] wire [31:0] _T_832_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117553.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117555.4] wire [31:0] _T_957_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] wire [4:0] _T_957_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] wire [4:0] _T_957_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] wire [4:0] _T_957_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] wire _T_958; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117745.4] wire [31:0] _T_852_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117579.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117581.4] wire [31:0] _T_959_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] wire [4:0] _T_959_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] wire [4:0] _T_959_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] wire [4:0] _T_959_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] wire _T_960; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117747.4] wire [31:0] _T_872_bits; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117605.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117607.4] wire [31:0] _T_961_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] wire [4:0] _T_961_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] wire [4:0] _T_961_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] wire [4:0] _T_961_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] wire _T_962; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117749.4] wire [31:0] _T_963_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] wire [4:0] _T_963_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] wire [4:0] _T_963_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] wire [4:0] _T_963_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] wire _T_964; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117751.4] wire [31:0] _T_965_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] wire [4:0] _T_965_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] wire [4:0] _T_965_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] wire [4:0] _T_965_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] wire _T_966; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117753.4] wire [31:0] _T_967_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] wire [4:0] _T_967_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] wire [4:0] _T_967_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] wire [4:0] _T_967_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] wire _T_968; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117755.4] wire [31:0] _T_969_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] wire [4:0] _T_969_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] wire [4:0] _T_969_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] wire [4:0] _T_969_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] wire _T_970; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117757.4] wire [31:0] _T_971_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] wire [4:0] _T_971_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] wire [4:0] _T_971_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] wire [4:0] _T_971_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] wire _T_972; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117759.4] wire [31:0] _T_973_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] wire [4:0] _T_973_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] wire [4:0] _T_973_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] wire [4:0] _T_973_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] wire _T_974; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117761.4] wire [31:0] _T_975_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] wire [4:0] _T_975_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] wire [4:0] _T_975_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] wire [4:0] _T_975_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] wire _T_976; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117763.4] assign _T = io_in[1:0]; // @[RVC.scala 163:20:freechips.rocketchip.system.TinyConfig.fir@116570.4] assign _T_2 = io_in[12:5]; // @[RVC.scala 53:22:freechips.rocketchip.system.TinyConfig.fir@116573.4] assign _T_3 = _T_2 != 8'h0; // @[RVC.scala 53:29:freechips.rocketchip.system.TinyConfig.fir@116574.4] assign _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 53:20:freechips.rocketchip.system.TinyConfig.fir@116575.4] assign _T_5 = io_in[10:7]; // @[RVC.scala 34:26:freechips.rocketchip.system.TinyConfig.fir@116576.4] assign _T_6 = io_in[12:11]; // @[RVC.scala 34:35:freechips.rocketchip.system.TinyConfig.fir@116577.4] assign _T_7 = io_in[5]; // @[RVC.scala 34:45:freechips.rocketchip.system.TinyConfig.fir@116578.4] assign _T_8 = io_in[6]; // @[RVC.scala 34:51:freechips.rocketchip.system.TinyConfig.fir@116579.4] assign _T_13 = io_in[4:2]; // @[RVC.scala 31:30:freechips.rocketchip.system.TinyConfig.fir@116584.4] assign _T_14 = {2'h1,_T_13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116585.4] assign _T_18 = {_T_5,_T_6,_T_7,_T_8,2'h0,5'h2,3'h0,2'h1,_T_13,_T_4}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116589.4] assign _T_25 = io_in[6:5]; // @[RVC.scala 36:20:freechips.rocketchip.system.TinyConfig.fir@116602.4] assign _T_26 = io_in[12:10]; // @[RVC.scala 36:28:freechips.rocketchip.system.TinyConfig.fir@116603.4] assign _T_28 = {_T_25,_T_26,3'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116605.4] assign _T_29 = io_in[9:7]; // @[RVC.scala 30:30:freechips.rocketchip.system.TinyConfig.fir@116606.4] assign _T_30 = {2'h1,_T_29}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116607.4] assign _T_36 = {_T_25,_T_26,3'h0,2'h1,_T_29,3'h3,2'h1,_T_13,7'h7}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116613.4] assign _T_50 = {_T_7,_T_26,_T_8,2'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116633.4] assign _T_58 = {_T_7,_T_26,_T_8,2'h0,2'h1,_T_29,3'h2,2'h1,_T_13,7'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116641.4] assign _T_80 = {_T_7,_T_26,_T_8,2'h0,2'h1,_T_29,3'h2,2'h1,_T_13,7'h7}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116669.4] assign _T_95 = _T_50[6:5]; // @[RVC.scala 63:32:freechips.rocketchip.system.TinyConfig.fir@116690.4] assign _T_106 = _T_50[4:0]; // @[RVC.scala 63:66:freechips.rocketchip.system.TinyConfig.fir@116701.4] assign _T_111 = {_T_95,2'h1,_T_13,2'h1,_T_29,3'h2,_T_106,7'h3f}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116706.4] assign _T_124 = _T_28[7:5]; // @[RVC.scala 66:30:freechips.rocketchip.system.TinyConfig.fir@116725.4] assign _T_133 = _T_28[4:0]; // @[RVC.scala 66:64:freechips.rocketchip.system.TinyConfig.fir@116734.4] assign _T_138 = {_T_124,2'h1,_T_13,2'h1,_T_29,3'h3,_T_133,7'h27}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116739.4] assign _T_169 = {_T_95,2'h1,_T_13,2'h1,_T_29,3'h2,_T_106,7'h23}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116776.4] assign _T_200 = {_T_95,2'h1,_T_13,2'h1,_T_29,3'h2,_T_106,7'h27}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116813.4] assign _T_209 = io_in[12]; // @[RVC.scala 43:30:freechips.rocketchip.system.TinyConfig.fir@116828.4] assign _T_211 = _T_209 ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116830.4] assign _T_212 = io_in[6:2]; // @[RVC.scala 43:38:freechips.rocketchip.system.TinyConfig.fir@116831.4] assign _T_213 = {_T_211,_T_212}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116832.4] assign _T_214 = io_in[11:7]; // @[RVC.scala 33:13:freechips.rocketchip.system.TinyConfig.fir@116833.4] assign _T_219 = {_T_211,_T_212,_T_214,3'h0,_T_214,7'h13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116838.4] assign _T_228 = _T_209 ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116853.4] assign _T_229 = io_in[8]; // @[RVC.scala 44:36:freechips.rocketchip.system.TinyConfig.fir@116854.4] assign _T_230 = io_in[10:9]; // @[RVC.scala 44:42:freechips.rocketchip.system.TinyConfig.fir@116855.4] assign _T_232 = io_in[7]; // @[RVC.scala 44:57:freechips.rocketchip.system.TinyConfig.fir@116857.4] assign _T_233 = io_in[2]; // @[RVC.scala 44:63:freechips.rocketchip.system.TinyConfig.fir@116858.4] assign _T_234 = io_in[11]; // @[RVC.scala 44:69:freechips.rocketchip.system.TinyConfig.fir@116859.4] assign _T_235 = io_in[5:3]; // @[RVC.scala 44:76:freechips.rocketchip.system.TinyConfig.fir@116860.4] assign _T_243 = {_T_228,_T_229,_T_230,_T_8,_T_232,_T_233,_T_234,_T_235,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116868.4] assign _T_244 = _T_243[20]; // @[RVC.scala 81:36:freechips.rocketchip.system.TinyConfig.fir@116869.4] assign _T_263 = _T_243[10:1]; // @[RVC.scala 81:46:freechips.rocketchip.system.TinyConfig.fir@116888.4] assign _T_282 = _T_243[11]; // @[RVC.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@116907.4] assign _T_301 = _T_243[19:12]; // @[RVC.scala 81:68:freechips.rocketchip.system.TinyConfig.fir@116926.4] assign _T_306 = {_T_244,_T_263,_T_282,_T_301,5'h1,7'h6f}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116931.4] assign _T_321 = {_T_211,_T_212,5'h0,3'h0,_T_214,7'h13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116952.4] assign _T_332 = _T_213 != 12'h0; // @[RVC.scala 90:29:freechips.rocketchip.system.TinyConfig.fir@116969.4] assign _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 90:20:freechips.rocketchip.system.TinyConfig.fir@116970.4] assign _T_336 = _T_209 ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@116973.4] assign _T_339 = {_T_336,_T_212,12'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116976.4] assign _T_340 = _T_339[31:12]; // @[RVC.scala 91:31:freechips.rocketchip.system.TinyConfig.fir@116977.4] assign _T_343 = {_T_340,_T_214,_T_333}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@116980.4] assign _T_351 = _T_214 == 5'h0; // @[RVC.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@116994.4] assign _T_353 = _T_214 == 5'h2; // @[RVC.scala 92:27:freechips.rocketchip.system.TinyConfig.fir@116996.4] assign _T_354 = _T_351 | _T_353; // @[RVC.scala 92:21:freechips.rocketchip.system.TinyConfig.fir@116997.4] assign _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 86:20:freechips.rocketchip.system.TinyConfig.fir@117004.4] assign _T_364 = _T_209 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@117007.4] assign _T_365 = io_in[4:3]; // @[RVC.scala 42:42:freechips.rocketchip.system.TinyConfig.fir@117008.4] assign _T_379 = {_T_364,_T_365,_T_7,_T_233,_T_8,4'h0,_T_214,3'h0,_T_214,_T_361}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117022.4] assign _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] assign _T_386_rd = _T_354 ? _T_214 : _T_214; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] assign _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 92:10:freechips.rocketchip.system.TinyConfig.fir@117035.4] assign _T_397 = {_T_209,_T_212,2'h1,_T_29,3'h5,2'h1,_T_29,7'h13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117046.4] assign _GEN_0 = {{5'd0}, _T_397}; // @[RVC.scala 99:23:freechips.rocketchip.system.TinyConfig.fir@117058.4] assign _T_409 = _GEN_0 | 31'h40000000; // @[RVC.scala 99:23:freechips.rocketchip.system.TinyConfig.fir@117058.4] assign _T_422 = {_T_211,_T_212,2'h1,_T_29,3'h7,2'h1,_T_29,7'h13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117071.4] assign _T_425 = {_T_209,_T_25}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117074.4] assign _T_426 = _T_425 == 3'h1; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117075.4] assign _T_427 = _T_426 ? 3'h4 : 3'h0; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117076.4] assign _T_428 = _T_425 == 3'h2; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117077.4] assign _T_429 = _T_428 ? 3'h6 : _T_427; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117078.4] assign _T_430 = _T_425 == 3'h3; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117079.4] assign _T_431 = _T_430 ? 3'h7 : _T_429; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117080.4] assign _T_432 = _T_425 == 3'h4; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117081.4] assign _T_433 = _T_432 ? 3'h0 : _T_431; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117082.4] assign _T_434 = _T_425 == 3'h5; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117083.4] assign _T_435 = _T_434 ? 3'h0 : _T_433; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117084.4] assign _T_436 = _T_425 == 3'h6; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117085.4] assign _T_437 = _T_436 ? 3'h2 : _T_435; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117086.4] assign _T_438 = _T_425 == 3'h7; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117087.4] assign _T_439 = _T_438 ? 3'h3 : _T_437; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117088.4] assign _T_441 = _T_25 == 2'h0; // @[RVC.scala 103:30:freechips.rocketchip.system.TinyConfig.fir@117090.4] assign _T_442 = _T_441 ? 31'h40000000 : 31'h0; // @[RVC.scala 103:22:freechips.rocketchip.system.TinyConfig.fir@117091.4] assign _T_444 = _T_209 ? 7'h3b : 7'h33; // @[RVC.scala 104:22:freechips.rocketchip.system.TinyConfig.fir@117093.4] assign _T_454 = {2'h1,_T_13,2'h1,_T_29,_T_439,2'h1,_T_29,_T_444}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117103.4] assign _GEN_1 = {{6'd0}, _T_454}; // @[RVC.scala 105:43:freechips.rocketchip.system.TinyConfig.fir@117104.4] assign _T_455 = _GEN_1 | _T_442; // @[RVC.scala 105:43:freechips.rocketchip.system.TinyConfig.fir@117104.4] assign _T_456 = io_in[11:10]; // @[RVC.scala 107:42:freechips.rocketchip.system.TinyConfig.fir@117105.4] assign _T_457 = _T_456 == 2'h1; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117106.4] assign _T_458 = _T_457 ? _T_409 : {{5'd0}, _T_397}; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117107.4] assign _T_459 = _T_456 == 2'h2; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117108.4] assign _T_460 = _T_459 ? _T_422 : {{1'd0}, _T_458}; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117109.4] assign _T_461 = _T_456 == 2'h3; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117110.4] assign _T_462 = _T_461 ? {{1'd0}, _T_455} : _T_460; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117111.4] assign _T_551 = {_T_244,_T_263,_T_282,_T_301,5'h0,7'h6f}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117206.4] assign _T_560 = _T_209 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.TinyConfig.fir@117221.4] assign _T_569 = {_T_560,_T_25,_T_233,_T_456,_T_365,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117230.4] assign _T_570 = _T_569[12]; // @[RVC.scala 95:29:freechips.rocketchip.system.TinyConfig.fir@117231.4] assign _T_583 = _T_569[10:5]; // @[RVC.scala 95:39:freechips.rocketchip.system.TinyConfig.fir@117244.4] assign _T_598 = _T_569[4:1]; // @[RVC.scala 95:72:freechips.rocketchip.system.TinyConfig.fir@117259.4] assign _T_611 = _T_569[11]; // @[RVC.scala 95:83:freechips.rocketchip.system.TinyConfig.fir@117272.4] assign _T_618 = {_T_570,_T_583,5'h0,2'h1,_T_29,3'h0,_T_598,_T_611,7'h63}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117279.4] assign _T_685 = {_T_570,_T_583,5'h0,2'h1,_T_29,3'h1,_T_598,_T_611,7'h63}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117352.4] assign _T_691 = _T_214 != 5'h0; // @[RVC.scala 113:27:freechips.rocketchip.system.TinyConfig.fir@117364.4] assign _T_692 = _T_691 ? 7'h3 : 7'h1f; // @[RVC.scala 113:23:freechips.rocketchip.system.TinyConfig.fir@117365.4] assign _T_701 = {_T_209,_T_212,_T_214,3'h1,_T_214,7'h13}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117374.4] assign _T_717 = {_T_13,_T_209,_T_25,3'h0,5'h2,3'h3,_T_214,7'h7}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117396.4] assign _T_722 = io_in[3:2]; // @[RVC.scala 37:22:freechips.rocketchip.system.TinyConfig.fir@117407.4] assign _T_724 = io_in[6:4]; // @[RVC.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@117409.4] assign _T_732 = {_T_722,_T_209,_T_724,2'h0,5'h2,3'h2,_T_214,_T_692}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117417.4] assign _T_747 = {_T_722,_T_209,_T_724,2'h0,5'h2,3'h2,_T_214,7'h7}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117438.4] assign _T_757 = {_T_212,5'h0,3'h0,_T_214,7'h33}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117454.4] assign _T_768 = {_T_212,_T_214,3'h0,_T_214,7'h33}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117471.4] assign _T_779 = {_T_212,_T_214,3'h0,12'h67}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117488.4] assign _T_780 = _T_779[24:7]; // @[RVC.scala 133:29:freechips.rocketchip.system.TinyConfig.fir@117489.4] assign _T_781 = {_T_780,7'h1f}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117490.4] assign _T_784 = _T_691 ? _T_779 : _T_781; // @[RVC.scala 134:33:freechips.rocketchip.system.TinyConfig.fir@117493.4] assign _T_790 = _T_212 != 5'h0; // @[RVC.scala 135:27:freechips.rocketchip.system.TinyConfig.fir@117505.4] assign _T_761_bits = {{7'd0}, _T_757}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117458.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117460.4] assign _T_788_bits = {{7'd0}, _T_784}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117497.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117499.4] assign _T_791_bits = _T_790 ? _T_761_bits : _T_788_bits; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] assign _T_791_rd = _T_790 ? _T_214 : 5'h0; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] assign _T_791_rs1 = _T_790 ? 5'h0 : _T_214; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] assign _T_791_rs2 = _T_790 ? _T_212 : _T_212; // @[RVC.scala 135:22:freechips.rocketchip.system.TinyConfig.fir@117506.4] assign _T_797 = {_T_212,_T_214,3'h0,12'he7}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117512.4] assign _T_799 = {_T_780,7'h73}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117514.4] assign _T_800 = _T_799 | 25'h100000; // @[RVC.scala 137:47:freechips.rocketchip.system.TinyConfig.fir@117515.4] assign _T_803 = _T_691 ? _T_797 : _T_800; // @[RVC.scala 138:33:freechips.rocketchip.system.TinyConfig.fir@117518.4] assign _T_773_bits = {{7'd0}, _T_768}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117476.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117478.4] assign _T_807_bits = {{7'd0}, _T_803}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117522.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117524.4] assign _T_810_bits = _T_790 ? _T_773_bits : _T_807_bits; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] assign _T_810_rd = _T_790 ? _T_214 : 5'h1; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] assign _T_810_rs1 = _T_790 ? _T_214 : _T_214; // @[RVC.scala 139:25:freechips.rocketchip.system.TinyConfig.fir@117531.4] assign _T_812_bits = _T_209 ? _T_810_bits : _T_791_bits; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] assign _T_812_rd = _T_209 ? _T_810_rd : _T_791_rd; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] assign _T_812_rs1 = _T_209 ? _T_810_rs1 : _T_791_rs1; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] assign _T_812_rs2 = _T_209 ? _T_791_rs2 : _T_791_rs2; // @[RVC.scala 140:10:freechips.rocketchip.system.TinyConfig.fir@117533.4] assign _T_816 = {_T_29,_T_26,3'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117537.4] assign _T_817 = _T_816[8:5]; // @[RVC.scala 124:34:freechips.rocketchip.system.TinyConfig.fir@117538.4] assign _T_823 = _T_816[4:0]; // @[RVC.scala 124:67:freechips.rocketchip.system.TinyConfig.fir@117544.4] assign _T_828 = {_T_817,_T_212,5'h2,3'h3,_T_823,7'h27}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117549.4] assign _T_833 = io_in[8:7]; // @[RVC.scala 39:22:freechips.rocketchip.system.TinyConfig.fir@117560.4] assign _T_834 = io_in[12:9]; // @[RVC.scala 39:30:freechips.rocketchip.system.TinyConfig.fir@117561.4] assign _T_836 = {_T_833,_T_834,2'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117563.4] assign _T_837 = _T_836[7:5]; // @[RVC.scala 123:33:freechips.rocketchip.system.TinyConfig.fir@117564.4] assign _T_843 = _T_836[4:0]; // @[RVC.scala 123:66:freechips.rocketchip.system.TinyConfig.fir@117570.4] assign _T_848 = {_T_837,_T_212,5'h2,3'h2,_T_843,7'h23}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117575.4] assign _T_868 = {_T_837,_T_212,5'h2,3'h2,_T_843,7'h27}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117601.4] assign _T_874 = io_in[19:15]; // @[RVC.scala 20:57:freechips.rocketchip.system.TinyConfig.fir@117613.4] assign _T_875 = io_in[24:20]; // @[RVC.scala 20:79:freechips.rocketchip.system.TinyConfig.fir@117614.4] assign _T_914 = io_in[15:13]; // @[RVC.scala 151:20:freechips.rocketchip.system.TinyConfig.fir@117701.4] assign _T_915 = {_T,_T_914}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117702.4] assign _T_916 = _T_915 == 5'h1; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117703.4] assign _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116621.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116623.4] assign _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116595.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116597.4] assign _T_917_bits = _T_916 ? _T_44_bits : _T_24_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] assign _T_917_rd = _T_916 ? _T_14 : _T_14; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] assign _T_917_rs1 = _T_916 ? _T_30 : 5'h2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117704.4] assign _T_918 = _T_915 == 5'h2; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117705.4] assign _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116649.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116651.4] assign _T_919_bits = _T_918 ? _T_66_bits : _T_917_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] assign _T_919_rd = _T_918 ? _T_14 : _T_917_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] assign _T_919_rs1 = _T_918 ? _T_30 : _T_917_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117706.4] assign _T_920 = _T_915 == 5'h3; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117707.4] assign _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116677.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116679.4] assign _T_921_bits = _T_920 ? _T_88_bits : _T_919_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] assign _T_921_rd = _T_920 ? _T_14 : _T_919_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] assign _T_921_rs1 = _T_920 ? _T_30 : _T_919_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117708.4] assign _T_922 = _T_915 == 5'h4; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117709.4] assign _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116714.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116716.4] assign _T_923_bits = _T_922 ? _T_119_bits : _T_921_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] assign _T_923_rd = _T_922 ? _T_14 : _T_921_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] assign _T_923_rs1 = _T_922 ? _T_30 : _T_921_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117710.4] assign _T_924 = _T_915 == 5'h5; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117711.4] assign _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116747.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116749.4] assign _T_925_bits = _T_924 ? _T_146_bits : _T_923_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] assign _T_925_rd = _T_924 ? _T_14 : _T_923_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] assign _T_925_rs1 = _T_924 ? _T_30 : _T_923_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117712.4] assign _T_926 = _T_915 == 5'h6; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117713.4] assign _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116784.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116786.4] assign _T_927_bits = _T_926 ? _T_177_bits : _T_925_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] assign _T_927_rd = _T_926 ? _T_14 : _T_925_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] assign _T_927_rs1 = _T_926 ? _T_30 : _T_925_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117714.4] assign _T_928 = _T_915 == 5'h7; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117715.4] assign _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@116821.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@116823.4] assign _T_929_bits = _T_928 ? _T_208_bits : _T_927_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] assign _T_929_rd = _T_928 ? _T_14 : _T_927_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] assign _T_929_rs1 = _T_928 ? _T_30 : _T_927_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117716.4] assign _T_930 = _T_915 == 5'h8; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117717.4] assign _T_931_bits = _T_930 ? _T_219 : _T_929_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] assign _T_931_rd = _T_930 ? _T_214 : _T_929_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] assign _T_931_rs1 = _T_930 ? _T_214 : _T_929_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] assign _T_931_rs2 = _T_930 ? _T_14 : _T_929_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117718.4] assign _T_932 = _T_915 == 5'h9; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117719.4] assign _T_933_bits = _T_932 ? _T_306 : _T_931_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] assign _T_933_rd = _T_932 ? 5'h1 : _T_931_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] assign _T_933_rs1 = _T_932 ? _T_214 : _T_931_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] assign _T_933_rs2 = _T_932 ? _T_14 : _T_931_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117720.4] assign _T_934 = _T_915 == 5'ha; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117721.4] assign _T_935_bits = _T_934 ? _T_321 : _T_933_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] assign _T_935_rd = _T_934 ? _T_214 : _T_933_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] assign _T_935_rs1 = _T_934 ? 5'h0 : _T_933_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] assign _T_935_rs2 = _T_934 ? _T_14 : _T_933_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117722.4] assign _T_936 = _T_915 == 5'hb; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117723.4] assign _T_937_bits = _T_936 ? _T_386_bits : _T_935_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] assign _T_937_rd = _T_936 ? _T_386_rd : _T_935_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] assign _T_937_rs1 = _T_936 ? _T_386_rd : _T_935_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] assign _T_937_rs2 = _T_936 ? _T_386_rs2 : _T_935_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117724.4] assign _T_938 = _T_915 == 5'hc; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117725.4] assign _T_939_bits = _T_938 ? _T_462 : _T_937_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] assign _T_939_rd = _T_938 ? _T_30 : _T_937_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] assign _T_939_rs1 = _T_938 ? _T_30 : _T_937_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] assign _T_939_rs2 = _T_938 ? _T_14 : _T_937_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117726.4] assign _T_940 = _T_915 == 5'hd; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117727.4] assign _T_941_bits = _T_940 ? _T_551 : _T_939_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] assign _T_941_rd = _T_940 ? 5'h0 : _T_939_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] assign _T_941_rs1 = _T_940 ? _T_30 : _T_939_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] assign _T_941_rs2 = _T_940 ? _T_14 : _T_939_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117728.4] assign _T_942 = _T_915 == 5'he; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117729.4] assign _T_943_bits = _T_942 ? _T_618 : _T_941_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] assign _T_943_rd = _T_942 ? _T_30 : _T_941_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] assign _T_943_rs1 = _T_942 ? _T_30 : _T_941_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] assign _T_943_rs2 = _T_942 ? 5'h0 : _T_941_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117730.4] assign _T_944 = _T_915 == 5'hf; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117731.4] assign _T_945_bits = _T_944 ? _T_685 : _T_943_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] assign _T_945_rd = _T_944 ? 5'h0 : _T_943_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] assign _T_945_rs1 = _T_944 ? _T_30 : _T_943_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] assign _T_945_rs2 = _T_944 ? 5'h0 : _T_943_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117732.4] assign _T_946 = _T_915 == 5'h10; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117733.4] assign _T_706_bits = {{6'd0}, _T_701}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117379.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117381.4] assign _T_947_bits = _T_946 ? _T_706_bits : _T_945_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] assign _T_947_rd = _T_946 ? _T_214 : _T_945_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] assign _T_947_rs1 = _T_946 ? _T_214 : _T_945_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] assign _T_947_rs2 = _T_946 ? _T_212 : _T_945_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117734.4] assign _T_948 = _T_915 == 5'h11; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117735.4] assign _T_721_bits = {{3'd0}, _T_717}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117400.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117402.4] assign _T_949_bits = _T_948 ? _T_721_bits : _T_947_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] assign _T_949_rd = _T_948 ? _T_214 : _T_947_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] assign _T_949_rs1 = _T_948 ? 5'h2 : _T_947_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] assign _T_949_rs2 = _T_948 ? _T_212 : _T_947_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117736.4] assign _T_950 = _T_915 == 5'h12; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117737.4] assign _T_736_bits = {{4'd0}, _T_732}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117421.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117423.4] assign _T_951_bits = _T_950 ? _T_736_bits : _T_949_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] assign _T_951_rd = _T_950 ? _T_214 : _T_949_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] assign _T_951_rs1 = _T_950 ? 5'h2 : _T_949_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] assign _T_951_rs2 = _T_950 ? _T_212 : _T_949_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117738.4] assign _T_952 = _T_915 == 5'h13; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117739.4] assign _T_751_bits = {{4'd0}, _T_747}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117442.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117444.4] assign _T_953_bits = _T_952 ? _T_751_bits : _T_951_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] assign _T_953_rd = _T_952 ? _T_214 : _T_951_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] assign _T_953_rs1 = _T_952 ? 5'h2 : _T_951_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] assign _T_953_rs2 = _T_952 ? _T_212 : _T_951_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117740.4] assign _T_954 = _T_915 == 5'h14; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117741.4] assign _T_955_bits = _T_954 ? _T_812_bits : _T_953_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] assign _T_955_rd = _T_954 ? _T_812_rd : _T_953_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] assign _T_955_rs1 = _T_954 ? _T_812_rs1 : _T_953_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] assign _T_955_rs2 = _T_954 ? _T_812_rs2 : _T_953_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117742.4] assign _T_956 = _T_915 == 5'h15; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117743.4] assign _T_832_bits = {{3'd0}, _T_828}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117553.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117555.4] assign _T_957_bits = _T_956 ? _T_832_bits : _T_955_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] assign _T_957_rd = _T_956 ? _T_214 : _T_955_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] assign _T_957_rs1 = _T_956 ? 5'h2 : _T_955_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] assign _T_957_rs2 = _T_956 ? _T_212 : _T_955_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117744.4] assign _T_958 = _T_915 == 5'h16; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117745.4] assign _T_852_bits = {{4'd0}, _T_848}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117579.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117581.4] assign _T_959_bits = _T_958 ? _T_852_bits : _T_957_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] assign _T_959_rd = _T_958 ? _T_214 : _T_957_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] assign _T_959_rs1 = _T_958 ? 5'h2 : _T_957_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] assign _T_959_rs2 = _T_958 ? _T_212 : _T_957_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117746.4] assign _T_960 = _T_915 == 5'h17; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117747.4] assign _T_872_bits = {{4'd0}, _T_868}; // @[RVC.scala 21:19:freechips.rocketchip.system.TinyConfig.fir@117605.4 RVC.scala 22:14:freechips.rocketchip.system.TinyConfig.fir@117607.4] assign _T_961_bits = _T_960 ? _T_872_bits : _T_959_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] assign _T_961_rd = _T_960 ? _T_214 : _T_959_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] assign _T_961_rs1 = _T_960 ? 5'h2 : _T_959_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] assign _T_961_rs2 = _T_960 ? _T_212 : _T_959_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117748.4] assign _T_962 = _T_915 == 5'h18; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117749.4] assign _T_963_bits = _T_962 ? io_in : _T_961_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] assign _T_963_rd = _T_962 ? _T_214 : _T_961_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] assign _T_963_rs1 = _T_962 ? _T_874 : _T_961_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] assign _T_963_rs2 = _T_962 ? _T_875 : _T_961_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117750.4] assign _T_964 = _T_915 == 5'h19; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117751.4] assign _T_965_bits = _T_964 ? io_in : _T_963_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] assign _T_965_rd = _T_964 ? _T_214 : _T_963_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] assign _T_965_rs1 = _T_964 ? _T_874 : _T_963_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] assign _T_965_rs2 = _T_964 ? _T_875 : _T_963_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117752.4] assign _T_966 = _T_915 == 5'h1a; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117753.4] assign _T_967_bits = _T_966 ? io_in : _T_965_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] assign _T_967_rd = _T_966 ? _T_214 : _T_965_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] assign _T_967_rs1 = _T_966 ? _T_874 : _T_965_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] assign _T_967_rs2 = _T_966 ? _T_875 : _T_965_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117754.4] assign _T_968 = _T_915 == 5'h1b; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117755.4] assign _T_969_bits = _T_968 ? io_in : _T_967_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] assign _T_969_rd = _T_968 ? _T_214 : _T_967_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] assign _T_969_rs1 = _T_968 ? _T_874 : _T_967_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] assign _T_969_rs2 = _T_968 ? _T_875 : _T_967_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117756.4] assign _T_970 = _T_915 == 5'h1c; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117757.4] assign _T_971_bits = _T_970 ? io_in : _T_969_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] assign _T_971_rd = _T_970 ? _T_214 : _T_969_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] assign _T_971_rs1 = _T_970 ? _T_874 : _T_969_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] assign _T_971_rs2 = _T_970 ? _T_875 : _T_969_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117758.4] assign _T_972 = _T_915 == 5'h1d; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117759.4] assign _T_973_bits = _T_972 ? io_in : _T_971_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] assign _T_973_rd = _T_972 ? _T_214 : _T_971_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] assign _T_973_rs1 = _T_972 ? _T_874 : _T_971_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] assign _T_973_rs2 = _T_972 ? _T_875 : _T_971_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117760.4] assign _T_974 = _T_915 == 5'h1e; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117761.4] assign _T_975_bits = _T_974 ? io_in : _T_973_bits; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] assign _T_975_rd = _T_974 ? _T_214 : _T_973_rd; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] assign _T_975_rs1 = _T_974 ? _T_874 : _T_973_rs1; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] assign _T_975_rs2 = _T_974 ? _T_875 : _T_973_rs2; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@117762.4] assign _T_976 = _T_915 == 5'h1f; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@117763.4] assign io_out_bits = _T_976 ? io_in : _T_975_bits; // @[RVC.scala 164:12:freechips.rocketchip.system.TinyConfig.fir@117765.4] assign io_out_rd = _T_976 ? _T_214 : _T_975_rd; // @[RVC.scala 164:12:freechips.rocketchip.system.TinyConfig.fir@117765.4] assign io_out_rs1 = _T_976 ? _T_874 : _T_975_rs1; // @[RVC.scala 164:12:freechips.rocketchip.system.TinyConfig.fir@117765.4] assign io_out_rs2 = _T_976 ? _T_875 : _T_975_rs2; // @[RVC.scala 164:12:freechips.rocketchip.system.TinyConfig.fir@117765.4] assign io_rvc = _T != 2'h3; // @[RVC.scala 163:12:freechips.rocketchip.system.TinyConfig.fir@116572.4] endmodule module IBuf( // @[:freechips.rocketchip.system.TinyConfig.fir@117767.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@117768.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@117769.4] output io_imem_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input io_imem_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input [31:0] io_imem_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input [31:0] io_imem_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input io_imem_bits_xcpt_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input io_imem_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input io_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [31:0] io_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] input io_inst_0_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_bits_xcpt0_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_bits_xcpt1_pf_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_bits_xcpt1_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output io_inst_0_bits_rvc, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [31:0] io_inst_0_bits_inst_bits, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [4:0] io_inst_0_bits_inst_rd, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [4:0] io_inst_0_bits_inst_rs1, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [4:0] io_inst_0_bits_inst_rs2, // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] output [31:0] io_inst_0_bits_raw // @[:freechips.rocketchip.system.TinyConfig.fir@117770.4] ); wire [31:0] RVCExpander_io_in; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] wire [31:0] RVCExpander_io_out_bits; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] wire [4:0] RVCExpander_io_out_rd; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] wire [4:0] RVCExpander_io_out_rs1; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] wire [4:0] RVCExpander_io_out_rs2; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] wire RVCExpander_io_rvc; // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] reg nBufValid; // @[IBuf.scala 34:47:freechips.rocketchip.system.TinyConfig.fir@117775.4] reg [31:0] _RAND_0; reg [31:0] buf__pc; // @[IBuf.scala 35:16:freechips.rocketchip.system.TinyConfig.fir@117776.4] reg [31:0] _RAND_1; reg [31:0] buf__data; // @[IBuf.scala 35:16:freechips.rocketchip.system.TinyConfig.fir@117776.4] reg [31:0] _RAND_2; reg buf__xcpt_ae_inst; // @[IBuf.scala 35:16:freechips.rocketchip.system.TinyConfig.fir@117776.4] reg [31:0] _RAND_3; reg buf__replay; // @[IBuf.scala 35:16:freechips.rocketchip.system.TinyConfig.fir@117776.4] reg [31:0] _RAND_4; wire pcWordBits; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@117778.4] wire [1:0] _GEN_56; // @[IBuf.scala 41:88:freechips.rocketchip.system.TinyConfig.fir@117784.4] wire [1:0] nIC; // @[IBuf.scala 41:88:freechips.rocketchip.system.TinyConfig.fir@117785.4] wire [1:0] _T_4; // @[IBuf.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@117788.4] wire [1:0] _GEN_57; // @[IBuf.scala 43:49:freechips.rocketchip.system.TinyConfig.fir@117789.4] wire [1:0] nValid; // @[IBuf.scala 43:49:freechips.rocketchip.system.TinyConfig.fir@117790.4] wire [3:0] _T_62; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@117865.4] wire [3:0] _T_64; // @[IBuf.scala 74:33:freechips.rocketchip.system.TinyConfig.fir@117867.4] wire [1:0] valid; // @[IBuf.scala 74:37:freechips.rocketchip.system.TinyConfig.fir@117868.4] wire _GEN_58; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117915.4] wire [1:0] _T_93; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117915.4] wire _T_94; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117916.4] wire _T_95; // @[IBuf.scala 93:34:freechips.rocketchip.system.TinyConfig.fir@117917.4] wire [1:0] _T_65; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@117869.4] wire [1:0] bufMask; // @[IBuf.scala 75:37:freechips.rocketchip.system.TinyConfig.fir@117871.4] wire [1:0] buf_replay; // @[IBuf.scala 77:23:freechips.rocketchip.system.TinyConfig.fir@117876.4] wire _T_97; // @[IBuf.scala 93:61:freechips.rocketchip.system.TinyConfig.fir@117919.4] wire _T_98; // @[IBuf.scala 93:48:freechips.rocketchip.system.TinyConfig.fir@117920.4] wire [1:0] _T_128; // @[IBuf.scala 102:71:freechips.rocketchip.system.TinyConfig.fir@117964.6] wire [1:0] nReady; // @[IBuf.scala 102:56:freechips.rocketchip.system.TinyConfig.fir@117959.4] wire [1:0] nICReady; // @[IBuf.scala 42:25:freechips.rocketchip.system.TinyConfig.fir@117787.4] wire _T_6; // @[IBuf.scala 44:47:freechips.rocketchip.system.TinyConfig.fir@117791.4] wire _T_7; // @[IBuf.scala 44:37:freechips.rocketchip.system.TinyConfig.fir@117792.4] wire _T_8; // @[IBuf.scala 44:73:freechips.rocketchip.system.TinyConfig.fir@117793.4] wire [1:0] _T_10; // @[IBuf.scala 44:92:freechips.rocketchip.system.TinyConfig.fir@117795.4] wire _T_11; // @[IBuf.scala 44:85:freechips.rocketchip.system.TinyConfig.fir@117796.4] wire _T_12; // @[IBuf.scala 44:80:freechips.rocketchip.system.TinyConfig.fir@117797.4] wire [1:0] _T_16; // @[IBuf.scala 48:64:freechips.rocketchip.system.TinyConfig.fir@117803.6] wire [1:0] _T_17; // @[IBuf.scala 48:23:freechips.rocketchip.system.TinyConfig.fir@117804.6] wire _T_19; // @[IBuf.scala 54:27:freechips.rocketchip.system.TinyConfig.fir@117807.6] wire _T_20; // @[IBuf.scala 54:62:freechips.rocketchip.system.TinyConfig.fir@117808.6] wire _T_21; // @[IBuf.scala 54:50:freechips.rocketchip.system.TinyConfig.fir@117809.6] wire _T_25; // @[IBuf.scala 54:68:freechips.rocketchip.system.TinyConfig.fir@117813.6] wire [1:0] _T_27; // @[IBuf.scala 55:32:freechips.rocketchip.system.TinyConfig.fir@117816.8] wire [15:0] _T_30; // @[IBuf.scala 127:58:freechips.rocketchip.system.TinyConfig.fir@117821.8] wire [63:0] _T_32; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117823.8] wire [5:0] _T_33; // @[IBuf.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@117824.8] wire [63:0] _T_34; // @[IBuf.scala 128:10:freechips.rocketchip.system.TinyConfig.fir@117825.8] wire [15:0] _T_35; // @[IBuf.scala 58:61:freechips.rocketchip.system.TinyConfig.fir@117826.8] wire [31:0] _T_37; // @[IBuf.scala 59:35:freechips.rocketchip.system.TinyConfig.fir@117829.8] wire [2:0] _T_38; // @[IBuf.scala 59:80:freechips.rocketchip.system.TinyConfig.fir@117830.8] wire [31:0] _GEN_65; // @[IBuf.scala 59:68:freechips.rocketchip.system.TinyConfig.fir@117831.8] wire [31:0] _T_40; // @[IBuf.scala 59:68:freechips.rocketchip.system.TinyConfig.fir@117832.8] wire [31:0] _T_41; // @[IBuf.scala 59:109:freechips.rocketchip.system.TinyConfig.fir@117833.8] wire [31:0] _T_42; // @[IBuf.scala 59:49:freechips.rocketchip.system.TinyConfig.fir@117834.8] wire [1:0] _GEN_0; // @[IBuf.scala 54:92:freechips.rocketchip.system.TinyConfig.fir@117814.6] wire [1:0] _GEN_23; // @[IBuf.scala 47:29:freechips.rocketchip.system.TinyConfig.fir@117800.4] wire [1:0] _GEN_46; // @[IBuf.scala 63:20:freechips.rocketchip.system.TinyConfig.fir@117839.4] wire [1:0] _T_44; // @[IBuf.scala 68:32:freechips.rocketchip.system.TinyConfig.fir@117843.4] wire [1:0] icShiftAmt; // @[IBuf.scala 68:44:freechips.rocketchip.system.TinyConfig.fir@117845.4] wire [15:0] _T_47; // @[IBuf.scala 69:87:freechips.rocketchip.system.TinyConfig.fir@117847.4] wire [63:0] _T_49; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117849.4] wire [15:0] _T_50; // @[IBuf.scala 120:58:freechips.rocketchip.system.TinyConfig.fir@117850.4] wire [127:0] _T_53; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117853.4] wire [5:0] _T_54; // @[IBuf.scala 121:19:freechips.rocketchip.system.TinyConfig.fir@117854.4] wire [190:0] _GEN_68; // @[IBuf.scala 121:10:freechips.rocketchip.system.TinyConfig.fir@117855.4] wire [190:0] _T_55; // @[IBuf.scala 121:10:freechips.rocketchip.system.TinyConfig.fir@117855.4] wire [31:0] icData; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@117856.4] wire [4:0] _T_57; // @[IBuf.scala 71:65:freechips.rocketchip.system.TinyConfig.fir@117858.4] wire [62:0] _T_58; // @[IBuf.scala 71:51:freechips.rocketchip.system.TinyConfig.fir@117859.4] wire [31:0] icMask; // @[IBuf.scala 71:92:freechips.rocketchip.system.TinyConfig.fir@117860.4] wire [31:0] _T_59; // @[IBuf.scala 72:21:freechips.rocketchip.system.TinyConfig.fir@117861.4] wire [31:0] _T_60; // @[IBuf.scala 72:43:freechips.rocketchip.system.TinyConfig.fir@117862.4] wire [31:0] _T_61; // @[IBuf.scala 72:41:freechips.rocketchip.system.TinyConfig.fir@117863.4] wire _T_67; // @[IBuf.scala 76:61:freechips.rocketchip.system.TinyConfig.fir@117872.4] wire _T_68; // @[IBuf.scala 76:61:freechips.rocketchip.system.TinyConfig.fir@117874.4] wire xcpt_1_ae_inst; // @[IBuf.scala 76:53:freechips.rocketchip.system.TinyConfig.fir@117875.4] wire [1:0] _T_69; // @[IBuf.scala 78:65:freechips.rocketchip.system.TinyConfig.fir@117877.4] wire [1:0] _T_70; // @[IBuf.scala 78:63:freechips.rocketchip.system.TinyConfig.fir@117878.4] wire [1:0] _T_71; // @[IBuf.scala 78:35:freechips.rocketchip.system.TinyConfig.fir@117879.4] wire [1:0] ic_replay; // @[IBuf.scala 78:30:freechips.rocketchip.system.TinyConfig.fir@117880.4] wire _T_80; // @[IBuf.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@117894.4] wire _T_83; // @[IBuf.scala 92:29:freechips.rocketchip.system.TinyConfig.fir@117905.4] wire _T_84; // @[IBuf.scala 92:37:freechips.rocketchip.system.TinyConfig.fir@117906.4] wire _GEN_69; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117909.4] wire [1:0] _T_87; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117909.4] wire _T_88; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117910.4] wire _T_89; // @[IBuf.scala 92:49:freechips.rocketchip.system.TinyConfig.fir@117911.4] wire _T_100; // @[IBuf.scala 94:32:freechips.rocketchip.system.TinyConfig.fir@117922.4] wire [1:0] _T_108; // @[IBuf.scala 96:63:freechips.rocketchip.system.TinyConfig.fir@117932.4] wire [1:0] _T_109; // @[IBuf.scala 96:35:freechips.rocketchip.system.TinyConfig.fir@117933.4] RVCExpander RVCExpander ( // @[IBuf.scala 86:21:freechips.rocketchip.system.TinyConfig.fir@117897.4] .io_in(RVCExpander_io_in), .io_out_bits(RVCExpander_io_out_bits), .io_out_rd(RVCExpander_io_out_rd), .io_out_rs1(RVCExpander_io_out_rs1), .io_out_rs2(RVCExpander_io_out_rs2), .io_rvc(RVCExpander_io_rvc) ); assign pcWordBits = io_imem_bits_pc[1]; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@117778.4] assign _GEN_56 = {{1'd0}, pcWordBits}; // @[IBuf.scala 41:88:freechips.rocketchip.system.TinyConfig.fir@117784.4] assign nIC = 2'h2 - _GEN_56; // @[IBuf.scala 41:88:freechips.rocketchip.system.TinyConfig.fir@117785.4] assign _T_4 = io_imem_valid ? nIC : 2'h0; // @[IBuf.scala 43:19:freechips.rocketchip.system.TinyConfig.fir@117788.4] assign _GEN_57 = {{1'd0}, nBufValid}; // @[IBuf.scala 43:49:freechips.rocketchip.system.TinyConfig.fir@117789.4] assign nValid = _T_4 + _GEN_57; // @[IBuf.scala 43:49:freechips.rocketchip.system.TinyConfig.fir@117790.4] assign _T_62 = 4'h1 << nValid; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@117865.4] assign _T_64 = _T_62 - 4'h1; // @[IBuf.scala 74:33:freechips.rocketchip.system.TinyConfig.fir@117867.4] assign valid = _T_64[1:0]; // @[IBuf.scala 74:37:freechips.rocketchip.system.TinyConfig.fir@117868.4] assign _GEN_58 = valid[1:1]; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117915.4] assign _T_93 = {{1'd0}, _GEN_58}; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117915.4] assign _T_94 = _T_93[0]; // @[IBuf.scala 93:42:freechips.rocketchip.system.TinyConfig.fir@117916.4] assign _T_95 = RVCExpander_io_rvc | _T_94; // @[IBuf.scala 93:34:freechips.rocketchip.system.TinyConfig.fir@117917.4] assign _T_65 = 2'h1 << nBufValid; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@117869.4] assign bufMask = _T_65 - 2'h1; // @[IBuf.scala 75:37:freechips.rocketchip.system.TinyConfig.fir@117871.4] assign buf_replay = buf__replay ? bufMask : 2'h0; // @[IBuf.scala 77:23:freechips.rocketchip.system.TinyConfig.fir@117876.4] assign _T_97 = buf_replay[0]; // @[IBuf.scala 93:61:freechips.rocketchip.system.TinyConfig.fir@117919.4] assign _T_98 = _T_95 | _T_97; // @[IBuf.scala 93:48:freechips.rocketchip.system.TinyConfig.fir@117920.4] assign _T_128 = RVCExpander_io_rvc ? 2'h1 : 2'h2; // @[IBuf.scala 102:71:freechips.rocketchip.system.TinyConfig.fir@117964.6] assign nReady = _T_98 ? _T_128 : 2'h0; // @[IBuf.scala 102:56:freechips.rocketchip.system.TinyConfig.fir@117959.4] assign nICReady = nReady - _GEN_57; // @[IBuf.scala 42:25:freechips.rocketchip.system.TinyConfig.fir@117787.4] assign _T_6 = nReady >= _GEN_57; // @[IBuf.scala 44:47:freechips.rocketchip.system.TinyConfig.fir@117791.4] assign _T_7 = io_inst_0_ready & _T_6; // @[IBuf.scala 44:37:freechips.rocketchip.system.TinyConfig.fir@117792.4] assign _T_8 = nICReady >= nIC; // @[IBuf.scala 44:73:freechips.rocketchip.system.TinyConfig.fir@117793.4] assign _T_10 = nIC - nICReady; // @[IBuf.scala 44:92:freechips.rocketchip.system.TinyConfig.fir@117795.4] assign _T_11 = 2'h1 >= _T_10; // @[IBuf.scala 44:85:freechips.rocketchip.system.TinyConfig.fir@117796.4] assign _T_12 = _T_8 | _T_11; // @[IBuf.scala 44:80:freechips.rocketchip.system.TinyConfig.fir@117797.4] assign _T_16 = _GEN_57 - nReady; // @[IBuf.scala 48:64:freechips.rocketchip.system.TinyConfig.fir@117803.6] assign _T_17 = _T_6 ? 2'h0 : _T_16; // @[IBuf.scala 48:23:freechips.rocketchip.system.TinyConfig.fir@117804.6] assign _T_19 = io_imem_valid & _T_6; // @[IBuf.scala 54:27:freechips.rocketchip.system.TinyConfig.fir@117807.6] assign _T_20 = nICReady < nIC; // @[IBuf.scala 54:62:freechips.rocketchip.system.TinyConfig.fir@117808.6] assign _T_21 = _T_19 & _T_20; // @[IBuf.scala 54:50:freechips.rocketchip.system.TinyConfig.fir@117809.6] assign _T_25 = _T_21 & _T_11; // @[IBuf.scala 54:68:freechips.rocketchip.system.TinyConfig.fir@117813.6] assign _T_27 = _GEN_56 + nICReady; // @[IBuf.scala 55:32:freechips.rocketchip.system.TinyConfig.fir@117816.8] assign _T_30 = io_imem_bits_data[31:16]; // @[IBuf.scala 127:58:freechips.rocketchip.system.TinyConfig.fir@117821.8] assign _T_32 = {_T_30,_T_30,io_imem_bits_data}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117823.8] assign _T_33 = {_T_27, 4'h0}; // @[IBuf.scala 128:19:freechips.rocketchip.system.TinyConfig.fir@117824.8] assign _T_34 = _T_32 >> _T_33; // @[IBuf.scala 128:10:freechips.rocketchip.system.TinyConfig.fir@117825.8] assign _T_35 = _T_34[15:0]; // @[IBuf.scala 58:61:freechips.rocketchip.system.TinyConfig.fir@117826.8] assign _T_37 = io_imem_bits_pc & 32'hfffffffc; // @[IBuf.scala 59:35:freechips.rocketchip.system.TinyConfig.fir@117829.8] assign _T_38 = {nICReady, 1'h0}; // @[IBuf.scala 59:80:freechips.rocketchip.system.TinyConfig.fir@117830.8] assign _GEN_65 = {{29'd0}, _T_38}; // @[IBuf.scala 59:68:freechips.rocketchip.system.TinyConfig.fir@117831.8] assign _T_40 = io_imem_bits_pc + _GEN_65; // @[IBuf.scala 59:68:freechips.rocketchip.system.TinyConfig.fir@117832.8] assign _T_41 = _T_40 & 32'h3; // @[IBuf.scala 59:109:freechips.rocketchip.system.TinyConfig.fir@117833.8] assign _T_42 = _T_37 | _T_41; // @[IBuf.scala 59:49:freechips.rocketchip.system.TinyConfig.fir@117834.8] assign _GEN_0 = _T_25 ? _T_10 : _T_17; // @[IBuf.scala 54:92:freechips.rocketchip.system.TinyConfig.fir@117814.6] assign _GEN_23 = io_inst_0_ready ? _GEN_0 : {{1'd0}, nBufValid}; // @[IBuf.scala 47:29:freechips.rocketchip.system.TinyConfig.fir@117800.4] assign _GEN_46 = io_kill ? 2'h0 : _GEN_23; // @[IBuf.scala 63:20:freechips.rocketchip.system.TinyConfig.fir@117839.4] assign _T_44 = 2'h2 + _GEN_57; // @[IBuf.scala 68:32:freechips.rocketchip.system.TinyConfig.fir@117843.4] assign icShiftAmt = _T_44 - _GEN_56; // @[IBuf.scala 68:44:freechips.rocketchip.system.TinyConfig.fir@117845.4] assign _T_47 = io_imem_bits_data[15:0]; // @[IBuf.scala 69:87:freechips.rocketchip.system.TinyConfig.fir@117847.4] assign _T_49 = {io_imem_bits_data,_T_47,_T_47}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117849.4] assign _T_50 = _T_49[63:48]; // @[IBuf.scala 120:58:freechips.rocketchip.system.TinyConfig.fir@117850.4] assign _T_53 = {_T_50,_T_50,_T_50,_T_50,io_imem_bits_data,_T_47,_T_47}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@117853.4] assign _T_54 = {icShiftAmt, 4'h0}; // @[IBuf.scala 121:19:freechips.rocketchip.system.TinyConfig.fir@117854.4] assign _GEN_68 = {{63'd0}, _T_53}; // @[IBuf.scala 121:10:freechips.rocketchip.system.TinyConfig.fir@117855.4] assign _T_55 = _GEN_68 << _T_54; // @[IBuf.scala 121:10:freechips.rocketchip.system.TinyConfig.fir@117855.4] assign icData = _T_55[95:64]; // @[package.scala 120:13:freechips.rocketchip.system.TinyConfig.fir@117856.4] assign _T_57 = {nBufValid, 4'h0}; // @[IBuf.scala 71:65:freechips.rocketchip.system.TinyConfig.fir@117858.4] assign _T_58 = 63'hffffffff << _T_57; // @[IBuf.scala 71:51:freechips.rocketchip.system.TinyConfig.fir@117859.4] assign icMask = _T_58[31:0]; // @[IBuf.scala 71:92:freechips.rocketchip.system.TinyConfig.fir@117860.4] assign _T_59 = icData & icMask; // @[IBuf.scala 72:21:freechips.rocketchip.system.TinyConfig.fir@117861.4] assign _T_60 = ~ icMask; // @[IBuf.scala 72:43:freechips.rocketchip.system.TinyConfig.fir@117862.4] assign _T_61 = buf__data & _T_60; // @[IBuf.scala 72:41:freechips.rocketchip.system.TinyConfig.fir@117863.4] assign _T_67 = bufMask[0]; // @[IBuf.scala 76:61:freechips.rocketchip.system.TinyConfig.fir@117872.4] assign _T_68 = bufMask[1]; // @[IBuf.scala 76:61:freechips.rocketchip.system.TinyConfig.fir@117874.4] assign xcpt_1_ae_inst = _T_68 ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 76:53:freechips.rocketchip.system.TinyConfig.fir@117875.4] assign _T_69 = ~ bufMask; // @[IBuf.scala 78:65:freechips.rocketchip.system.TinyConfig.fir@117877.4] assign _T_70 = valid & _T_69; // @[IBuf.scala 78:63:freechips.rocketchip.system.TinyConfig.fir@117878.4] assign _T_71 = io_imem_bits_replay ? _T_70 : 2'h0; // @[IBuf.scala 78:35:freechips.rocketchip.system.TinyConfig.fir@117879.4] assign ic_replay = buf_replay | _T_71; // @[IBuf.scala 78:30:freechips.rocketchip.system.TinyConfig.fir@117880.4] assign _T_80 = nBufValid > 1'h0; // @[IBuf.scala 82:26:freechips.rocketchip.system.TinyConfig.fir@117894.4] assign _T_83 = ic_replay[0]; // @[IBuf.scala 92:29:freechips.rocketchip.system.TinyConfig.fir@117905.4] assign _T_84 = RVCExpander_io_rvc == 1'h0; // @[IBuf.scala 92:37:freechips.rocketchip.system.TinyConfig.fir@117906.4] assign _GEN_69 = ic_replay[1:1]; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117909.4] assign _T_87 = {{1'd0}, _GEN_69}; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117909.4] assign _T_88 = _T_87[0]; // @[IBuf.scala 92:61:freechips.rocketchip.system.TinyConfig.fir@117910.4] assign _T_89 = _T_84 & _T_88; // @[IBuf.scala 92:49:freechips.rocketchip.system.TinyConfig.fir@117911.4] assign _T_100 = valid[0]; // @[IBuf.scala 94:32:freechips.rocketchip.system.TinyConfig.fir@117922.4] assign _T_108 = {1'h0,xcpt_1_ae_inst}; // @[IBuf.scala 96:63:freechips.rocketchip.system.TinyConfig.fir@117932.4] assign _T_109 = RVCExpander_io_rvc ? 2'h0 : _T_108; // @[IBuf.scala 96:35:freechips.rocketchip.system.TinyConfig.fir@117933.4] assign io_imem_ready = _T_7 & _T_12; // @[IBuf.scala 44:17:freechips.rocketchip.system.TinyConfig.fir@117799.4] assign io_pc = _T_80 ? buf__pc : io_imem_bits_pc; // @[IBuf.scala 82:9:freechips.rocketchip.system.TinyConfig.fir@117896.4] assign io_inst_0_valid = _T_100 & _T_98; // @[IBuf.scala 94:24:freechips.rocketchip.system.TinyConfig.fir@117924.4] assign io_inst_0_bits_xcpt0_ae_inst = _T_67 ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 95:29:freechips.rocketchip.system.TinyConfig.fir@117927.4] assign io_inst_0_bits_xcpt1_pf_inst = _T_109[1]; // @[IBuf.scala 96:29:freechips.rocketchip.system.TinyConfig.fir@117943.4] assign io_inst_0_bits_xcpt1_ae_inst = _T_109[0]; // @[IBuf.scala 96:29:freechips.rocketchip.system.TinyConfig.fir@117943.4] assign io_inst_0_bits_replay = _T_83 | _T_89; // @[IBuf.scala 97:30:freechips.rocketchip.system.TinyConfig.fir@117944.4] assign io_inst_0_bits_rvc = RVCExpander_io_rvc; // @[IBuf.scala 98:27:freechips.rocketchip.system.TinyConfig.fir@117945.4] assign io_inst_0_bits_inst_bits = RVCExpander_io_out_bits; // @[IBuf.scala 88:26:freechips.rocketchip.system.TinyConfig.fir@117902.4] assign io_inst_0_bits_inst_rd = RVCExpander_io_out_rd; // @[IBuf.scala 88:26:freechips.rocketchip.system.TinyConfig.fir@117902.4] assign io_inst_0_bits_inst_rs1 = RVCExpander_io_out_rs1; // @[IBuf.scala 88:26:freechips.rocketchip.system.TinyConfig.fir@117902.4] assign io_inst_0_bits_inst_rs2 = RVCExpander_io_out_rs2; // @[IBuf.scala 88:26:freechips.rocketchip.system.TinyConfig.fir@117902.4] assign io_inst_0_bits_raw = _T_59 | _T_61; // @[IBuf.scala 89:25:freechips.rocketchip.system.TinyConfig.fir@117903.4] assign RVCExpander_io_in = _T_59 | _T_61; // @[IBuf.scala 87:15:freechips.rocketchip.system.TinyConfig.fir@117901.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; nBufValid = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; buf__pc = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; buf__data = _RAND_2[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; buf__xcpt_ae_inst = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; buf__replay = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin nBufValid <= 1'h0; end else begin nBufValid <= _GEN_46[0]; end if (io_inst_0_ready) begin if (_T_25) begin buf__pc <= _T_42; end end if (io_inst_0_ready) begin if (_T_25) begin buf__data <= {{16'd0}, _T_35}; end end if (io_inst_0_ready) begin if (_T_25) begin buf__xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst; end end if (io_inst_0_ready) begin if (_T_25) begin buf__replay <= io_imem_bits_replay; end end end endmodule module CSRFile( // @[:freechips.rocketchip.system.TinyConfig.fir@117976.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@117977.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@117978.4] input io_ungated_clock, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_interrupts_debug, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_interrupts_mtip, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_interrupts_msip, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_interrupts_meip, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [11:0] io_rw_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [2:0] io_rw_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_rw_rdata, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [31:0] io_rw_wdata, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [11:0] io_decode_0_csr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_decode_0_fp_illegal, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_decode_0_fp_csr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_decode_0_read_illegal, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_decode_0_write_illegal, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_decode_0_write_flush, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_csr_stall, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_eret, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_singleStep, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_debug, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_cease, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_status_isa, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_dprv, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_prv, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_sd, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [26:0] io_status_zero2, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_sxl, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_uxl, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_sd_rv32, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [7:0] io_status_zero1, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_tsr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_tw, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_tvm, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_mxr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_sum, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_mprv, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_xs, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_fs, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_mpp, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_status_hpp, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_spp, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_mpie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_hpie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_spie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_upie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_mie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_hie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_sie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_status_uie, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_evec, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_exception, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input io_retire, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [31:0] io_cause, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [31:0] io_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [31:0] io_tval, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_time, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_interrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_interrupt_cause, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_bp_0_control_action, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_bp_0_control_tmatch, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_bp_0_control_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_bp_0_control_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_bp_0_control_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_bp_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [1:0] io_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [29:0] io_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_pmp_7_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] input [31:0] io_inst_0, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_trace_0_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_trace_0_iaddr, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output [31:0] io_trace_0_insn, // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] output io_trace_0_exception // @[:freechips.rocketchip.system.TinyConfig.fir@117979.4] ); reg reg_mstatus_spp; // @[CSR.scala 238:24:freechips.rocketchip.system.TinyConfig.fir@118054.4] reg [31:0] _RAND_0; reg reg_mstatus_mpie; // @[CSR.scala 238:24:freechips.rocketchip.system.TinyConfig.fir@118054.4] reg [31:0] _RAND_1; reg reg_mstatus_mie; // @[CSR.scala 238:24:freechips.rocketchip.system.TinyConfig.fir@118054.4] reg [31:0] _RAND_2; reg reg_dcsr_ebreakm; // @[CSR.scala 246:21:freechips.rocketchip.system.TinyConfig.fir@118097.4] reg [31:0] _RAND_3; reg [2:0] reg_dcsr_cause; // @[CSR.scala 246:21:freechips.rocketchip.system.TinyConfig.fir@118097.4] reg [31:0] _RAND_4; reg reg_dcsr_step; // @[CSR.scala 246:21:freechips.rocketchip.system.TinyConfig.fir@118097.4] reg [31:0] _RAND_5; reg reg_debug; // @[CSR.scala 287:22:freechips.rocketchip.system.TinyConfig.fir@118153.4] reg [31:0] _RAND_6; reg [31:0] reg_dpc; // @[CSR.scala 288:20:freechips.rocketchip.system.TinyConfig.fir@118154.4] reg [31:0] _RAND_7; reg [31:0] reg_dscratch; // @[CSR.scala 289:25:freechips.rocketchip.system.TinyConfig.fir@118155.4] reg [31:0] _RAND_8; reg reg_singleStepped; // @[CSR.scala 290:30:freechips.rocketchip.system.TinyConfig.fir@118156.4] reg [31:0] _RAND_9; reg reg_bp_0_control_dmode; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_10; reg reg_bp_0_control_action; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_11; reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_12; reg reg_bp_0_control_x; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_13; reg reg_bp_0_control_w; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_14; reg reg_bp_0_control_r; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_15; reg [31:0] reg_bp_0_address; // @[CSR.scala 293:19:freechips.rocketchip.system.TinyConfig.fir@118158.4] reg [31:0] _RAND_16; reg reg_pmp_0_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_17; reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_18; reg reg_pmp_0_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_19; reg reg_pmp_0_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_20; reg reg_pmp_0_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_21; reg [29:0] reg_pmp_0_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_22; reg reg_pmp_1_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_23; reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_24; reg reg_pmp_1_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_25; reg reg_pmp_1_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_26; reg reg_pmp_1_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_27; reg [29:0] reg_pmp_1_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_28; reg reg_pmp_2_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_29; reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_30; reg reg_pmp_2_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_31; reg reg_pmp_2_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_32; reg reg_pmp_2_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_33; reg [29:0] reg_pmp_2_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_34; reg reg_pmp_3_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_35; reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_36; reg reg_pmp_3_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_37; reg reg_pmp_3_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_38; reg reg_pmp_3_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_39; reg [29:0] reg_pmp_3_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_40; reg reg_pmp_4_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_41; reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_42; reg reg_pmp_4_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_43; reg reg_pmp_4_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_44; reg reg_pmp_4_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_45; reg [29:0] reg_pmp_4_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_46; reg reg_pmp_5_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_47; reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_48; reg reg_pmp_5_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_49; reg reg_pmp_5_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_50; reg reg_pmp_5_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_51; reg [29:0] reg_pmp_5_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_52; reg reg_pmp_6_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_53; reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_54; reg reg_pmp_6_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_55; reg reg_pmp_6_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_56; reg reg_pmp_6_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_57; reg [29:0] reg_pmp_6_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_58; reg reg_pmp_7_cfg_l; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_59; reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_60; reg reg_pmp_7_cfg_x; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_61; reg reg_pmp_7_cfg_w; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_62; reg reg_pmp_7_cfg_r; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_63; reg [29:0] reg_pmp_7_addr; // @[CSR.scala 294:20:freechips.rocketchip.system.TinyConfig.fir@118159.4] reg [31:0] _RAND_64; reg [31:0] reg_mie; // @[CSR.scala 296:20:freechips.rocketchip.system.TinyConfig.fir@118160.4] reg [31:0] _RAND_65; reg [31:0] reg_mepc; // @[CSR.scala 306:21:freechips.rocketchip.system.TinyConfig.fir@118168.4] reg [31:0] _RAND_66; reg [31:0] reg_mcause; // @[CSR.scala 307:23:freechips.rocketchip.system.TinyConfig.fir@118169.4] reg [31:0] _RAND_67; reg [31:0] reg_mtval; // @[CSR.scala 308:22:freechips.rocketchip.system.TinyConfig.fir@118170.4] reg [31:0] _RAND_68; reg [31:0] reg_mscratch; // @[CSR.scala 309:25:freechips.rocketchip.system.TinyConfig.fir@118171.4] reg [31:0] _RAND_69; reg [31:0] reg_mtvec; // @[CSR.scala 312:27:freechips.rocketchip.system.TinyConfig.fir@118172.4] reg [31:0] _RAND_70; reg reg_wfi; // @[CSR.scala 332:50:freechips.rocketchip.system.TinyConfig.fir@118185.4] reg [31:0] _RAND_71; reg [5:0] _T_83; // @[Counters.scala 46:37:freechips.rocketchip.system.TinyConfig.fir@118188.4] reg [31:0] _RAND_72; wire [5:0] _GEN_415; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118189.4] wire [6:0] _T_84; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118189.4] reg [57:0] _T_85; // @[Counters.scala 51:27:freechips.rocketchip.system.TinyConfig.fir@118191.4] reg [63:0] _RAND_73; wire _T_86; // @[Counters.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@118192.4] wire [57:0] _T_88; // @[Counters.scala 52:43:freechips.rocketchip.system.TinyConfig.fir@118195.6] wire [63:0] _T_89; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118198.4] wire _T_90; // @[CSR.scala 338:103:freechips.rocketchip.system.TinyConfig.fir@118199.4] reg [5:0] _T_91; // @[Counters.scala 46:37:freechips.rocketchip.system.TinyConfig.fir@118200.4] reg [31:0] _RAND_74; wire [5:0] _GEN_416; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118201.4] wire [6:0] _T_92; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118201.4] reg [57:0] _T_93; // @[Counters.scala 51:27:freechips.rocketchip.system.TinyConfig.fir@118203.4] reg [63:0] _RAND_75; wire _T_94; // @[Counters.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@118204.4] wire [57:0] _T_96; // @[Counters.scala 52:43:freechips.rocketchip.system.TinyConfig.fir@118207.6] wire [63:0] _T_97; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118210.4] wire [15:0] _T_112; // @[CSR.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@118232.4] wire [15:0] read_mip; // @[CSR.scala 351:29:freechips.rocketchip.system.TinyConfig.fir@118233.4] wire [31:0] _GEN_417; // @[CSR.scala 354:56:freechips.rocketchip.system.TinyConfig.fir@118234.4] wire [31:0] pending_interrupts; // @[CSR.scala 354:56:freechips.rocketchip.system.TinyConfig.fir@118234.4] wire [14:0] d_interrupts; // @[CSR.scala 355:42:freechips.rocketchip.system.TinyConfig.fir@118236.4] wire [31:0] _T_116; // @[CSR.scala 356:73:freechips.rocketchip.system.TinyConfig.fir@118239.4] wire [31:0] _T_118; // @[CSR.scala 356:71:freechips.rocketchip.system.TinyConfig.fir@118241.4] wire [31:0] m_interrupts; // @[CSR.scala 356:25:freechips.rocketchip.system.TinyConfig.fir@118242.4] wire _T_124; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118249.4] wire _T_125; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118250.4] wire _T_126; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118251.4] wire _T_127; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118252.4] wire _T_128; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118253.4] wire _T_129; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118254.4] wire _T_130; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118255.4] wire _T_131; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118256.4] wire _T_132; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118257.4] wire _T_133; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118258.4] wire _T_134; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118259.4] wire _T_135; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118260.4] wire _T_136; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118261.4] wire _T_137; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118262.4] wire _T_138; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118263.4] wire _T_139; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118264.4] wire _T_140; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118265.4] wire _T_141; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118266.4] wire _T_142; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118267.4] wire _T_143; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118268.4] wire _T_144; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118269.4] wire _T_145; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118270.4] wire _T_146; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118271.4] wire _T_147; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118272.4] wire _T_148; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118273.4] wire _T_162; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118287.4] wire _T_163; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118288.4] wire _T_164; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118289.4] wire _T_165; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118290.4] wire _T_166; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118291.4] wire _T_167; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118292.4] wire _T_168; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118293.4] wire _T_169; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118294.4] wire _T_170; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118295.4] wire _T_171; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118296.4] wire _T_172; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118297.4] wire _T_173; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118298.4] wire _T_174; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118299.4] wire _T_175; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118300.4] wire _T_176; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118301.4] wire _T_177; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118302.4] wire _T_178; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118303.4] wire _T_179; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118304.4] wire _T_180; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118305.4] wire _T_181; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118306.4] wire _T_182; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118307.4] wire _T_183; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118308.4] wire _T_184; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118309.4] wire anyInterrupt; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118310.4] wire [3:0] _T_249; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118375.4] wire [3:0] _T_250; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118376.4] wire [3:0] _T_251; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118377.4] wire [3:0] _T_252; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118378.4] wire [3:0] _T_253; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118379.4] wire [3:0] _T_254; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118380.4] wire [3:0] _T_255; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118381.4] wire [3:0] _T_256; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118382.4] wire [3:0] _T_257; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118383.4] wire [3:0] _T_258; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118384.4] wire [3:0] _T_259; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118385.4] wire [3:0] _T_260; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118386.4] wire [3:0] _T_261; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118387.4] wire [3:0] _T_262; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118388.4] wire [3:0] _T_263; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118389.4] wire [3:0] _T_264; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118390.4] wire [3:0] _T_265; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118391.4] wire [3:0] _T_266; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118392.4] wire [3:0] _T_267; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118393.4] wire [3:0] _T_268; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118394.4] wire [3:0] _T_269; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118395.4] wire [3:0] _T_270; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118396.4] wire [3:0] _T_271; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118397.4] wire [3:0] whichInterrupt; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118398.4] wire [31:0] _GEN_418; // @[CSR.scala 360:43:freechips.rocketchip.system.TinyConfig.fir@118399.4] wire _T_273; // @[CSR.scala 361:36:freechips.rocketchip.system.TinyConfig.fir@118401.4] wire _T_274; // @[CSR.scala 361:33:freechips.rocketchip.system.TinyConfig.fir@118402.4] wire _T_275; // @[CSR.scala 361:51:freechips.rocketchip.system.TinyConfig.fir@118403.4] wire _T_276; // @[CSR.scala 361:88:freechips.rocketchip.system.TinyConfig.fir@118404.4] wire _T_277; // @[CSR.scala 361:76:freechips.rocketchip.system.TinyConfig.fir@118405.4] wire _T_280; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118413.4] wire [30:0] _T_281; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118414.4] wire [30:0] _T_284; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118417.4] wire [30:0] _T_285; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118418.4] wire [30:0] _T_286; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118419.4] wire [32:0] _T_287; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118420.4] wire _T_289; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118425.4] wire [30:0] _T_290; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118426.4] wire [30:0] _T_293; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118429.4] wire [30:0] _T_294; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118430.4] wire [30:0] _T_295; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118431.4] wire [32:0] _T_296; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118432.4] wire _T_298; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118437.4] wire [30:0] _T_299; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118438.4] wire [30:0] _T_302; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118441.4] wire [30:0] _T_303; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118442.4] wire [30:0] _T_304; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118443.4] wire [32:0] _T_305; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118444.4] wire _T_307; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118449.4] wire [30:0] _T_308; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118450.4] wire [30:0] _T_311; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118453.4] wire [30:0] _T_312; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118454.4] wire [30:0] _T_313; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118455.4] wire [32:0] _T_314; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118456.4] wire _T_316; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118461.4] wire [30:0] _T_317; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118462.4] wire [30:0] _T_320; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118465.4] wire [30:0] _T_321; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118466.4] wire [30:0] _T_322; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118467.4] wire [32:0] _T_323; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118468.4] wire _T_325; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118473.4] wire [30:0] _T_326; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118474.4] wire [30:0] _T_329; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118477.4] wire [30:0] _T_330; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118478.4] wire [30:0] _T_331; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118479.4] wire [32:0] _T_332; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118480.4] wire _T_334; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118485.4] wire [30:0] _T_335; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118486.4] wire [30:0] _T_338; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118489.4] wire [30:0] _T_339; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118490.4] wire [30:0] _T_340; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118491.4] wire [32:0] _T_341; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118492.4] wire _T_343; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118497.4] wire [30:0] _T_344; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118498.4] wire [30:0] _T_347; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118501.4] wire [30:0] _T_348; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118502.4] wire [30:0] _T_349; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118503.4] wire [32:0] _T_350; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118504.4] reg [31:0] reg_misa; // @[CSR.scala 378:21:freechips.rocketchip.system.TinyConfig.fir@118514.4] reg [31:0] _RAND_76; wire [6:0] _T_356; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118520.4] wire [18:0] _T_364; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118528.4] wire [14:0] _T_370; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118534.4] wire [101:0] _T_379; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118543.4] wire [31:0] read_mstatus; // @[CSR.scala 379:40:freechips.rocketchip.system.TinyConfig.fir@118544.4] wire _T_380; // @[CSR.scala 936:41:freechips.rocketchip.system.TinyConfig.fir@118545.4] wire [6:0] _T_381; // @[CSR.scala 936:39:freechips.rocketchip.system.TinyConfig.fir@118546.4] wire [31:0] _T_383; // @[package.scala 131:41:freechips.rocketchip.system.TinyConfig.fir@118548.4] wire [31:0] _T_384; // @[package.scala 131:37:freechips.rocketchip.system.TinyConfig.fir@118549.4] wire [31:0] read_mtvec; // @[package.scala 131:35:freechips.rocketchip.system.TinyConfig.fir@118550.4] wire [6:0] _T_395; // @[CSR.scala 385:48:freechips.rocketchip.system.TinyConfig.fir@118562.4] wire [31:0] _T_403; // @[CSR.scala 385:48:freechips.rocketchip.system.TinyConfig.fir@118570.4] wire [31:0] _T_404; // @[CSR.scala 935:28:freechips.rocketchip.system.TinyConfig.fir@118571.4] wire _T_405; // @[CSR.scala 935:45:freechips.rocketchip.system.TinyConfig.fir@118572.4] wire [1:0] _T_406; // @[CSR.scala 935:36:freechips.rocketchip.system.TinyConfig.fir@118573.4] wire [31:0] _GEN_419; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118574.4] wire [31:0] _T_407; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118574.4] wire [31:0] _T_408; // @[CSR.scala 935:26:freechips.rocketchip.system.TinyConfig.fir@118575.4] wire [31:0] _T_421; // @[CSR.scala 399:27:freechips.rocketchip.system.TinyConfig.fir@118588.4] wire [31:0] _T_422; // @[CSR.scala 935:28:freechips.rocketchip.system.TinyConfig.fir@118589.4] wire [31:0] _T_425; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118592.4] wire [31:0] _T_426; // @[CSR.scala 935:26:freechips.rocketchip.system.TinyConfig.fir@118593.4] wire [31:0] _T_457; // @[CSR.scala 436:50:freechips.rocketchip.system.TinyConfig.fir@118624.4] wire [31:0] _T_458; // @[CSR.scala 437:54:freechips.rocketchip.system.TinyConfig.fir@118625.4] wire [7:0] _T_473; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118651.4] wire [7:0] _T_483; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118661.4] wire [15:0] _T_489; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118667.4] wire [31:0] _T_491; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118669.4] wire [7:0] _T_496; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118674.4] wire [7:0] _T_506; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118684.4] wire [15:0] _T_512; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118690.4] wire [31:0] _T_514; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118692.4] wire _T_562; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118744.4] wire _T_563; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118745.4] wire _T_564; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118746.4] wire _T_565; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118747.4] wire _T_566; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118748.4] wire _T_567; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118749.4] wire _T_568; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118750.4] wire _T_569; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118751.4] wire _T_570; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118752.4] wire _T_571; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118753.4] wire _T_572; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118754.4] wire _T_574; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118756.4] wire _T_575; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118757.4] wire _T_576; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118758.4] wire _T_577; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118759.4] wire _T_578; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118760.4] wire _T_666; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118848.4] wire _T_667; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118849.4] wire _T_668; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118850.4] wire _T_669; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118851.4] wire _T_672; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118854.4] wire _T_673; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118855.4] wire _T_674; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118856.4] wire _T_675; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118857.4] wire _T_676; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118858.4] wire _T_677; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118859.4] wire _T_678; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118860.4] wire _T_679; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118861.4] wire _T_689; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118871.4] wire _T_691; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118873.4] wire _T_692; // @[CSR.scala 913:13:freechips.rocketchip.system.TinyConfig.fir@118874.4] wire [31:0] _T_693; // @[CSR.scala 913:9:freechips.rocketchip.system.TinyConfig.fir@118875.4] wire [31:0] _T_694; // @[CSR.scala 913:34:freechips.rocketchip.system.TinyConfig.fir@118876.4] wire [1:0] _T_695; // @[CSR.scala 913:53:freechips.rocketchip.system.TinyConfig.fir@118877.4] wire _T_696; // @[CSR.scala 913:59:freechips.rocketchip.system.TinyConfig.fir@118878.4] wire [31:0] _T_697; // @[CSR.scala 913:49:freechips.rocketchip.system.TinyConfig.fir@118879.4] wire [31:0] _T_698; // @[CSR.scala 913:45:freechips.rocketchip.system.TinyConfig.fir@118880.4] wire [31:0] wdata; // @[CSR.scala 913:43:freechips.rocketchip.system.TinyConfig.fir@118881.4] wire system_insn; // @[CSR.scala 500:31:freechips.rocketchip.system.TinyConfig.fir@118882.4] wire [31:0] _T_699; // @[CSR.scala 512:28:freechips.rocketchip.system.TinyConfig.fir@118883.4] wire [31:0] _T_700; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118884.4] wire _T_701; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118885.4] wire [31:0] _T_703; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118887.4] wire _T_704; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118888.4] wire [31:0] _T_706; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118890.4] wire _T_707; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118891.4] wire [31:0] _T_709; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118893.4] wire _T_710; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118894.4] wire [31:0] _T_712; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118896.4] wire _T_713; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118897.4] wire insn_call; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118900.4] wire insn_break; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118902.4] wire insn_ret; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118904.4] wire insn_cease; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118906.4] wire insn_wfi; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118908.4] wire _T_764; // @[CSR.scala 524:39:freechips.rocketchip.system.TinyConfig.fir@118954.4] wire _T_765; // @[CSR.scala 524:57:freechips.rocketchip.system.TinyConfig.fir@118955.4] wire _T_766; // @[CSR.scala 524:48:freechips.rocketchip.system.TinyConfig.fir@118956.4] wire _T_779; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118972.4] wire _T_780; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118973.4] wire _T_781; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118974.4] wire _T_782; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118975.4] wire _T_783; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118976.4] wire _T_784; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118977.4] wire _T_785; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118978.4] wire _T_786; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118979.4] wire _T_787; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118980.4] wire _T_788; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118981.4] wire _T_789; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118982.4] wire _T_790; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118983.4] wire _T_791; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118984.4] wire _T_792; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118985.4] wire _T_793; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118986.4] wire _T_794; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118987.4] wire _T_795; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118988.4] wire _T_796; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118989.4] wire _T_797; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118990.4] wire _T_798; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118991.4] wire _T_799; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118992.4] wire _T_800; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118993.4] wire _T_801; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118994.4] wire _T_802; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118995.4] wire _T_803; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118996.4] wire _T_804; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118997.4] wire _T_805; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118998.4] wire _T_806; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118999.4] wire _T_807; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119000.4] wire _T_808; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119001.4] wire _T_809; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119002.4] wire _T_810; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119003.4] wire _T_811; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119004.4] wire _T_812; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119005.4] wire _T_813; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119006.4] wire _T_814; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119007.4] wire _T_815; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119008.4] wire _T_816; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119009.4] wire _T_817; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119010.4] wire _T_818; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119011.4] wire _T_819; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119012.4] wire _T_820; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119013.4] wire _T_821; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119014.4] wire _T_822; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119015.4] wire _T_823; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119016.4] wire _T_824; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119017.4] wire _T_825; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119018.4] wire _T_826; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119019.4] wire _T_827; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119020.4] wire _T_828; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119021.4] wire _T_829; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119022.4] wire _T_830; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119023.4] wire _T_831; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119024.4] wire _T_832; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119025.4] wire _T_833; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119026.4] wire _T_834; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119027.4] wire _T_835; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119028.4] wire _T_836; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119029.4] wire _T_837; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119030.4] wire _T_838; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119031.4] wire _T_839; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119032.4] wire _T_840; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119033.4] wire _T_841; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119034.4] wire _T_842; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119035.4] wire _T_843; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119036.4] wire _T_844; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119037.4] wire _T_845; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119038.4] wire _T_846; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119039.4] wire _T_847; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119040.4] wire _T_848; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119041.4] wire _T_849; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119042.4] wire _T_850; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119043.4] wire _T_851; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119044.4] wire _T_852; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119045.4] wire _T_853; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119046.4] wire _T_854; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119047.4] wire _T_855; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119048.4] wire _T_856; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119049.4] wire _T_857; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119050.4] wire _T_858; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119051.4] wire _T_859; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119052.4] wire _T_860; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119053.4] wire _T_861; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119054.4] wire _T_862; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119055.4] wire _T_863; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119056.4] wire _T_864; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119057.4] wire _T_865; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119058.4] wire _T_866; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119059.4] wire _T_867; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119060.4] wire _T_868; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119061.4] wire _T_869; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119062.4] wire _T_870; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119063.4] wire _T_871; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119064.4] wire _T_872; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119065.4] wire _T_873; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119066.4] wire _T_874; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119067.4] wire _T_875; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119068.4] wire _T_876; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119069.4] wire _T_877; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119070.4] wire _T_878; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119071.4] wire _T_879; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119072.4] wire _T_880; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119073.4] wire _T_881; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119074.4] wire _T_882; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119075.4] wire _T_883; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119076.4] wire _T_884; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119077.4] wire _T_885; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119078.4] wire _T_886; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119079.4] wire _T_887; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119080.4] wire _T_888; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119081.4] wire _T_889; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119082.4] wire _T_890; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119083.4] wire _T_891; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119084.4] wire _T_892; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119085.4] wire _T_893; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119086.4] wire _T_894; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119087.4] wire _T_895; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119088.4] wire _T_896; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119089.4] wire _T_897; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119090.4] wire _T_898; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119091.4] wire _T_899; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119092.4] wire _T_900; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119093.4] wire _T_901; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119094.4] wire _T_902; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119095.4] wire _T_903; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119096.4] wire _T_904; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119097.4] wire _T_905; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119098.4] wire _T_906; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119099.4] wire _T_907; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119100.4] wire _T_908; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119101.4] wire _T_909; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119102.4] wire _T_910; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119103.4] wire _T_911; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119104.4] wire _T_912; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119105.4] wire _T_913; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119106.4] wire _T_914; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119107.4] wire _T_915; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119108.4] wire _T_916; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119109.4] wire _T_917; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119110.4] wire _T_918; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119111.4] wire _T_919; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119112.4] wire _T_920; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119113.4] wire _T_921; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119114.4] wire _T_922; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119115.4] wire _T_923; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119116.4] wire _T_924; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119117.4] wire _T_925; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119118.4] wire _T_926; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119119.4] wire _T_927; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119120.4] wire _T_928; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119121.4] wire _T_929; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119122.4] wire _T_930; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119123.4] wire _T_931; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119124.4] wire _T_932; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119125.4] wire _T_933; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119126.4] wire _T_934; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119127.4] wire _T_935; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119128.4] wire _T_936; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119129.4] wire _T_937; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119130.4] wire _T_938; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119131.4] wire _T_939; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119132.4] wire _T_940; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119133.4] wire _T_941; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119134.4] wire _T_942; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119135.4] wire _T_943; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119136.4] wire _T_944; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119137.4] wire _T_945; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119138.4] wire _T_946; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119139.4] wire _T_947; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119140.4] wire _T_948; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119141.4] wire _T_949; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119142.4] wire _T_950; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119143.4] wire _T_951; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119144.4] wire _T_952; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119145.4] wire _T_953; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119146.4] wire _T_954; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119147.4] wire _T_955; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119148.4] wire _T_956; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119149.4] wire _T_957; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119150.4] wire _T_958; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119151.4] wire _T_959; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119152.4] wire _T_960; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119153.4] wire _T_961; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119154.4] wire _T_962; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119155.4] wire _T_963; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119156.4] wire _T_964; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119157.4] wire _T_965; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119158.4] wire _T_966; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119159.4] wire _T_967; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119160.4] wire _T_968; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119161.4] wire _T_969; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119162.4] wire _T_970; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119163.4] wire _T_971; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119164.4] wire _T_972; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119165.4] wire _T_973; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119166.4] wire _T_974; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119167.4] wire _T_975; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119168.4] wire _T_976; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119169.4] wire _T_977; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119170.4] wire _T_978; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119171.4] wire _T_979; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119172.4] wire _T_980; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119173.4] wire _T_981; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119174.4] wire _T_982; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119175.4] wire _T_983; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119176.4] wire _T_984; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119177.4] wire _T_985; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119178.4] wire _T_986; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119179.4] wire _T_987; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119180.4] wire _T_988; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119181.4] wire _T_989; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119182.4] wire _T_990; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119183.4] wire _T_991; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119184.4] wire _T_992; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119185.4] wire _T_993; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119186.4] wire _T_994; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119187.4] wire _T_995; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119188.4] wire _T_996; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119189.4] wire _T_997; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119190.4] wire _T_998; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119191.4] wire _T_999; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119192.4] wire _T_1000; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119193.4] wire _T_1001; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119194.4] wire _T_1002; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119195.4] wire _T_1003; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119196.4] wire _T_1004; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119197.4] wire _T_1005; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119198.4] wire _T_1006; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119199.4] wire _T_1007; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119200.4] wire _T_1008; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119201.4] wire _T_1009; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119202.4] wire _T_1010; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119203.4] wire _T_1011; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119204.4] wire _T_1012; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119205.4] wire _T_1013; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119206.4] wire _T_1014; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119207.4] wire _T_1015; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119208.4] wire _T_1016; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119209.4] wire _T_1017; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119210.4] wire _T_1018; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119211.4] wire _T_1019; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119212.4] wire _T_1020; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119213.4] wire _T_1021; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119214.4] wire _T_1022; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119215.4] wire _T_1023; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119216.4] wire _T_1024; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119217.4] wire _T_1025; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119218.4] wire _T_1026; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119219.4] wire _T_1027; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119220.4] wire _T_1028; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119221.4] wire _T_1029; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119222.4] wire _T_1030; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119223.4] wire _T_1031; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119224.4] wire _T_1032; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119225.4] wire _T_1033; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119226.4] wire _T_1034; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119227.4] wire _T_1035; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119228.4] wire _T_1036; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119229.4] wire _T_1037; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119230.4] wire _T_1038; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119231.4] wire _T_1039; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119232.4] wire _T_1040; // @[CSR.scala 528:7:freechips.rocketchip.system.TinyConfig.fir@119233.4] wire _T_1059; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119252.4] wire _T_1060; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119253.4] wire _T_1062; // @[CSR.scala 531:52:freechips.rocketchip.system.TinyConfig.fir@119255.4] wire _T_1063; // @[CSR.scala 531:49:freechips.rocketchip.system.TinyConfig.fir@119256.4] wire _T_1064; // @[CSR.scala 530:148:freechips.rocketchip.system.TinyConfig.fir@119257.4] wire _T_1065; // @[CSR.scala 532:21:freechips.rocketchip.system.TinyConfig.fir@119258.4] wire [1:0] _T_1067; // @[CSR.scala 533:39:freechips.rocketchip.system.TinyConfig.fir@119261.4] wire _T_1069; // @[CSR.scala 534:40:freechips.rocketchip.system.TinyConfig.fir@119264.4] wire _T_1070; // @[CSR.scala 534:71:freechips.rocketchip.system.TinyConfig.fir@119265.4] wire _T_1071; // @[CSR.scala 534:57:freechips.rocketchip.system.TinyConfig.fir@119266.4] wire _T_1072; // @[CSR.scala 534:99:freechips.rocketchip.system.TinyConfig.fir@119267.4] wire _T_1073; // @[CSR.scala 534:130:freechips.rocketchip.system.TinyConfig.fir@119268.4] wire _T_1074; // @[CSR.scala 534:116:freechips.rocketchip.system.TinyConfig.fir@119269.4] wire _T_1075; // @[CSR.scala 534:85:freechips.rocketchip.system.TinyConfig.fir@119270.4] wire [31:0] _T_1090; // @[CSR.scala 543:14:freechips.rocketchip.system.TinyConfig.fir@119287.4] wire [31:0] cause; // @[CSR.scala 542:8:freechips.rocketchip.system.TinyConfig.fir@119288.4] wire [7:0] cause_lsbs; // @[CSR.scala 544:25:freechips.rocketchip.system.TinyConfig.fir@119289.4] wire _T_1091; // @[CSR.scala 545:30:freechips.rocketchip.system.TinyConfig.fir@119290.4] wire _T_1092; // @[CSR.scala 545:53:freechips.rocketchip.system.TinyConfig.fir@119291.4] wire causeIsDebugInt; // @[CSR.scala 545:39:freechips.rocketchip.system.TinyConfig.fir@119292.4] wire _T_1094; // @[CSR.scala 546:29:freechips.rocketchip.system.TinyConfig.fir@119294.4] wire causeIsDebugTrigger; // @[CSR.scala 546:44:freechips.rocketchip.system.TinyConfig.fir@119296.4] wire _T_1098; // @[CSR.scala 547:42:freechips.rocketchip.system.TinyConfig.fir@119299.4] wire [3:0] _T_1101; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@119302.4] wire _GEN_421; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119303.4] wire [3:0] _T_1102; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119303.4] wire _T_1103; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119304.4] wire causeIsDebugBreak; // @[CSR.scala 547:56:freechips.rocketchip.system.TinyConfig.fir@119305.4] wire _T_1104; // @[CSR.scala 548:60:freechips.rocketchip.system.TinyConfig.fir@119306.4] wire _T_1105; // @[CSR.scala 548:79:freechips.rocketchip.system.TinyConfig.fir@119307.4] wire _T_1106; // @[CSR.scala 548:102:freechips.rocketchip.system.TinyConfig.fir@119308.4] wire trapToDebug; // @[CSR.scala 548:123:freechips.rocketchip.system.TinyConfig.fir@119309.4] wire [11:0] _T_1108; // @[CSR.scala 549:37:freechips.rocketchip.system.TinyConfig.fir@119311.4] wire [11:0] debugTVec; // @[CSR.scala 549:22:freechips.rocketchip.system.TinyConfig.fir@119312.4] wire [4:0] _T_1118; // @[CSR.scala 558:32:freechips.rocketchip.system.TinyConfig.fir@119323.4] wire [6:0] _T_1119; // @[CSR.scala 558:59:freechips.rocketchip.system.TinyConfig.fir@119324.4] wire [24:0] _T_1120; // @[CSR.scala 559:33:freechips.rocketchip.system.TinyConfig.fir@119325.4] wire [31:0] _T_1121; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@119326.4] wire _T_1122; // @[CSR.scala 560:24:freechips.rocketchip.system.TinyConfig.fir@119327.4] wire _T_1124; // @[CSR.scala 560:28:freechips.rocketchip.system.TinyConfig.fir@119329.4] wire [2:0] _T_1125; // @[CSR.scala 560:70:freechips.rocketchip.system.TinyConfig.fir@119330.4] wire _T_1126; // @[CSR.scala 560:94:freechips.rocketchip.system.TinyConfig.fir@119331.4] wire _T_1127; // @[CSR.scala 560:55:freechips.rocketchip.system.TinyConfig.fir@119332.4] wire [29:0] _T_1128; // @[CSR.scala 561:38:freechips.rocketchip.system.TinyConfig.fir@119333.4] wire [31:0] _T_1129; // @[CSR.scala 561:56:freechips.rocketchip.system.TinyConfig.fir@119334.4] wire [31:0] notDebugTVec; // @[CSR.scala 561:8:freechips.rocketchip.system.TinyConfig.fir@119335.4] wire [31:0] tvec; // @[CSR.scala 563:17:freechips.rocketchip.system.TinyConfig.fir@119336.4] wire _T_1130; // @[CSR.scala 566:24:freechips.rocketchip.system.TinyConfig.fir@119339.4] wire _T_1134; // @[CSR.scala 569:32:freechips.rocketchip.system.TinyConfig.fir@119346.4] wire _T_1135; // @[CSR.scala 569:53:freechips.rocketchip.system.TinyConfig.fir@119347.4] wire exception; // @[CSR.scala 578:43:freechips.rocketchip.system.TinyConfig.fir@119362.4] wire [1:0] _T_1142; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119363.4] wire [1:0] _T_1144; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119365.4] wire [2:0] _T_1146; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119367.4] wire _T_1148; // @[CSR.scala 579:79:freechips.rocketchip.system.TinyConfig.fir@119369.4] wire _T_1150; // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119371.4] wire _T_1151; // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119372.4] wire _T_1153; // @[CSR.scala 581:18:freechips.rocketchip.system.TinyConfig.fir@119378.4] wire _T_1155; // @[CSR.scala 581:36:freechips.rocketchip.system.TinyConfig.fir@119380.4] wire _T_1156; // @[CSR.scala 582:28:freechips.rocketchip.system.TinyConfig.fir@119384.4] wire _T_1157; // @[CSR.scala 582:32:freechips.rocketchip.system.TinyConfig.fir@119385.4] wire _T_1158; // @[CSR.scala 582:55:freechips.rocketchip.system.TinyConfig.fir@119386.4] wire _T_1160; // @[CSR.scala 584:22:freechips.rocketchip.system.TinyConfig.fir@119391.4] wire _T_1168; // @[CSR.scala 587:10:freechips.rocketchip.system.TinyConfig.fir@119409.4] wire _T_1169; // @[CSR.scala 587:42:freechips.rocketchip.system.TinyConfig.fir@119410.4] wire _T_1170; // @[CSR.scala 587:29:freechips.rocketchip.system.TinyConfig.fir@119411.4] wire _T_1172; // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119413.4] wire _T_1173; // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119414.4] wire [31:0] _T_1174; // @[CSR.scala 934:28:freechips.rocketchip.system.TinyConfig.fir@119419.4] wire [31:0] _T_1175; // @[CSR.scala 934:31:freechips.rocketchip.system.TinyConfig.fir@119420.4] wire [31:0] epc; // @[CSR.scala 934:26:freechips.rocketchip.system.TinyConfig.fir@119421.4] wire [1:0] _T_1177; // @[CSR.scala 598:86:freechips.rocketchip.system.TinyConfig.fir@119431.10] wire [1:0] _T_1178; // @[CSR.scala 598:56:freechips.rocketchip.system.TinyConfig.fir@119432.10] wire [1:0] _GEN_48; // @[CSR.scala 602:27:freechips.rocketchip.system.TinyConfig.fir@119440.8] wire [1:0] _GEN_67; // @[CSR.scala 594:24:freechips.rocketchip.system.TinyConfig.fir@119426.6] wire [1:0] _GEN_85; // @[CSR.scala 593:20:freechips.rocketchip.system.TinyConfig.fir@119425.4] wire _T_1468; // @[CSR.scala 649:47:freechips.rocketchip.system.TinyConfig.fir@119758.8] wire [31:0] _GEN_95; // @[CSR.scala 649:53:freechips.rocketchip.system.TinyConfig.fir@119760.8] reg _T_1481; // @[Reg.scala 27:20:freechips.rocketchip.system.TinyConfig.fir@119786.4] reg [31:0] _RAND_77; wire [31:0] _T_1483; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119804.4] wire [31:0] _T_1484; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119805.4] wire [31:0] _T_1485; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119806.4] wire [31:0] _T_1486; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119807.4] wire [31:0] _T_1487; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119808.4] wire [15:0] _T_1488; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119809.4] wire [31:0] _T_1489; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119810.4] wire [31:0] _T_1490; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119811.4] wire [31:0] _T_1491; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119812.4] wire [31:0] _T_1492; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119813.4] wire [31:0] _T_1493; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119814.4] wire [31:0] _T_1495; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119816.4] wire [31:0] _T_1496; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119817.4] wire [31:0] _T_1497; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119818.4] wire [63:0] _T_1498; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119819.4] wire [63:0] _T_1499; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119820.4] wire [31:0] _T_1587; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119908.4] wire [31:0] _T_1588; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119909.4] wire [31:0] _T_1589; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119910.4] wire [31:0] _T_1590; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119911.4] wire [29:0] _T_1593; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119914.4] wire [29:0] _T_1594; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119915.4] wire [29:0] _T_1595; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119916.4] wire [29:0] _T_1596; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119917.4] wire [29:0] _T_1597; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119918.4] wire [29:0] _T_1598; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119919.4] wire [29:0] _T_1599; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119920.4] wire [29:0] _T_1600; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119921.4] wire [31:0] _T_1610; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119931.4] wire [31:0] _T_1612; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119933.4] wire [31:0] _T_1614; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119935.4] wire [31:0] _T_1615; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119936.4] wire [31:0] _T_1616; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119937.4] wire [31:0] _T_1617; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119938.4] wire [31:0] _GEN_424; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119939.4] wire [31:0] _T_1618; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119939.4] wire [31:0] _T_1619; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119940.4] wire [31:0] _T_1620; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119941.4] wire [31:0] _T_1621; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119942.4] wire [31:0] _T_1622; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119943.4] wire [31:0] _T_1623; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119944.4] wire [31:0] _T_1625; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119946.4] wire [31:0] _T_1626; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119947.4] wire [31:0] _T_1627; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119948.4] wire [63:0] _GEN_425; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119949.4] wire [63:0] _T_1628; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119949.4] wire [63:0] _T_1629; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119950.4] wire [63:0] _GEN_426; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120038.4] wire [63:0] _T_1717; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120038.4] wire [63:0] _GEN_427; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120039.4] wire [63:0] _T_1718; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120039.4] wire [63:0] _GEN_428; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120040.4] wire [63:0] _T_1719; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120040.4] wire [63:0] _GEN_429; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120041.4] wire [63:0] _T_1720; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120041.4] wire [63:0] _GEN_430; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120044.4] wire [63:0] _T_1723; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120044.4] wire [63:0] _GEN_431; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120045.4] wire [63:0] _T_1724; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120045.4] wire [63:0] _GEN_432; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120046.4] wire [63:0] _T_1725; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120046.4] wire [63:0] _GEN_433; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120047.4] wire [63:0] _T_1726; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120047.4] wire [63:0] _GEN_434; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120048.4] wire [63:0] _T_1727; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120048.4] wire [63:0] _GEN_435; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120049.4] wire [63:0] _T_1728; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120049.4] wire [63:0] _GEN_436; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120050.4] wire [63:0] _T_1729; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120050.4] wire [63:0] _GEN_437; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120051.4] wire [63:0] _T_1730; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120051.4] wire [63:0] _GEN_438; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120061.4] wire [63:0] _T_1740; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120061.4] wire [63:0] _GEN_439; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120063.4] wire [63:0] _T_1742; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120063.4] wire _T_1746; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120070.6] wire _T_1747; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120071.6] wire _T_1748; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120072.6] wire _T_3320; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@122175.4] wire csr_wen; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@122176.4] wire [101:0] _T_3334; // @[:freechips.rocketchip.system.TinyConfig.fir@122194.8 :freechips.rocketchip.system.TinyConfig.fir@122196.8] wire _T_3338; // @[CSR.scala 701:47:freechips.rocketchip.system.TinyConfig.fir@122203.8] wire _T_3342; // @[CSR.scala 701:47:freechips.rocketchip.system.TinyConfig.fir@122211.8] wire _T_3365; // @[CSR.scala 725:20:freechips.rocketchip.system.TinyConfig.fir@122261.8] wire _T_3366; // @[CSR.scala 727:39:freechips.rocketchip.system.TinyConfig.fir@122262.8] wire _T_3367; // @[CSR.scala 727:33:freechips.rocketchip.system.TinyConfig.fir@122263.8] wire _T_3369; // @[CSR.scala 727:51:freechips.rocketchip.system.TinyConfig.fir@122265.8] wire _T_3370; // @[CSR.scala 727:43:freechips.rocketchip.system.TinyConfig.fir@122266.8] wire [31:0] _T_3371; // @[CSR.scala 729:25:freechips.rocketchip.system.TinyConfig.fir@122268.10] wire _T_3372; // @[CSR.scala 729:35:freechips.rocketchip.system.TinyConfig.fir@122269.10] wire [3:0] _T_3373; // @[CSR.scala 729:38:freechips.rocketchip.system.TinyConfig.fir@122270.10] wire [31:0] _GEN_440; // @[CSR.scala 729:32:freechips.rocketchip.system.TinyConfig.fir@122271.10] wire [31:0] _T_3374; // @[CSR.scala 729:32:freechips.rocketchip.system.TinyConfig.fir@122271.10] wire [31:0] _T_3375; // @[CSR.scala 729:23:freechips.rocketchip.system.TinyConfig.fir@122272.10] wire [31:0] _T_3376; // @[CSR.scala 729:55:freechips.rocketchip.system.TinyConfig.fir@122273.10] wire [31:0] _T_3378; // @[CSR.scala 729:73:freechips.rocketchip.system.TinyConfig.fir@122275.10] wire [31:0] _T_3379; // @[CSR.scala 729:62:freechips.rocketchip.system.TinyConfig.fir@122276.10] wire [31:0] _T_3421; // @[CSR.scala 744:59:freechips.rocketchip.system.TinyConfig.fir@122343.8] wire [31:0] _T_3423; // @[CSR.scala 934:31:freechips.rocketchip.system.TinyConfig.fir@122348.8] wire [31:0] _T_3424; // @[CSR.scala 934:26:freechips.rocketchip.system.TinyConfig.fir@122349.8] wire [31:0] _T_3425; // @[CSR.scala 749:62:freechips.rocketchip.system.TinyConfig.fir@122359.8] wire [31:0] _T_3427; // @[CSR.scala 928:47:freechips.rocketchip.system.TinyConfig.fir@122367.8] wire [63:0] _T_3428; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122368.8] wire [57:0] _T_3429; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122370.8] wire [63:0] _GEN_130; // @[CSR.scala 928:31:freechips.rocketchip.system.TinyConfig.fir@122366.6] wire [31:0] _T_3431; // @[CSR.scala 929:74:freechips.rocketchip.system.TinyConfig.fir@122375.8] wire [63:0] _T_3432; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122376.8] wire [57:0] _T_3433; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122378.8] wire [63:0] _GEN_132; // @[CSR.scala 929:31:freechips.rocketchip.system.TinyConfig.fir@122373.6] wire [31:0] _T_3434; // @[CSR.scala 928:47:freechips.rocketchip.system.TinyConfig.fir@122382.8] wire [63:0] _T_3435; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122383.8] wire [57:0] _T_3436; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122385.8] wire [63:0] _GEN_134; // @[CSR.scala 928:31:freechips.rocketchip.system.TinyConfig.fir@122381.6] wire [31:0] _T_3438; // @[CSR.scala 929:74:freechips.rocketchip.system.TinyConfig.fir@122390.8] wire [63:0] _T_3439; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122391.8] wire [57:0] _T_3440; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122393.8] wire [63:0] _GEN_136; // @[CSR.scala 929:31:freechips.rocketchip.system.TinyConfig.fir@122388.6] wire _T_3453; // @[CSR.scala 768:43:freechips.rocketchip.system.TinyConfig.fir@122422.8] wire _T_3461; // @[CSR.scala 819:37:freechips.rocketchip.system.TinyConfig.fir@122446.6] wire _T_3462; // @[CSR.scala 819:55:freechips.rocketchip.system.TinyConfig.fir@122447.6] wire _T_3466; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122459.10] wire _T_3467; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122461.10] wire [1:0] _T_3473; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122473.10] wire [31:0] _T_3496; // @[CSR.scala 913:9:freechips.rocketchip.system.TinyConfig.fir@122505.10] wire [31:0] _T_3497; // @[CSR.scala 913:34:freechips.rocketchip.system.TinyConfig.fir@122506.10] wire [31:0] _T_3502; // @[CSR.scala 913:43:freechips.rocketchip.system.TinyConfig.fir@122511.10] wire _T_3515; // @[CSR.scala 828:96:freechips.rocketchip.system.TinyConfig.fir@122537.10] wire _T_3518; // @[CSR.scala 828:96:freechips.rocketchip.system.TinyConfig.fir@122543.10] wire _T_3520; // @[CSR.scala 829:38:freechips.rocketchip.system.TinyConfig.fir@122547.10] wire _T_3604; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122693.6] wire _T_3605; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122694.6] wire [7:0] _T_3608; // @[:freechips.rocketchip.system.TinyConfig.fir@122699.8 :freechips.rocketchip.system.TinyConfig.fir@122701.8] wire _T_3609; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122702.8] wire _T_3610; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122704.8] wire _T_3611; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122706.8] wire [1:0] _T_3612; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122708.8] wire _T_3614; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122712.8] wire _T_3615; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122715.8] wire _T_3616; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122718.6] wire _T_3617; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122719.6] wire _T_3619; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122721.6] wire _T_3620; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122722.6] wire _T_3621; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122723.6] wire _T_3622; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122724.6] wire _T_3623; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122725.6] wire [31:0] _GEN_215; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122726.6] wire _T_3624; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122729.6] wire _T_3625; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122730.6] wire [23:0] _T_3626; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122732.8] wire [7:0] _T_3628; // @[:freechips.rocketchip.system.TinyConfig.fir@122735.8 :freechips.rocketchip.system.TinyConfig.fir@122737.8] wire _T_3629; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122738.8] wire _T_3630; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122740.8] wire _T_3631; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122742.8] wire [1:0] _T_3632; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122744.8] wire _T_3634; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122748.8] wire _T_3635; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122751.8] wire _T_3636; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122754.6] wire _T_3637; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122755.6] wire _T_3639; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122757.6] wire _T_3640; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122758.6] wire _T_3641; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122759.6] wire _T_3642; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122760.6] wire _T_3643; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122761.6] wire [31:0] _GEN_222; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122762.6] wire _T_3644; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122765.6] wire _T_3645; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122766.6] wire [15:0] _T_3646; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122768.8] wire [7:0] _T_3648; // @[:freechips.rocketchip.system.TinyConfig.fir@122771.8 :freechips.rocketchip.system.TinyConfig.fir@122773.8] wire _T_3649; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122774.8] wire _T_3650; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122776.8] wire _T_3651; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122778.8] wire [1:0] _T_3652; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122780.8] wire _T_3654; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122784.8] wire _T_3655; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122787.8] wire _T_3656; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122790.6] wire _T_3657; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122791.6] wire _T_3659; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122793.6] wire _T_3660; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122794.6] wire _T_3661; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122795.6] wire _T_3662; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122796.6] wire _T_3663; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122797.6] wire [31:0] _GEN_229; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122798.6] wire _T_3664; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122801.6] wire _T_3665; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122802.6] wire [7:0] _T_3666; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122804.8] wire _T_3669; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122810.8] wire _T_3670; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122812.8] wire _T_3671; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122814.8] wire [1:0] _T_3672; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122816.8] wire _T_3674; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122820.8] wire _T_3675; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122823.8] wire _T_3676; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122826.6] wire _T_3677; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122827.6] wire _T_3679; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122829.6] wire _T_3680; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122830.6] wire _T_3681; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122831.6] wire _T_3682; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122832.6] wire _T_3683; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122833.6] wire [31:0] _GEN_236; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122834.6] wire _T_3684; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122837.6] wire _T_3685; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122838.6] wire _T_3696; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122862.6] wire _T_3697; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122863.6] wire _T_3699; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122865.6] wire _T_3700; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122866.6] wire _T_3701; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122867.6] wire _T_3702; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122868.6] wire _T_3703; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122869.6] wire [31:0] _GEN_243; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122870.6] wire _T_3704; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122873.6] wire _T_3705; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122874.6] wire _T_3716; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122898.6] wire _T_3717; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122899.6] wire _T_3719; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122901.6] wire _T_3720; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122902.6] wire _T_3721; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122903.6] wire _T_3722; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122904.6] wire _T_3723; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122905.6] wire [31:0] _GEN_250; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122906.6] wire _T_3724; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122909.6] wire _T_3725; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122910.6] wire _T_3736; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122934.6] wire _T_3737; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122935.6] wire _T_3739; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122937.6] wire _T_3740; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122938.6] wire _T_3741; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122939.6] wire _T_3742; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122940.6] wire _T_3743; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122941.6] wire [31:0] _GEN_257; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122942.6] wire _T_3744; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122945.6] wire _T_3745; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122946.6] wire _T_3761; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122975.6] wire _T_3762; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122976.6] wire _T_3763; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122977.6] wire [31:0] _GEN_264; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122978.6] wire [63:0] _GEN_282; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [63:0] _GEN_284; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_329; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_336; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_343; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_350; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_357; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_364; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_371; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire [31:0] _GEN_378; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] wire _T_3810; // @[CSR.scala 892:26:freechips.rocketchip.system.TinyConfig.fir@123141.4] assign _GEN_415 = {{5'd0}, io_retire}; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118189.4] assign _T_84 = _T_83 + _GEN_415; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118189.4] assign _T_86 = _T_84[6]; // @[Counters.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@118192.4] assign _T_88 = _T_85 + 58'h1; // @[Counters.scala 52:43:freechips.rocketchip.system.TinyConfig.fir@118195.6] assign _T_89 = {_T_85,_T_83}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118198.4] assign _T_90 = io_csr_stall == 1'h0; // @[CSR.scala 338:103:freechips.rocketchip.system.TinyConfig.fir@118199.4] assign _GEN_416 = {{5'd0}, _T_90}; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118201.4] assign _T_92 = _T_91 + _GEN_416; // @[Counters.scala 47:33:freechips.rocketchip.system.TinyConfig.fir@118201.4] assign _T_94 = _T_92[6]; // @[Counters.scala 52:20:freechips.rocketchip.system.TinyConfig.fir@118204.4] assign _T_96 = _T_93 + 58'h1; // @[Counters.scala 52:43:freechips.rocketchip.system.TinyConfig.fir@118207.6] assign _T_97 = {_T_93,_T_91}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118210.4] assign _T_112 = {4'h0,io_interrupts_meip,1'h0,2'h0,io_interrupts_mtip,1'h0,2'h0,io_interrupts_msip,1'h0,2'h0}; // @[CSR.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@118232.4] assign read_mip = _T_112 & 16'h888; // @[CSR.scala 351:29:freechips.rocketchip.system.TinyConfig.fir@118233.4] assign _GEN_417 = {{16'd0}, read_mip}; // @[CSR.scala 354:56:freechips.rocketchip.system.TinyConfig.fir@118234.4] assign pending_interrupts = _GEN_417 & reg_mie; // @[CSR.scala 354:56:freechips.rocketchip.system.TinyConfig.fir@118234.4] assign d_interrupts = {io_interrupts_debug, 14'h0}; // @[CSR.scala 355:42:freechips.rocketchip.system.TinyConfig.fir@118236.4] assign _T_116 = ~ pending_interrupts; // @[CSR.scala 356:73:freechips.rocketchip.system.TinyConfig.fir@118239.4] assign _T_118 = ~ _T_116; // @[CSR.scala 356:71:freechips.rocketchip.system.TinyConfig.fir@118241.4] assign m_interrupts = reg_mstatus_mie ? _T_118 : 32'h0; // @[CSR.scala 356:25:freechips.rocketchip.system.TinyConfig.fir@118242.4] assign _T_124 = d_interrupts[14]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118249.4] assign _T_125 = d_interrupts[13]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118250.4] assign _T_126 = d_interrupts[12]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118251.4] assign _T_127 = d_interrupts[11]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118252.4] assign _T_128 = d_interrupts[3]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118253.4] assign _T_129 = d_interrupts[7]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118254.4] assign _T_130 = d_interrupts[9]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118255.4] assign _T_131 = d_interrupts[1]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118256.4] assign _T_132 = d_interrupts[5]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118257.4] assign _T_133 = d_interrupts[8]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118258.4] assign _T_134 = d_interrupts[0]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118259.4] assign _T_135 = d_interrupts[4]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118260.4] assign _T_136 = m_interrupts[15]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118261.4] assign _T_137 = m_interrupts[14]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118262.4] assign _T_138 = m_interrupts[13]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118263.4] assign _T_139 = m_interrupts[12]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118264.4] assign _T_140 = m_interrupts[11]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118265.4] assign _T_141 = m_interrupts[3]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118266.4] assign _T_142 = m_interrupts[7]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118267.4] assign _T_143 = m_interrupts[9]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118268.4] assign _T_144 = m_interrupts[1]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118269.4] assign _T_145 = m_interrupts[5]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118270.4] assign _T_146 = m_interrupts[8]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118271.4] assign _T_147 = m_interrupts[0]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118272.4] assign _T_148 = m_interrupts[4]; // @[CSR.scala 907:76:freechips.rocketchip.system.TinyConfig.fir@118273.4] assign _T_162 = _T_124 | _T_125; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118287.4] assign _T_163 = _T_162 | _T_126; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118288.4] assign _T_164 = _T_163 | _T_127; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118289.4] assign _T_165 = _T_164 | _T_128; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118290.4] assign _T_166 = _T_165 | _T_129; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118291.4] assign _T_167 = _T_166 | _T_130; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118292.4] assign _T_168 = _T_167 | _T_131; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118293.4] assign _T_169 = _T_168 | _T_132; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118294.4] assign _T_170 = _T_169 | _T_133; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118295.4] assign _T_171 = _T_170 | _T_134; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118296.4] assign _T_172 = _T_171 | _T_135; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118297.4] assign _T_173 = _T_172 | _T_136; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118298.4] assign _T_174 = _T_173 | _T_137; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118299.4] assign _T_175 = _T_174 | _T_138; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118300.4] assign _T_176 = _T_175 | _T_139; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118301.4] assign _T_177 = _T_176 | _T_140; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118302.4] assign _T_178 = _T_177 | _T_141; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118303.4] assign _T_179 = _T_178 | _T_142; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118304.4] assign _T_180 = _T_179 | _T_143; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118305.4] assign _T_181 = _T_180 | _T_144; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118306.4] assign _T_182 = _T_181 | _T_145; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118307.4] assign _T_183 = _T_182 | _T_146; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118308.4] assign _T_184 = _T_183 | _T_147; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118309.4] assign anyInterrupt = _T_184 | _T_148; // @[CSR.scala 907:90:freechips.rocketchip.system.TinyConfig.fir@118310.4] assign _T_249 = _T_147 ? 4'h0 : 4'h4; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118375.4] assign _T_250 = _T_146 ? 4'h8 : _T_249; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118376.4] assign _T_251 = _T_145 ? 4'h5 : _T_250; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118377.4] assign _T_252 = _T_144 ? 4'h1 : _T_251; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118378.4] assign _T_253 = _T_143 ? 4'h9 : _T_252; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118379.4] assign _T_254 = _T_142 ? 4'h7 : _T_253; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118380.4] assign _T_255 = _T_141 ? 4'h3 : _T_254; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118381.4] assign _T_256 = _T_140 ? 4'hb : _T_255; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118382.4] assign _T_257 = _T_139 ? 4'hc : _T_256; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118383.4] assign _T_258 = _T_138 ? 4'hd : _T_257; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118384.4] assign _T_259 = _T_137 ? 4'he : _T_258; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118385.4] assign _T_260 = _T_136 ? 4'hf : _T_259; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118386.4] assign _T_261 = _T_135 ? 4'h4 : _T_260; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118387.4] assign _T_262 = _T_134 ? 4'h0 : _T_261; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118388.4] assign _T_263 = _T_133 ? 4'h8 : _T_262; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118389.4] assign _T_264 = _T_132 ? 4'h5 : _T_263; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118390.4] assign _T_265 = _T_131 ? 4'h1 : _T_264; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118391.4] assign _T_266 = _T_130 ? 4'h9 : _T_265; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118392.4] assign _T_267 = _T_129 ? 4'h7 : _T_266; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118393.4] assign _T_268 = _T_128 ? 4'h3 : _T_267; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118394.4] assign _T_269 = _T_127 ? 4'hb : _T_268; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118395.4] assign _T_270 = _T_126 ? 4'hc : _T_269; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118396.4] assign _T_271 = _T_125 ? 4'hd : _T_270; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118397.4] assign whichInterrupt = _T_124 ? 4'he : _T_271; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@118398.4] assign _GEN_418 = {{28'd0}, whichInterrupt}; // @[CSR.scala 360:43:freechips.rocketchip.system.TinyConfig.fir@118399.4] assign _T_273 = io_singleStep == 1'h0; // @[CSR.scala 361:36:freechips.rocketchip.system.TinyConfig.fir@118401.4] assign _T_274 = anyInterrupt & _T_273; // @[CSR.scala 361:33:freechips.rocketchip.system.TinyConfig.fir@118402.4] assign _T_275 = _T_274 | reg_singleStepped; // @[CSR.scala 361:51:freechips.rocketchip.system.TinyConfig.fir@118403.4] assign _T_276 = reg_debug | io_status_cease; // @[CSR.scala 361:88:freechips.rocketchip.system.TinyConfig.fir@118404.4] assign _T_277 = _T_276 == 1'h0; // @[CSR.scala 361:76:freechips.rocketchip.system.TinyConfig.fir@118405.4] assign _T_280 = reg_pmp_0_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118413.4] assign _T_281 = {reg_pmp_0_addr,_T_280}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118414.4] assign _T_284 = _T_281 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118417.4] assign _T_285 = ~ _T_284; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118418.4] assign _T_286 = _T_281 & _T_285; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118419.4] assign _T_287 = {_T_286,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118420.4] assign _T_289 = reg_pmp_1_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118425.4] assign _T_290 = {reg_pmp_1_addr,_T_289}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118426.4] assign _T_293 = _T_290 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118429.4] assign _T_294 = ~ _T_293; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118430.4] assign _T_295 = _T_290 & _T_294; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118431.4] assign _T_296 = {_T_295,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118432.4] assign _T_298 = reg_pmp_2_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118437.4] assign _T_299 = {reg_pmp_2_addr,_T_298}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118438.4] assign _T_302 = _T_299 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118441.4] assign _T_303 = ~ _T_302; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118442.4] assign _T_304 = _T_299 & _T_303; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118443.4] assign _T_305 = {_T_304,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118444.4] assign _T_307 = reg_pmp_3_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118449.4] assign _T_308 = {reg_pmp_3_addr,_T_307}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118450.4] assign _T_311 = _T_308 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118453.4] assign _T_312 = ~ _T_311; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118454.4] assign _T_313 = _T_308 & _T_312; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118455.4] assign _T_314 = {_T_313,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118456.4] assign _T_316 = reg_pmp_4_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118461.4] assign _T_317 = {reg_pmp_4_addr,_T_316}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118462.4] assign _T_320 = _T_317 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118465.4] assign _T_321 = ~ _T_320; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118466.4] assign _T_322 = _T_317 & _T_321; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118467.4] assign _T_323 = {_T_322,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118468.4] assign _T_325 = reg_pmp_5_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118473.4] assign _T_326 = {reg_pmp_5_addr,_T_325}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118474.4] assign _T_329 = _T_326 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118477.4] assign _T_330 = ~ _T_329; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118478.4] assign _T_331 = _T_326 & _T_330; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118479.4] assign _T_332 = {_T_331,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118480.4] assign _T_334 = reg_pmp_6_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118485.4] assign _T_335 = {reg_pmp_6_addr,_T_334}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118486.4] assign _T_338 = _T_335 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118489.4] assign _T_339 = ~ _T_338; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118490.4] assign _T_340 = _T_335 & _T_339; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118491.4] assign _T_341 = {_T_340,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118492.4] assign _T_343 = reg_pmp_7_cfg_a[0]; // @[PMP.scala 57:31:freechips.rocketchip.system.TinyConfig.fir@118497.4] assign _T_344 = {reg_pmp_7_addr,_T_343}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118498.4] assign _T_347 = _T_344 + 31'h1; // @[PMP.scala 58:23:freechips.rocketchip.system.TinyConfig.fir@118501.4] assign _T_348 = ~ _T_347; // @[PMP.scala 58:16:freechips.rocketchip.system.TinyConfig.fir@118502.4] assign _T_349 = _T_344 & _T_348; // @[PMP.scala 58:14:freechips.rocketchip.system.TinyConfig.fir@118503.4] assign _T_350 = {_T_349,2'h3}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118504.4] assign _T_356 = {io_status_hpie,io_status_spie,io_status_upie,io_status_mie,io_status_hie,io_status_sie,io_status_uie}; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118520.4] assign _T_364 = {io_status_sum,io_status_mprv,io_status_xs,io_status_fs,io_status_mpp,io_status_hpp,io_status_spp,io_status_mpie,_T_356}; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118528.4] assign _T_370 = {io_status_uxl,io_status_sd_rv32,io_status_zero1,io_status_tsr,io_status_tw,io_status_tvm,io_status_mxr}; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118534.4] assign _T_379 = {io_status_debug,io_status_cease,io_status_isa,io_status_dprv,io_status_prv,io_status_sd,io_status_zero2,io_status_sxl,_T_370,_T_364}; // @[CSR.scala 379:38:freechips.rocketchip.system.TinyConfig.fir@118543.4] assign read_mstatus = _T_379[31:0]; // @[CSR.scala 379:40:freechips.rocketchip.system.TinyConfig.fir@118544.4] assign _T_380 = reg_mtvec[0]; // @[CSR.scala 936:41:freechips.rocketchip.system.TinyConfig.fir@118545.4] assign _T_381 = _T_380 ? 7'h7e : 7'h2; // @[CSR.scala 936:39:freechips.rocketchip.system.TinyConfig.fir@118546.4] assign _T_383 = {{25'd0}, _T_381}; // @[package.scala 131:41:freechips.rocketchip.system.TinyConfig.fir@118548.4] assign _T_384 = ~ _T_383; // @[package.scala 131:37:freechips.rocketchip.system.TinyConfig.fir@118549.4] assign read_mtvec = reg_mtvec & _T_384; // @[package.scala 131:35:freechips.rocketchip.system.TinyConfig.fir@118550.4] assign _T_395 = {4'h8,reg_bp_0_control_x,reg_bp_0_control_w,reg_bp_0_control_r}; // @[CSR.scala 385:48:freechips.rocketchip.system.TinyConfig.fir@118562.4] assign _T_403 = {4'h2,reg_bp_0_control_dmode,14'h400,reg_bp_0_control_action,1'h0,2'h0,reg_bp_0_control_tmatch,_T_395}; // @[CSR.scala 385:48:freechips.rocketchip.system.TinyConfig.fir@118570.4] assign _T_404 = ~ reg_mepc; // @[CSR.scala 935:28:freechips.rocketchip.system.TinyConfig.fir@118571.4] assign _T_405 = reg_misa[2]; // @[CSR.scala 935:45:freechips.rocketchip.system.TinyConfig.fir@118572.4] assign _T_406 = _T_405 ? 2'h1 : 2'h3; // @[CSR.scala 935:36:freechips.rocketchip.system.TinyConfig.fir@118573.4] assign _GEN_419 = {{30'd0}, _T_406}; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118574.4] assign _T_407 = _T_404 | _GEN_419; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118574.4] assign _T_408 = ~ _T_407; // @[CSR.scala 935:26:freechips.rocketchip.system.TinyConfig.fir@118575.4] assign _T_421 = {4'h4,12'h0,reg_dcsr_ebreakm,3'h0,2'h0,1'h0,reg_dcsr_cause,3'h0,reg_dcsr_step,2'h3}; // @[CSR.scala 399:27:freechips.rocketchip.system.TinyConfig.fir@118588.4] assign _T_422 = ~ reg_dpc; // @[CSR.scala 935:28:freechips.rocketchip.system.TinyConfig.fir@118589.4] assign _T_425 = _T_422 | _GEN_419; // @[CSR.scala 935:31:freechips.rocketchip.system.TinyConfig.fir@118592.4] assign _T_426 = ~ _T_425; // @[CSR.scala 935:26:freechips.rocketchip.system.TinyConfig.fir@118593.4] assign _T_457 = _T_97[63:32]; // @[CSR.scala 436:50:freechips.rocketchip.system.TinyConfig.fir@118624.4] assign _T_458 = _T_89[63:32]; // @[CSR.scala 437:54:freechips.rocketchip.system.TinyConfig.fir@118625.4] assign _T_473 = {reg_pmp_0_cfg_l,2'h0,reg_pmp_0_cfg_a,reg_pmp_0_cfg_x,reg_pmp_0_cfg_w,reg_pmp_0_cfg_r}; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118651.4] assign _T_483 = {reg_pmp_2_cfg_l,2'h0,reg_pmp_2_cfg_a,reg_pmp_2_cfg_x,reg_pmp_2_cfg_w,reg_pmp_2_cfg_r}; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118661.4] assign _T_489 = {reg_pmp_1_cfg_l,2'h0,reg_pmp_1_cfg_a,reg_pmp_1_cfg_x,reg_pmp_1_cfg_w,reg_pmp_1_cfg_r,_T_473}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118667.4] assign _T_491 = {reg_pmp_3_cfg_l,2'h0,reg_pmp_3_cfg_a,reg_pmp_3_cfg_x,reg_pmp_3_cfg_w,reg_pmp_3_cfg_r,_T_483,_T_489}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118669.4] assign _T_496 = {reg_pmp_4_cfg_l,2'h0,reg_pmp_4_cfg_a,reg_pmp_4_cfg_x,reg_pmp_4_cfg_w,reg_pmp_4_cfg_r}; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118674.4] assign _T_506 = {reg_pmp_6_cfg_l,2'h0,reg_pmp_6_cfg_a,reg_pmp_6_cfg_x,reg_pmp_6_cfg_w,reg_pmp_6_cfg_r}; // @[package.scala 36:38:freechips.rocketchip.system.TinyConfig.fir@118684.4] assign _T_512 = {reg_pmp_5_cfg_l,2'h0,reg_pmp_5_cfg_a,reg_pmp_5_cfg_x,reg_pmp_5_cfg_w,reg_pmp_5_cfg_r,_T_496}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118690.4] assign _T_514 = {reg_pmp_7_cfg_l,2'h0,reg_pmp_7_cfg_a,reg_pmp_7_cfg_x,reg_pmp_7_cfg_w,reg_pmp_7_cfg_r,_T_506,_T_512}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@118692.4] assign _T_562 = io_rw_addr == 12'h7a1; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118744.4] assign _T_563 = io_rw_addr == 12'h7a2; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118745.4] assign _T_564 = io_rw_addr == 12'h301; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118746.4] assign _T_565 = io_rw_addr == 12'h300; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118747.4] assign _T_566 = io_rw_addr == 12'h305; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118748.4] assign _T_567 = io_rw_addr == 12'h344; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118749.4] assign _T_568 = io_rw_addr == 12'h304; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118750.4] assign _T_569 = io_rw_addr == 12'h340; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118751.4] assign _T_570 = io_rw_addr == 12'h341; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118752.4] assign _T_571 = io_rw_addr == 12'h343; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118753.4] assign _T_572 = io_rw_addr == 12'h342; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118754.4] assign _T_574 = io_rw_addr == 12'h7b0; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118756.4] assign _T_575 = io_rw_addr == 12'h7b1; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118757.4] assign _T_576 = io_rw_addr == 12'h7b2; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118758.4] assign _T_577 = io_rw_addr == 12'hb00; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118759.4] assign _T_578 = io_rw_addr == 12'hb02; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118760.4] assign _T_666 = io_rw_addr == 12'hb80; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118848.4] assign _T_667 = io_rw_addr == 12'hb82; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118849.4] assign _T_668 = io_rw_addr == 12'h3a0; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118850.4] assign _T_669 = io_rw_addr == 12'h3a1; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118851.4] assign _T_672 = io_rw_addr == 12'h3b0; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118854.4] assign _T_673 = io_rw_addr == 12'h3b1; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118855.4] assign _T_674 = io_rw_addr == 12'h3b2; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118856.4] assign _T_675 = io_rw_addr == 12'h3b3; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118857.4] assign _T_676 = io_rw_addr == 12'h3b4; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118858.4] assign _T_677 = io_rw_addr == 12'h3b5; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118859.4] assign _T_678 = io_rw_addr == 12'h3b6; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118860.4] assign _T_679 = io_rw_addr == 12'h3b7; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118861.4] assign _T_689 = io_rw_addr == 12'hf12; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118871.4] assign _T_691 = io_rw_addr == 12'hf13; // @[CSR.scala 497:73:freechips.rocketchip.system.TinyConfig.fir@118873.4] assign _T_692 = io_rw_cmd[1]; // @[CSR.scala 913:13:freechips.rocketchip.system.TinyConfig.fir@118874.4] assign _T_693 = _T_692 ? io_rw_rdata : 32'h0; // @[CSR.scala 913:9:freechips.rocketchip.system.TinyConfig.fir@118875.4] assign _T_694 = _T_693 | io_rw_wdata; // @[CSR.scala 913:34:freechips.rocketchip.system.TinyConfig.fir@118876.4] assign _T_695 = io_rw_cmd[1:0]; // @[CSR.scala 913:53:freechips.rocketchip.system.TinyConfig.fir@118877.4] assign _T_696 = _T_695 == 2'h3; // @[CSR.scala 913:59:freechips.rocketchip.system.TinyConfig.fir@118878.4] assign _T_697 = _T_696 ? io_rw_wdata : 32'h0; // @[CSR.scala 913:49:freechips.rocketchip.system.TinyConfig.fir@118879.4] assign _T_698 = ~ _T_697; // @[CSR.scala 913:45:freechips.rocketchip.system.TinyConfig.fir@118880.4] assign wdata = _T_694 & _T_698; // @[CSR.scala 913:43:freechips.rocketchip.system.TinyConfig.fir@118881.4] assign system_insn = io_rw_cmd == 3'h4; // @[CSR.scala 500:31:freechips.rocketchip.system.TinyConfig.fir@118882.4] assign _T_699 = {io_rw_addr, 20'h0}; // @[CSR.scala 512:28:freechips.rocketchip.system.TinyConfig.fir@118883.4] assign _T_700 = _T_699 & 32'h20100000; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118884.4] assign _T_701 = _T_700 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118885.4] assign _T_703 = _T_699 & 32'h10100000; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118887.4] assign _T_704 = _T_703 == 32'h100000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118888.4] assign _T_706 = _T_699 & 32'h20400000; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118890.4] assign _T_707 = _T_706 == 32'h20000000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118891.4] assign _T_709 = _T_699 & 32'h20200000; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118893.4] assign _T_710 = _T_709 == 32'h20000000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118894.4] assign _T_712 = _T_699 & 32'h30000000; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@118896.4] assign _T_713 = _T_712 == 32'h10000000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@118897.4] assign insn_call = system_insn & _T_701; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118900.4] assign insn_break = system_insn & _T_704; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118902.4] assign insn_ret = system_insn & _T_707; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118904.4] assign insn_cease = system_insn & _T_710; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118906.4] assign insn_wfi = system_insn & _T_713; // @[CSR.scala 512:95:freechips.rocketchip.system.TinyConfig.fir@118908.4] assign _T_764 = io_status_fs == 2'h0; // @[CSR.scala 524:39:freechips.rocketchip.system.TinyConfig.fir@118954.4] assign _T_765 = reg_misa[5]; // @[CSR.scala 524:57:freechips.rocketchip.system.TinyConfig.fir@118955.4] assign _T_766 = _T_765 == 1'h0; // @[CSR.scala 524:48:freechips.rocketchip.system.TinyConfig.fir@118956.4] assign _T_779 = io_decode_0_csr == 12'h7a0; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118972.4] assign _T_780 = io_decode_0_csr == 12'h7a1; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118973.4] assign _T_781 = io_decode_0_csr == 12'h7a2; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118974.4] assign _T_782 = io_decode_0_csr == 12'h301; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118975.4] assign _T_783 = io_decode_0_csr == 12'h300; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118976.4] assign _T_784 = io_decode_0_csr == 12'h305; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118977.4] assign _T_785 = io_decode_0_csr == 12'h344; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118978.4] assign _T_786 = io_decode_0_csr == 12'h304; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118979.4] assign _T_787 = io_decode_0_csr == 12'h340; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118980.4] assign _T_788 = io_decode_0_csr == 12'h341; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118981.4] assign _T_789 = io_decode_0_csr == 12'h343; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118982.4] assign _T_790 = io_decode_0_csr == 12'h342; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118983.4] assign _T_791 = io_decode_0_csr == 12'hf14; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118984.4] assign _T_792 = io_decode_0_csr == 12'h7b0; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118985.4] assign _T_793 = io_decode_0_csr == 12'h7b1; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118986.4] assign _T_794 = io_decode_0_csr == 12'h7b2; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118987.4] assign _T_795 = io_decode_0_csr == 12'hb00; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118988.4] assign _T_796 = io_decode_0_csr == 12'hb02; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118989.4] assign _T_797 = io_decode_0_csr == 12'h323; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118990.4] assign _T_798 = io_decode_0_csr == 12'hb03; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118991.4] assign _T_799 = io_decode_0_csr == 12'hb83; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118992.4] assign _T_800 = io_decode_0_csr == 12'h324; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118993.4] assign _T_801 = io_decode_0_csr == 12'hb04; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118994.4] assign _T_802 = io_decode_0_csr == 12'hb84; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118995.4] assign _T_803 = io_decode_0_csr == 12'h325; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118996.4] assign _T_804 = io_decode_0_csr == 12'hb05; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118997.4] assign _T_805 = io_decode_0_csr == 12'hb85; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118998.4] assign _T_806 = io_decode_0_csr == 12'h326; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@118999.4] assign _T_807 = io_decode_0_csr == 12'hb06; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119000.4] assign _T_808 = io_decode_0_csr == 12'hb86; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119001.4] assign _T_809 = io_decode_0_csr == 12'h327; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119002.4] assign _T_810 = io_decode_0_csr == 12'hb07; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119003.4] assign _T_811 = io_decode_0_csr == 12'hb87; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119004.4] assign _T_812 = io_decode_0_csr == 12'h328; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119005.4] assign _T_813 = io_decode_0_csr == 12'hb08; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119006.4] assign _T_814 = io_decode_0_csr == 12'hb88; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119007.4] assign _T_815 = io_decode_0_csr == 12'h329; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119008.4] assign _T_816 = io_decode_0_csr == 12'hb09; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119009.4] assign _T_817 = io_decode_0_csr == 12'hb89; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119010.4] assign _T_818 = io_decode_0_csr == 12'h32a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119011.4] assign _T_819 = io_decode_0_csr == 12'hb0a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119012.4] assign _T_820 = io_decode_0_csr == 12'hb8a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119013.4] assign _T_821 = io_decode_0_csr == 12'h32b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119014.4] assign _T_822 = io_decode_0_csr == 12'hb0b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119015.4] assign _T_823 = io_decode_0_csr == 12'hb8b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119016.4] assign _T_824 = io_decode_0_csr == 12'h32c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119017.4] assign _T_825 = io_decode_0_csr == 12'hb0c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119018.4] assign _T_826 = io_decode_0_csr == 12'hb8c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119019.4] assign _T_827 = io_decode_0_csr == 12'h32d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119020.4] assign _T_828 = io_decode_0_csr == 12'hb0d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119021.4] assign _T_829 = io_decode_0_csr == 12'hb8d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119022.4] assign _T_830 = io_decode_0_csr == 12'h32e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119023.4] assign _T_831 = io_decode_0_csr == 12'hb0e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119024.4] assign _T_832 = io_decode_0_csr == 12'hb8e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119025.4] assign _T_833 = io_decode_0_csr == 12'h32f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119026.4] assign _T_834 = io_decode_0_csr == 12'hb0f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119027.4] assign _T_835 = io_decode_0_csr == 12'hb8f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119028.4] assign _T_836 = io_decode_0_csr == 12'h330; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119029.4] assign _T_837 = io_decode_0_csr == 12'hb10; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119030.4] assign _T_838 = io_decode_0_csr == 12'hb90; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119031.4] assign _T_839 = io_decode_0_csr == 12'h331; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119032.4] assign _T_840 = io_decode_0_csr == 12'hb11; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119033.4] assign _T_841 = io_decode_0_csr == 12'hb91; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119034.4] assign _T_842 = io_decode_0_csr == 12'h332; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119035.4] assign _T_843 = io_decode_0_csr == 12'hb12; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119036.4] assign _T_844 = io_decode_0_csr == 12'hb92; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119037.4] assign _T_845 = io_decode_0_csr == 12'h333; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119038.4] assign _T_846 = io_decode_0_csr == 12'hb13; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119039.4] assign _T_847 = io_decode_0_csr == 12'hb93; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119040.4] assign _T_848 = io_decode_0_csr == 12'h334; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119041.4] assign _T_849 = io_decode_0_csr == 12'hb14; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119042.4] assign _T_850 = io_decode_0_csr == 12'hb94; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119043.4] assign _T_851 = io_decode_0_csr == 12'h335; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119044.4] assign _T_852 = io_decode_0_csr == 12'hb15; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119045.4] assign _T_853 = io_decode_0_csr == 12'hb95; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119046.4] assign _T_854 = io_decode_0_csr == 12'h336; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119047.4] assign _T_855 = io_decode_0_csr == 12'hb16; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119048.4] assign _T_856 = io_decode_0_csr == 12'hb96; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119049.4] assign _T_857 = io_decode_0_csr == 12'h337; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119050.4] assign _T_858 = io_decode_0_csr == 12'hb17; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119051.4] assign _T_859 = io_decode_0_csr == 12'hb97; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119052.4] assign _T_860 = io_decode_0_csr == 12'h338; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119053.4] assign _T_861 = io_decode_0_csr == 12'hb18; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119054.4] assign _T_862 = io_decode_0_csr == 12'hb98; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119055.4] assign _T_863 = io_decode_0_csr == 12'h339; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119056.4] assign _T_864 = io_decode_0_csr == 12'hb19; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119057.4] assign _T_865 = io_decode_0_csr == 12'hb99; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119058.4] assign _T_866 = io_decode_0_csr == 12'h33a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119059.4] assign _T_867 = io_decode_0_csr == 12'hb1a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119060.4] assign _T_868 = io_decode_0_csr == 12'hb9a; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119061.4] assign _T_869 = io_decode_0_csr == 12'h33b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119062.4] assign _T_870 = io_decode_0_csr == 12'hb1b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119063.4] assign _T_871 = io_decode_0_csr == 12'hb9b; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119064.4] assign _T_872 = io_decode_0_csr == 12'h33c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119065.4] assign _T_873 = io_decode_0_csr == 12'hb1c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119066.4] assign _T_874 = io_decode_0_csr == 12'hb9c; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119067.4] assign _T_875 = io_decode_0_csr == 12'h33d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119068.4] assign _T_876 = io_decode_0_csr == 12'hb1d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119069.4] assign _T_877 = io_decode_0_csr == 12'hb9d; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119070.4] assign _T_878 = io_decode_0_csr == 12'h33e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119071.4] assign _T_879 = io_decode_0_csr == 12'hb1e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119072.4] assign _T_880 = io_decode_0_csr == 12'hb9e; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119073.4] assign _T_881 = io_decode_0_csr == 12'h33f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119074.4] assign _T_882 = io_decode_0_csr == 12'hb1f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119075.4] assign _T_883 = io_decode_0_csr == 12'hb9f; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119076.4] assign _T_884 = io_decode_0_csr == 12'hb80; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119077.4] assign _T_885 = io_decode_0_csr == 12'hb82; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119078.4] assign _T_886 = io_decode_0_csr == 12'h3a0; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119079.4] assign _T_887 = io_decode_0_csr == 12'h3a1; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119080.4] assign _T_888 = io_decode_0_csr == 12'h3a2; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119081.4] assign _T_889 = io_decode_0_csr == 12'h3a3; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119082.4] assign _T_890 = io_decode_0_csr == 12'h3b0; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119083.4] assign _T_891 = io_decode_0_csr == 12'h3b1; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119084.4] assign _T_892 = io_decode_0_csr == 12'h3b2; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119085.4] assign _T_893 = io_decode_0_csr == 12'h3b3; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119086.4] assign _T_894 = io_decode_0_csr == 12'h3b4; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119087.4] assign _T_895 = io_decode_0_csr == 12'h3b5; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119088.4] assign _T_896 = io_decode_0_csr == 12'h3b6; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119089.4] assign _T_897 = io_decode_0_csr == 12'h3b7; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119090.4] assign _T_898 = io_decode_0_csr == 12'h3b8; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119091.4] assign _T_899 = io_decode_0_csr == 12'h3b9; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119092.4] assign _T_900 = io_decode_0_csr == 12'h3ba; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119093.4] assign _T_901 = io_decode_0_csr == 12'h3bb; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119094.4] assign _T_902 = io_decode_0_csr == 12'h3bc; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119095.4] assign _T_903 = io_decode_0_csr == 12'h3bd; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119096.4] assign _T_904 = io_decode_0_csr == 12'h3be; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119097.4] assign _T_905 = io_decode_0_csr == 12'h3bf; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119098.4] assign _T_906 = io_decode_0_csr == 12'h7c1; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119099.4] assign _T_907 = io_decode_0_csr == 12'hf12; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119100.4] assign _T_908 = io_decode_0_csr == 12'hf11; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119101.4] assign _T_909 = io_decode_0_csr == 12'hf13; // @[CSR.scala 517:99:freechips.rocketchip.system.TinyConfig.fir@119102.4] assign _T_910 = _T_779 | _T_780; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119103.4] assign _T_911 = _T_910 | _T_781; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119104.4] assign _T_912 = _T_911 | _T_782; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119105.4] assign _T_913 = _T_912 | _T_783; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119106.4] assign _T_914 = _T_913 | _T_784; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119107.4] assign _T_915 = _T_914 | _T_785; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119108.4] assign _T_916 = _T_915 | _T_786; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119109.4] assign _T_917 = _T_916 | _T_787; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119110.4] assign _T_918 = _T_917 | _T_788; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119111.4] assign _T_919 = _T_918 | _T_789; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119112.4] assign _T_920 = _T_919 | _T_790; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119113.4] assign _T_921 = _T_920 | _T_791; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119114.4] assign _T_922 = _T_921 | _T_792; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119115.4] assign _T_923 = _T_922 | _T_793; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119116.4] assign _T_924 = _T_923 | _T_794; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119117.4] assign _T_925 = _T_924 | _T_795; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119118.4] assign _T_926 = _T_925 | _T_796; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119119.4] assign _T_927 = _T_926 | _T_797; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119120.4] assign _T_928 = _T_927 | _T_798; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119121.4] assign _T_929 = _T_928 | _T_799; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119122.4] assign _T_930 = _T_929 | _T_800; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119123.4] assign _T_931 = _T_930 | _T_801; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119124.4] assign _T_932 = _T_931 | _T_802; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119125.4] assign _T_933 = _T_932 | _T_803; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119126.4] assign _T_934 = _T_933 | _T_804; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119127.4] assign _T_935 = _T_934 | _T_805; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119128.4] assign _T_936 = _T_935 | _T_806; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119129.4] assign _T_937 = _T_936 | _T_807; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119130.4] assign _T_938 = _T_937 | _T_808; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119131.4] assign _T_939 = _T_938 | _T_809; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119132.4] assign _T_940 = _T_939 | _T_810; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119133.4] assign _T_941 = _T_940 | _T_811; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119134.4] assign _T_942 = _T_941 | _T_812; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119135.4] assign _T_943 = _T_942 | _T_813; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119136.4] assign _T_944 = _T_943 | _T_814; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119137.4] assign _T_945 = _T_944 | _T_815; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119138.4] assign _T_946 = _T_945 | _T_816; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119139.4] assign _T_947 = _T_946 | _T_817; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119140.4] assign _T_948 = _T_947 | _T_818; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119141.4] assign _T_949 = _T_948 | _T_819; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119142.4] assign _T_950 = _T_949 | _T_820; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119143.4] assign _T_951 = _T_950 | _T_821; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119144.4] assign _T_952 = _T_951 | _T_822; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119145.4] assign _T_953 = _T_952 | _T_823; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119146.4] assign _T_954 = _T_953 | _T_824; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119147.4] assign _T_955 = _T_954 | _T_825; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119148.4] assign _T_956 = _T_955 | _T_826; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119149.4] assign _T_957 = _T_956 | _T_827; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119150.4] assign _T_958 = _T_957 | _T_828; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119151.4] assign _T_959 = _T_958 | _T_829; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119152.4] assign _T_960 = _T_959 | _T_830; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119153.4] assign _T_961 = _T_960 | _T_831; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119154.4] assign _T_962 = _T_961 | _T_832; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119155.4] assign _T_963 = _T_962 | _T_833; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119156.4] assign _T_964 = _T_963 | _T_834; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119157.4] assign _T_965 = _T_964 | _T_835; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119158.4] assign _T_966 = _T_965 | _T_836; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119159.4] assign _T_967 = _T_966 | _T_837; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119160.4] assign _T_968 = _T_967 | _T_838; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119161.4] assign _T_969 = _T_968 | _T_839; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119162.4] assign _T_970 = _T_969 | _T_840; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119163.4] assign _T_971 = _T_970 | _T_841; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119164.4] assign _T_972 = _T_971 | _T_842; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119165.4] assign _T_973 = _T_972 | _T_843; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119166.4] assign _T_974 = _T_973 | _T_844; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119167.4] assign _T_975 = _T_974 | _T_845; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119168.4] assign _T_976 = _T_975 | _T_846; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119169.4] assign _T_977 = _T_976 | _T_847; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119170.4] assign _T_978 = _T_977 | _T_848; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119171.4] assign _T_979 = _T_978 | _T_849; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119172.4] assign _T_980 = _T_979 | _T_850; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119173.4] assign _T_981 = _T_980 | _T_851; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119174.4] assign _T_982 = _T_981 | _T_852; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119175.4] assign _T_983 = _T_982 | _T_853; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119176.4] assign _T_984 = _T_983 | _T_854; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119177.4] assign _T_985 = _T_984 | _T_855; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119178.4] assign _T_986 = _T_985 | _T_856; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119179.4] assign _T_987 = _T_986 | _T_857; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119180.4] assign _T_988 = _T_987 | _T_858; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119181.4] assign _T_989 = _T_988 | _T_859; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119182.4] assign _T_990 = _T_989 | _T_860; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119183.4] assign _T_991 = _T_990 | _T_861; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119184.4] assign _T_992 = _T_991 | _T_862; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119185.4] assign _T_993 = _T_992 | _T_863; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119186.4] assign _T_994 = _T_993 | _T_864; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119187.4] assign _T_995 = _T_994 | _T_865; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119188.4] assign _T_996 = _T_995 | _T_866; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119189.4] assign _T_997 = _T_996 | _T_867; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119190.4] assign _T_998 = _T_997 | _T_868; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119191.4] assign _T_999 = _T_998 | _T_869; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119192.4] assign _T_1000 = _T_999 | _T_870; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119193.4] assign _T_1001 = _T_1000 | _T_871; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119194.4] assign _T_1002 = _T_1001 | _T_872; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119195.4] assign _T_1003 = _T_1002 | _T_873; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119196.4] assign _T_1004 = _T_1003 | _T_874; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119197.4] assign _T_1005 = _T_1004 | _T_875; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119198.4] assign _T_1006 = _T_1005 | _T_876; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119199.4] assign _T_1007 = _T_1006 | _T_877; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119200.4] assign _T_1008 = _T_1007 | _T_878; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119201.4] assign _T_1009 = _T_1008 | _T_879; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119202.4] assign _T_1010 = _T_1009 | _T_880; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119203.4] assign _T_1011 = _T_1010 | _T_881; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119204.4] assign _T_1012 = _T_1011 | _T_882; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119205.4] assign _T_1013 = _T_1012 | _T_883; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119206.4] assign _T_1014 = _T_1013 | _T_884; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119207.4] assign _T_1015 = _T_1014 | _T_885; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119208.4] assign _T_1016 = _T_1015 | _T_886; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119209.4] assign _T_1017 = _T_1016 | _T_887; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119210.4] assign _T_1018 = _T_1017 | _T_888; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119211.4] assign _T_1019 = _T_1018 | _T_889; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119212.4] assign _T_1020 = _T_1019 | _T_890; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119213.4] assign _T_1021 = _T_1020 | _T_891; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119214.4] assign _T_1022 = _T_1021 | _T_892; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119215.4] assign _T_1023 = _T_1022 | _T_893; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119216.4] assign _T_1024 = _T_1023 | _T_894; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119217.4] assign _T_1025 = _T_1024 | _T_895; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119218.4] assign _T_1026 = _T_1025 | _T_896; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119219.4] assign _T_1027 = _T_1026 | _T_897; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119220.4] assign _T_1028 = _T_1027 | _T_898; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119221.4] assign _T_1029 = _T_1028 | _T_899; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119222.4] assign _T_1030 = _T_1029 | _T_900; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119223.4] assign _T_1031 = _T_1030 | _T_901; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119224.4] assign _T_1032 = _T_1031 | _T_902; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119225.4] assign _T_1033 = _T_1032 | _T_903; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119226.4] assign _T_1034 = _T_1033 | _T_904; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119227.4] assign _T_1035 = _T_1034 | _T_905; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119228.4] assign _T_1036 = _T_1035 | _T_906; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119229.4] assign _T_1037 = _T_1036 | _T_907; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119230.4] assign _T_1038 = _T_1037 | _T_908; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119231.4] assign _T_1039 = _T_1038 | _T_909; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119232.4] assign _T_1040 = _T_1039 == 1'h0; // @[CSR.scala 528:7:freechips.rocketchip.system.TinyConfig.fir@119233.4] assign _T_1059 = _T_792 | _T_793; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119252.4] assign _T_1060 = _T_1059 | _T_794; // @[CSR.scala 517:115:freechips.rocketchip.system.TinyConfig.fir@119253.4] assign _T_1062 = reg_debug == 1'h0; // @[CSR.scala 531:52:freechips.rocketchip.system.TinyConfig.fir@119255.4] assign _T_1063 = _T_1060 & _T_1062; // @[CSR.scala 531:49:freechips.rocketchip.system.TinyConfig.fir@119256.4] assign _T_1064 = _T_1040 | _T_1063; // @[CSR.scala 530:148:freechips.rocketchip.system.TinyConfig.fir@119257.4] assign _T_1065 = io_decode_0_fp_csr & io_decode_0_fp_illegal; // @[CSR.scala 532:21:freechips.rocketchip.system.TinyConfig.fir@119258.4] assign _T_1067 = io_decode_0_csr[11:10]; // @[CSR.scala 533:39:freechips.rocketchip.system.TinyConfig.fir@119261.4] assign _T_1069 = io_decode_0_csr >= 12'h340; // @[CSR.scala 534:40:freechips.rocketchip.system.TinyConfig.fir@119264.4] assign _T_1070 = io_decode_0_csr <= 12'h343; // @[CSR.scala 534:71:freechips.rocketchip.system.TinyConfig.fir@119265.4] assign _T_1071 = _T_1069 & _T_1070; // @[CSR.scala 534:57:freechips.rocketchip.system.TinyConfig.fir@119266.4] assign _T_1072 = io_decode_0_csr >= 12'h140; // @[CSR.scala 534:99:freechips.rocketchip.system.TinyConfig.fir@119267.4] assign _T_1073 = io_decode_0_csr <= 12'h143; // @[CSR.scala 534:130:freechips.rocketchip.system.TinyConfig.fir@119268.4] assign _T_1074 = _T_1072 & _T_1073; // @[CSR.scala 534:116:freechips.rocketchip.system.TinyConfig.fir@119269.4] assign _T_1075 = _T_1071 | _T_1074; // @[CSR.scala 534:85:freechips.rocketchip.system.TinyConfig.fir@119270.4] assign _T_1090 = insn_break ? 32'h3 : io_cause; // @[CSR.scala 543:14:freechips.rocketchip.system.TinyConfig.fir@119287.4] assign cause = insn_call ? 32'hb : _T_1090; // @[CSR.scala 542:8:freechips.rocketchip.system.TinyConfig.fir@119288.4] assign cause_lsbs = cause[7:0]; // @[CSR.scala 544:25:freechips.rocketchip.system.TinyConfig.fir@119289.4] assign _T_1091 = cause[31]; // @[CSR.scala 545:30:freechips.rocketchip.system.TinyConfig.fir@119290.4] assign _T_1092 = cause_lsbs == 8'he; // @[CSR.scala 545:53:freechips.rocketchip.system.TinyConfig.fir@119291.4] assign causeIsDebugInt = _T_1091 & _T_1092; // @[CSR.scala 545:39:freechips.rocketchip.system.TinyConfig.fir@119292.4] assign _T_1094 = _T_1091 == 1'h0; // @[CSR.scala 546:29:freechips.rocketchip.system.TinyConfig.fir@119294.4] assign causeIsDebugTrigger = _T_1094 & _T_1092; // @[CSR.scala 546:44:freechips.rocketchip.system.TinyConfig.fir@119296.4] assign _T_1098 = _T_1094 & insn_break; // @[CSR.scala 547:42:freechips.rocketchip.system.TinyConfig.fir@119299.4] assign _T_1101 = {reg_dcsr_ebreakm,1'h0,2'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@119302.4] assign _GEN_421 = _T_1101[3:3]; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119303.4] assign _T_1102 = {{3'd0}, _GEN_421}; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119303.4] assign _T_1103 = _T_1102[0]; // @[CSR.scala 547:134:freechips.rocketchip.system.TinyConfig.fir@119304.4] assign causeIsDebugBreak = _T_1098 & _T_1103; // @[CSR.scala 547:56:freechips.rocketchip.system.TinyConfig.fir@119305.4] assign _T_1104 = reg_singleStepped | causeIsDebugInt; // @[CSR.scala 548:60:freechips.rocketchip.system.TinyConfig.fir@119306.4] assign _T_1105 = _T_1104 | causeIsDebugTrigger; // @[CSR.scala 548:79:freechips.rocketchip.system.TinyConfig.fir@119307.4] assign _T_1106 = _T_1105 | causeIsDebugBreak; // @[CSR.scala 548:102:freechips.rocketchip.system.TinyConfig.fir@119308.4] assign trapToDebug = _T_1106 | reg_debug; // @[CSR.scala 548:123:freechips.rocketchip.system.TinyConfig.fir@119309.4] assign _T_1108 = insn_break ? 12'h800 : 12'h808; // @[CSR.scala 549:37:freechips.rocketchip.system.TinyConfig.fir@119311.4] assign debugTVec = reg_debug ? _T_1108 : 12'h800; // @[CSR.scala 549:22:freechips.rocketchip.system.TinyConfig.fir@119312.4] assign _T_1118 = cause[4:0]; // @[CSR.scala 558:32:freechips.rocketchip.system.TinyConfig.fir@119323.4] assign _T_1119 = {_T_1118, 2'h0}; // @[CSR.scala 558:59:freechips.rocketchip.system.TinyConfig.fir@119324.4] assign _T_1120 = read_mtvec[31:7]; // @[CSR.scala 559:33:freechips.rocketchip.system.TinyConfig.fir@119325.4] assign _T_1121 = {_T_1120,_T_1119}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@119326.4] assign _T_1122 = read_mtvec[0]; // @[CSR.scala 560:24:freechips.rocketchip.system.TinyConfig.fir@119327.4] assign _T_1124 = _T_1122 & _T_1091; // @[CSR.scala 560:28:freechips.rocketchip.system.TinyConfig.fir@119329.4] assign _T_1125 = cause_lsbs[7:5]; // @[CSR.scala 560:70:freechips.rocketchip.system.TinyConfig.fir@119330.4] assign _T_1126 = _T_1125 == 3'h0; // @[CSR.scala 560:94:freechips.rocketchip.system.TinyConfig.fir@119331.4] assign _T_1127 = _T_1124 & _T_1126; // @[CSR.scala 560:55:freechips.rocketchip.system.TinyConfig.fir@119332.4] assign _T_1128 = read_mtvec[31:2]; // @[CSR.scala 561:38:freechips.rocketchip.system.TinyConfig.fir@119333.4] assign _T_1129 = {_T_1128, 2'h0}; // @[CSR.scala 561:56:freechips.rocketchip.system.TinyConfig.fir@119334.4] assign notDebugTVec = _T_1127 ? _T_1121 : _T_1129; // @[CSR.scala 561:8:freechips.rocketchip.system.TinyConfig.fir@119335.4] assign tvec = trapToDebug ? {{20'd0}, debugTVec} : notDebugTVec; // @[CSR.scala 563:17:freechips.rocketchip.system.TinyConfig.fir@119336.4] assign _T_1130 = insn_call | insn_break; // @[CSR.scala 566:24:freechips.rocketchip.system.TinyConfig.fir@119339.4] assign _T_1134 = io_status_fs == 2'h3; // @[CSR.scala 569:32:freechips.rocketchip.system.TinyConfig.fir@119346.4] assign _T_1135 = io_status_xs == 2'h3; // @[CSR.scala 569:53:freechips.rocketchip.system.TinyConfig.fir@119347.4] assign exception = _T_1130 | io_exception; // @[CSR.scala 578:43:freechips.rocketchip.system.TinyConfig.fir@119362.4] assign _T_1142 = insn_ret + insn_call; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119363.4] assign _T_1144 = insn_break + io_exception; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119365.4] assign _T_1146 = _T_1142 + _T_1144; // @[Bitwise.scala 48:55:freechips.rocketchip.system.TinyConfig.fir@119367.4] assign _T_1148 = _T_1146 <= 3'h1; // @[CSR.scala 579:79:freechips.rocketchip.system.TinyConfig.fir@119369.4] assign _T_1150 = _T_1148 | reset; // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119371.4] assign _T_1151 = _T_1150 == 1'h0; // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119372.4] assign _T_1153 = insn_wfi & _T_273; // @[CSR.scala 581:18:freechips.rocketchip.system.TinyConfig.fir@119378.4] assign _T_1155 = _T_1153 & _T_1062; // @[CSR.scala 581:36:freechips.rocketchip.system.TinyConfig.fir@119380.4] assign _T_1156 = pending_interrupts != 32'h0; // @[CSR.scala 582:28:freechips.rocketchip.system.TinyConfig.fir@119384.4] assign _T_1157 = _T_1156 | io_interrupts_debug; // @[CSR.scala 582:32:freechips.rocketchip.system.TinyConfig.fir@119385.4] assign _T_1158 = _T_1157 | exception; // @[CSR.scala 582:55:freechips.rocketchip.system.TinyConfig.fir@119386.4] assign _T_1160 = io_retire | exception; // @[CSR.scala 584:22:freechips.rocketchip.system.TinyConfig.fir@119391.4] assign _T_1168 = reg_singleStepped == 1'h0; // @[CSR.scala 587:10:freechips.rocketchip.system.TinyConfig.fir@119409.4] assign _T_1169 = io_retire == 1'h0; // @[CSR.scala 587:42:freechips.rocketchip.system.TinyConfig.fir@119410.4] assign _T_1170 = _T_1168 | _T_1169; // @[CSR.scala 587:29:freechips.rocketchip.system.TinyConfig.fir@119411.4] assign _T_1172 = _T_1170 | reset; // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119413.4] assign _T_1173 = _T_1172 == 1'h0; // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119414.4] assign _T_1174 = ~ io_pc; // @[CSR.scala 934:28:freechips.rocketchip.system.TinyConfig.fir@119419.4] assign _T_1175 = _T_1174 | 32'h1; // @[CSR.scala 934:31:freechips.rocketchip.system.TinyConfig.fir@119420.4] assign epc = ~ _T_1175; // @[CSR.scala 934:26:freechips.rocketchip.system.TinyConfig.fir@119421.4] assign _T_1177 = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala 598:86:freechips.rocketchip.system.TinyConfig.fir@119431.10] assign _T_1178 = causeIsDebugInt ? 2'h3 : _T_1177; // @[CSR.scala 598:56:freechips.rocketchip.system.TinyConfig.fir@119432.10] assign _GEN_48 = {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 602:27:freechips.rocketchip.system.TinyConfig.fir@119440.8] assign _GEN_67 = trapToDebug ? {{1'd0}, reg_mstatus_spp} : _GEN_48; // @[CSR.scala 594:24:freechips.rocketchip.system.TinyConfig.fir@119426.6] assign _GEN_85 = exception ? _GEN_67 : {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 593:20:freechips.rocketchip.system.TinyConfig.fir@119425.4] assign _T_1468 = io_rw_addr[10]; // @[CSR.scala 649:47:freechips.rocketchip.system.TinyConfig.fir@119758.8] assign _GEN_95 = _T_1468 ? _T_426 : _T_408; // @[CSR.scala 649:53:freechips.rocketchip.system.TinyConfig.fir@119760.8] assign _T_1483 = _T_562 ? _T_403 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119804.4] assign _T_1484 = _T_563 ? reg_bp_0_address : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119805.4] assign _T_1485 = _T_564 ? reg_misa : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119806.4] assign _T_1486 = _T_565 ? read_mstatus : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119807.4] assign _T_1487 = _T_566 ? read_mtvec : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119808.4] assign _T_1488 = _T_567 ? read_mip : 16'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119809.4] assign _T_1489 = _T_568 ? reg_mie : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119810.4] assign _T_1490 = _T_569 ? reg_mscratch : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119811.4] assign _T_1491 = _T_570 ? _T_408 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119812.4] assign _T_1492 = _T_571 ? reg_mtval : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119813.4] assign _T_1493 = _T_572 ? reg_mcause : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119814.4] assign _T_1495 = _T_574 ? _T_421 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119816.4] assign _T_1496 = _T_575 ? _T_426 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119817.4] assign _T_1497 = _T_576 ? reg_dscratch : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119818.4] assign _T_1498 = _T_577 ? _T_97 : 64'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119819.4] assign _T_1499 = _T_578 ? _T_89 : 64'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119820.4] assign _T_1587 = _T_666 ? _T_457 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119908.4] assign _T_1588 = _T_667 ? _T_458 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119909.4] assign _T_1589 = _T_668 ? _T_491 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119910.4] assign _T_1590 = _T_669 ? _T_514 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119911.4] assign _T_1593 = _T_672 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119914.4] assign _T_1594 = _T_673 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119915.4] assign _T_1595 = _T_674 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119916.4] assign _T_1596 = _T_675 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119917.4] assign _T_1597 = _T_676 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119918.4] assign _T_1598 = _T_677 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119919.4] assign _T_1599 = _T_678 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119920.4] assign _T_1600 = _T_679 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119921.4] assign _T_1610 = _T_689 ? 32'h1 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119931.4] assign _T_1612 = _T_691 ? 32'h20181004 : 32'h0; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119933.4] assign _T_1614 = _T_1483 | _T_1484; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119935.4] assign _T_1615 = _T_1614 | _T_1485; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119936.4] assign _T_1616 = _T_1615 | _T_1486; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119937.4] assign _T_1617 = _T_1616 | _T_1487; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119938.4] assign _GEN_424 = {{16'd0}, _T_1488}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119939.4] assign _T_1618 = _T_1617 | _GEN_424; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119939.4] assign _T_1619 = _T_1618 | _T_1489; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119940.4] assign _T_1620 = _T_1619 | _T_1490; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119941.4] assign _T_1621 = _T_1620 | _T_1491; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119942.4] assign _T_1622 = _T_1621 | _T_1492; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119943.4] assign _T_1623 = _T_1622 | _T_1493; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119944.4] assign _T_1625 = _T_1623 | _T_1495; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119946.4] assign _T_1626 = _T_1625 | _T_1496; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119947.4] assign _T_1627 = _T_1626 | _T_1497; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119948.4] assign _GEN_425 = {{32'd0}, _T_1627}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119949.4] assign _T_1628 = _GEN_425 | _T_1498; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119949.4] assign _T_1629 = _T_1628 | _T_1499; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@119950.4] assign _GEN_426 = {{32'd0}, _T_1587}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120038.4] assign _T_1717 = _T_1629 | _GEN_426; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120038.4] assign _GEN_427 = {{32'd0}, _T_1588}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120039.4] assign _T_1718 = _T_1717 | _GEN_427; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120039.4] assign _GEN_428 = {{32'd0}, _T_1589}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120040.4] assign _T_1719 = _T_1718 | _GEN_428; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120040.4] assign _GEN_429 = {{32'd0}, _T_1590}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120041.4] assign _T_1720 = _T_1719 | _GEN_429; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120041.4] assign _GEN_430 = {{34'd0}, _T_1593}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120044.4] assign _T_1723 = _T_1720 | _GEN_430; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120044.4] assign _GEN_431 = {{34'd0}, _T_1594}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120045.4] assign _T_1724 = _T_1723 | _GEN_431; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120045.4] assign _GEN_432 = {{34'd0}, _T_1595}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120046.4] assign _T_1725 = _T_1724 | _GEN_432; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120046.4] assign _GEN_433 = {{34'd0}, _T_1596}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120047.4] assign _T_1726 = _T_1725 | _GEN_433; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120047.4] assign _GEN_434 = {{34'd0}, _T_1597}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120048.4] assign _T_1727 = _T_1726 | _GEN_434; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120048.4] assign _GEN_435 = {{34'd0}, _T_1598}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120049.4] assign _T_1728 = _T_1727 | _GEN_435; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120049.4] assign _GEN_436 = {{34'd0}, _T_1599}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120050.4] assign _T_1729 = _T_1728 | _GEN_436; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120050.4] assign _GEN_437 = {{34'd0}, _T_1600}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120051.4] assign _T_1730 = _T_1729 | _GEN_437; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120051.4] assign _GEN_438 = {{32'd0}, _T_1610}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120061.4] assign _T_1740 = _T_1730 | _GEN_438; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120061.4] assign _GEN_439 = {{32'd0}, _T_1612}; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120063.4] assign _T_1742 = _T_1740 | _GEN_439; // @[Mux.scala 28:72:freechips.rocketchip.system.TinyConfig.fir@120063.4] assign _T_1746 = io_rw_cmd == 3'h5; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120070.6] assign _T_1747 = io_rw_cmd == 3'h6; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120071.6] assign _T_1748 = io_rw_cmd == 3'h7; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@120072.6] assign _T_3320 = _T_1747 | _T_1748; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@122175.4] assign csr_wen = _T_3320 | _T_1746; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@122176.4] assign _T_3334 = {{70'd0}, wdata}; // @[:freechips.rocketchip.system.TinyConfig.fir@122194.8 :freechips.rocketchip.system.TinyConfig.fir@122196.8] assign _T_3338 = _T_3334[3]; // @[CSR.scala 701:47:freechips.rocketchip.system.TinyConfig.fir@122203.8] assign _T_3342 = _T_3334[7]; // @[CSR.scala 701:47:freechips.rocketchip.system.TinyConfig.fir@122211.8] assign _T_3365 = wdata[5]; // @[CSR.scala 725:20:freechips.rocketchip.system.TinyConfig.fir@122261.8] assign _T_3366 = io_pc[1]; // @[CSR.scala 727:39:freechips.rocketchip.system.TinyConfig.fir@122262.8] assign _T_3367 = _T_3366 == 1'h0; // @[CSR.scala 727:33:freechips.rocketchip.system.TinyConfig.fir@122263.8] assign _T_3369 = wdata[2]; // @[CSR.scala 727:51:freechips.rocketchip.system.TinyConfig.fir@122265.8] assign _T_3370 = _T_3367 | _T_3369; // @[CSR.scala 727:43:freechips.rocketchip.system.TinyConfig.fir@122266.8] assign _T_3371 = ~ wdata; // @[CSR.scala 729:25:freechips.rocketchip.system.TinyConfig.fir@122268.10] assign _T_3372 = _T_3365 == 1'h0; // @[CSR.scala 729:35:freechips.rocketchip.system.TinyConfig.fir@122269.10] assign _T_3373 = {_T_3372, 3'h0}; // @[CSR.scala 729:38:freechips.rocketchip.system.TinyConfig.fir@122270.10] assign _GEN_440 = {{28'd0}, _T_3373}; // @[CSR.scala 729:32:freechips.rocketchip.system.TinyConfig.fir@122271.10] assign _T_3374 = _T_3371 | _GEN_440; // @[CSR.scala 729:32:freechips.rocketchip.system.TinyConfig.fir@122271.10] assign _T_3375 = ~ _T_3374; // @[CSR.scala 729:23:freechips.rocketchip.system.TinyConfig.fir@122272.10] assign _T_3376 = _T_3375 & 32'h1005; // @[CSR.scala 729:55:freechips.rocketchip.system.TinyConfig.fir@122273.10] assign _T_3378 = reg_misa & 32'hffffeffa; // @[CSR.scala 729:73:freechips.rocketchip.system.TinyConfig.fir@122275.10] assign _T_3379 = _T_3376 | _T_3378; // @[CSR.scala 729:62:freechips.rocketchip.system.TinyConfig.fir@122276.10] assign _T_3421 = wdata & 32'h888; // @[CSR.scala 744:59:freechips.rocketchip.system.TinyConfig.fir@122343.8] assign _T_3423 = _T_3371 | 32'h1; // @[CSR.scala 934:31:freechips.rocketchip.system.TinyConfig.fir@122348.8] assign _T_3424 = ~ _T_3423; // @[CSR.scala 934:26:freechips.rocketchip.system.TinyConfig.fir@122349.8] assign _T_3425 = wdata & 32'h8000000f; // @[CSR.scala 749:62:freechips.rocketchip.system.TinyConfig.fir@122359.8] assign _T_3427 = _T_97[63:32]; // @[CSR.scala 928:47:freechips.rocketchip.system.TinyConfig.fir@122367.8] assign _T_3428 = {_T_3427,wdata}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122368.8] assign _T_3429 = _T_3428[63:6]; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122370.8] assign _GEN_130 = _T_577 ? _T_3428 : {{57'd0}, _T_92}; // @[CSR.scala 928:31:freechips.rocketchip.system.TinyConfig.fir@122366.6] assign _T_3431 = _T_97[31:0]; // @[CSR.scala 929:74:freechips.rocketchip.system.TinyConfig.fir@122375.8] assign _T_3432 = {wdata,_T_3431}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122376.8] assign _T_3433 = _T_3432[63:6]; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122378.8] assign _GEN_132 = _T_666 ? _T_3432 : _GEN_130; // @[CSR.scala 929:31:freechips.rocketchip.system.TinyConfig.fir@122373.6] assign _T_3434 = _T_89[63:32]; // @[CSR.scala 928:47:freechips.rocketchip.system.TinyConfig.fir@122382.8] assign _T_3435 = {_T_3434,wdata}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122383.8] assign _T_3436 = _T_3435[63:6]; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122385.8] assign _GEN_134 = _T_578 ? _T_3435 : {{57'd0}, _T_84}; // @[CSR.scala 928:31:freechips.rocketchip.system.TinyConfig.fir@122381.6] assign _T_3438 = _T_89[31:0]; // @[CSR.scala 929:74:freechips.rocketchip.system.TinyConfig.fir@122390.8] assign _T_3439 = {wdata,_T_3438}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@122391.8] assign _T_3440 = _T_3439[63:6]; // @[Counters.scala 67:28:freechips.rocketchip.system.TinyConfig.fir@122393.8] assign _GEN_136 = _T_667 ? _T_3439 : _GEN_134; // @[CSR.scala 929:31:freechips.rocketchip.system.TinyConfig.fir@122388.6] assign _T_3453 = wdata[15]; // @[CSR.scala 768:43:freechips.rocketchip.system.TinyConfig.fir@122422.8] assign _T_3461 = reg_bp_0_control_dmode == 1'h0; // @[CSR.scala 819:37:freechips.rocketchip.system.TinyConfig.fir@122446.6] assign _T_3462 = _T_3461 | reg_debug; // @[CSR.scala 819:55:freechips.rocketchip.system.TinyConfig.fir@122447.6] assign _T_3466 = wdata[0]; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122459.10] assign _T_3467 = wdata[1]; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122461.10] assign _T_3473 = wdata[8:7]; // @[CSR.scala 822:41:freechips.rocketchip.system.TinyConfig.fir@122473.10] assign _T_3496 = _T_692 ? _T_403 : 32'h0; // @[CSR.scala 913:9:freechips.rocketchip.system.TinyConfig.fir@122505.10] assign _T_3497 = _T_3496 | io_rw_wdata; // @[CSR.scala 913:34:freechips.rocketchip.system.TinyConfig.fir@122506.10] assign _T_3502 = _T_3497 & _T_698; // @[CSR.scala 913:43:freechips.rocketchip.system.TinyConfig.fir@122511.10] assign _T_3515 = _T_3502[12]; // @[CSR.scala 828:96:freechips.rocketchip.system.TinyConfig.fir@122537.10] assign _T_3518 = _T_3502[27]; // @[CSR.scala 828:96:freechips.rocketchip.system.TinyConfig.fir@122543.10] assign _T_3520 = _T_3518 & reg_debug; // @[CSR.scala 829:38:freechips.rocketchip.system.TinyConfig.fir@122547.10] assign _T_3604 = reg_pmp_0_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122693.6] assign _T_3605 = _T_668 & _T_3604; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122694.6] assign _T_3608 = wdata[7:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@122699.8 :freechips.rocketchip.system.TinyConfig.fir@122701.8] assign _T_3609 = _T_3608[0]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122702.8] assign _T_3610 = _T_3608[1]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122704.8] assign _T_3611 = _T_3608[2]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122706.8] assign _T_3612 = _T_3608[4:3]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122708.8] assign _T_3614 = _T_3608[7]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122712.8] assign _T_3615 = _T_3610 & _T_3609; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122715.8] assign _T_3616 = reg_pmp_1_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122718.6] assign _T_3617 = _T_3616 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122719.6] assign _T_3619 = _T_3617 & _T_289; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122721.6] assign _T_3620 = reg_pmp_1_cfg_l & _T_3619; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122722.6] assign _T_3621 = reg_pmp_0_cfg_l | _T_3620; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122723.6] assign _T_3622 = _T_3621 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122724.6] assign _T_3623 = _T_672 & _T_3622; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122725.6] assign _GEN_215 = _T_3623 ? wdata : {{2'd0}, reg_pmp_0_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122726.6] assign _T_3624 = reg_pmp_1_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122729.6] assign _T_3625 = _T_668 & _T_3624; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122730.6] assign _T_3626 = wdata[31:8]; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122732.8] assign _T_3628 = _T_3626[7:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@122735.8 :freechips.rocketchip.system.TinyConfig.fir@122737.8] assign _T_3629 = _T_3628[0]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122738.8] assign _T_3630 = _T_3628[1]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122740.8] assign _T_3631 = _T_3628[2]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122742.8] assign _T_3632 = _T_3628[4:3]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122744.8] assign _T_3634 = _T_3628[7]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122748.8] assign _T_3635 = _T_3630 & _T_3629; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122751.8] assign _T_3636 = reg_pmp_2_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122754.6] assign _T_3637 = _T_3636 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122755.6] assign _T_3639 = _T_3637 & _T_298; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122757.6] assign _T_3640 = reg_pmp_2_cfg_l & _T_3639; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122758.6] assign _T_3641 = reg_pmp_1_cfg_l | _T_3640; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122759.6] assign _T_3642 = _T_3641 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122760.6] assign _T_3643 = _T_673 & _T_3642; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122761.6] assign _GEN_222 = _T_3643 ? wdata : {{2'd0}, reg_pmp_1_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122762.6] assign _T_3644 = reg_pmp_2_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122765.6] assign _T_3645 = _T_668 & _T_3644; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122766.6] assign _T_3646 = wdata[31:16]; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122768.8] assign _T_3648 = _T_3646[7:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@122771.8 :freechips.rocketchip.system.TinyConfig.fir@122773.8] assign _T_3649 = _T_3648[0]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122774.8] assign _T_3650 = _T_3648[1]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122776.8] assign _T_3651 = _T_3648[2]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122778.8] assign _T_3652 = _T_3648[4:3]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122780.8] assign _T_3654 = _T_3648[7]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122784.8] assign _T_3655 = _T_3650 & _T_3649; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122787.8] assign _T_3656 = reg_pmp_3_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122790.6] assign _T_3657 = _T_3656 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122791.6] assign _T_3659 = _T_3657 & _T_307; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122793.6] assign _T_3660 = reg_pmp_3_cfg_l & _T_3659; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122794.6] assign _T_3661 = reg_pmp_2_cfg_l | _T_3660; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122795.6] assign _T_3662 = _T_3661 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122796.6] assign _T_3663 = _T_674 & _T_3662; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122797.6] assign _GEN_229 = _T_3663 ? wdata : {{2'd0}, reg_pmp_2_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122798.6] assign _T_3664 = reg_pmp_3_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122801.6] assign _T_3665 = _T_668 & _T_3664; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122802.6] assign _T_3666 = wdata[31:24]; // @[CSR.scala 840:53:freechips.rocketchip.system.TinyConfig.fir@122804.8] assign _T_3669 = _T_3666[0]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122810.8] assign _T_3670 = _T_3666[1]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122812.8] assign _T_3671 = _T_3666[2]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122814.8] assign _T_3672 = _T_3666[4:3]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122816.8] assign _T_3674 = _T_3666[7]; // @[CSR.scala 840:46:freechips.rocketchip.system.TinyConfig.fir@122820.8] assign _T_3675 = _T_3670 & _T_3669; // @[CSR.scala 843:31:freechips.rocketchip.system.TinyConfig.fir@122823.8] assign _T_3676 = reg_pmp_4_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122826.6] assign _T_3677 = _T_3676 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122827.6] assign _T_3679 = _T_3677 & _T_316; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122829.6] assign _T_3680 = reg_pmp_4_cfg_l & _T_3679; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122830.6] assign _T_3681 = reg_pmp_3_cfg_l | _T_3680; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122831.6] assign _T_3682 = _T_3681 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122832.6] assign _T_3683 = _T_675 & _T_3682; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122833.6] assign _GEN_236 = _T_3683 ? wdata : {{2'd0}, reg_pmp_3_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122834.6] assign _T_3684 = reg_pmp_4_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122837.6] assign _T_3685 = _T_669 & _T_3684; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122838.6] assign _T_3696 = reg_pmp_5_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122862.6] assign _T_3697 = _T_3696 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122863.6] assign _T_3699 = _T_3697 & _T_325; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122865.6] assign _T_3700 = reg_pmp_5_cfg_l & _T_3699; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122866.6] assign _T_3701 = reg_pmp_4_cfg_l | _T_3700; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122867.6] assign _T_3702 = _T_3701 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122868.6] assign _T_3703 = _T_676 & _T_3702; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122869.6] assign _GEN_243 = _T_3703 ? wdata : {{2'd0}, reg_pmp_4_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122870.6] assign _T_3704 = reg_pmp_5_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122873.6] assign _T_3705 = _T_669 & _T_3704; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122874.6] assign _T_3716 = reg_pmp_6_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122898.6] assign _T_3717 = _T_3716 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122899.6] assign _T_3719 = _T_3717 & _T_334; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122901.6] assign _T_3720 = reg_pmp_6_cfg_l & _T_3719; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122902.6] assign _T_3721 = reg_pmp_5_cfg_l | _T_3720; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122903.6] assign _T_3722 = _T_3721 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122904.6] assign _T_3723 = _T_677 & _T_3722; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122905.6] assign _GEN_250 = _T_3723 ? wdata : {{2'd0}, reg_pmp_5_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122906.6] assign _T_3724 = reg_pmp_6_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122909.6] assign _T_3725 = _T_669 & _T_3724; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122910.6] assign _T_3736 = reg_pmp_7_cfg_a[1]; // @[PMP.scala 45:20:freechips.rocketchip.system.TinyConfig.fir@122934.6] assign _T_3737 = _T_3736 == 1'h0; // @[PMP.scala 47:13:freechips.rocketchip.system.TinyConfig.fir@122935.6] assign _T_3739 = _T_3737 & _T_343; // @[PMP.scala 47:20:freechips.rocketchip.system.TinyConfig.fir@122937.6] assign _T_3740 = reg_pmp_7_cfg_l & _T_3739; // @[PMP.scala 49:62:freechips.rocketchip.system.TinyConfig.fir@122938.6] assign _T_3741 = reg_pmp_6_cfg_l | _T_3740; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122939.6] assign _T_3742 = _T_3741 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122940.6] assign _T_3743 = _T_678 & _T_3742; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122941.6] assign _GEN_257 = _T_3743 ? wdata : {{2'd0}, reg_pmp_6_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122942.6] assign _T_3744 = reg_pmp_7_cfg_l == 1'h0; // @[CSR.scala 839:60:freechips.rocketchip.system.TinyConfig.fir@122945.6] assign _T_3745 = _T_669 & _T_3744; // @[CSR.scala 839:57:freechips.rocketchip.system.TinyConfig.fir@122946.6] assign _T_3761 = reg_pmp_7_cfg_l | _T_3740; // @[PMP.scala 49:44:freechips.rocketchip.system.TinyConfig.fir@122975.6] assign _T_3762 = _T_3761 == 1'h0; // @[CSR.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@122976.6] assign _T_3763 = _T_679 & _T_3762; // @[CSR.scala 848:45:freechips.rocketchip.system.TinyConfig.fir@122977.6] assign _GEN_264 = _T_3763 ? wdata : {{2'd0}, reg_pmp_7_addr}; // @[CSR.scala 848:71:freechips.rocketchip.system.TinyConfig.fir@122978.6] assign _GEN_282 = csr_wen ? _GEN_132 : {{57'd0}, _T_92}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_284 = csr_wen ? _GEN_136 : {{57'd0}, _T_84}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_329 = csr_wen ? _GEN_215 : {{2'd0}, reg_pmp_0_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_336 = csr_wen ? _GEN_222 : {{2'd0}, reg_pmp_1_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_343 = csr_wen ? _GEN_229 : {{2'd0}, reg_pmp_2_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_350 = csr_wen ? _GEN_236 : {{2'd0}, reg_pmp_3_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_357 = csr_wen ? _GEN_243 : {{2'd0}, reg_pmp_4_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_364 = csr_wen ? _GEN_250 : {{2'd0}, reg_pmp_5_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_371 = csr_wen ? _GEN_257 : {{2'd0}, reg_pmp_6_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _GEN_378 = csr_wen ? _GEN_264 : {{2'd0}, reg_pmp_7_addr}; // @[CSR.scala 699:18:freechips.rocketchip.system.TinyConfig.fir@122190.4] assign _T_3810 = io_retire > 1'h0; // @[CSR.scala 892:26:freechips.rocketchip.system.TinyConfig.fir@123141.4] assign io_rw_rdata = _T_1742[31:0]; // @[CSR.scala 672:15:freechips.rocketchip.system.TinyConfig.fir@120066.4] assign io_decode_0_fp_illegal = _T_764 | _T_766; // @[CSR.scala 524:23:freechips.rocketchip.system.TinyConfig.fir@118958.4] assign io_decode_0_fp_csr = 1'h0; // @[CSR.scala 525:19:freechips.rocketchip.system.TinyConfig.fir@118964.4] assign io_decode_0_read_illegal = _T_1064 | _T_1065; // @[CSR.scala 527:25:freechips.rocketchip.system.TinyConfig.fir@119260.4] assign io_decode_0_write_illegal = _T_1067 == 2'h3; // @[CSR.scala 533:26:freechips.rocketchip.system.TinyConfig.fir@119263.4] assign io_decode_0_write_flush = _T_1075 == 1'h0; // @[CSR.scala 534:24:freechips.rocketchip.system.TinyConfig.fir@119272.4] assign io_csr_stall = reg_wfi | io_status_cease; // @[CSR.scala 663:16:freechips.rocketchip.system.TinyConfig.fir@119785.4] assign io_eret = _T_1130 | insn_ret; // @[CSR.scala 566:11:freechips.rocketchip.system.TinyConfig.fir@119341.4] assign io_singleStep = reg_dcsr_step & _T_1062; // @[CSR.scala 567:17:freechips.rocketchip.system.TinyConfig.fir@119344.4] assign io_status_debug = reg_debug; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 570:19:freechips.rocketchip.system.TinyConfig.fir@119350.4] assign io_status_cease = _T_1481; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 664:19:freechips.rocketchip.system.TinyConfig.fir@119790.4] assign io_status_isa = reg_misa; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 571:17:freechips.rocketchip.system.TinyConfig.fir@119351.4] assign io_status_dprv = 2'h3; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 574:18:freechips.rocketchip.system.TinyConfig.fir@119359.4] assign io_status_prv = 2'h3; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_sd = _T_1134 | _T_1135; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 569:16:freechips.rocketchip.system.TinyConfig.fir@119349.4] assign io_status_zero2 = 27'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_sxl = 2'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 573:17:freechips.rocketchip.system.TinyConfig.fir@119353.4] assign io_status_uxl = 2'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 572:17:freechips.rocketchip.system.TinyConfig.fir@119352.4] assign io_status_sd_rv32 = io_status_sd; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4 CSR.scala 576:23:freechips.rocketchip.system.TinyConfig.fir@119360.4] assign io_status_zero1 = 8'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_tsr = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_tw = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_tvm = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_mxr = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_sum = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_mprv = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_xs = 2'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_fs = 2'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_mpp = 2'h3; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_hpp = 2'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_spp = reg_mstatus_spp; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_mpie = reg_mstatus_mpie; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_hpie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_spie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_upie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_mie = reg_mstatus_mie; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_hie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_sie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_status_uie = 1'h0; // @[CSR.scala 568:13:freechips.rocketchip.system.TinyConfig.fir@119345.4] assign io_evec = insn_ret ? _GEN_95 : tvec; // @[CSR.scala 564:11:freechips.rocketchip.system.TinyConfig.fir@119337.4 CSR.scala 648:15:freechips.rocketchip.system.TinyConfig.fir@119755.8 CSR.scala 652:15:freechips.rocketchip.system.TinyConfig.fir@119768.10 CSR.scala 658:15:freechips.rocketchip.system.TinyConfig.fir@119780.10] assign io_time = _T_97[31:0]; // @[CSR.scala 662:11:freechips.rocketchip.system.TinyConfig.fir@119783.4] assign io_interrupt = _T_275 & _T_277; // @[CSR.scala 361:16:freechips.rocketchip.system.TinyConfig.fir@118407.4] assign io_interrupt_cause = 32'h80000000 + _GEN_418; // @[CSR.scala 362:22:freechips.rocketchip.system.TinyConfig.fir@118408.4] assign io_bp_0_control_action = reg_bp_0_control_action; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_bp_0_control_tmatch = reg_bp_0_control_tmatch; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_bp_0_control_x = reg_bp_0_control_x; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_bp_0_control_w = reg_bp_0_control_w; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_bp_0_control_r = reg_bp_0_control_r; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_bp_0_address = reg_bp_0_address; // @[CSR.scala 363:9:freechips.rocketchip.system.TinyConfig.fir@118409.4] assign io_pmp_0_cfg_l = reg_pmp_0_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_cfg_a = reg_pmp_0_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_cfg_x = reg_pmp_0_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_cfg_w = reg_pmp_0_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_cfg_r = reg_pmp_0_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_addr = reg_pmp_0_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_0_mask = _T_287[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118506.4] assign io_pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_addr = reg_pmp_1_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_1_mask = _T_296[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118507.4] assign io_pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_addr = reg_pmp_2_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_2_mask = _T_305[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118508.4] assign io_pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_addr = reg_pmp_3_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_3_mask = _T_314[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118509.4] assign io_pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_addr = reg_pmp_4_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_4_mask = _T_323[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118510.4] assign io_pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_addr = reg_pmp_5_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_5_mask = _T_332[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118511.4] assign io_pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_addr = reg_pmp_6_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_6_mask = _T_341[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118512.4] assign io_pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_addr = reg_pmp_7_addr; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_pmp_7_mask = _T_350[31:0]; // @[CSR.scala 364:10:freechips.rocketchip.system.TinyConfig.fir@118513.4] assign io_trace_0_valid = _T_3810 | io_trace_0_exception; // @[CSR.scala 892:13:freechips.rocketchip.system.TinyConfig.fir@123143.4] assign io_trace_0_iaddr = io_pc; // @[CSR.scala 894:13:freechips.rocketchip.system.TinyConfig.fir@123145.4] assign io_trace_0_insn = io_inst_0; // @[CSR.scala 893:12:freechips.rocketchip.system.TinyConfig.fir@123144.4] assign io_trace_0_exception = _T_1130 | io_exception; // @[CSR.scala 891:17:freechips.rocketchip.system.TinyConfig.fir@123140.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; reg_mstatus_spp = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; reg_mstatus_mpie = _RAND_1[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; reg_mstatus_mie = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; reg_dcsr_ebreakm = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; reg_dcsr_cause = _RAND_4[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; reg_dcsr_step = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; reg_debug = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; reg_dpc = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; reg_dscratch = _RAND_8[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; reg_singleStepped = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; reg_bp_0_control_dmode = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; reg_bp_0_control_action = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; reg_bp_0_control_tmatch = _RAND_12[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; reg_bp_0_control_x = _RAND_13[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; reg_bp_0_control_w = _RAND_14[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; reg_bp_0_control_r = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; reg_bp_0_address = _RAND_16[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; reg_pmp_0_cfg_l = _RAND_17[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; reg_pmp_0_cfg_a = _RAND_18[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; reg_pmp_0_cfg_x = _RAND_19[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; reg_pmp_0_cfg_w = _RAND_20[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; reg_pmp_0_cfg_r = _RAND_21[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; reg_pmp_0_addr = _RAND_22[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; reg_pmp_1_cfg_l = _RAND_23[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_24 = {1{`RANDOM}}; reg_pmp_1_cfg_a = _RAND_24[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_25 = {1{`RANDOM}}; reg_pmp_1_cfg_x = _RAND_25[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_26 = {1{`RANDOM}}; reg_pmp_1_cfg_w = _RAND_26[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_27 = {1{`RANDOM}}; reg_pmp_1_cfg_r = _RAND_27[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_28 = {1{`RANDOM}}; reg_pmp_1_addr = _RAND_28[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_29 = {1{`RANDOM}}; reg_pmp_2_cfg_l = _RAND_29[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_30 = {1{`RANDOM}}; reg_pmp_2_cfg_a = _RAND_30[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_31 = {1{`RANDOM}}; reg_pmp_2_cfg_x = _RAND_31[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_32 = {1{`RANDOM}}; reg_pmp_2_cfg_w = _RAND_32[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_33 = {1{`RANDOM}}; reg_pmp_2_cfg_r = _RAND_33[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_34 = {1{`RANDOM}}; reg_pmp_2_addr = _RAND_34[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_35 = {1{`RANDOM}}; reg_pmp_3_cfg_l = _RAND_35[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_36 = {1{`RANDOM}}; reg_pmp_3_cfg_a = _RAND_36[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_37 = {1{`RANDOM}}; reg_pmp_3_cfg_x = _RAND_37[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_38 = {1{`RANDOM}}; reg_pmp_3_cfg_w = _RAND_38[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_39 = {1{`RANDOM}}; reg_pmp_3_cfg_r = _RAND_39[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_40 = {1{`RANDOM}}; reg_pmp_3_addr = _RAND_40[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_41 = {1{`RANDOM}}; reg_pmp_4_cfg_l = _RAND_41[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_42 = {1{`RANDOM}}; reg_pmp_4_cfg_a = _RAND_42[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_43 = {1{`RANDOM}}; reg_pmp_4_cfg_x = _RAND_43[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_44 = {1{`RANDOM}}; reg_pmp_4_cfg_w = _RAND_44[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_45 = {1{`RANDOM}}; reg_pmp_4_cfg_r = _RAND_45[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_46 = {1{`RANDOM}}; reg_pmp_4_addr = _RAND_46[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_47 = {1{`RANDOM}}; reg_pmp_5_cfg_l = _RAND_47[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_48 = {1{`RANDOM}}; reg_pmp_5_cfg_a = _RAND_48[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_49 = {1{`RANDOM}}; reg_pmp_5_cfg_x = _RAND_49[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_50 = {1{`RANDOM}}; reg_pmp_5_cfg_w = _RAND_50[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_51 = {1{`RANDOM}}; reg_pmp_5_cfg_r = _RAND_51[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_52 = {1{`RANDOM}}; reg_pmp_5_addr = _RAND_52[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_53 = {1{`RANDOM}}; reg_pmp_6_cfg_l = _RAND_53[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_54 = {1{`RANDOM}}; reg_pmp_6_cfg_a = _RAND_54[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_55 = {1{`RANDOM}}; reg_pmp_6_cfg_x = _RAND_55[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_56 = {1{`RANDOM}}; reg_pmp_6_cfg_w = _RAND_56[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_57 = {1{`RANDOM}}; reg_pmp_6_cfg_r = _RAND_57[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_58 = {1{`RANDOM}}; reg_pmp_6_addr = _RAND_58[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_59 = {1{`RANDOM}}; reg_pmp_7_cfg_l = _RAND_59[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_60 = {1{`RANDOM}}; reg_pmp_7_cfg_a = _RAND_60[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_61 = {1{`RANDOM}}; reg_pmp_7_cfg_x = _RAND_61[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_62 = {1{`RANDOM}}; reg_pmp_7_cfg_w = _RAND_62[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_63 = {1{`RANDOM}}; reg_pmp_7_cfg_r = _RAND_63[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_64 = {1{`RANDOM}}; reg_pmp_7_addr = _RAND_64[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_65 = {1{`RANDOM}}; reg_mie = _RAND_65[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_66 = {1{`RANDOM}}; reg_mepc = _RAND_66[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_67 = {1{`RANDOM}}; reg_mcause = _RAND_67[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_68 = {1{`RANDOM}}; reg_mtval = _RAND_68[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_69 = {1{`RANDOM}}; reg_mscratch = _RAND_69[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_70 = {1{`RANDOM}}; reg_mtvec = _RAND_70[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_71 = {1{`RANDOM}}; reg_wfi = _RAND_71[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_72 = {1{`RANDOM}}; _T_83 = _RAND_72[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_73 = {2{`RANDOM}}; _T_85 = _RAND_73[57:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_74 = {1{`RANDOM}}; _T_91 = _RAND_74[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_75 = {2{`RANDOM}}; _T_93 = _RAND_75[57:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_76 = {1{`RANDOM}}; reg_misa = _RAND_76[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_77 = {1{`RANDOM}}; _T_1481 = _RAND_77[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin reg_mstatus_spp <= 1'h0; end else begin reg_mstatus_spp <= _GEN_85[0]; end if (reset) begin reg_mstatus_mpie <= 1'h0; end else begin if (csr_wen) begin if (_T_565) begin reg_mstatus_mpie <= _T_3342; end else begin if (insn_ret) begin if (_T_1468) begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mpie <= reg_mstatus_mie; end end end else begin reg_mstatus_mpie <= 1'h1; end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mpie <= reg_mstatus_mie; end end end end end else begin if (insn_ret) begin if (_T_1468) begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mpie <= reg_mstatus_mie; end end end else begin reg_mstatus_mpie <= 1'h1; end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mpie <= reg_mstatus_mie; end end end end end if (reset) begin reg_mstatus_mie <= 1'h0; end else begin if (csr_wen) begin if (_T_565) begin reg_mstatus_mie <= _T_3338; end else begin if (insn_ret) begin if (_T_1468) begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mie <= 1'h0; end end end else begin reg_mstatus_mie <= reg_mstatus_mpie; end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mie <= 1'h0; end end end end end else begin if (insn_ret) begin if (_T_1468) begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mie <= 1'h0; end end end else begin reg_mstatus_mie <= reg_mstatus_mpie; end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mstatus_mie <= 1'h0; end end end end end if (reset) begin reg_dcsr_ebreakm <= 1'h0; end else begin if (csr_wen) begin if (_T_574) begin reg_dcsr_ebreakm <= _T_3453; end end end if (reset) begin reg_dcsr_cause <= 3'h0; end else begin if (exception) begin if (trapToDebug) begin if (_T_1062) begin if (reg_singleStepped) begin reg_dcsr_cause <= 3'h4; end else begin reg_dcsr_cause <= {{1'd0}, _T_1178}; end end end end end if (reset) begin reg_dcsr_step <= 1'h0; end else begin if (csr_wen) begin if (_T_574) begin reg_dcsr_step <= _T_3369; end end end if (reset) begin reg_debug <= 1'h0; end else begin if (insn_ret) begin if (_T_1468) begin reg_debug <= 1'h0; end else begin if (exception) begin if (trapToDebug) begin if (_T_1062) begin reg_debug <= 1'h1; end end end end end else begin if (exception) begin if (trapToDebug) begin if (_T_1062) begin reg_debug <= 1'h1; end end end end end if (csr_wen) begin if (_T_575) begin reg_dpc <= _T_3424; end else begin if (exception) begin if (trapToDebug) begin if (_T_1062) begin reg_dpc <= epc; end end end end end else begin if (exception) begin if (trapToDebug) begin if (_T_1062) begin reg_dpc <= epc; end end end end if (csr_wen) begin if (_T_576) begin reg_dscratch <= wdata; end end if (_T_273) begin reg_singleStepped <= 1'h0; end else begin if (_T_1160) begin reg_singleStepped <= 1'h1; end end if (reset) begin reg_bp_0_control_dmode <= 1'h0; end else begin if (csr_wen) begin if (_T_3462) begin if (_T_562) begin reg_bp_0_control_dmode <= _T_3520; end end end end if (reset) begin reg_bp_0_control_action <= 1'h0; end else begin if (csr_wen) begin if (_T_3462) begin if (_T_562) begin if (_T_3520) begin reg_bp_0_control_action <= _T_3515; end else begin reg_bp_0_control_action <= 1'h0; end end end end end if (csr_wen) begin if (_T_3462) begin if (_T_562) begin reg_bp_0_control_tmatch <= _T_3473; end end end if (reset) begin reg_bp_0_control_x <= 1'h0; end else begin if (csr_wen) begin if (_T_3462) begin if (_T_562) begin reg_bp_0_control_x <= _T_3369; end end end end if (reset) begin reg_bp_0_control_w <= 1'h0; end else begin if (csr_wen) begin if (_T_3462) begin if (_T_562) begin reg_bp_0_control_w <= _T_3467; end end end end if (reset) begin reg_bp_0_control_r <= 1'h0; end else begin if (csr_wen) begin if (_T_3462) begin if (_T_562) begin reg_bp_0_control_r <= _T_3466; end end end end if (csr_wen) begin if (_T_3462) begin if (_T_563) begin reg_bp_0_address <= wdata; end end end if (reset) begin reg_pmp_0_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3605) begin reg_pmp_0_cfg_l <= _T_3614; end end end if (reset) begin reg_pmp_0_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3605) begin reg_pmp_0_cfg_a <= _T_3612; end end end if (csr_wen) begin if (_T_3605) begin reg_pmp_0_cfg_x <= _T_3611; end end if (csr_wen) begin if (_T_3605) begin reg_pmp_0_cfg_w <= _T_3615; end end if (csr_wen) begin if (_T_3605) begin reg_pmp_0_cfg_r <= _T_3609; end end reg_pmp_0_addr <= _GEN_329[29:0]; if (reset) begin reg_pmp_1_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3625) begin reg_pmp_1_cfg_l <= _T_3634; end end end if (reset) begin reg_pmp_1_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3625) begin reg_pmp_1_cfg_a <= _T_3632; end end end if (csr_wen) begin if (_T_3625) begin reg_pmp_1_cfg_x <= _T_3631; end end if (csr_wen) begin if (_T_3625) begin reg_pmp_1_cfg_w <= _T_3635; end end if (csr_wen) begin if (_T_3625) begin reg_pmp_1_cfg_r <= _T_3629; end end reg_pmp_1_addr <= _GEN_336[29:0]; if (reset) begin reg_pmp_2_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3645) begin reg_pmp_2_cfg_l <= _T_3654; end end end if (reset) begin reg_pmp_2_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3645) begin reg_pmp_2_cfg_a <= _T_3652; end end end if (csr_wen) begin if (_T_3645) begin reg_pmp_2_cfg_x <= _T_3651; end end if (csr_wen) begin if (_T_3645) begin reg_pmp_2_cfg_w <= _T_3655; end end if (csr_wen) begin if (_T_3645) begin reg_pmp_2_cfg_r <= _T_3649; end end reg_pmp_2_addr <= _GEN_343[29:0]; if (reset) begin reg_pmp_3_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3665) begin reg_pmp_3_cfg_l <= _T_3674; end end end if (reset) begin reg_pmp_3_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3665) begin reg_pmp_3_cfg_a <= _T_3672; end end end if (csr_wen) begin if (_T_3665) begin reg_pmp_3_cfg_x <= _T_3671; end end if (csr_wen) begin if (_T_3665) begin reg_pmp_3_cfg_w <= _T_3675; end end if (csr_wen) begin if (_T_3665) begin reg_pmp_3_cfg_r <= _T_3669; end end reg_pmp_3_addr <= _GEN_350[29:0]; if (reset) begin reg_pmp_4_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3685) begin reg_pmp_4_cfg_l <= _T_3614; end end end if (reset) begin reg_pmp_4_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3685) begin reg_pmp_4_cfg_a <= _T_3612; end end end if (csr_wen) begin if (_T_3685) begin reg_pmp_4_cfg_x <= _T_3611; end end if (csr_wen) begin if (_T_3685) begin reg_pmp_4_cfg_w <= _T_3615; end end if (csr_wen) begin if (_T_3685) begin reg_pmp_4_cfg_r <= _T_3609; end end reg_pmp_4_addr <= _GEN_357[29:0]; if (reset) begin reg_pmp_5_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3705) begin reg_pmp_5_cfg_l <= _T_3634; end end end if (reset) begin reg_pmp_5_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3705) begin reg_pmp_5_cfg_a <= _T_3632; end end end if (csr_wen) begin if (_T_3705) begin reg_pmp_5_cfg_x <= _T_3631; end end if (csr_wen) begin if (_T_3705) begin reg_pmp_5_cfg_w <= _T_3635; end end if (csr_wen) begin if (_T_3705) begin reg_pmp_5_cfg_r <= _T_3629; end end reg_pmp_5_addr <= _GEN_364[29:0]; if (reset) begin reg_pmp_6_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3725) begin reg_pmp_6_cfg_l <= _T_3654; end end end if (reset) begin reg_pmp_6_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3725) begin reg_pmp_6_cfg_a <= _T_3652; end end end if (csr_wen) begin if (_T_3725) begin reg_pmp_6_cfg_x <= _T_3651; end end if (csr_wen) begin if (_T_3725) begin reg_pmp_6_cfg_w <= _T_3655; end end if (csr_wen) begin if (_T_3725) begin reg_pmp_6_cfg_r <= _T_3649; end end reg_pmp_6_addr <= _GEN_371[29:0]; if (reset) begin reg_pmp_7_cfg_l <= 1'h0; end else begin if (csr_wen) begin if (_T_3745) begin reg_pmp_7_cfg_l <= _T_3674; end end end if (reset) begin reg_pmp_7_cfg_a <= 2'h0; end else begin if (csr_wen) begin if (_T_3745) begin reg_pmp_7_cfg_a <= _T_3672; end end end if (csr_wen) begin if (_T_3745) begin reg_pmp_7_cfg_x <= _T_3671; end end if (csr_wen) begin if (_T_3745) begin reg_pmp_7_cfg_w <= _T_3675; end end if (csr_wen) begin if (_T_3745) begin reg_pmp_7_cfg_r <= _T_3669; end end reg_pmp_7_addr <= _GEN_378[29:0]; if (csr_wen) begin if (_T_568) begin reg_mie <= _T_3421; end end if (csr_wen) begin if (_T_570) begin reg_mepc <= _T_3424; end else begin if (exception) begin if (!(trapToDebug)) begin reg_mepc <= epc; end end end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mepc <= epc; end end end if (csr_wen) begin if (_T_572) begin reg_mcause <= _T_3425; end else begin if (exception) begin if (!(trapToDebug)) begin if (insn_call) begin reg_mcause <= 32'hb; end else begin if (insn_break) begin reg_mcause <= 32'h3; end else begin reg_mcause <= io_cause; end end end end end end else begin if (exception) begin if (!(trapToDebug)) begin if (insn_call) begin reg_mcause <= 32'hb; end else begin if (insn_break) begin reg_mcause <= 32'h3; end else begin reg_mcause <= io_cause; end end end end end if (csr_wen) begin if (_T_571) begin reg_mtval <= wdata; end else begin if (exception) begin if (!(trapToDebug)) begin reg_mtval <= io_tval; end end end end else begin if (exception) begin if (!(trapToDebug)) begin reg_mtval <= io_tval; end end end if (csr_wen) begin if (_T_569) begin reg_mscratch <= wdata; end end if (reset) begin reg_mtvec <= 32'h0; end else begin if (csr_wen) begin if (_T_566) begin reg_mtvec <= wdata; end end end if (reset) begin _T_83 <= 6'h0; end else begin _T_83 <= _GEN_284[5:0]; end if (reset) begin _T_85 <= 58'h0; end else begin if (csr_wen) begin if (_T_667) begin _T_85 <= _T_3440; end else begin if (_T_578) begin _T_85 <= _T_3436; end else begin if (_T_86) begin _T_85 <= _T_88; end end end end else begin if (_T_86) begin _T_85 <= _T_88; end end end if (reset) begin reg_misa <= 32'h40801105; end else begin if (csr_wen) begin if (_T_564) begin if (_T_3370) begin reg_misa <= _T_3379; end end end end if (reset) begin _T_1481 <= 1'h0; end else begin if (insn_cease) begin _T_1481 <= 1'h1; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1151) begin $fwrite(32'h80000002,"Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:579 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n"); // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119374.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1151) begin $fatal; // @[CSR.scala 579:9:freechips.rocketchip.system.TinyConfig.fir@119375.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1173) begin $fwrite(32'h80000002,"Assertion failed\n at CSR.scala:587 assert(!reg_singleStepped || io.retire === UInt(0))\n"); // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119416.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_1173) begin $fatal; // @[CSR.scala 587:9:freechips.rocketchip.system.TinyConfig.fir@119417.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end always @(posedge io_ungated_clock) begin if (reset) begin reg_wfi <= 1'h0; end else begin if (_T_1158) begin reg_wfi <= 1'h0; end else begin if (_T_1155) begin reg_wfi <= 1'h1; end end end if (reset) begin _T_91 <= 6'h0; end else begin _T_91 <= _GEN_282[5:0]; end if (reset) begin _T_93 <= 58'h0; end else begin if (csr_wen) begin if (_T_666) begin _T_93 <= _T_3433; end else begin if (_T_577) begin _T_93 <= _T_3429; end else begin if (_T_94) begin _T_93 <= _T_96; end end end end else begin if (_T_94) begin _T_93 <= _T_96; end end end end endmodule module BreakpointUnit( // @[:freechips.rocketchip.system.TinyConfig.fir@123153.2] input io_status_debug, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input io_bp_0_control_action, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input [1:0] io_bp_0_control_tmatch, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input io_bp_0_control_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input io_bp_0_control_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input io_bp_0_control_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input [31:0] io_bp_0_address, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input [31:0] io_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] input [31:0] io_ea, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_xcpt_if, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_xcpt_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_xcpt_st, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_debug_if, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_debug_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] output io_debug_st // @[:freechips.rocketchip.system.TinyConfig.fir@123156.4] ); wire _T; // @[Breakpoint.scala 30:35:freechips.rocketchip.system.TinyConfig.fir@123167.4] wire _T_7; // @[Breakpoint.scala 79:16:freechips.rocketchip.system.TinyConfig.fir@123174.4] wire _T_8; // @[Breakpoint.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@123175.4] wire _T_9; // @[Breakpoint.scala 44:8:freechips.rocketchip.system.TinyConfig.fir@123176.4] wire _T_10; // @[Breakpoint.scala 44:36:freechips.rocketchip.system.TinyConfig.fir@123177.4] wire _T_11; // @[Breakpoint.scala 44:20:freechips.rocketchip.system.TinyConfig.fir@123178.4] wire [31:0] _T_12; // @[Breakpoint.scala 41:6:freechips.rocketchip.system.TinyConfig.fir@123179.4] wire _T_14; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123181.4] wire _T_15; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123182.4] wire _T_16; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123183.4] wire _T_17; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123184.4] wire _T_18; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123185.4] wire _T_19; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123186.4] wire [3:0] _T_22; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123189.4] wire [31:0] _GEN_9; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123190.4] wire [31:0] _T_23; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123190.4] wire [31:0] _T_24; // @[Breakpoint.scala 41:24:freechips.rocketchip.system.TinyConfig.fir@123191.4] wire [31:0] _T_35; // @[Breakpoint.scala 41:33:freechips.rocketchip.system.TinyConfig.fir@123202.4] wire _T_36; // @[Breakpoint.scala 41:19:freechips.rocketchip.system.TinyConfig.fir@123203.4] wire _T_37; // @[Breakpoint.scala 47:8:freechips.rocketchip.system.TinyConfig.fir@123204.4] wire _T_38; // @[Breakpoint.scala 79:32:freechips.rocketchip.system.TinyConfig.fir@123205.4] wire _T_39; // @[Breakpoint.scala 80:16:freechips.rocketchip.system.TinyConfig.fir@123206.4] wire _T_70; // @[Breakpoint.scala 80:32:freechips.rocketchip.system.TinyConfig.fir@123237.4] wire _T_71; // @[Breakpoint.scala 81:16:freechips.rocketchip.system.TinyConfig.fir@123238.4] wire _T_73; // @[Breakpoint.scala 44:8:freechips.rocketchip.system.TinyConfig.fir@123240.4] wire _T_75; // @[Breakpoint.scala 44:20:freechips.rocketchip.system.TinyConfig.fir@123242.4] wire [31:0] _T_76; // @[Breakpoint.scala 41:6:freechips.rocketchip.system.TinyConfig.fir@123243.4] wire [31:0] _T_87; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123254.4] wire _T_100; // @[Breakpoint.scala 41:19:freechips.rocketchip.system.TinyConfig.fir@123267.4] wire _T_101; // @[Breakpoint.scala 47:8:freechips.rocketchip.system.TinyConfig.fir@123268.4] wire _T_102; // @[Breakpoint.scala 81:32:freechips.rocketchip.system.TinyConfig.fir@123269.4] wire _T_106; // @[Breakpoint.scala 88:51:freechips.rocketchip.system.TinyConfig.fir@123276.6] assign _T = io_status_debug == 1'h0; // @[Breakpoint.scala 30:35:freechips.rocketchip.system.TinyConfig.fir@123167.4] assign _T_7 = _T & io_bp_0_control_r; // @[Breakpoint.scala 79:16:freechips.rocketchip.system.TinyConfig.fir@123174.4] assign _T_8 = io_bp_0_control_tmatch[1]; // @[Breakpoint.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@123175.4] assign _T_9 = io_ea >= io_bp_0_address; // @[Breakpoint.scala 44:8:freechips.rocketchip.system.TinyConfig.fir@123176.4] assign _T_10 = io_bp_0_control_tmatch[0]; // @[Breakpoint.scala 44:36:freechips.rocketchip.system.TinyConfig.fir@123177.4] assign _T_11 = _T_9 ^ _T_10; // @[Breakpoint.scala 44:20:freechips.rocketchip.system.TinyConfig.fir@123178.4] assign _T_12 = ~ io_ea; // @[Breakpoint.scala 41:6:freechips.rocketchip.system.TinyConfig.fir@123179.4] assign _T_14 = io_bp_0_address[0]; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123181.4] assign _T_15 = _T_10 & _T_14; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123182.4] assign _T_16 = io_bp_0_address[1]; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123183.4] assign _T_17 = _T_15 & _T_16; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123184.4] assign _T_18 = io_bp_0_address[2]; // @[Breakpoint.scala 38:83:freechips.rocketchip.system.TinyConfig.fir@123185.4] assign _T_19 = _T_17 & _T_18; // @[Breakpoint.scala 38:73:freechips.rocketchip.system.TinyConfig.fir@123186.4] assign _T_22 = {_T_19,_T_17,_T_15,_T_10}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123189.4] assign _GEN_9 = {{28'd0}, _T_22}; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123190.4] assign _T_23 = _T_12 | _GEN_9; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123190.4] assign _T_24 = ~ io_bp_0_address; // @[Breakpoint.scala 41:24:freechips.rocketchip.system.TinyConfig.fir@123191.4] assign _T_35 = _T_24 | _GEN_9; // @[Breakpoint.scala 41:33:freechips.rocketchip.system.TinyConfig.fir@123202.4] assign _T_36 = _T_23 == _T_35; // @[Breakpoint.scala 41:19:freechips.rocketchip.system.TinyConfig.fir@123203.4] assign _T_37 = _T_8 ? _T_11 : _T_36; // @[Breakpoint.scala 47:8:freechips.rocketchip.system.TinyConfig.fir@123204.4] assign _T_38 = _T_7 & _T_37; // @[Breakpoint.scala 79:32:freechips.rocketchip.system.TinyConfig.fir@123205.4] assign _T_39 = _T & io_bp_0_control_w; // @[Breakpoint.scala 80:16:freechips.rocketchip.system.TinyConfig.fir@123206.4] assign _T_70 = _T_39 & _T_37; // @[Breakpoint.scala 80:32:freechips.rocketchip.system.TinyConfig.fir@123237.4] assign _T_71 = _T & io_bp_0_control_x; // @[Breakpoint.scala 81:16:freechips.rocketchip.system.TinyConfig.fir@123238.4] assign _T_73 = io_pc >= io_bp_0_address; // @[Breakpoint.scala 44:8:freechips.rocketchip.system.TinyConfig.fir@123240.4] assign _T_75 = _T_73 ^ _T_10; // @[Breakpoint.scala 44:20:freechips.rocketchip.system.TinyConfig.fir@123242.4] assign _T_76 = ~ io_pc; // @[Breakpoint.scala 41:6:freechips.rocketchip.system.TinyConfig.fir@123243.4] assign _T_87 = _T_76 | _GEN_9; // @[Breakpoint.scala 41:9:freechips.rocketchip.system.TinyConfig.fir@123254.4] assign _T_100 = _T_87 == _T_35; // @[Breakpoint.scala 41:19:freechips.rocketchip.system.TinyConfig.fir@123267.4] assign _T_101 = _T_8 ? _T_75 : _T_100; // @[Breakpoint.scala 47:8:freechips.rocketchip.system.TinyConfig.fir@123268.4] assign _T_102 = _T_71 & _T_101; // @[Breakpoint.scala 81:32:freechips.rocketchip.system.TinyConfig.fir@123269.4] assign _T_106 = io_bp_0_control_action == 1'h0; // @[Breakpoint.scala 88:51:freechips.rocketchip.system.TinyConfig.fir@123276.6] assign io_xcpt_if = _T_102 ? _T_106 : 1'h0; // @[Breakpoint.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@123161.4 Breakpoint.scala 90:40:freechips.rocketchip.system.TinyConfig.fir@123295.6] assign io_xcpt_ld = _T_38 ? _T_106 : 1'h0; // @[Breakpoint.scala 71:14:freechips.rocketchip.system.TinyConfig.fir@123162.4 Breakpoint.scala 88:40:freechips.rocketchip.system.TinyConfig.fir@123277.6] assign io_xcpt_st = _T_70 ? _T_106 : 1'h0; // @[Breakpoint.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@123163.4 Breakpoint.scala 89:40:freechips.rocketchip.system.TinyConfig.fir@123286.6] assign io_debug_if = _T_102 ? io_bp_0_control_action : 1'h0; // @[Breakpoint.scala 73:15:freechips.rocketchip.system.TinyConfig.fir@123164.4 Breakpoint.scala 90:73:freechips.rocketchip.system.TinyConfig.fir@123297.6] assign io_debug_ld = _T_38 ? io_bp_0_control_action : 1'h0; // @[Breakpoint.scala 74:15:freechips.rocketchip.system.TinyConfig.fir@123165.4 Breakpoint.scala 88:73:freechips.rocketchip.system.TinyConfig.fir@123279.6] assign io_debug_st = _T_70 ? io_bp_0_control_action : 1'h0; // @[Breakpoint.scala 75:15:freechips.rocketchip.system.TinyConfig.fir@123166.4 Breakpoint.scala 89:73:freechips.rocketchip.system.TinyConfig.fir@123288.6] endmodule module ALU( // @[:freechips.rocketchip.system.TinyConfig.fir@123304.2] input [3:0] io_fn, // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] input [31:0] io_in2, // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] input [31:0] io_in1, // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] output [31:0] io_out, // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] output [31:0] io_adder_out, // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] output io_cmp_out // @[:freechips.rocketchip.system.TinyConfig.fir@123307.4] ); wire _T; // @[ALU.scala 40:29:freechips.rocketchip.system.TinyConfig.fir@123312.4] wire [31:0] _T_1; // @[ALU.scala 62:35:freechips.rocketchip.system.TinyConfig.fir@123313.4] wire [31:0] in2_inv; // @[ALU.scala 62:20:freechips.rocketchip.system.TinyConfig.fir@123314.4] wire [31:0] in1_xor_in2; // @[ALU.scala 63:28:freechips.rocketchip.system.TinyConfig.fir@123315.4] wire [31:0] _T_3; // @[ALU.scala 64:26:freechips.rocketchip.system.TinyConfig.fir@123317.4] wire [31:0] _GEN_0; // @[ALU.scala 64:36:freechips.rocketchip.system.TinyConfig.fir@123319.4] wire _T_7; // @[ALU.scala 68:15:freechips.rocketchip.system.TinyConfig.fir@123322.4] wire _T_8; // @[ALU.scala 68:34:freechips.rocketchip.system.TinyConfig.fir@123323.4] wire _T_9; // @[ALU.scala 68:24:freechips.rocketchip.system.TinyConfig.fir@123324.4] wire _T_10; // @[ALU.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@123325.4] wire _T_11; // @[ALU.scala 42:35:freechips.rocketchip.system.TinyConfig.fir@123326.4] wire _T_14; // @[ALU.scala 69:8:freechips.rocketchip.system.TinyConfig.fir@123329.4] wire slt; // @[ALU.scala 68:8:freechips.rocketchip.system.TinyConfig.fir@123330.4] wire _T_15; // @[ALU.scala 43:35:freechips.rocketchip.system.TinyConfig.fir@123331.4] wire _T_17; // @[ALU.scala 44:26:freechips.rocketchip.system.TinyConfig.fir@123333.4] wire _T_18; // @[ALU.scala 70:68:freechips.rocketchip.system.TinyConfig.fir@123334.4] wire _T_19; // @[ALU.scala 70:41:freechips.rocketchip.system.TinyConfig.fir@123335.4] wire [4:0] shamt; // @[ALU.scala 74:28:freechips.rocketchip.system.TinyConfig.fir@123338.4] wire _T_21; // @[ALU.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@123339.4] wire _T_22; // @[ALU.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@123340.4] wire _T_23; // @[ALU.scala 82:35:freechips.rocketchip.system.TinyConfig.fir@123341.4] wire [15:0] _T_26; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123344.4] wire [31:0] _T_27; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123345.4] wire [15:0] _T_28; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123346.4] wire [31:0] _T_29; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123347.4] wire [31:0] _T_31; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123349.4] wire [31:0] _T_32; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123350.4] wire [23:0] _T_36; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123354.4] wire [31:0] _GEN_1; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123355.4] wire [31:0] _T_37; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123355.4] wire [23:0] _T_38; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123356.4] wire [31:0] _T_39; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123357.4] wire [31:0] _T_41; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123359.4] wire [31:0] _T_42; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123360.4] wire [27:0] _T_46; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123364.4] wire [31:0] _GEN_2; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123365.4] wire [31:0] _T_47; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123365.4] wire [27:0] _T_48; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123366.4] wire [31:0] _T_49; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123367.4] wire [31:0] _T_51; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123369.4] wire [31:0] _T_52; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123370.4] wire [29:0] _T_56; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123374.4] wire [31:0] _GEN_3; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123375.4] wire [31:0] _T_57; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123375.4] wire [29:0] _T_58; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123376.4] wire [31:0] _T_59; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123377.4] wire [31:0] _T_61; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123379.4] wire [31:0] _T_62; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123380.4] wire [30:0] _T_66; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123384.4] wire [31:0] _GEN_4; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123385.4] wire [31:0] _T_67; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123385.4] wire [30:0] _T_68; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123386.4] wire [31:0] _T_69; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123387.4] wire [31:0] _T_71; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123389.4] wire [31:0] _T_72; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123390.4] wire [31:0] shin; // @[ALU.scala 82:17:freechips.rocketchip.system.TinyConfig.fir@123391.4] wire _T_74; // @[ALU.scala 83:41:freechips.rocketchip.system.TinyConfig.fir@123393.4] wire _T_75; // @[ALU.scala 83:35:freechips.rocketchip.system.TinyConfig.fir@123394.4] wire [32:0] _T_76; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123395.4] wire [32:0] _T_77; // @[ALU.scala 83:57:freechips.rocketchip.system.TinyConfig.fir@123396.4] wire [32:0] _T_78; // @[ALU.scala 83:64:freechips.rocketchip.system.TinyConfig.fir@123397.4] wire [31:0] shout_r; // @[ALU.scala 83:73:freechips.rocketchip.system.TinyConfig.fir@123398.4] wire [15:0] _T_81; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123401.4] wire [31:0] _T_82; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123402.4] wire [15:0] _T_83; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123403.4] wire [31:0] _T_84; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123404.4] wire [31:0] _T_86; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123406.4] wire [31:0] _T_87; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123407.4] wire [23:0] _T_91; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123411.4] wire [31:0] _GEN_5; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123412.4] wire [31:0] _T_92; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123412.4] wire [23:0] _T_93; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123413.4] wire [31:0] _T_94; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123414.4] wire [31:0] _T_96; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123416.4] wire [31:0] _T_97; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123417.4] wire [27:0] _T_101; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123421.4] wire [31:0] _GEN_6; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123422.4] wire [31:0] _T_102; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123422.4] wire [27:0] _T_103; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123423.4] wire [31:0] _T_104; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123424.4] wire [31:0] _T_106; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123426.4] wire [31:0] _T_107; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123427.4] wire [29:0] _T_111; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123431.4] wire [31:0] _GEN_7; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123432.4] wire [31:0] _T_112; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123432.4] wire [29:0] _T_113; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123433.4] wire [31:0] _T_114; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123434.4] wire [31:0] _T_116; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123436.4] wire [31:0] _T_117; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123437.4] wire [30:0] _T_121; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123441.4] wire [31:0] _GEN_8; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123442.4] wire [31:0] _T_122; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123442.4] wire [30:0] _T_123; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123443.4] wire [31:0] _T_124; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123444.4] wire [31:0] _T_126; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123446.4] wire [31:0] shout_l; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123447.4] wire [31:0] _T_130; // @[ALU.scala 85:18:freechips.rocketchip.system.TinyConfig.fir@123451.4] wire _T_131; // @[ALU.scala 86:25:freechips.rocketchip.system.TinyConfig.fir@123452.4] wire [31:0] _T_132; // @[ALU.scala 86:18:freechips.rocketchip.system.TinyConfig.fir@123453.4] wire [31:0] shout; // @[ALU.scala 85:74:freechips.rocketchip.system.TinyConfig.fir@123454.4] wire _T_133; // @[ALU.scala 89:25:freechips.rocketchip.system.TinyConfig.fir@123455.4] wire _T_134; // @[ALU.scala 89:45:freechips.rocketchip.system.TinyConfig.fir@123456.4] wire _T_135; // @[ALU.scala 89:36:freechips.rocketchip.system.TinyConfig.fir@123457.4] wire [31:0] _T_136; // @[ALU.scala 89:18:freechips.rocketchip.system.TinyConfig.fir@123458.4] wire _T_138; // @[ALU.scala 90:44:freechips.rocketchip.system.TinyConfig.fir@123460.4] wire _T_139; // @[ALU.scala 90:35:freechips.rocketchip.system.TinyConfig.fir@123461.4] wire [31:0] _T_140; // @[ALU.scala 90:63:freechips.rocketchip.system.TinyConfig.fir@123462.4] wire [31:0] _T_141; // @[ALU.scala 90:18:freechips.rocketchip.system.TinyConfig.fir@123463.4] wire [31:0] logic_; // @[ALU.scala 89:78:freechips.rocketchip.system.TinyConfig.fir@123464.4] wire _T_142; // @[ALU.scala 41:30:freechips.rocketchip.system.TinyConfig.fir@123465.4] wire _T_143; // @[ALU.scala 91:35:freechips.rocketchip.system.TinyConfig.fir@123466.4] wire [31:0] _GEN_9; // @[ALU.scala 91:43:freechips.rocketchip.system.TinyConfig.fir@123467.4] wire [31:0] _T_144; // @[ALU.scala 91:43:freechips.rocketchip.system.TinyConfig.fir@123467.4] wire [31:0] shift_logic; // @[ALU.scala 91:51:freechips.rocketchip.system.TinyConfig.fir@123468.4] wire _T_145; // @[ALU.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@123469.4] wire _T_146; // @[ALU.scala 92:43:freechips.rocketchip.system.TinyConfig.fir@123470.4] wire _T_147; // @[ALU.scala 92:34:freechips.rocketchip.system.TinyConfig.fir@123471.4] assign _T = io_fn[3]; // @[ALU.scala 40:29:freechips.rocketchip.system.TinyConfig.fir@123312.4] assign _T_1 = ~ io_in2; // @[ALU.scala 62:35:freechips.rocketchip.system.TinyConfig.fir@123313.4] assign in2_inv = _T ? _T_1 : io_in2; // @[ALU.scala 62:20:freechips.rocketchip.system.TinyConfig.fir@123314.4] assign in1_xor_in2 = io_in1 ^ in2_inv; // @[ALU.scala 63:28:freechips.rocketchip.system.TinyConfig.fir@123315.4] assign _T_3 = io_in1 + in2_inv; // @[ALU.scala 64:26:freechips.rocketchip.system.TinyConfig.fir@123317.4] assign _GEN_0 = {{31'd0}, _T}; // @[ALU.scala 64:36:freechips.rocketchip.system.TinyConfig.fir@123319.4] assign _T_7 = io_in1[31]; // @[ALU.scala 68:15:freechips.rocketchip.system.TinyConfig.fir@123322.4] assign _T_8 = io_in2[31]; // @[ALU.scala 68:34:freechips.rocketchip.system.TinyConfig.fir@123323.4] assign _T_9 = _T_7 == _T_8; // @[ALU.scala 68:24:freechips.rocketchip.system.TinyConfig.fir@123324.4] assign _T_10 = io_adder_out[31]; // @[ALU.scala 68:56:freechips.rocketchip.system.TinyConfig.fir@123325.4] assign _T_11 = io_fn[1]; // @[ALU.scala 42:35:freechips.rocketchip.system.TinyConfig.fir@123326.4] assign _T_14 = _T_11 ? _T_8 : _T_7; // @[ALU.scala 69:8:freechips.rocketchip.system.TinyConfig.fir@123329.4] assign slt = _T_9 ? _T_10 : _T_14; // @[ALU.scala 68:8:freechips.rocketchip.system.TinyConfig.fir@123330.4] assign _T_15 = io_fn[0]; // @[ALU.scala 43:35:freechips.rocketchip.system.TinyConfig.fir@123331.4] assign _T_17 = _T == 1'h0; // @[ALU.scala 44:26:freechips.rocketchip.system.TinyConfig.fir@123333.4] assign _T_18 = in1_xor_in2 == 32'h0; // @[ALU.scala 70:68:freechips.rocketchip.system.TinyConfig.fir@123334.4] assign _T_19 = _T_17 ? _T_18 : slt; // @[ALU.scala 70:41:freechips.rocketchip.system.TinyConfig.fir@123335.4] assign shamt = io_in2[4:0]; // @[ALU.scala 74:28:freechips.rocketchip.system.TinyConfig.fir@123338.4] assign _T_21 = io_fn == 4'h5; // @[ALU.scala 82:24:freechips.rocketchip.system.TinyConfig.fir@123339.4] assign _T_22 = io_fn == 4'hb; // @[ALU.scala 82:44:freechips.rocketchip.system.TinyConfig.fir@123340.4] assign _T_23 = _T_21 | _T_22; // @[ALU.scala 82:35:freechips.rocketchip.system.TinyConfig.fir@123341.4] assign _T_26 = io_in1[31:16]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123344.4] assign _T_27 = {{16'd0}, _T_26}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123345.4] assign _T_28 = io_in1[15:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123346.4] assign _T_29 = {_T_28, 16'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123347.4] assign _T_31 = _T_29 & 32'hffff0000; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123349.4] assign _T_32 = _T_27 | _T_31; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123350.4] assign _T_36 = _T_32[31:8]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123354.4] assign _GEN_1 = {{8'd0}, _T_36}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123355.4] assign _T_37 = _GEN_1 & 32'hff00ff; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123355.4] assign _T_38 = _T_32[23:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123356.4] assign _T_39 = {_T_38, 8'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123357.4] assign _T_41 = _T_39 & 32'hff00ff00; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123359.4] assign _T_42 = _T_37 | _T_41; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123360.4] assign _T_46 = _T_42[31:4]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123364.4] assign _GEN_2 = {{4'd0}, _T_46}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123365.4] assign _T_47 = _GEN_2 & 32'hf0f0f0f; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123365.4] assign _T_48 = _T_42[27:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123366.4] assign _T_49 = {_T_48, 4'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123367.4] assign _T_51 = _T_49 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123369.4] assign _T_52 = _T_47 | _T_51; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123370.4] assign _T_56 = _T_52[31:2]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123374.4] assign _GEN_3 = {{2'd0}, _T_56}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123375.4] assign _T_57 = _GEN_3 & 32'h33333333; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123375.4] assign _T_58 = _T_52[29:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123376.4] assign _T_59 = {_T_58, 2'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123377.4] assign _T_61 = _T_59 & 32'hcccccccc; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123379.4] assign _T_62 = _T_57 | _T_61; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123380.4] assign _T_66 = _T_62[31:1]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123384.4] assign _GEN_4 = {{1'd0}, _T_66}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123385.4] assign _T_67 = _GEN_4 & 32'h55555555; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123385.4] assign _T_68 = _T_62[30:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123386.4] assign _T_69 = {_T_68, 1'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123387.4] assign _T_71 = _T_69 & 32'haaaaaaaa; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123389.4] assign _T_72 = _T_67 | _T_71; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123390.4] assign shin = _T_23 ? io_in1 : _T_72; // @[ALU.scala 82:17:freechips.rocketchip.system.TinyConfig.fir@123391.4] assign _T_74 = shin[31]; // @[ALU.scala 83:41:freechips.rocketchip.system.TinyConfig.fir@123393.4] assign _T_75 = _T & _T_74; // @[ALU.scala 83:35:freechips.rocketchip.system.TinyConfig.fir@123394.4] assign _T_76 = {_T_75,shin}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123395.4] assign _T_77 = $signed(_T_76); // @[ALU.scala 83:57:freechips.rocketchip.system.TinyConfig.fir@123396.4] assign _T_78 = $signed(_T_77) >>> shamt; // @[ALU.scala 83:64:freechips.rocketchip.system.TinyConfig.fir@123397.4] assign shout_r = _T_78[31:0]; // @[ALU.scala 83:73:freechips.rocketchip.system.TinyConfig.fir@123398.4] assign _T_81 = shout_r[31:16]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123401.4] assign _T_82 = {{16'd0}, _T_81}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123402.4] assign _T_83 = shout_r[15:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123403.4] assign _T_84 = {_T_83, 16'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123404.4] assign _T_86 = _T_84 & 32'hffff0000; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123406.4] assign _T_87 = _T_82 | _T_86; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123407.4] assign _T_91 = _T_87[31:8]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123411.4] assign _GEN_5 = {{8'd0}, _T_91}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123412.4] assign _T_92 = _GEN_5 & 32'hff00ff; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123412.4] assign _T_93 = _T_87[23:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123413.4] assign _T_94 = {_T_93, 8'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123414.4] assign _T_96 = _T_94 & 32'hff00ff00; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123416.4] assign _T_97 = _T_92 | _T_96; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123417.4] assign _T_101 = _T_97[31:4]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123421.4] assign _GEN_6 = {{4'd0}, _T_101}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123422.4] assign _T_102 = _GEN_6 & 32'hf0f0f0f; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123422.4] assign _T_103 = _T_97[27:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123423.4] assign _T_104 = {_T_103, 4'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123424.4] assign _T_106 = _T_104 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123426.4] assign _T_107 = _T_102 | _T_106; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123427.4] assign _T_111 = _T_107[31:2]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123431.4] assign _GEN_7 = {{2'd0}, _T_111}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123432.4] assign _T_112 = _GEN_7 & 32'h33333333; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123432.4] assign _T_113 = _T_107[29:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123433.4] assign _T_114 = {_T_113, 2'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123434.4] assign _T_116 = _T_114 & 32'hcccccccc; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123436.4] assign _T_117 = _T_112 | _T_116; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123437.4] assign _T_121 = _T_117[31:1]; // @[Bitwise.scala 103:21:freechips.rocketchip.system.TinyConfig.fir@123441.4] assign _GEN_8 = {{1'd0}, _T_121}; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123442.4] assign _T_122 = _GEN_8 & 32'h55555555; // @[Bitwise.scala 103:31:freechips.rocketchip.system.TinyConfig.fir@123442.4] assign _T_123 = _T_117[30:0]; // @[Bitwise.scala 103:46:freechips.rocketchip.system.TinyConfig.fir@123443.4] assign _T_124 = {_T_123, 1'h0}; // @[Bitwise.scala 103:65:freechips.rocketchip.system.TinyConfig.fir@123444.4] assign _T_126 = _T_124 & 32'haaaaaaaa; // @[Bitwise.scala 103:75:freechips.rocketchip.system.TinyConfig.fir@123446.4] assign shout_l = _T_122 | _T_126; // @[Bitwise.scala 103:39:freechips.rocketchip.system.TinyConfig.fir@123447.4] assign _T_130 = _T_23 ? shout_r : 32'h0; // @[ALU.scala 85:18:freechips.rocketchip.system.TinyConfig.fir@123451.4] assign _T_131 = io_fn == 4'h1; // @[ALU.scala 86:25:freechips.rocketchip.system.TinyConfig.fir@123452.4] assign _T_132 = _T_131 ? shout_l : 32'h0; // @[ALU.scala 86:18:freechips.rocketchip.system.TinyConfig.fir@123453.4] assign shout = _T_130 | _T_132; // @[ALU.scala 85:74:freechips.rocketchip.system.TinyConfig.fir@123454.4] assign _T_133 = io_fn == 4'h4; // @[ALU.scala 89:25:freechips.rocketchip.system.TinyConfig.fir@123455.4] assign _T_134 = io_fn == 4'h6; // @[ALU.scala 89:45:freechips.rocketchip.system.TinyConfig.fir@123456.4] assign _T_135 = _T_133 | _T_134; // @[ALU.scala 89:36:freechips.rocketchip.system.TinyConfig.fir@123457.4] assign _T_136 = _T_135 ? in1_xor_in2 : 32'h0; // @[ALU.scala 89:18:freechips.rocketchip.system.TinyConfig.fir@123458.4] assign _T_138 = io_fn == 4'h7; // @[ALU.scala 90:44:freechips.rocketchip.system.TinyConfig.fir@123460.4] assign _T_139 = _T_134 | _T_138; // @[ALU.scala 90:35:freechips.rocketchip.system.TinyConfig.fir@123461.4] assign _T_140 = io_in1 & io_in2; // @[ALU.scala 90:63:freechips.rocketchip.system.TinyConfig.fir@123462.4] assign _T_141 = _T_139 ? _T_140 : 32'h0; // @[ALU.scala 90:18:freechips.rocketchip.system.TinyConfig.fir@123463.4] assign logic_ = _T_136 | _T_141; // @[ALU.scala 89:78:freechips.rocketchip.system.TinyConfig.fir@123464.4] assign _T_142 = io_fn >= 4'hc; // @[ALU.scala 41:30:freechips.rocketchip.system.TinyConfig.fir@123465.4] assign _T_143 = _T_142 & slt; // @[ALU.scala 91:35:freechips.rocketchip.system.TinyConfig.fir@123466.4] assign _GEN_9 = {{31'd0}, _T_143}; // @[ALU.scala 91:43:freechips.rocketchip.system.TinyConfig.fir@123467.4] assign _T_144 = _GEN_9 | logic_; // @[ALU.scala 91:43:freechips.rocketchip.system.TinyConfig.fir@123467.4] assign shift_logic = _T_144 | shout; // @[ALU.scala 91:51:freechips.rocketchip.system.TinyConfig.fir@123468.4] assign _T_145 = io_fn == 4'h0; // @[ALU.scala 92:23:freechips.rocketchip.system.TinyConfig.fir@123469.4] assign _T_146 = io_fn == 4'ha; // @[ALU.scala 92:43:freechips.rocketchip.system.TinyConfig.fir@123470.4] assign _T_147 = _T_145 | _T_146; // @[ALU.scala 92:34:freechips.rocketchip.system.TinyConfig.fir@123471.4] assign io_out = _T_147 ? io_adder_out : shift_logic; // @[ALU.scala 94:10:freechips.rocketchip.system.TinyConfig.fir@123473.4] assign io_adder_out = _T_3 + _GEN_0; // @[ALU.scala 64:16:freechips.rocketchip.system.TinyConfig.fir@123321.4] assign io_cmp_out = _T_15 ^ _T_19; // @[ALU.scala 70:14:freechips.rocketchip.system.TinyConfig.fir@123337.4] endmodule module MulDiv( // @[:freechips.rocketchip.system.TinyConfig.fir@123475.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@123476.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@123477.4] output io_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input io_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input [3:0] io_req_bits_fn, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input [31:0] io_req_bits_in1, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input [31:0] io_req_bits_in2, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input [4:0] io_req_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input io_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] input io_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] output io_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] output [31:0] io_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] output [4:0] io_resp_bits_tag // @[:freechips.rocketchip.system.TinyConfig.fir@123478.4] ); reg [2:0] state; // @[Multiplier.scala 51:18:freechips.rocketchip.system.TinyConfig.fir@123483.4] reg [31:0] _RAND_0; reg [4:0] req_tag; // @[Multiplier.scala 53:16:freechips.rocketchip.system.TinyConfig.fir@123484.4] reg [31:0] _RAND_1; reg [5:0] count; // @[Multiplier.scala 54:18:freechips.rocketchip.system.TinyConfig.fir@123485.4] reg [31:0] _RAND_2; reg neg_out; // @[Multiplier.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@123486.4] reg [31:0] _RAND_3; reg isHi; // @[Multiplier.scala 58:17:freechips.rocketchip.system.TinyConfig.fir@123487.4] reg [31:0] _RAND_4; reg resHi; // @[Multiplier.scala 59:18:freechips.rocketchip.system.TinyConfig.fir@123488.4] reg [31:0] _RAND_5; reg [32:0] divisor; // @[Multiplier.scala 60:20:freechips.rocketchip.system.TinyConfig.fir@123489.4] reg [63:0] _RAND_6; reg [65:0] remainder; // @[Multiplier.scala 61:22:freechips.rocketchip.system.TinyConfig.fir@123490.4] reg [95:0] _RAND_7; wire [3:0] _T; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123491.4] wire cmdMul; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123492.4] wire [3:0] _T_3; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123494.4] wire _T_4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123495.4] wire [3:0] _T_5; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123496.4] wire _T_6; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123497.4] wire cmdHi; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123499.4] wire [3:0] _T_9; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123500.4] wire _T_10; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123501.4] wire [3:0] _T_11; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123502.4] wire _T_12; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123503.4] wire lhsSigned; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123505.4] wire _T_16; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123507.4] wire rhsSigned; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123509.4] wire _T_22; // @[Multiplier.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@123517.4] wire lhs_sign; // @[Multiplier.scala 81:23:freechips.rocketchip.system.TinyConfig.fir@123519.4] wire [15:0] _T_26; // @[Multiplier.scala 82:43:freechips.rocketchip.system.TinyConfig.fir@123522.4] wire [15:0] _T_28; // @[Multiplier.scala 83:15:freechips.rocketchip.system.TinyConfig.fir@123524.4] wire [31:0] lhs_in; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123525.4] wire _T_32; // @[Multiplier.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@123529.4] wire rhs_sign; // @[Multiplier.scala 81:23:freechips.rocketchip.system.TinyConfig.fir@123531.4] wire [15:0] _T_36; // @[Multiplier.scala 82:43:freechips.rocketchip.system.TinyConfig.fir@123534.4] wire [15:0] _T_38; // @[Multiplier.scala 83:15:freechips.rocketchip.system.TinyConfig.fir@123536.4] wire [32:0] _T_39; // @[Multiplier.scala 88:29:freechips.rocketchip.system.TinyConfig.fir@123538.4] wire [32:0] subtractor; // @[Multiplier.scala 88:37:freechips.rocketchip.system.TinyConfig.fir@123540.4] wire [31:0] _T_41; // @[Multiplier.scala 89:36:freechips.rocketchip.system.TinyConfig.fir@123541.4] wire [31:0] _T_42; // @[Multiplier.scala 89:57:freechips.rocketchip.system.TinyConfig.fir@123542.4] wire [31:0] result; // @[Multiplier.scala 89:19:freechips.rocketchip.system.TinyConfig.fir@123543.4] wire [31:0] negated_remainder; // @[Multiplier.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@123545.4] wire _T_44; // @[Multiplier.scala 92:39:freechips.rocketchip.system.TinyConfig.fir@123546.4] wire _T_45; // @[Multiplier.scala 93:20:freechips.rocketchip.system.TinyConfig.fir@123548.6] wire _T_46; // @[Multiplier.scala 96:18:freechips.rocketchip.system.TinyConfig.fir@123552.6] wire _T_47; // @[Multiplier.scala 101:39:freechips.rocketchip.system.TinyConfig.fir@123558.4] wire _T_48; // @[Multiplier.scala 106:39:freechips.rocketchip.system.TinyConfig.fir@123564.4] wire [32:0] _T_49; // @[Multiplier.scala 107:31:freechips.rocketchip.system.TinyConfig.fir@123566.6] wire [64:0] _T_51; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123568.6] wire _T_52; // @[Multiplier.scala 108:31:freechips.rocketchip.system.TinyConfig.fir@123569.6] wire [31:0] _T_53; // @[Multiplier.scala 109:24:freechips.rocketchip.system.TinyConfig.fir@123570.6] wire [32:0] _T_54; // @[Multiplier.scala 110:23:freechips.rocketchip.system.TinyConfig.fir@123571.6] wire [32:0] _T_55; // @[Multiplier.scala 110:37:freechips.rocketchip.system.TinyConfig.fir@123572.6] wire [32:0] _T_56; // @[Multiplier.scala 111:26:freechips.rocketchip.system.TinyConfig.fir@123573.6] wire [7:0] _T_57; // @[Multiplier.scala 112:38:freechips.rocketchip.system.TinyConfig.fir@123574.6] wire [8:0] _T_58; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123575.6] wire [8:0] _T_59; // @[Multiplier.scala 112:60:freechips.rocketchip.system.TinyConfig.fir@123576.6] wire [32:0] _GEN_35; // @[Multiplier.scala 112:67:freechips.rocketchip.system.TinyConfig.fir@123577.6] wire [41:0] _T_60; // @[Multiplier.scala 112:67:freechips.rocketchip.system.TinyConfig.fir@123577.6] wire [41:0] _GEN_36; // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123578.6] wire [41:0] _T_62; // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123579.6] wire [41:0] _T_63; // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123580.6] wire [23:0] _T_64; // @[Multiplier.scala 113:38:freechips.rocketchip.system.TinyConfig.fir@123581.6] wire [41:0] _T_65; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123582.6] wire [65:0] _T_66; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123583.6] wire _T_67; // @[Multiplier.scala 114:32:freechips.rocketchip.system.TinyConfig.fir@123584.6] wire _T_68; // @[Multiplier.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@123585.6] wire _T_77; // @[Multiplier.scala 118:7:freechips.rocketchip.system.TinyConfig.fir@123594.6] wire [32:0] _T_88; // @[Multiplier.scala 120:37:freechips.rocketchip.system.TinyConfig.fir@123605.6] wire [31:0] _T_90; // @[Multiplier.scala 120:82:freechips.rocketchip.system.TinyConfig.fir@123607.6] wire [64:0] _T_91; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123608.6] wire [32:0] _T_92; // @[Multiplier.scala 121:34:freechips.rocketchip.system.TinyConfig.fir@123609.6] wire [31:0] _T_93; // @[Multiplier.scala 121:67:freechips.rocketchip.system.TinyConfig.fir@123610.6] wire [65:0] _T_95; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123612.6] wire [5:0] _T_97; // @[Multiplier.scala 123:20:freechips.rocketchip.system.TinyConfig.fir@123615.6] wire _T_98; // @[Multiplier.scala 124:25:freechips.rocketchip.system.TinyConfig.fir@123617.6] wire _T_100; // @[Multiplier.scala 129:39:freechips.rocketchip.system.TinyConfig.fir@123624.4] wire _T_101; // @[Multiplier.scala 133:28:freechips.rocketchip.system.TinyConfig.fir@123626.6] wire [31:0] _T_102; // @[Multiplier.scala 134:24:freechips.rocketchip.system.TinyConfig.fir@123627.6] wire [31:0] _T_103; // @[Multiplier.scala 134:45:freechips.rocketchip.system.TinyConfig.fir@123628.6] wire [31:0] _T_104; // @[Multiplier.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@123629.6] wire _T_106; // @[Multiplier.scala 134:67:freechips.rocketchip.system.TinyConfig.fir@123631.6] wire [64:0] _T_108; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123633.6] wire _T_109; // @[Multiplier.scala 138:17:freechips.rocketchip.system.TinyConfig.fir@123635.6] wire _T_113; // @[Multiplier.scala 146:24:freechips.rocketchip.system.TinyConfig.fir@123644.6] wire _T_116; // @[Multiplier.scala 146:30:freechips.rocketchip.system.TinyConfig.fir@123647.6] wire _T_118; // @[Multiplier.scala 159:18:freechips.rocketchip.system.TinyConfig.fir@123649.6] wire _T_119; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@123654.4] wire _T_120; // @[Multiplier.scala 161:24:freechips.rocketchip.system.TinyConfig.fir@123655.4] wire _T_121; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@123659.4] wire _T_122; // @[Multiplier.scala 165:46:freechips.rocketchip.system.TinyConfig.fir@123661.6] wire _T_129; // @[Multiplier.scala 169:46:freechips.rocketchip.system.TinyConfig.fir@123672.6] wire [32:0] _T_131; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123675.6] wire [15:0] _T_140; // @[Multiplier.scala 176:69:freechips.rocketchip.system.TinyConfig.fir@123689.4] wire [15:0] loOut; // @[Multiplier.scala 176:86:freechips.rocketchip.system.TinyConfig.fir@123690.4] wire _T_149; // @[Multiplier.scala 180:27:freechips.rocketchip.system.TinyConfig.fir@123702.4] wire _T_150; // @[Multiplier.scala 180:51:freechips.rocketchip.system.TinyConfig.fir@123703.4] assign _T = io_req_bits_fn & 4'h4; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123491.4] assign cmdMul = _T == 4'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123492.4] assign _T_3 = io_req_bits_fn & 4'h5; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123494.4] assign _T_4 = _T_3 == 4'h1; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123495.4] assign _T_5 = io_req_bits_fn & 4'h2; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123496.4] assign _T_6 = _T_5 == 4'h2; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123497.4] assign cmdHi = _T_4 | _T_6; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123499.4] assign _T_9 = io_req_bits_fn & 4'h6; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123500.4] assign _T_10 = _T_9 == 4'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123501.4] assign _T_11 = io_req_bits_fn & 4'h1; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123502.4] assign _T_12 = _T_11 == 4'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123503.4] assign lhsSigned = _T_10 | _T_12; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123505.4] assign _T_16 = _T_3 == 4'h4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123507.4] assign rhsSigned = _T_10 | _T_16; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123509.4] assign _T_22 = io_req_bits_in1[31]; // @[Multiplier.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@123517.4] assign lhs_sign = lhsSigned & _T_22; // @[Multiplier.scala 81:23:freechips.rocketchip.system.TinyConfig.fir@123519.4] assign _T_26 = io_req_bits_in1[31:16]; // @[Multiplier.scala 82:43:freechips.rocketchip.system.TinyConfig.fir@123522.4] assign _T_28 = io_req_bits_in1[15:0]; // @[Multiplier.scala 83:15:freechips.rocketchip.system.TinyConfig.fir@123524.4] assign lhs_in = {_T_26,_T_28}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123525.4] assign _T_32 = io_req_bits_in2[31]; // @[Multiplier.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@123529.4] assign rhs_sign = rhsSigned & _T_32; // @[Multiplier.scala 81:23:freechips.rocketchip.system.TinyConfig.fir@123531.4] assign _T_36 = io_req_bits_in2[31:16]; // @[Multiplier.scala 82:43:freechips.rocketchip.system.TinyConfig.fir@123534.4] assign _T_38 = io_req_bits_in2[15:0]; // @[Multiplier.scala 83:15:freechips.rocketchip.system.TinyConfig.fir@123536.4] assign _T_39 = remainder[64:32]; // @[Multiplier.scala 88:29:freechips.rocketchip.system.TinyConfig.fir@123538.4] assign subtractor = _T_39 - divisor; // @[Multiplier.scala 88:37:freechips.rocketchip.system.TinyConfig.fir@123540.4] assign _T_41 = remainder[64:33]; // @[Multiplier.scala 89:36:freechips.rocketchip.system.TinyConfig.fir@123541.4] assign _T_42 = remainder[31:0]; // @[Multiplier.scala 89:57:freechips.rocketchip.system.TinyConfig.fir@123542.4] assign result = resHi ? _T_41 : _T_42; // @[Multiplier.scala 89:19:freechips.rocketchip.system.TinyConfig.fir@123543.4] assign negated_remainder = 32'h0 - result; // @[Multiplier.scala 90:27:freechips.rocketchip.system.TinyConfig.fir@123545.4] assign _T_44 = state == 3'h1; // @[Multiplier.scala 92:39:freechips.rocketchip.system.TinyConfig.fir@123546.4] assign _T_45 = remainder[31]; // @[Multiplier.scala 93:20:freechips.rocketchip.system.TinyConfig.fir@123548.6] assign _T_46 = divisor[31]; // @[Multiplier.scala 96:18:freechips.rocketchip.system.TinyConfig.fir@123552.6] assign _T_47 = state == 3'h5; // @[Multiplier.scala 101:39:freechips.rocketchip.system.TinyConfig.fir@123558.4] assign _T_48 = state == 3'h2; // @[Multiplier.scala 106:39:freechips.rocketchip.system.TinyConfig.fir@123564.4] assign _T_49 = remainder[65:33]; // @[Multiplier.scala 107:31:freechips.rocketchip.system.TinyConfig.fir@123566.6] assign _T_51 = {_T_49,_T_42}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123568.6] assign _T_52 = remainder[32]; // @[Multiplier.scala 108:31:freechips.rocketchip.system.TinyConfig.fir@123569.6] assign _T_53 = _T_51[31:0]; // @[Multiplier.scala 109:24:freechips.rocketchip.system.TinyConfig.fir@123570.6] assign _T_54 = _T_51[64:32]; // @[Multiplier.scala 110:23:freechips.rocketchip.system.TinyConfig.fir@123571.6] assign _T_55 = $signed(_T_54); // @[Multiplier.scala 110:37:freechips.rocketchip.system.TinyConfig.fir@123572.6] assign _T_56 = $signed(divisor); // @[Multiplier.scala 111:26:freechips.rocketchip.system.TinyConfig.fir@123573.6] assign _T_57 = _T_53[7:0]; // @[Multiplier.scala 112:38:freechips.rocketchip.system.TinyConfig.fir@123574.6] assign _T_58 = {_T_52,_T_57}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123575.6] assign _T_59 = $signed(_T_58); // @[Multiplier.scala 112:60:freechips.rocketchip.system.TinyConfig.fir@123576.6] assign _GEN_35 = {{24{_T_59[8]}},_T_59}; // @[Multiplier.scala 112:67:freechips.rocketchip.system.TinyConfig.fir@123577.6] assign _T_60 = $signed(_GEN_35) * $signed(_T_56); // @[Multiplier.scala 112:67:freechips.rocketchip.system.TinyConfig.fir@123577.6] assign _GEN_36 = {{9{_T_55[32]}},_T_55}; // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123578.6] assign _T_62 = $signed(_T_60) + $signed(_GEN_36); // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123579.6] assign _T_63 = $signed(_T_62); // @[Multiplier.scala 112:76:freechips.rocketchip.system.TinyConfig.fir@123580.6] assign _T_64 = _T_53[31:8]; // @[Multiplier.scala 113:38:freechips.rocketchip.system.TinyConfig.fir@123581.6] assign _T_65 = $unsigned(_T_63); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123582.6] assign _T_66 = {_T_65,_T_64}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123583.6] assign _T_67 = count == 6'h2; // @[Multiplier.scala 114:32:freechips.rocketchip.system.TinyConfig.fir@123584.6] assign _T_68 = _T_67 & neg_out; // @[Multiplier.scala 114:57:freechips.rocketchip.system.TinyConfig.fir@123585.6] assign _T_77 = isHi == 1'h0; // @[Multiplier.scala 118:7:freechips.rocketchip.system.TinyConfig.fir@123594.6] assign _T_88 = _T_66[64:32]; // @[Multiplier.scala 120:37:freechips.rocketchip.system.TinyConfig.fir@123605.6] assign _T_90 = _T_66[31:0]; // @[Multiplier.scala 120:82:freechips.rocketchip.system.TinyConfig.fir@123607.6] assign _T_91 = {_T_88,_T_90}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123608.6] assign _T_92 = _T_91[64:32]; // @[Multiplier.scala 121:34:freechips.rocketchip.system.TinyConfig.fir@123609.6] assign _T_93 = _T_91[31:0]; // @[Multiplier.scala 121:67:freechips.rocketchip.system.TinyConfig.fir@123610.6] assign _T_95 = {_T_92,_T_68,_T_93}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123612.6] assign _T_97 = count + 6'h1; // @[Multiplier.scala 123:20:freechips.rocketchip.system.TinyConfig.fir@123615.6] assign _T_98 = count == 6'h3; // @[Multiplier.scala 124:25:freechips.rocketchip.system.TinyConfig.fir@123617.6] assign _T_100 = state == 3'h3; // @[Multiplier.scala 129:39:freechips.rocketchip.system.TinyConfig.fir@123624.4] assign _T_101 = subtractor[32]; // @[Multiplier.scala 133:28:freechips.rocketchip.system.TinyConfig.fir@123626.6] assign _T_102 = remainder[63:32]; // @[Multiplier.scala 134:24:freechips.rocketchip.system.TinyConfig.fir@123627.6] assign _T_103 = subtractor[31:0]; // @[Multiplier.scala 134:45:freechips.rocketchip.system.TinyConfig.fir@123628.6] assign _T_104 = _T_101 ? _T_102 : _T_103; // @[Multiplier.scala 134:14:freechips.rocketchip.system.TinyConfig.fir@123629.6] assign _T_106 = _T_101 == 1'h0; // @[Multiplier.scala 134:67:freechips.rocketchip.system.TinyConfig.fir@123631.6] assign _T_108 = {_T_104,_T_42,_T_106}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123633.6] assign _T_109 = count == 6'h20; // @[Multiplier.scala 138:17:freechips.rocketchip.system.TinyConfig.fir@123635.6] assign _T_113 = count == 6'h0; // @[Multiplier.scala 146:24:freechips.rocketchip.system.TinyConfig.fir@123644.6] assign _T_116 = _T_113 & _T_106; // @[Multiplier.scala 146:30:freechips.rocketchip.system.TinyConfig.fir@123647.6] assign _T_118 = _T_116 & _T_77; // @[Multiplier.scala 159:18:freechips.rocketchip.system.TinyConfig.fir@123649.6] assign _T_119 = io_resp_ready & io_resp_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@123654.4] assign _T_120 = _T_119 | io_kill; // @[Multiplier.scala 161:24:freechips.rocketchip.system.TinyConfig.fir@123655.4] assign _T_121 = io_req_ready & io_req_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@123659.4] assign _T_122 = lhs_sign | rhs_sign; // @[Multiplier.scala 165:46:freechips.rocketchip.system.TinyConfig.fir@123661.6] assign _T_129 = lhs_sign != rhs_sign; // @[Multiplier.scala 169:46:freechips.rocketchip.system.TinyConfig.fir@123672.6] assign _T_131 = {rhs_sign,_T_36,_T_38}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123675.6] assign _T_140 = result[31:16]; // @[Multiplier.scala 176:69:freechips.rocketchip.system.TinyConfig.fir@123689.4] assign loOut = result[15:0]; // @[Multiplier.scala 176:86:freechips.rocketchip.system.TinyConfig.fir@123690.4] assign _T_149 = state == 3'h6; // @[Multiplier.scala 180:27:freechips.rocketchip.system.TinyConfig.fir@123702.4] assign _T_150 = state == 3'h7; // @[Multiplier.scala 180:51:freechips.rocketchip.system.TinyConfig.fir@123703.4] assign io_req_ready = state == 3'h0; // @[Multiplier.scala 181:16:freechips.rocketchip.system.TinyConfig.fir@123707.4] assign io_resp_valid = _T_149 | _T_150; // @[Multiplier.scala 180:17:freechips.rocketchip.system.TinyConfig.fir@123705.4] assign io_resp_bits_data = {_T_140,loOut}; // @[Multiplier.scala 179:21:freechips.rocketchip.system.TinyConfig.fir@123701.4] assign io_resp_bits_tag = req_tag; // @[Multiplier.scala 178:16:freechips.rocketchip.system.TinyConfig.fir@123699.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; state = _RAND_0[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; req_tag = _RAND_1[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; count = _RAND_2[5:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; neg_out = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; isHi = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; resHi = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {2{`RANDOM}}; divisor = _RAND_6[32:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {3{`RANDOM}}; remainder = _RAND_7[65:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin state <= 3'h0; end else begin if (_T_121) begin if (cmdMul) begin state <= 3'h2; end else begin if (_T_122) begin state <= 3'h1; end else begin state <= 3'h3; end end end else begin if (_T_120) begin state <= 3'h0; end else begin if (_T_100) begin if (_T_109) begin if (neg_out) begin state <= 3'h5; end else begin state <= 3'h7; end end else begin if (_T_48) begin if (_T_98) begin state <= 3'h6; end else begin if (_T_47) begin state <= 3'h7; end else begin if (_T_44) begin state <= 3'h3; end end end end else begin if (_T_47) begin state <= 3'h7; end else begin if (_T_44) begin state <= 3'h3; end end end end end else begin if (_T_48) begin if (_T_98) begin state <= 3'h6; end else begin if (_T_47) begin state <= 3'h7; end else begin if (_T_44) begin state <= 3'h3; end end end end else begin if (_T_47) begin state <= 3'h7; end else begin if (_T_44) begin state <= 3'h3; end end end end end end end if (_T_121) begin req_tag <= io_req_bits_tag; end if (_T_121) begin count <= 6'h0; end else begin if (_T_100) begin count <= _T_97; end else begin if (_T_48) begin count <= _T_97; end end end if (_T_121) begin if (cmdHi) begin neg_out <= lhs_sign; end else begin neg_out <= _T_129; end end else begin if (_T_100) begin if (_T_118) begin neg_out <= 1'h0; end end end if (_T_121) begin isHi <= cmdHi; end if (_T_121) begin resHi <= 1'h0; end else begin if (_T_100) begin if (_T_109) begin resHi <= isHi; end else begin if (_T_48) begin if (_T_98) begin resHi <= isHi; end else begin if (_T_47) begin resHi <= 1'h0; end end end else begin if (_T_47) begin resHi <= 1'h0; end end end end else begin if (_T_48) begin if (_T_98) begin resHi <= isHi; end else begin if (_T_47) begin resHi <= 1'h0; end end end else begin if (_T_47) begin resHi <= 1'h0; end end end end if (_T_121) begin divisor <= _T_131; end else begin if (_T_44) begin if (_T_46) begin divisor <= subtractor; end end end if (_T_121) begin remainder <= {{34'd0}, lhs_in}; end else begin if (_T_100) begin remainder <= {{1'd0}, _T_108}; end else begin if (_T_48) begin remainder <= _T_95; end else begin if (_T_47) begin remainder <= {{34'd0}, negated_remainder}; end else begin if (_T_44) begin if (_T_45) begin remainder <= {{34'd0}, negated_remainder}; end end end end end end end endmodule module PlusArgTimeout( // @[:freechips.rocketchip.system.TinyConfig.fir@123717.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@123718.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@123719.4] input [31:0] io_count // @[:freechips.rocketchip.system.TinyConfig.fir@123720.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 28:19:freechips.rocketchip.system.TinyConfig.fir@123722.4] wire _T; // @[PlusArg.scala 29:13:freechips.rocketchip.system.TinyConfig.fir@123724.4] wire _T_1; // @[PlusArg.scala 30:22:freechips.rocketchip.system.TinyConfig.fir@123726.6] wire _T_3; // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123728.6] wire _T_4; // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123729.6] plusarg_reader #(.FORMAT("max_core_cycles=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 28:19:freechips.rocketchip.system.TinyConfig.fir@123722.4] .out(plusarg_reader_out) ); assign _T = plusarg_reader_out > 32'h0; // @[PlusArg.scala 29:13:freechips.rocketchip.system.TinyConfig.fir@123724.4] assign _T_1 = io_count < plusarg_reader_out; // @[PlusArg.scala 30:22:freechips.rocketchip.system.TinyConfig.fir@123726.6] assign _T_3 = _T_1 | reset; // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123728.6] assign _T_4 = _T_3 == 1'h0; // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123729.6] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & _T_4) begin $fwrite(32'h80000002,"Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:30 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n"); // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123731.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T & _T_4) begin $fatal; // @[PlusArg.scala 30:12:freechips.rocketchip.system.TinyConfig.fir@123732.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Rocket( // @[:freechips.rocketchip.system.TinyConfig.fir@123736.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@123737.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@123738.4] input io_interrupts_debug, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_interrupts_mtip, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_interrupts_msip, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_interrupts_meip, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_might_request, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_imem_req_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_req_bits_speculative, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_imem_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input [31:0] io_imem_resp_bits_pc, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input [31:0] io_imem_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_imem_resp_bits_xcpt_ae_inst, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_imem_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_btb_update_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_bht_update_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_imem_flush_icache, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_dmem_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_dmem_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [6:0] io_dmem_req_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [4:0] io_dmem_req_bits_cmd, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_dmem_req_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_dmem_req_bits_signed, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_dmem_s1_kill, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_dmem_s1_data_data, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_nack, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input [6:0] io_dmem_resp_bits_tag, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input [31:0] io_dmem_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_resp_bits_replay, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_resp_bits_has_data, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input [31:0] io_dmem_resp_bits_data_word_bypass, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_replay_next, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_ma_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_ma_st, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_pf_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_pf_st, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_ae_ld, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_s2_xcpt_ae_st, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_ordered, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] input io_dmem_perf_grant, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_0_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_0_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_0_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_0_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_0_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_0_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_0_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_1_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_1_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_1_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_1_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_1_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_1_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_1_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_2_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_2_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_2_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_2_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_2_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_2_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_2_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_3_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_3_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_3_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_3_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_3_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_3_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_3_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_4_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_4_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_4_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_4_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_4_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_4_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_4_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_5_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_5_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_5_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_5_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_5_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_5_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_5_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_6_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_6_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_6_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_6_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_6_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_6_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_6_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_7_cfg_l, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [1:0] io_ptw_pmp_7_cfg_a, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_7_cfg_x, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_7_cfg_w, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output io_ptw_pmp_7_cfg_r, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [29:0] io_ptw_pmp_7_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_pmp_7_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] output [31:0] io_ptw_customCSRs_csrs_0_value // @[:freechips.rocketchip.system.TinyConfig.fir@123739.4] ); wire ibuf_clock; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_reset; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_imem_ready; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_imem_valid; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [31:0] ibuf_io_imem_bits_pc; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [31:0] ibuf_io_imem_bits_data; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_imem_bits_xcpt_ae_inst; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_imem_bits_replay; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_kill; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [31:0] ibuf_io_pc; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_ready; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_valid; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [31:0] ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [4:0] ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [4:0] ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [4:0] ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] wire [31:0] ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] reg [31:0] _T_288 [0:30]; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] reg [31:0] _RAND_0; wire [31:0] _T_288__T_293_data; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire [4:0] _T_288__T_293_addr; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] reg [31:0] _RAND_1; wire [31:0] _T_288__T_299_data; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire [4:0] _T_288__T_299_addr; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] reg [31:0] _RAND_2; wire [31:0] _T_288__T_953_data; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire [4:0] _T_288__T_953_addr; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire _T_288__T_953_mask; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire _T_288__T_953_en; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] wire csr_clock; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_reset; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_ungated_clock; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_interrupts_debug; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_interrupts_mtip; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_interrupts_msip; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_interrupts_meip; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [11:0] csr_io_rw_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [2:0] csr_io_rw_cmd; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_rw_rdata; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_rw_wdata; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [11:0] csr_io_decode_0_csr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_decode_0_fp_illegal; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_decode_0_fp_csr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_decode_0_read_illegal; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_decode_0_write_illegal; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_decode_0_write_flush; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_csr_stall; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_eret; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_singleStep; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_debug; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_cease; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_status_isa; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_dprv; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_prv; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_sd; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [26:0] csr_io_status_zero2; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_sxl; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_uxl; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_sd_rv32; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [7:0] csr_io_status_zero1; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_tsr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_tw; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_tvm; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_mxr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_sum; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_mprv; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_xs; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_fs; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_mpp; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_status_hpp; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_spp; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_mpie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_hpie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_spie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_upie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_mie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_hie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_sie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_status_uie; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_evec; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_exception; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_retire; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_cause; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pc; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_tval; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_time; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_interrupt; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_interrupt_cause; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_bp_0_control_action; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_bp_0_control_tmatch; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_bp_0_control_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_bp_0_control_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_bp_0_control_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_bp_0_address; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_0_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_0_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_0_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_0_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_0_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_0_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_0_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_1_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_1_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_1_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_1_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_1_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_1_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_1_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_2_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_2_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_2_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_2_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_2_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_2_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_2_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_3_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_3_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_3_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_3_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_3_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_3_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_3_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_4_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_4_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_4_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_4_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_4_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_4_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_4_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_5_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_5_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_5_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_5_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_5_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_5_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_5_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_6_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_6_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_6_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_6_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_6_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_6_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_6_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_7_cfg_l; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [1:0] csr_io_pmp_7_cfg_a; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_7_cfg_x; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_7_cfg_w; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_pmp_7_cfg_r; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [29:0] csr_io_pmp_7_addr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_pmp_7_mask; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_inst_0; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_trace_0_valid; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_trace_0_iaddr; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire [31:0] csr_io_trace_0_insn; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire csr_io_trace_0_exception; // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] wire bpu_io_status_debug; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_bp_0_control_action; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire [1:0] bpu_io_bp_0_control_tmatch; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_bp_0_control_x; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_bp_0_control_w; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_bp_0_control_r; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire [31:0] bpu_io_bp_0_address; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire [31:0] bpu_io_pc; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire [31:0] bpu_io_ea; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_xcpt_if; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_xcpt_ld; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_xcpt_st; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_debug_if; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_debug_ld; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire bpu_io_debug_st; // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] wire [3:0] alu_io_fn; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire [31:0] alu_io_in2; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire [31:0] alu_io_in1; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire [31:0] alu_io_out; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire [31:0] alu_io_adder_out; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire alu_io_cmp_out; // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] wire div_clock; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_reset; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_io_req_ready; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_io_req_valid; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [3:0] div_io_req_bits_fn; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [31:0] div_io_req_bits_in1; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [31:0] div_io_req_bits_in2; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [4:0] div_io_req_bits_tag; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_io_kill; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_io_resp_ready; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire div_io_resp_valid; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [31:0] div_io_resp_bits_data; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire [4:0] div_io_resp_bits_tag; // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] wire PlusArgTimeout_clock; // @[PlusArg.scala 53:11:freechips.rocketchip.system.TinyConfig.fir@125518.4] wire PlusArgTimeout_reset; // @[PlusArg.scala 53:11:freechips.rocketchip.system.TinyConfig.fir@125518.4] wire [31:0] PlusArgTimeout_io_count; // @[PlusArg.scala 53:11:freechips.rocketchip.system.TinyConfig.fir@125518.4] reg id_reg_pause; // @[RocketCore.scala 101:25:freechips.rocketchip.system.TinyConfig.fir@123746.4] reg [31:0] _RAND_3; reg imem_might_request_reg; // @[RocketCore.scala 102:35:freechips.rocketchip.system.TinyConfig.fir@123747.4] reg [31:0] _RAND_4; reg ex_ctrl_branch; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_5; reg ex_ctrl_jal; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_6; reg ex_ctrl_jalr; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_7; reg ex_ctrl_rxs2; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_8; reg [1:0] ex_ctrl_sel_alu2; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_9; reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_10; reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_11; reg [3:0] ex_ctrl_alu_fn; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_12; reg ex_ctrl_mem; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_13; reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_14; reg ex_ctrl_div; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_15; reg ex_ctrl_wxd; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_16; reg [2:0] ex_ctrl_csr; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_17; reg ex_ctrl_fence_i; // @[RocketCore.scala 174:20:freechips.rocketchip.system.TinyConfig.fir@123751.4] reg [31:0] _RAND_18; reg mem_ctrl_branch; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_19; reg mem_ctrl_jal; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_20; reg mem_ctrl_jalr; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_21; reg mem_ctrl_mem; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_22; reg mem_ctrl_div; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_23; reg mem_ctrl_wxd; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_24; reg [2:0] mem_ctrl_csr; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_25; reg mem_ctrl_fence_i; // @[RocketCore.scala 175:21:freechips.rocketchip.system.TinyConfig.fir@123752.4] reg [31:0] _RAND_26; reg wb_ctrl_mem; // @[RocketCore.scala 176:20:freechips.rocketchip.system.TinyConfig.fir@123753.4] reg [31:0] _RAND_27; reg wb_ctrl_div; // @[RocketCore.scala 176:20:freechips.rocketchip.system.TinyConfig.fir@123753.4] reg [31:0] _RAND_28; reg wb_ctrl_wxd; // @[RocketCore.scala 176:20:freechips.rocketchip.system.TinyConfig.fir@123753.4] reg [31:0] _RAND_29; reg [2:0] wb_ctrl_csr; // @[RocketCore.scala 176:20:freechips.rocketchip.system.TinyConfig.fir@123753.4] reg [31:0] _RAND_30; reg wb_ctrl_fence_i; // @[RocketCore.scala 176:20:freechips.rocketchip.system.TinyConfig.fir@123753.4] reg [31:0] _RAND_31; reg ex_reg_xcpt_interrupt; // @[RocketCore.scala 178:35:freechips.rocketchip.system.TinyConfig.fir@123754.4] reg [31:0] _RAND_32; reg ex_reg_valid; // @[RocketCore.scala 179:35:freechips.rocketchip.system.TinyConfig.fir@123755.4] reg [31:0] _RAND_33; reg ex_reg_rvc; // @[RocketCore.scala 180:35:freechips.rocketchip.system.TinyConfig.fir@123756.4] reg [31:0] _RAND_34; reg ex_reg_xcpt; // @[RocketCore.scala 182:35:freechips.rocketchip.system.TinyConfig.fir@123758.4] reg [31:0] _RAND_35; reg ex_reg_flush_pipe; // @[RocketCore.scala 183:35:freechips.rocketchip.system.TinyConfig.fir@123759.4] reg [31:0] _RAND_36; reg ex_reg_load_use; // @[RocketCore.scala 184:35:freechips.rocketchip.system.TinyConfig.fir@123760.4] reg [31:0] _RAND_37; reg [31:0] ex_reg_cause; // @[RocketCore.scala 185:35:freechips.rocketchip.system.TinyConfig.fir@123761.4] reg [31:0] _RAND_38; reg ex_reg_replay; // @[RocketCore.scala 186:26:freechips.rocketchip.system.TinyConfig.fir@123762.4] reg [31:0] _RAND_39; reg [31:0] ex_reg_pc; // @[RocketCore.scala 187:22:freechips.rocketchip.system.TinyConfig.fir@123763.4] reg [31:0] _RAND_40; reg [1:0] ex_reg_mem_size; // @[RocketCore.scala 188:28:freechips.rocketchip.system.TinyConfig.fir@123764.4] reg [31:0] _RAND_41; reg [31:0] ex_reg_inst; // @[RocketCore.scala 189:24:freechips.rocketchip.system.TinyConfig.fir@123765.4] reg [31:0] _RAND_42; reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala 190:28:freechips.rocketchip.system.TinyConfig.fir@123766.4] reg [31:0] _RAND_43; reg mem_reg_xcpt_interrupt; // @[RocketCore.scala 195:36:freechips.rocketchip.system.TinyConfig.fir@123770.4] reg [31:0] _RAND_44; reg mem_reg_valid; // @[RocketCore.scala 196:36:freechips.rocketchip.system.TinyConfig.fir@123771.4] reg [31:0] _RAND_45; reg mem_reg_rvc; // @[RocketCore.scala 197:36:freechips.rocketchip.system.TinyConfig.fir@123772.4] reg [31:0] _RAND_46; reg mem_reg_xcpt; // @[RocketCore.scala 199:36:freechips.rocketchip.system.TinyConfig.fir@123774.4] reg [31:0] _RAND_47; reg mem_reg_replay; // @[RocketCore.scala 200:36:freechips.rocketchip.system.TinyConfig.fir@123775.4] reg [31:0] _RAND_48; reg mem_reg_flush_pipe; // @[RocketCore.scala 201:36:freechips.rocketchip.system.TinyConfig.fir@123776.4] reg [31:0] _RAND_49; reg [31:0] mem_reg_cause; // @[RocketCore.scala 202:36:freechips.rocketchip.system.TinyConfig.fir@123777.4] reg [31:0] _RAND_50; reg mem_reg_slow_bypass; // @[RocketCore.scala 203:36:freechips.rocketchip.system.TinyConfig.fir@123778.4] reg [31:0] _RAND_51; reg mem_reg_load; // @[RocketCore.scala 204:36:freechips.rocketchip.system.TinyConfig.fir@123779.4] reg [31:0] _RAND_52; reg mem_reg_store; // @[RocketCore.scala 205:36:freechips.rocketchip.system.TinyConfig.fir@123780.4] reg [31:0] _RAND_53; reg [31:0] mem_reg_pc; // @[RocketCore.scala 207:23:freechips.rocketchip.system.TinyConfig.fir@123782.4] reg [31:0] _RAND_54; reg [31:0] mem_reg_inst; // @[RocketCore.scala 208:25:freechips.rocketchip.system.TinyConfig.fir@123783.4] reg [31:0] _RAND_55; reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala 210:29:freechips.rocketchip.system.TinyConfig.fir@123785.4] reg [31:0] _RAND_56; reg [31:0] mem_reg_wdata; // @[RocketCore.scala 213:26:freechips.rocketchip.system.TinyConfig.fir@123788.4] reg [31:0] _RAND_57; reg [31:0] mem_reg_rs2; // @[RocketCore.scala 214:24:freechips.rocketchip.system.TinyConfig.fir@123789.4] reg [31:0] _RAND_58; reg mem_br_taken; // @[RocketCore.scala 215:25:freechips.rocketchip.system.TinyConfig.fir@123790.4] reg [31:0] _RAND_59; reg wb_reg_valid; // @[RocketCore.scala 219:35:freechips.rocketchip.system.TinyConfig.fir@123794.4] reg [31:0] _RAND_60; reg wb_reg_xcpt; // @[RocketCore.scala 220:35:freechips.rocketchip.system.TinyConfig.fir@123795.4] reg [31:0] _RAND_61; reg wb_reg_replay; // @[RocketCore.scala 221:35:freechips.rocketchip.system.TinyConfig.fir@123796.4] reg [31:0] _RAND_62; reg wb_reg_flush_pipe; // @[RocketCore.scala 222:35:freechips.rocketchip.system.TinyConfig.fir@123797.4] reg [31:0] _RAND_63; reg [31:0] wb_reg_cause; // @[RocketCore.scala 223:35:freechips.rocketchip.system.TinyConfig.fir@123798.4] reg [31:0] _RAND_64; reg [31:0] wb_reg_pc; // @[RocketCore.scala 225:22:freechips.rocketchip.system.TinyConfig.fir@123800.4] reg [31:0] _RAND_65; reg [31:0] wb_reg_inst; // @[RocketCore.scala 227:24:freechips.rocketchip.system.TinyConfig.fir@123802.4] reg [31:0] _RAND_66; reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala 228:28:freechips.rocketchip.system.TinyConfig.fir@123803.4] reg [31:0] _RAND_67; reg [31:0] wb_reg_wdata; // @[RocketCore.scala 229:25:freechips.rocketchip.system.TinyConfig.fir@123804.4] reg [31:0] _RAND_68; wire replay_wb_common; // @[RocketCore.scala 604:42:freechips.rocketchip.system.TinyConfig.fir@125021.4] wire _T_898; // @[RocketCore.scala 582:19:freechips.rocketchip.system.TinyConfig.fir@124984.4] wire _T_899; // @[RocketCore.scala 582:34:freechips.rocketchip.system.TinyConfig.fir@124985.4] wire _T_910; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124996.4] wire _T_901; // @[RocketCore.scala 583:34:freechips.rocketchip.system.TinyConfig.fir@124987.4] wire _T_911; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124997.4] wire _T_903; // @[RocketCore.scala 584:34:freechips.rocketchip.system.TinyConfig.fir@124989.4] wire _T_912; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124998.4] wire _T_905; // @[RocketCore.scala 585:34:freechips.rocketchip.system.TinyConfig.fir@124991.4] wire _T_913; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124999.4] wire _T_907; // @[RocketCore.scala 586:34:freechips.rocketchip.system.TinyConfig.fir@124993.4] wire _T_914; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@125000.4] wire _T_909; // @[RocketCore.scala 587:34:freechips.rocketchip.system.TinyConfig.fir@124995.4] wire wb_xcpt; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@125001.4] wire _T_932; // @[RocketCore.scala 607:27:freechips.rocketchip.system.TinyConfig.fir@125026.4] wire _T_933; // @[RocketCore.scala 607:38:freechips.rocketchip.system.TinyConfig.fir@125027.4] wire take_pc_wb; // @[RocketCore.scala 607:53:freechips.rocketchip.system.TinyConfig.fir@125028.4] wire _T_779; // @[RocketCore.scala 488:40:freechips.rocketchip.system.TinyConfig.fir@124795.4] wire _T_780; // @[RocketCore.scala 488:57:freechips.rocketchip.system.TinyConfig.fir@124796.4] wire mem_cfi_taken; // @[RocketCore.scala 488:74:freechips.rocketchip.system.TinyConfig.fir@124797.4] wire take_pc_mem; // @[RocketCore.scala 491:32:freechips.rocketchip.system.TinyConfig.fir@124802.4] wire take_pc_mem_wb; // @[RocketCore.scala 234:35:freechips.rocketchip.system.TinyConfig.fir@123809.4] wire [31:0] _T; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123818.4] wire _T_1; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123819.4] wire [31:0] _T_2; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123820.4] wire _T_3; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123821.4] wire [31:0] _T_4; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123822.4] wire _T_5; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123823.4] wire [31:0] _T_6; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123824.4] wire _T_7; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123825.4] wire [31:0] _T_8; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123826.4] wire _T_9; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123827.4] wire [31:0] _T_10; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123828.4] wire _T_11; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123829.4] wire [31:0] _T_12; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123830.4] wire _T_13; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123831.4] wire [31:0] _T_14; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123832.4] wire _T_15; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123833.4] wire [31:0] _T_16; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123834.4] wire _T_17; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123835.4] wire [31:0] _T_18; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123836.4] wire _T_19; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123837.4] wire _T_21; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123839.4] wire [31:0] _T_22; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123840.4] wire _T_23; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123841.4] wire _T_25; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123843.4] wire [31:0] _T_26; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123844.4] wire _T_27; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123845.4] wire [31:0] _T_28; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123846.4] wire _T_29; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123847.4] wire [31:0] _T_30; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123848.4] wire _T_31; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123849.4] wire [31:0] _T_32; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123850.4] wire _T_33; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123851.4] wire _T_34; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123852.4] wire _T_35; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123853.4] wire [31:0] _T_36; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123854.4] wire _T_37; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123855.4] wire [31:0] _T_38; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123856.4] wire _T_39; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123857.4] wire [31:0] _T_40; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123858.4] wire _T_41; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123859.4] wire _T_43; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123861.4] wire _T_45; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123863.4] wire _T_46; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123864.4] wire _T_47; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123865.4] wire _T_48; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123866.4] wire _T_49; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123867.4] wire _T_50; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123868.4] wire _T_51; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123869.4] wire _T_52; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123870.4] wire _T_53; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123871.4] wire _T_54; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123872.4] wire _T_55; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123873.4] wire _T_56; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123874.4] wire _T_57; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123875.4] wire _T_58; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123876.4] wire _T_59; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123877.4] wire _T_60; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123878.4] wire _T_61; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123879.4] wire _T_62; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123880.4] wire _T_63; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123881.4] wire _T_64; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123882.4] wire _T_65; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123883.4] wire id_ctrl_legal; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123884.4] wire [31:0] _T_67; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123885.4] wire id_ctrl_branch; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123886.4] wire [31:0] _T_70; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123888.4] wire id_ctrl_jal; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123889.4] wire [31:0] _T_73; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123891.4] wire id_ctrl_jalr; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123892.4] wire [31:0] _T_76; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123894.4] wire _T_77; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123895.4] wire [31:0] _T_78; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123896.4] wire _T_79; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123897.4] wire [31:0] _T_80; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123898.4] wire _T_81; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123899.4] wire _T_83; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123901.4] wire id_ctrl_rxs2; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123902.4] wire [31:0] _T_85; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123903.4] wire _T_86; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123904.4] wire [31:0] _T_87; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123905.4] wire _T_88; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123906.4] wire [31:0] _T_89; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123907.4] wire _T_90; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123908.4] wire [31:0] _T_91; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123909.4] wire _T_92; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123910.4] wire _T_94; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123912.4] wire _T_95; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123913.4] wire id_ctrl_rxs1; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123914.4] wire [31:0] _T_97; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123915.4] wire _T_98; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123916.4] wire [31:0] _T_99; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123917.4] wire _T_100; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123918.4] wire [31:0] _T_101; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123919.4] wire _T_102; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123920.4] wire [31:0] _T_103; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123921.4] wire _T_104; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123922.4] wire _T_106; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123924.4] wire _T_107; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123925.4] wire _T_108; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123926.4] wire _T_109; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123927.4] wire _T_111; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123929.4] wire [31:0] _T_112; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123930.4] wire _T_113; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123931.4] wire _T_115; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123933.4] wire _T_116; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123934.4] wire [1:0] id_ctrl_sel_alu2; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123935.4] wire [31:0] _T_118; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123936.4] wire _T_119; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123937.4] wire _T_121; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123939.4] wire _T_122; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123940.4] wire _T_123; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123941.4] wire [31:0] _T_124; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123942.4] wire _T_125; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123943.4] wire _T_127; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123945.4] wire [1:0] id_ctrl_sel_alu1; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123946.4] wire [31:0] _T_129; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123947.4] wire _T_130; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123948.4] wire _T_132; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123950.4] wire _T_134; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123952.4] wire _T_136; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123954.4] wire _T_138; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123956.4] wire [31:0] _T_139; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123957.4] wire _T_140; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123958.4] wire [31:0] _T_141; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123959.4] wire _T_142; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123960.4] wire _T_144; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123962.4] wire _T_145; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123963.4] wire [2:0] id_ctrl_sel_imm; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123965.4] wire [31:0] _T_151; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123969.4] wire _T_152; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123970.4] wire [31:0] _T_153; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123971.4] wire _T_154; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123972.4] wire [31:0] _T_155; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123973.4] wire _T_156; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123974.4] wire [31:0] _T_157; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123975.4] wire _T_158; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123976.4] wire _T_160; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123978.4] wire _T_161; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123979.4] wire _T_162; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123980.4] wire [31:0] _T_163; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123981.4] wire _T_164; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123982.4] wire [31:0] _T_165; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123983.4] wire _T_166; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123984.4] wire [31:0] _T_167; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123985.4] wire _T_168; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123986.4] wire [31:0] _T_169; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123987.4] wire _T_170; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123988.4] wire [31:0] _T_171; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123989.4] wire _T_172; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123990.4] wire [31:0] _T_173; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123991.4] wire _T_174; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123992.4] wire [31:0] _T_175; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123993.4] wire _T_176; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123994.4] wire _T_178; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123996.4] wire _T_179; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123997.4] wire _T_180; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123998.4] wire _T_181; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123999.4] wire _T_182; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124000.4] wire _T_183; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124001.4] wire [31:0] _T_184; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124002.4] wire _T_185; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124003.4] wire [31:0] _T_186; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124004.4] wire _T_187; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124005.4] wire [31:0] _T_188; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124006.4] wire _T_189; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124007.4] wire [31:0] _T_190; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124008.4] wire _T_191; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124009.4] wire [31:0] _T_192; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124010.4] wire _T_193; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124011.4] wire _T_195; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124013.4] wire _T_196; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124014.4] wire _T_197; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124015.4] wire _T_198; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124016.4] wire [31:0] _T_199; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124017.4] wire _T_200; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124018.4] wire [31:0] _T_201; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124019.4] wire _T_202; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124020.4] wire [31:0] _T_203; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124021.4] wire _T_204; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124022.4] wire _T_206; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124024.4] wire _T_207; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124025.4] wire _T_208; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124026.4] wire _T_209; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124027.4] wire [3:0] id_ctrl_alu_fn; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124030.4] wire _T_214; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124032.4] wire _T_215; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124033.4] wire _T_216; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124034.4] wire _T_217; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124035.4] wire id_ctrl_mem; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124036.4] wire [31:0] _T_219; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124037.4] wire _T_220; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124038.4] wire [31:0] _T_221; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124039.4] wire _T_222; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124040.4] wire [31:0] _T_223; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124041.4] wire _T_224; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124042.4] wire _T_226; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124044.4] wire _T_227; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124045.4] wire [31:0] _T_228; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124046.4] wire _T_229; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124047.4] wire [31:0] _T_230; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124048.4] wire _T_231; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124049.4] wire _T_233; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124051.4] wire [31:0] _T_234; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124052.4] wire _T_235; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124053.4] wire [31:0] _T_236; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124054.4] wire _T_237; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124055.4] wire _T_239; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124057.4] wire _T_240; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124058.4] wire [31:0] _T_241; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124059.4] wire _T_242; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124060.4] wire [4:0] id_ctrl_mem_cmd; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124065.4] wire [31:0] _T_248; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124066.4] wire id_ctrl_div; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124067.4] wire _T_252; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124070.4] wire _T_254; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124072.4] wire [31:0] _T_255; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124073.4] wire _T_256; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124074.4] wire [31:0] _T_257; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124075.4] wire _T_258; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124076.4] wire [31:0] _T_259; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124077.4] wire _T_260; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124078.4] wire _T_262; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124080.4] wire _T_263; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124081.4] wire _T_264; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124082.4] wire _T_265; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124083.4] wire _T_266; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124084.4] wire id_ctrl_wxd; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124085.4] wire [31:0] _T_268; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124086.4] wire _T_269; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124087.4] wire _T_272; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124090.4] wire _T_275; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124093.4] wire [2:0] id_ctrl_csr; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124096.4] wire [31:0] _T_279; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124097.4] wire id_ctrl_fence_i; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124098.4] wire [31:0] _T_282; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124100.4] wire id_ctrl_fence; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124101.4] wire id_ctrl_amo; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124104.4] reg id_reg_fence; // @[RocketCore.scala 252:25:freechips.rocketchip.system.TinyConfig.fir@124136.4] reg [31:0] _RAND_69; wire _T_289; // @[RocketCore.scala 950:45:freechips.rocketchip.system.TinyConfig.fir@124140.4] wire [4:0] _T_291; // @[RocketCore.scala 944:44:freechips.rocketchip.system.TinyConfig.fir@124142.4] wire [31:0] _T_294; // @[RocketCore.scala 950:25:freechips.rocketchip.system.TinyConfig.fir@124145.4] wire [4:0] _T_297; // @[RocketCore.scala 944:44:freechips.rocketchip.system.TinyConfig.fir@124151.4] wire [31:0] _T_300; // @[RocketCore.scala 950:25:freechips.rocketchip.system.TinyConfig.fir@124154.4] wire _T_367; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124229.4] wire _T_368; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124230.4] wire _T_369; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124231.4] wire _T_370; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124232.4] wire id_csr_en; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124233.4] wire id_system_insn; // @[RocketCore.scala 262:36:freechips.rocketchip.system.TinyConfig.fir@124234.4] wire id_csr_ren; // @[RocketCore.scala 263:54:freechips.rocketchip.system.TinyConfig.fir@124239.4] wire _T_375; // @[RocketCore.scala 265:50:freechips.rocketchip.system.TinyConfig.fir@124241.4] wire id_sfence; // @[RocketCore.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@124242.4] wire _T_376; // @[RocketCore.scala 266:32:freechips.rocketchip.system.TinyConfig.fir@124243.4] wire _T_377; // @[RocketCore.scala 266:67:freechips.rocketchip.system.TinyConfig.fir@124244.4] wire _T_378; // @[RocketCore.scala 266:64:freechips.rocketchip.system.TinyConfig.fir@124245.4] wire _T_379; // @[RocketCore.scala 266:79:freechips.rocketchip.system.TinyConfig.fir@124246.4] wire id_csr_flush; // @[RocketCore.scala 266:50:freechips.rocketchip.system.TinyConfig.fir@124247.4] wire _T_380; // @[RocketCore.scala 274:25:freechips.rocketchip.system.TinyConfig.fir@124250.4] wire _T_382; // @[RocketCore.scala 275:55:freechips.rocketchip.system.TinyConfig.fir@124252.4] wire _T_383; // @[RocketCore.scala 275:37:freechips.rocketchip.system.TinyConfig.fir@124253.4] wire _T_384; // @[RocketCore.scala 275:34:freechips.rocketchip.system.TinyConfig.fir@124254.4] wire _T_385; // @[RocketCore.scala 274:40:freechips.rocketchip.system.TinyConfig.fir@124255.4] wire _T_386; // @[RocketCore.scala 276:38:freechips.rocketchip.system.TinyConfig.fir@124256.4] wire _T_387; // @[RocketCore.scala 276:20:freechips.rocketchip.system.TinyConfig.fir@124257.4] wire _T_388; // @[RocketCore.scala 276:17:freechips.rocketchip.system.TinyConfig.fir@124258.4] wire _T_389; // @[RocketCore.scala 275:65:freechips.rocketchip.system.TinyConfig.fir@124259.4] wire _T_397; // @[RocketCore.scala 279:51:freechips.rocketchip.system.TinyConfig.fir@124267.4] wire _T_398; // @[RocketCore.scala 279:33:freechips.rocketchip.system.TinyConfig.fir@124268.4] wire _T_399; // @[RocketCore.scala 279:30:freechips.rocketchip.system.TinyConfig.fir@124269.4] wire _T_400; // @[RocketCore.scala 278:47:freechips.rocketchip.system.TinyConfig.fir@124270.4] wire _T_408; // @[RocketCore.scala 282:64:freechips.rocketchip.system.TinyConfig.fir@124278.4] wire _T_409; // @[RocketCore.scala 282:49:freechips.rocketchip.system.TinyConfig.fir@124279.4] wire _T_410; // @[RocketCore.scala 282:15:freechips.rocketchip.system.TinyConfig.fir@124280.4] wire id_illegal_insn; // @[RocketCore.scala 281:81:freechips.rocketchip.system.TinyConfig.fir@124281.4] wire id_amo_aq; // @[RocketCore.scala 285:29:freechips.rocketchip.system.TinyConfig.fir@124287.4] wire id_amo_rl; // @[RocketCore.scala 286:29:freechips.rocketchip.system.TinyConfig.fir@124288.4] wire [3:0] id_fence_succ; // @[RocketCore.scala 288:33:freechips.rocketchip.system.TinyConfig.fir@124290.4] wire _T_416; // @[RocketCore.scala 289:52:freechips.rocketchip.system.TinyConfig.fir@124291.4] wire id_fence_next; // @[RocketCore.scala 289:37:freechips.rocketchip.system.TinyConfig.fir@124292.4] wire _T_417; // @[RocketCore.scala 290:21:freechips.rocketchip.system.TinyConfig.fir@124293.4] wire id_mem_busy; // @[RocketCore.scala 290:38:freechips.rocketchip.system.TinyConfig.fir@124294.4] wire _T_418; // @[RocketCore.scala 291:9:freechips.rocketchip.system.TinyConfig.fir@124295.4] wire _T_426; // @[RocketCore.scala 296:33:freechips.rocketchip.system.TinyConfig.fir@124307.4] wire _T_427; // @[RocketCore.scala 296:46:freechips.rocketchip.system.TinyConfig.fir@124308.4] wire _T_429; // @[RocketCore.scala 296:81:freechips.rocketchip.system.TinyConfig.fir@124310.4] wire _T_430; // @[RocketCore.scala 296:65:freechips.rocketchip.system.TinyConfig.fir@124311.4] wire id_do_fence; // @[RocketCore.scala 296:17:freechips.rocketchip.system.TinyConfig.fir@124312.4] wire _T_433; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124325.4] wire _T_434; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124326.4] wire _T_436; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124328.4] wire _T_437; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124329.4] wire _T_438; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124330.4] wire id_xcpt; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124331.4] wire [1:0] _T_439; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124332.4] wire [3:0] _T_440; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124333.4] wire [3:0] _T_441; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124334.4] wire [3:0] _T_443; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124336.4] wire [3:0] _T_444; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124337.4] wire [4:0] ex_waddr; // @[RocketCore.scala 332:29:freechips.rocketchip.system.TinyConfig.fir@124348.4] wire [4:0] mem_waddr; // @[RocketCore.scala 333:31:freechips.rocketchip.system.TinyConfig.fir@124349.4] wire [4:0] wb_waddr; // @[RocketCore.scala 334:29:freechips.rocketchip.system.TinyConfig.fir@124350.4] wire _T_453; // @[RocketCore.scala 337:19:freechips.rocketchip.system.TinyConfig.fir@124351.4] wire _T_454; // @[RocketCore.scala 338:20:freechips.rocketchip.system.TinyConfig.fir@124352.4] wire _T_455; // @[RocketCore.scala 338:39:freechips.rocketchip.system.TinyConfig.fir@124353.4] wire _T_456; // @[RocketCore.scala 338:36:freechips.rocketchip.system.TinyConfig.fir@124354.4] wire id_bypass_src_0_0; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124356.4] wire _T_459; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124358.4] wire id_bypass_src_0_1; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124359.4] wire _T_460; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124360.4] wire id_bypass_src_0_2; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124361.4] wire id_bypass_src_0_3; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124363.4] wire id_bypass_src_1_0; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124364.4] wire _T_463; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124366.4] wire id_bypass_src_1_1; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124367.4] wire _T_464; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124368.4] wire id_bypass_src_1_2; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124369.4] wire id_bypass_src_1_3; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124371.4] reg ex_reg_rs_bypass_0; // @[RocketCore.scala 344:29:freechips.rocketchip.system.TinyConfig.fir@124372.4] reg [31:0] _RAND_70; reg ex_reg_rs_bypass_1; // @[RocketCore.scala 344:29:freechips.rocketchip.system.TinyConfig.fir@124372.4] reg [31:0] _RAND_71; reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala 345:26:freechips.rocketchip.system.TinyConfig.fir@124373.4] reg [31:0] _RAND_72; reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala 345:26:freechips.rocketchip.system.TinyConfig.fir@124373.4] reg [31:0] _RAND_73; reg [29:0] ex_reg_rs_msb_0; // @[RocketCore.scala 346:26:freechips.rocketchip.system.TinyConfig.fir@124374.4] reg [31:0] _RAND_74; reg [29:0] ex_reg_rs_msb_1; // @[RocketCore.scala 346:26:freechips.rocketchip.system.TinyConfig.fir@124374.4] reg [31:0] _RAND_75; wire _T_466; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124375.4] wire [31:0] _T_467; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124376.4] wire _T_468; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124377.4] wire [31:0] _T_469; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124378.4] wire _T_470; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124379.4] wire [31:0] _T_471; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124380.4] wire [31:0] _T_472; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124381.4] wire [31:0] ex_rs_0; // @[RocketCore.scala 348:14:freechips.rocketchip.system.TinyConfig.fir@124382.4] wire _T_473; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124383.4] wire [31:0] _T_474; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124384.4] wire _T_475; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124385.4] wire [31:0] _T_476; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124386.4] wire _T_477; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124387.4] wire [31:0] _T_478; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124388.4] wire [31:0] _T_479; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124389.4] wire [31:0] ex_rs_1; // @[RocketCore.scala 348:14:freechips.rocketchip.system.TinyConfig.fir@124390.4] wire _T_480; // @[RocketCore.scala 965:24:freechips.rocketchip.system.TinyConfig.fir@124391.4] wire _T_481; // @[RocketCore.scala 965:48:freechips.rocketchip.system.TinyConfig.fir@124392.4] wire _T_482; // @[RocketCore.scala 965:53:freechips.rocketchip.system.TinyConfig.fir@124393.4] wire _T_483; // @[RocketCore.scala 965:19:freechips.rocketchip.system.TinyConfig.fir@124394.4] wire _T_484; // @[RocketCore.scala 966:26:freechips.rocketchip.system.TinyConfig.fir@124395.4] wire [10:0] _T_485; // @[RocketCore.scala 966:41:freechips.rocketchip.system.TinyConfig.fir@124396.4] wire [10:0] _T_486; // @[RocketCore.scala 966:49:freechips.rocketchip.system.TinyConfig.fir@124397.4] wire [10:0] _T_487; // @[RocketCore.scala 966:21:freechips.rocketchip.system.TinyConfig.fir@124398.4] wire _T_488; // @[RocketCore.scala 967:26:freechips.rocketchip.system.TinyConfig.fir@124399.4] wire _T_489; // @[RocketCore.scala 967:43:freechips.rocketchip.system.TinyConfig.fir@124400.4] wire _T_490; // @[RocketCore.scala 967:36:freechips.rocketchip.system.TinyConfig.fir@124401.4] wire [7:0] _T_491; // @[RocketCore.scala 967:65:freechips.rocketchip.system.TinyConfig.fir@124402.4] wire [7:0] _T_492; // @[RocketCore.scala 967:73:freechips.rocketchip.system.TinyConfig.fir@124403.4] wire [7:0] _T_493; // @[RocketCore.scala 967:21:freechips.rocketchip.system.TinyConfig.fir@124404.4] wire _T_496; // @[RocketCore.scala 968:33:freechips.rocketchip.system.TinyConfig.fir@124407.4] wire _T_497; // @[RocketCore.scala 969:23:freechips.rocketchip.system.TinyConfig.fir@124408.4] wire _T_498; // @[RocketCore.scala 969:39:freechips.rocketchip.system.TinyConfig.fir@124409.4] wire _T_499; // @[RocketCore.scala 969:44:freechips.rocketchip.system.TinyConfig.fir@124410.4] wire _T_500; // @[RocketCore.scala 970:23:freechips.rocketchip.system.TinyConfig.fir@124411.4] wire _T_501; // @[RocketCore.scala 970:39:freechips.rocketchip.system.TinyConfig.fir@124412.4] wire _T_502; // @[RocketCore.scala 970:43:freechips.rocketchip.system.TinyConfig.fir@124413.4] wire _T_503; // @[RocketCore.scala 970:18:freechips.rocketchip.system.TinyConfig.fir@124414.4] wire _T_504; // @[RocketCore.scala 969:18:freechips.rocketchip.system.TinyConfig.fir@124415.4] wire _T_505; // @[RocketCore.scala 968:18:freechips.rocketchip.system.TinyConfig.fir@124416.4] wire [5:0] _T_509; // @[RocketCore.scala 971:66:freechips.rocketchip.system.TinyConfig.fir@124420.4] wire [5:0] _T_510; // @[RocketCore.scala 971:20:freechips.rocketchip.system.TinyConfig.fir@124421.4] wire _T_512; // @[RocketCore.scala 973:24:freechips.rocketchip.system.TinyConfig.fir@124423.4] wire _T_514; // @[RocketCore.scala 973:34:freechips.rocketchip.system.TinyConfig.fir@124425.4] wire [3:0] _T_515; // @[RocketCore.scala 973:57:freechips.rocketchip.system.TinyConfig.fir@124426.4] wire [3:0] _T_517; // @[RocketCore.scala 974:39:freechips.rocketchip.system.TinyConfig.fir@124428.4] wire [3:0] _T_518; // @[RocketCore.scala 974:52:freechips.rocketchip.system.TinyConfig.fir@124429.4] wire [3:0] _T_519; // @[RocketCore.scala 974:19:freechips.rocketchip.system.TinyConfig.fir@124430.4] wire [3:0] _T_520; // @[RocketCore.scala 973:19:freechips.rocketchip.system.TinyConfig.fir@124431.4] wire [3:0] _T_521; // @[RocketCore.scala 972:19:freechips.rocketchip.system.TinyConfig.fir@124432.4] wire _T_524; // @[RocketCore.scala 976:22:freechips.rocketchip.system.TinyConfig.fir@124435.4] wire _T_527; // @[RocketCore.scala 977:37:freechips.rocketchip.system.TinyConfig.fir@124438.4] wire _T_528; // @[RocketCore.scala 977:17:freechips.rocketchip.system.TinyConfig.fir@124439.4] wire _T_529; // @[RocketCore.scala 976:17:freechips.rocketchip.system.TinyConfig.fir@124440.4] wire _T_530; // @[RocketCore.scala 975:17:freechips.rocketchip.system.TinyConfig.fir@124441.4] wire _T_533; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124444.4] wire [7:0] _T_534; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124445.4] wire [10:0] _T_536; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124447.4] wire _T_537; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124448.4] wire [31:0] _T_540; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124451.4] wire [31:0] ex_imm; // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124452.4] wire [31:0] _T_541; // @[RocketCore.scala 351:24:freechips.rocketchip.system.TinyConfig.fir@124453.4] wire [31:0] _T_542; // @[RocketCore.scala 352:24:freechips.rocketchip.system.TinyConfig.fir@124454.4] wire _T_543; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124455.4] wire [31:0] _T_544; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124456.4] wire _T_545; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124457.4] wire [31:0] ex_op1; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124458.4] wire [31:0] _T_546; // @[RocketCore.scala 354:24:freechips.rocketchip.system.TinyConfig.fir@124459.4] wire [3:0] _T_547; // @[RocketCore.scala 356:19:freechips.rocketchip.system.TinyConfig.fir@124460.4] wire _T_548; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124461.4] wire [3:0] _T_549; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124462.4] wire _T_550; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124463.4] wire [31:0] _T_551; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124464.4] wire _T_552; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124465.4] wire [31:0] ex_op2; // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124466.4] wire _T_1147; // @[RocketCore.scala 745:17:freechips.rocketchip.system.TinyConfig.fir@125330.4] wire _T_1148; // @[RocketCore.scala 745:40:freechips.rocketchip.system.TinyConfig.fir@125331.4] wire _T_1149; // @[RocketCore.scala 745:71:freechips.rocketchip.system.TinyConfig.fir@125332.4] wire _T_987; // @[RocketCore.scala 676:55:freechips.rocketchip.system.TinyConfig.fir@125144.4] wire _T_988; // @[RocketCore.scala 676:42:freechips.rocketchip.system.TinyConfig.fir@125145.4] wire _T_1035; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125200.4] wire _T_1036; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125201.4] wire _T_989; // @[RocketCore.scala 677:55:freechips.rocketchip.system.TinyConfig.fir@125146.4] wire _T_990; // @[RocketCore.scala 677:42:freechips.rocketchip.system.TinyConfig.fir@125147.4] wire _T_1037; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125202.4] wire _T_1038; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125203.4] wire _T_1041; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125206.4] wire _T_991; // @[RocketCore.scala 678:55:freechips.rocketchip.system.TinyConfig.fir@125148.4] wire _T_992; // @[RocketCore.scala 678:42:freechips.rocketchip.system.TinyConfig.fir@125149.4] wire _T_1039; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125204.4] wire _T_1040; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125205.4] wire _T_1042; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125207.4] wire data_hazard_ex; // @[RocketCore.scala 696:36:freechips.rocketchip.system.TinyConfig.fir@125208.4] wire _T_1028; // @[RocketCore.scala 695:38:freechips.rocketchip.system.TinyConfig.fir@125192.4] wire _T_1029; // @[RocketCore.scala 695:48:freechips.rocketchip.system.TinyConfig.fir@125193.4] wire _T_1030; // @[RocketCore.scala 695:64:freechips.rocketchip.system.TinyConfig.fir@125194.4] wire ex_cannot_bypass; // @[RocketCore.scala 695:94:freechips.rocketchip.system.TinyConfig.fir@125196.4] wire _T_1054; // @[RocketCore.scala 698:54:freechips.rocketchip.system.TinyConfig.fir@125221.4] wire id_ex_hazard; // @[RocketCore.scala 698:35:freechips.rocketchip.system.TinyConfig.fir@125223.4] wire _T_1062; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125232.4] wire _T_1063; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125233.4] wire _T_1064; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125234.4] wire _T_1065; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125235.4] wire _T_1068; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125238.4] wire _T_1066; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125236.4] wire _T_1067; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125237.4] wire _T_1069; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125239.4] wire data_hazard_mem; // @[RocketCore.scala 705:38:freechips.rocketchip.system.TinyConfig.fir@125240.4] wire _T_1056; // @[RocketCore.scala 704:40:freechips.rocketchip.system.TinyConfig.fir@125225.4] wire _T_1057; // @[RocketCore.scala 704:66:freechips.rocketchip.system.TinyConfig.fir@125226.4] wire _T_1058; // @[RocketCore.scala 704:50:freechips.rocketchip.system.TinyConfig.fir@125227.4] wire mem_cannot_bypass; // @[RocketCore.scala 704:100:freechips.rocketchip.system.TinyConfig.fir@125229.4] wire _T_1081; // @[RocketCore.scala 707:57:freechips.rocketchip.system.TinyConfig.fir@125253.4] wire id_mem_hazard; // @[RocketCore.scala 707:37:freechips.rocketchip.system.TinyConfig.fir@125255.4] wire _T_1119; // @[RocketCore.scala 734:18:freechips.rocketchip.system.TinyConfig.fir@125301.4] wire _T_1085; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125259.4] wire _T_1086; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125260.4] wire _T_1087; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125261.4] wire _T_1088; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125262.4] wire _T_1091; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125265.4] wire _T_1089; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125263.4] wire _T_1090; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125264.4] wire _T_1092; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125266.4] wire data_hazard_wb; // @[RocketCore.scala 711:36:freechips.rocketchip.system.TinyConfig.fir@125267.4] wire _T_606; // @[RocketCore.scala 459:39:freechips.rocketchip.system.TinyConfig.fir@124607.4] wire wb_dcache_miss; // @[RocketCore.scala 459:36:freechips.rocketchip.system.TinyConfig.fir@124608.4] wire wb_set_sboard; // @[RocketCore.scala 603:35:freechips.rocketchip.system.TinyConfig.fir@125019.4] wire _T_1104; // @[RocketCore.scala 713:54:freechips.rocketchip.system.TinyConfig.fir@125280.4] wire id_wb_hazard; // @[RocketCore.scala 713:35:freechips.rocketchip.system.TinyConfig.fir@125282.4] wire _T_1120; // @[RocketCore.scala 734:35:freechips.rocketchip.system.TinyConfig.fir@125302.4] reg [31:0] _T_993; // @[RocketCore.scala 929:25:freechips.rocketchip.system.TinyConfig.fir@125150.4] reg [31:0] _RAND_76; wire [30:0] _T_994; // @[RocketCore.scala 930:35:freechips.rocketchip.system.TinyConfig.fir@125151.4] wire [31:0] _T_995; // @[RocketCore.scala 930:40:freechips.rocketchip.system.TinyConfig.fir@125152.4] wire [31:0] _T_1001; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125161.4] wire _T_1002; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125162.4] wire dmem_resp_valid; // @[RocketCore.scala 613:44:freechips.rocketchip.system.TinyConfig.fir@125036.4] wire dmem_resp_replay; // @[RocketCore.scala 614:42:freechips.rocketchip.system.TinyConfig.fir@125037.4] wire _T_935; // @[RocketCore.scala 610:45:freechips.rocketchip.system.TinyConfig.fir@125030.4] wire dmem_resp_xpu; // @[RocketCore.scala 610:23:freechips.rocketchip.system.TinyConfig.fir@125032.4] wire _T_940; // @[RocketCore.scala 629:26:freechips.rocketchip.system.TinyConfig.fir@125050.4] wire _T_939; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@125046.4] wire ll_wen; // @[RocketCore.scala 629:44:freechips.rocketchip.system.TinyConfig.fir@125051.4] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala 612:46:freechips.rocketchip.system.TinyConfig.fir@125035.4] wire [4:0] ll_waddr; // @[RocketCore.scala 629:44:freechips.rocketchip.system.TinyConfig.fir@125051.4] wire _T_1003; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125163.4] wire _T_1004; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125164.4] wire _T_1005; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125165.4] wire _T_1006; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125166.4] wire _T_1007; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125167.4] wire [31:0] _T_1008; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125168.4] wire _T_1009; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125169.4] wire _T_1010; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125170.4] wire _T_1011; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125171.4] wire _T_1012; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125172.4] wire _T_1013; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125173.4] wire _T_1014; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125174.4] wire _T_1022; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125182.4] wire [31:0] _T_1015; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125175.4] wire _T_1016; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125176.4] wire _T_1017; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125177.4] wire _T_1018; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125178.4] wire _T_1019; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125179.4] wire _T_1020; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125180.4] wire _T_1021; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125181.4] wire id_sboard_hazard; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125183.4] wire _T_1121; // @[RocketCore.scala 734:51:freechips.rocketchip.system.TinyConfig.fir@125303.4] wire _T_1122; // @[RocketCore.scala 735:40:freechips.rocketchip.system.TinyConfig.fir@125304.4] wire _T_1123; // @[RocketCore.scala 735:57:freechips.rocketchip.system.TinyConfig.fir@125305.4] wire _T_1124; // @[RocketCore.scala 735:23:freechips.rocketchip.system.TinyConfig.fir@125306.4] wire _T_1125; // @[RocketCore.scala 734:71:freechips.rocketchip.system.TinyConfig.fir@125307.4] reg blocked; // @[RocketCore.scala 726:22:freechips.rocketchip.system.TinyConfig.fir@125283.4] reg [31:0] _RAND_77; wire _T_1113; // @[RocketCore.scala 728:16:freechips.rocketchip.system.TinyConfig.fir@125292.4] wire dcache_blocked; // @[RocketCore.scala 728:13:freechips.rocketchip.system.TinyConfig.fir@125293.4] wire _T_1132; // @[RocketCore.scala 738:17:freechips.rocketchip.system.TinyConfig.fir@125314.4] wire _T_1133; // @[RocketCore.scala 737:32:freechips.rocketchip.system.TinyConfig.fir@125315.4] wire wb_wxd; // @[RocketCore.scala 602:29:freechips.rocketchip.system.TinyConfig.fir@125018.4] wire _T_1136; // @[RocketCore.scala 740:65:freechips.rocketchip.system.TinyConfig.fir@125318.4] wire _T_1137; // @[RocketCore.scala 740:62:freechips.rocketchip.system.TinyConfig.fir@125319.4] wire _T_1138; // @[RocketCore.scala 740:40:freechips.rocketchip.system.TinyConfig.fir@125320.4] wire _T_1139; // @[RocketCore.scala 740:21:freechips.rocketchip.system.TinyConfig.fir@125321.4] wire _T_1140; // @[RocketCore.scala 740:75:freechips.rocketchip.system.TinyConfig.fir@125322.4] wire _T_1141; // @[RocketCore.scala 740:17:freechips.rocketchip.system.TinyConfig.fir@125323.4] wire _T_1142; // @[RocketCore.scala 739:34:freechips.rocketchip.system.TinyConfig.fir@125324.4] wire _T_1145; // @[RocketCore.scala 741:15:freechips.rocketchip.system.TinyConfig.fir@125327.4] wire _T_1146; // @[RocketCore.scala 742:17:freechips.rocketchip.system.TinyConfig.fir@125328.4] wire ctrl_stalld; // @[RocketCore.scala 743:22:freechips.rocketchip.system.TinyConfig.fir@125329.4] wire _T_1150; // @[RocketCore.scala 745:89:freechips.rocketchip.system.TinyConfig.fir@125333.4] wire ctrl_killd; // @[RocketCore.scala 745:104:freechips.rocketchip.system.TinyConfig.fir@125334.4] wire _T_556; // @[RocketCore.scala 396:19:freechips.rocketchip.system.TinyConfig.fir@124488.4] wire _T_557; // @[RocketCore.scala 397:20:freechips.rocketchip.system.TinyConfig.fir@124490.4] wire _T_558; // @[RocketCore.scala 397:29:freechips.rocketchip.system.TinyConfig.fir@124491.4] wire _T_568; // @[RocketCore.scala 407:42:freechips.rocketchip.system.TinyConfig.fir@124510.6] wire _T_569; // @[RocketCore.scala 407:25:freechips.rocketchip.system.TinyConfig.fir@124511.6] wire [1:0] _T_570; // @[RocketCore.scala 414:22:freechips.rocketchip.system.TinyConfig.fir@124523.8] wire _T_571; // @[RocketCore.scala 414:29:freechips.rocketchip.system.TinyConfig.fir@124524.8] wire [1:0] _T_572; // @[RocketCore.scala 419:40:freechips.rocketchip.system.TinyConfig.fir@124530.8] wire _T_573; // @[RocketCore.scala 419:47:freechips.rocketchip.system.TinyConfig.fir@124531.8] wire _T_574; // @[RocketCore.scala 419:28:freechips.rocketchip.system.TinyConfig.fir@124532.8] wire _T_575; // @[RocketCore.scala 424:42:freechips.rocketchip.system.TinyConfig.fir@124538.6] wire [1:0] _T_576; // @[RocketCore.scala 426:34:freechips.rocketchip.system.TinyConfig.fir@124541.6] wire _T_578; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124544.6] wire _T_579; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124545.6] wire [1:0] _T_582; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124549.8] wire _T_583; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124552.6] wire _T_584; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124553.6] wire do_bypass; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124554.6] wire _T_587; // @[RocketCore.scala 436:26:freechips.rocketchip.system.TinyConfig.fir@124560.6] wire _T_588; // @[RocketCore.scala 436:23:freechips.rocketchip.system.TinyConfig.fir@124561.6] wire _T_941; // @[RocketCore.scala 637:34:freechips.rocketchip.system.TinyConfig.fir@125056.4] wire _T_942; // @[RocketCore.scala 637:31:freechips.rocketchip.system.TinyConfig.fir@125057.4] wire _T_943; // @[RocketCore.scala 637:48:freechips.rocketchip.system.TinyConfig.fir@125058.4] wire wb_valid; // @[RocketCore.scala 637:45:freechips.rocketchip.system.TinyConfig.fir@125059.4] wire wb_wen; // @[RocketCore.scala 638:25:freechips.rocketchip.system.TinyConfig.fir@125060.4] wire rf_wen; // @[RocketCore.scala 639:23:freechips.rocketchip.system.TinyConfig.fir@125061.4] wire [4:0] rf_waddr; // @[RocketCore.scala 640:21:freechips.rocketchip.system.TinyConfig.fir@125062.4] wire _T_950; // @[RocketCore.scala 955:16:freechips.rocketchip.system.TinyConfig.fir@125071.6] wire _T_954; // @[RocketCore.scala 958:20:freechips.rocketchip.system.TinyConfig.fir@125077.8] wire _T_944; // @[RocketCore.scala 641:38:freechips.rocketchip.system.TinyConfig.fir@125063.4] wire [31:0] ll_wdata; // @[:freechips.rocketchip.system.TinyConfig.fir@125040.4 :freechips.rocketchip.system.TinyConfig.fir@125042.4] wire _T_946; // @[RocketCore.scala 643:34:freechips.rocketchip.system.TinyConfig.fir@125065.4] wire [31:0] _T_948; // @[RocketCore.scala 643:21:freechips.rocketchip.system.TinyConfig.fir@125067.4] wire [31:0] _T_949; // @[RocketCore.scala 642:21:freechips.rocketchip.system.TinyConfig.fir@125068.4] wire [31:0] rf_wdata; // @[RocketCore.scala 641:21:freechips.rocketchip.system.TinyConfig.fir@125069.4] wire [31:0] _GEN_230; // @[RocketCore.scala 958:31:freechips.rocketchip.system.TinyConfig.fir@125078.8] wire [31:0] _GEN_237; // @[RocketCore.scala 955:29:freechips.rocketchip.system.TinyConfig.fir@125072.6] wire [31:0] id_rs_0; // @[RocketCore.scala 646:17:freechips.rocketchip.system.TinyConfig.fir@125070.4] wire [1:0] _T_589; // @[RocketCore.scala 437:37:freechips.rocketchip.system.TinyConfig.fir@124563.8] wire [29:0] _T_590; // @[RocketCore.scala 438:38:freechips.rocketchip.system.TinyConfig.fir@124565.8] wire _T_591; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124568.6] wire _T_592; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124569.6] wire do_bypass_1; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124570.6] wire _T_595; // @[RocketCore.scala 436:26:freechips.rocketchip.system.TinyConfig.fir@124576.6] wire _T_596; // @[RocketCore.scala 436:23:freechips.rocketchip.system.TinyConfig.fir@124577.6] wire _T_955; // @[RocketCore.scala 958:20:freechips.rocketchip.system.TinyConfig.fir@125081.8] wire [31:0] _GEN_231; // @[RocketCore.scala 958:31:freechips.rocketchip.system.TinyConfig.fir@125082.8] wire [31:0] _GEN_238; // @[RocketCore.scala 955:29:freechips.rocketchip.system.TinyConfig.fir@125072.6] wire [31:0] id_rs_1; // @[RocketCore.scala 646:17:freechips.rocketchip.system.TinyConfig.fir@125070.4] wire [1:0] _T_597; // @[RocketCore.scala 437:37:freechips.rocketchip.system.TinyConfig.fir@124579.8] wire [29:0] _T_598; // @[RocketCore.scala 438:38:freechips.rocketchip.system.TinyConfig.fir@124581.8] wire [15:0] _T_599; // @[RocketCore.scala 442:62:freechips.rocketchip.system.TinyConfig.fir@124585.8] wire [31:0] inst; // @[RocketCore.scala 442:21:freechips.rocketchip.system.TinyConfig.fir@124586.8] wire [1:0] _T_600; // @[RocketCore.scala 444:31:freechips.rocketchip.system.TinyConfig.fir@124588.8] wire [29:0] _T_601; // @[RocketCore.scala 445:32:freechips.rocketchip.system.TinyConfig.fir@124590.8] wire _T_1083; // @[RocketCore.scala 708:32:freechips.rocketchip.system.TinyConfig.fir@125256.4] wire id_load_use; // @[RocketCore.scala 708:51:freechips.rocketchip.system.TinyConfig.fir@125257.4] wire _T_603; // @[RocketCore.scala 448:21:freechips.rocketchip.system.TinyConfig.fir@124595.4] wire _T_604; // @[RocketCore.scala 448:41:freechips.rocketchip.system.TinyConfig.fir@124596.4] wire _T_605; // @[RocketCore.scala 458:34:freechips.rocketchip.system.TinyConfig.fir@124605.4] wire ex_pc_valid; // @[RocketCore.scala 458:51:freechips.rocketchip.system.TinyConfig.fir@124606.4] wire _T_607; // @[RocketCore.scala 460:45:freechips.rocketchip.system.TinyConfig.fir@124609.4] wire _T_608; // @[RocketCore.scala 460:42:freechips.rocketchip.system.TinyConfig.fir@124610.4] wire _T_609; // @[RocketCore.scala 461:45:freechips.rocketchip.system.TinyConfig.fir@124611.4] wire _T_610; // @[RocketCore.scala 461:42:freechips.rocketchip.system.TinyConfig.fir@124612.4] wire replay_ex_structural; // @[RocketCore.scala 460:64:freechips.rocketchip.system.TinyConfig.fir@124613.4] wire replay_ex_load_use; // @[RocketCore.scala 462:43:freechips.rocketchip.system.TinyConfig.fir@124614.4] wire _T_611; // @[RocketCore.scala 463:75:freechips.rocketchip.system.TinyConfig.fir@124615.4] wire _T_612; // @[RocketCore.scala 463:50:freechips.rocketchip.system.TinyConfig.fir@124616.4] wire replay_ex; // @[RocketCore.scala 463:33:freechips.rocketchip.system.TinyConfig.fir@124617.4] wire _T_613; // @[RocketCore.scala 464:35:freechips.rocketchip.system.TinyConfig.fir@124618.4] wire _T_614; // @[RocketCore.scala 464:51:freechips.rocketchip.system.TinyConfig.fir@124619.4] wire ctrl_killx; // @[RocketCore.scala 464:48:freechips.rocketchip.system.TinyConfig.fir@124620.4] wire _T_615; // @[RocketCore.scala 466:40:freechips.rocketchip.system.TinyConfig.fir@124621.4] wire _T_616; // @[RocketCore.scala 466:69:freechips.rocketchip.system.TinyConfig.fir@124622.4] wire ex_slow_bypass; // @[RocketCore.scala 466:50:freechips.rocketchip.system.TinyConfig.fir@124623.4] wire ex_xcpt; // @[RocketCore.scala 470:28:freechips.rocketchip.system.TinyConfig.fir@124627.4] wire _T_627; // @[RocketCore.scala 476:36:freechips.rocketchip.system.TinyConfig.fir@124636.4] wire mem_pc_valid; // @[RocketCore.scala 476:54:freechips.rocketchip.system.TinyConfig.fir@124637.4] wire [31:0] _T_628; // @[RocketCore.scala 477:34:freechips.rocketchip.system.TinyConfig.fir@124638.4] wire _T_631; // @[RocketCore.scala 965:48:freechips.rocketchip.system.TinyConfig.fir@124641.4] wire _T_632; // @[RocketCore.scala 965:53:freechips.rocketchip.system.TinyConfig.fir@124642.4] wire [10:0] _T_637; // @[RocketCore.scala 966:21:freechips.rocketchip.system.TinyConfig.fir@124647.4] wire [7:0] _T_641; // @[RocketCore.scala 967:65:freechips.rocketchip.system.TinyConfig.fir@124651.4] wire [7:0] _T_642; // @[RocketCore.scala 967:73:freechips.rocketchip.system.TinyConfig.fir@124652.4] wire [7:0] _T_643; // @[RocketCore.scala 967:21:freechips.rocketchip.system.TinyConfig.fir@124653.4] wire _T_648; // @[RocketCore.scala 969:39:freechips.rocketchip.system.TinyConfig.fir@124658.4] wire _T_649; // @[RocketCore.scala 969:44:freechips.rocketchip.system.TinyConfig.fir@124659.4] wire _T_651; // @[RocketCore.scala 970:39:freechips.rocketchip.system.TinyConfig.fir@124661.4] wire _T_652; // @[RocketCore.scala 970:43:freechips.rocketchip.system.TinyConfig.fir@124662.4] wire [5:0] _T_659; // @[RocketCore.scala 971:66:freechips.rocketchip.system.TinyConfig.fir@124669.4] wire [3:0] _T_665; // @[RocketCore.scala 973:57:freechips.rocketchip.system.TinyConfig.fir@124675.4] wire [3:0] _T_668; // @[RocketCore.scala 974:52:freechips.rocketchip.system.TinyConfig.fir@124678.4] wire _T_683; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124693.4] wire [7:0] _T_684; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124694.4] wire [10:0] _T_686; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124696.4] wire _T_687; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124697.4] wire [31:0] _T_690; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124700.4] wire [31:0] _T_691; // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124701.4] wire _T_745; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124755.4] wire [7:0] _T_746; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124756.4] wire [31:0] _T_752; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124762.4] wire [31:0] _T_753; // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124763.4] wire [3:0] _T_754; // @[RocketCore.scala 480:8:freechips.rocketchip.system.TinyConfig.fir@124764.4] wire [31:0] _T_755; // @[RocketCore.scala 479:8:freechips.rocketchip.system.TinyConfig.fir@124765.4] wire [31:0] _T_756; // @[RocketCore.scala 478:8:freechips.rocketchip.system.TinyConfig.fir@124766.4] wire [31:0] _T_758; // @[RocketCore.scala 477:41:freechips.rocketchip.system.TinyConfig.fir@124768.4] wire [31:0] mem_br_target; // @[RocketCore.scala 477:41:freechips.rocketchip.system.TinyConfig.fir@124769.4] wire [31:0] _T_760; // @[RocketCore.scala 481:106:freechips.rocketchip.system.TinyConfig.fir@124771.4] wire [31:0] _T_761; // @[RocketCore.scala 481:21:freechips.rocketchip.system.TinyConfig.fir@124772.4] wire [31:0] _T_762; // @[RocketCore.scala 481:129:freechips.rocketchip.system.TinyConfig.fir@124773.4] wire [31:0] _T_763; // @[RocketCore.scala 481:129:freechips.rocketchip.system.TinyConfig.fir@124774.4] wire [31:0] mem_npc; // @[RocketCore.scala 481:141:freechips.rocketchip.system.TinyConfig.fir@124775.4] wire _T_764; // @[RocketCore.scala 483:30:freechips.rocketchip.system.TinyConfig.fir@124776.4] wire _T_765; // @[RocketCore.scala 484:31:freechips.rocketchip.system.TinyConfig.fir@124777.4] wire _T_766; // @[RocketCore.scala 484:62:freechips.rocketchip.system.TinyConfig.fir@124778.4] wire _T_767; // @[RocketCore.scala 484:8:freechips.rocketchip.system.TinyConfig.fir@124779.4] wire mem_wrong_npc; // @[RocketCore.scala 483:8:freechips.rocketchip.system.TinyConfig.fir@124780.4] wire _T_770; // @[RocketCore.scala 485:66:freechips.rocketchip.system.TinyConfig.fir@124783.4] wire mem_npc_misaligned; // @[RocketCore.scala 485:56:freechips.rocketchip.system.TinyConfig.fir@124784.4] wire _T_773; // @[RocketCore.scala 486:27:freechips.rocketchip.system.TinyConfig.fir@124787.4] wire _T_774; // @[RocketCore.scala 486:59:freechips.rocketchip.system.TinyConfig.fir@124788.4] wire _T_775; // @[RocketCore.scala 486:41:freechips.rocketchip.system.TinyConfig.fir@124789.4] wire [31:0] _T_777; // @[RocketCore.scala 486:26:freechips.rocketchip.system.TinyConfig.fir@124791.4] wire [31:0] mem_int_wdata; // @[RocketCore.scala 486:119:freechips.rocketchip.system.TinyConfig.fir@124792.4] wire _T_778; // @[RocketCore.scala 487:33:freechips.rocketchip.system.TinyConfig.fir@124793.4] wire mem_cfi; // @[RocketCore.scala 487:50:freechips.rocketchip.system.TinyConfig.fir@124794.4] wire _T_785; // @[RocketCore.scala 493:20:freechips.rocketchip.system.TinyConfig.fir@124804.4] wire _T_792; // @[RocketCore.scala 500:23:freechips.rocketchip.system.TinyConfig.fir@124815.4] wire _T_793; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@124825.8] wire _T_794; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@124826.8] wire _T_795; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@124827.8] wire _T_797; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@124829.8] wire _T_798; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124830.8] wire _T_799; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124831.8] wire _T_800; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124832.8] wire _T_801; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124833.8] wire _T_802; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124834.8] wire _T_803; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124835.8] wire _T_804; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124836.8] wire _T_805; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124837.8] wire _T_806; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124838.8] wire _T_807; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124839.8] wire _T_808; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124840.8] wire _T_809; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124841.8] wire _T_810; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124842.8] wire _T_811; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124843.8] wire _T_812; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124844.8] wire _T_813; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124845.8] wire _T_814; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@124846.8] wire _T_815; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@124847.8] wire _T_816; // @[RocketCore.scala 507:33:freechips.rocketchip.system.TinyConfig.fir@124848.8] wire _T_817; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@124850.8] wire _T_818; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@124851.8] wire _T_819; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@124852.8] wire _T_821; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@124854.8] wire _T_839; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@124872.8] wire _T_840; // @[RocketCore.scala 508:34:freechips.rocketchip.system.TinyConfig.fir@124873.8] wire [31:0] _T_841; // @[RocketCore.scala 520:25:freechips.rocketchip.system.TinyConfig.fir@124885.8] wire _T_844; // @[RocketCore.scala 523:24:freechips.rocketchip.system.TinyConfig.fir@124890.8] wire _T_846; // @[AMOALU.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@124894.10] wire [7:0] _T_847; // @[AMOALU.scala 26:66:freechips.rocketchip.system.TinyConfig.fir@124895.10] wire [31:0] _T_849; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124897.10] wire _T_850; // @[AMOALU.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@124898.10] wire [15:0] _T_851; // @[AMOALU.scala 26:66:freechips.rocketchip.system.TinyConfig.fir@124899.10] wire [31:0] _T_852; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124900.10] wire _T_855; // @[RocketCore.scala 527:24:freechips.rocketchip.system.TinyConfig.fir@124905.8] wire _T_856; // @[RocketCore.scala 534:38:freechips.rocketchip.system.TinyConfig.fir@124911.4] wire _T_857; // @[RocketCore.scala 534:75:freechips.rocketchip.system.TinyConfig.fir@124912.4] wire mem_breakpoint; // @[RocketCore.scala 534:57:freechips.rocketchip.system.TinyConfig.fir@124913.4] wire _T_858; // @[RocketCore.scala 535:44:freechips.rocketchip.system.TinyConfig.fir@124914.4] wire _T_859; // @[RocketCore.scala 535:82:freechips.rocketchip.system.TinyConfig.fir@124915.4] wire mem_debug_breakpoint; // @[RocketCore.scala 535:64:freechips.rocketchip.system.TinyConfig.fir@124916.4] wire mem_ldst_xcpt; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124917.4] wire [3:0] mem_ldst_cause; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124918.4] wire _T_860; // @[RocketCore.scala 541:29:freechips.rocketchip.system.TinyConfig.fir@124919.4] wire _T_861; // @[RocketCore.scala 542:20:freechips.rocketchip.system.TinyConfig.fir@124920.4] wire _T_862; // @[RocketCore.scala 543:20:freechips.rocketchip.system.TinyConfig.fir@124921.4] wire _T_863; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124922.4] wire mem_xcpt; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124923.4] wire [3:0] _T_864; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124924.4] wire dcache_kill_mem; // @[RocketCore.scala 552:55:freechips.rocketchip.system.TinyConfig.fir@124937.4] wire replay_mem; // @[RocketCore.scala 554:37:freechips.rocketchip.system.TinyConfig.fir@124940.4] wire _T_878; // @[RocketCore.scala 555:38:freechips.rocketchip.system.TinyConfig.fir@124942.4] wire _T_879; // @[RocketCore.scala 555:52:freechips.rocketchip.system.TinyConfig.fir@124943.4] wire _T_880; // @[RocketCore.scala 555:71:freechips.rocketchip.system.TinyConfig.fir@124944.4] wire killm_common; // @[RocketCore.scala 555:68:freechips.rocketchip.system.TinyConfig.fir@124945.4] reg _T_882; // @[RocketCore.scala 556:37:freechips.rocketchip.system.TinyConfig.fir@124947.4] reg [31:0] _RAND_78; wire ctrl_killm; // @[RocketCore.scala 557:33:freechips.rocketchip.system.TinyConfig.fir@124951.4] wire _T_885; // @[RocketCore.scala 560:19:freechips.rocketchip.system.TinyConfig.fir@124953.4] wire _T_886; // @[RocketCore.scala 561:34:freechips.rocketchip.system.TinyConfig.fir@124955.4] wire [2:0] _T_915; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125002.4] wire [3:0] _T_916; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125003.4] wire [3:0] _T_917; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125004.4] wire [3:0] _T_918; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125005.4] wire [3:0] _T_919; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125006.4] wire [31:0] wb_cause; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125007.4] wire _T_920; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125008.4] wire _T_922; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125010.4] wire _T_924; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125012.4] wire _T_926; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125014.4] wire [1:0] _T_957; // @[RocketCore.scala 654:66:freechips.rocketchip.system.TinyConfig.fir@125093.4] wire _T_958; // @[RocketCore.scala 654:73:freechips.rocketchip.system.TinyConfig.fir@125094.4] wire [15:0] _T_959; // @[RocketCore.scala 654:91:freechips.rocketchip.system.TinyConfig.fir@125095.4] wire [15:0] _T_960; // @[RocketCore.scala 654:50:freechips.rocketchip.system.TinyConfig.fir@125096.4] wire [15:0] _T_961; // @[RocketCore.scala 654:119:freechips.rocketchip.system.TinyConfig.fir@125097.4] wire _T_963; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125106.4] wire _T_964; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125107.4] wire _T_969; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125112.4] wire _T_970; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125113.4] wire _T_971; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125114.4] wire _T_972; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125115.4] wire _T_973; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125116.4] wire _T_974; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125117.4] wire _T_975; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125118.4] wire _T_976; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125119.4] wire _T_977; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125120.4] wire _T_978; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125121.4] wire _T_979; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125122.4] wire _T_980; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125123.4] wire _T_981; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125124.4] wire tval_valid; // @[RocketCore.scala 661:28:freechips.rocketchip.system.TinyConfig.fir@125125.4] wire [2:0] _T_984; // @[CSR.scala 130:15:freechips.rocketchip.system.TinyConfig.fir@125137.4] wire [2:0] _T_985; // @[CSR.scala 130:11:freechips.rocketchip.system.TinyConfig.fir@125138.4] wire [31:0] _T_996; // @[RocketCore.scala 933:62:freechips.rocketchip.system.TinyConfig.fir@125153.4] wire [31:0] _T_997; // @[RocketCore.scala 933:49:freechips.rocketchip.system.TinyConfig.fir@125154.4] wire [31:0] _T_998; // @[RocketCore.scala 925:64:freechips.rocketchip.system.TinyConfig.fir@125155.4] wire [31:0] _T_999; // @[RocketCore.scala 925:62:freechips.rocketchip.system.TinyConfig.fir@125156.4] wire _T_1023; // @[RocketCore.scala 692:28:freechips.rocketchip.system.TinyConfig.fir@125184.4] wire [31:0] _T_1024; // @[RocketCore.scala 933:62:freechips.rocketchip.system.TinyConfig.fir@125185.4] wire [31:0] _T_1025; // @[RocketCore.scala 933:49:freechips.rocketchip.system.TinyConfig.fir@125186.4] wire [31:0] _T_1026; // @[RocketCore.scala 924:60:freechips.rocketchip.system.TinyConfig.fir@125187.4] wire _T_1027; // @[RocketCore.scala 936:17:freechips.rocketchip.system.TinyConfig.fir@125188.4] wire _T_1109; // @[RocketCore.scala 727:60:freechips.rocketchip.system.TinyConfig.fir@125287.4] wire _T_1110; // @[RocketCore.scala 727:95:freechips.rocketchip.system.TinyConfig.fir@125288.4] wire _T_1111; // @[RocketCore.scala 727:116:freechips.rocketchip.system.TinyConfig.fir@125289.4] wire _T_1153; // @[RocketCore.scala 750:17:freechips.rocketchip.system.TinyConfig.fir@125339.4] wire [31:0] _T_1154; // @[RocketCore.scala 751:8:freechips.rocketchip.system.TinyConfig.fir@125340.4] wire _T_1156; // @[RocketCore.scala 753:40:freechips.rocketchip.system.TinyConfig.fir@125343.4] wire _T_1157; // @[RocketCore.scala 753:62:freechips.rocketchip.system.TinyConfig.fir@125344.4] wire _T_1159; // @[RocketCore.scala 755:43:freechips.rocketchip.system.TinyConfig.fir@125347.4] wire _T_1160; // @[CustomCSRs.scala 38:61:freechips.rocketchip.system.TinyConfig.fir@125348.4] wire _T_1167; // @[RocketCore.scala 767:45:freechips.rocketchip.system.TinyConfig.fir@125364.4] wire _T_1168; // @[RocketCore.scala 767:60:freechips.rocketchip.system.TinyConfig.fir@125365.4] wire _T_1169; // @[RocketCore.scala 767:81:freechips.rocketchip.system.TinyConfig.fir@125366.4] wire _T_1170; // @[RocketCore.scala 767:90:freechips.rocketchip.system.TinyConfig.fir@125367.4] wire [5:0] ex_dcache_tag; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@125417.4] wire _T_1196; // @[RocketCore.scala 803:42:freechips.rocketchip.system.TinyConfig.fir@125421.4] wire [4:0] _T_1213; // @[RocketCore.scala 815:58:freechips.rocketchip.system.TinyConfig.fir@125456.4] wire [4:0] _T_1214; // @[RocketCore.scala 815:58:freechips.rocketchip.system.TinyConfig.fir@125458.4] wire [4:0] _T_1216; // @[RocketCore.scala 820:28:freechips.rocketchip.system.TinyConfig.fir@125465.4] wire _T_1217; // @[RocketCore.scala 820:62:freechips.rocketchip.system.TinyConfig.fir@125466.4] wire unpause; // @[RocketCore.scala 820:92:freechips.rocketchip.system.TinyConfig.fir@125468.4] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala 846:41:freechips.rocketchip.system.TinyConfig.fir@125484.4] wire _T_1224; // @[RocketCore.scala 847:55:freechips.rocketchip.system.TinyConfig.fir@125486.4] wire coreMonitorBundle_valid; // @[RocketCore.scala 847:52:freechips.rocketchip.system.TinyConfig.fir@125487.4] wire [31:0] coreMonitorBundle_pc; // @[RocketCore.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@125489.4] wire _T_1228; // @[RocketCore.scala 849:44:freechips.rocketchip.system.TinyConfig.fir@125492.4] wire _T_1229; // @[RocketCore.scala 849:41:freechips.rocketchip.system.TinyConfig.fir@125493.4] wire [4:0] coreMonitorBundle_wrdst; // @[RocketCore.scala 849:33:freechips.rocketchip.system.TinyConfig.fir@125494.4] reg [31:0] _T_1232; // @[RocketCore.scala 853:43:freechips.rocketchip.system.TinyConfig.fir@125500.4] reg [31:0] _RAND_79; reg [31:0] coreMonitorBundle_rd0val; // @[RocketCore.scala 853:34:freechips.rocketchip.system.TinyConfig.fir@125502.4] reg [31:0] _RAND_80; reg [31:0] _T_1235; // @[RocketCore.scala 855:43:freechips.rocketchip.system.TinyConfig.fir@125507.4] reg [31:0] _RAND_81; reg [31:0] coreMonitorBundle_rd1val; // @[RocketCore.scala 855:34:freechips.rocketchip.system.TinyConfig.fir@125509.4] reg [31:0] _RAND_82; wire _T_1238; // @[RocketCore.scala 885:11:freechips.rocketchip.system.TinyConfig.fir@125514.4] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala 841:31:freechips.rocketchip.system.TinyConfig.fir@125479.4 RocketCore.scala 856:26:freechips.rocketchip.system.TinyConfig.fir@125512.4] IBuf ibuf ( // @[RocketCore.scala 238:20:freechips.rocketchip.system.TinyConfig.fir@123810.4] .clock(ibuf_clock), .reset(ibuf_reset), .io_imem_ready(ibuf_io_imem_ready), .io_imem_valid(ibuf_io_imem_valid), .io_imem_bits_pc(ibuf_io_imem_bits_pc), .io_imem_bits_data(ibuf_io_imem_bits_data), .io_imem_bits_xcpt_ae_inst(ibuf_io_imem_bits_xcpt_ae_inst), .io_imem_bits_replay(ibuf_io_imem_bits_replay), .io_kill(ibuf_io_kill), .io_pc(ibuf_io_pc), .io_inst_0_ready(ibuf_io_inst_0_ready), .io_inst_0_valid(ibuf_io_inst_0_valid), .io_inst_0_bits_xcpt0_ae_inst(ibuf_io_inst_0_bits_xcpt0_ae_inst), .io_inst_0_bits_xcpt1_pf_inst(ibuf_io_inst_0_bits_xcpt1_pf_inst), .io_inst_0_bits_xcpt1_ae_inst(ibuf_io_inst_0_bits_xcpt1_ae_inst), .io_inst_0_bits_replay(ibuf_io_inst_0_bits_replay), .io_inst_0_bits_rvc(ibuf_io_inst_0_bits_rvc), .io_inst_0_bits_inst_bits(ibuf_io_inst_0_bits_inst_bits), .io_inst_0_bits_inst_rd(ibuf_io_inst_0_bits_inst_rd), .io_inst_0_bits_inst_rs1(ibuf_io_inst_0_bits_inst_rs1), .io_inst_0_bits_inst_rs2(ibuf_io_inst_0_bits_inst_rs2), .io_inst_0_bits_raw(ibuf_io_inst_0_bits_raw) ); CSRFile csr ( // @[RocketCore.scala 260:19:freechips.rocketchip.system.TinyConfig.fir@124225.4] .clock(csr_clock), .reset(csr_reset), .io_ungated_clock(csr_io_ungated_clock), .io_interrupts_debug(csr_io_interrupts_debug), .io_interrupts_mtip(csr_io_interrupts_mtip), .io_interrupts_msip(csr_io_interrupts_msip), .io_interrupts_meip(csr_io_interrupts_meip), .io_rw_addr(csr_io_rw_addr), .io_rw_cmd(csr_io_rw_cmd), .io_rw_rdata(csr_io_rw_rdata), .io_rw_wdata(csr_io_rw_wdata), .io_decode_0_csr(csr_io_decode_0_csr), .io_decode_0_fp_illegal(csr_io_decode_0_fp_illegal), .io_decode_0_fp_csr(csr_io_decode_0_fp_csr), .io_decode_0_read_illegal(csr_io_decode_0_read_illegal), .io_decode_0_write_illegal(csr_io_decode_0_write_illegal), .io_decode_0_write_flush(csr_io_decode_0_write_flush), .io_csr_stall(csr_io_csr_stall), .io_eret(csr_io_eret), .io_singleStep(csr_io_singleStep), .io_status_debug(csr_io_status_debug), .io_status_cease(csr_io_status_cease), .io_status_isa(csr_io_status_isa), .io_status_dprv(csr_io_status_dprv), .io_status_prv(csr_io_status_prv), .io_status_sd(csr_io_status_sd), .io_status_zero2(csr_io_status_zero2), .io_status_sxl(csr_io_status_sxl), .io_status_uxl(csr_io_status_uxl), .io_status_sd_rv32(csr_io_status_sd_rv32), .io_status_zero1(csr_io_status_zero1), .io_status_tsr(csr_io_status_tsr), .io_status_tw(csr_io_status_tw), .io_status_tvm(csr_io_status_tvm), .io_status_mxr(csr_io_status_mxr), .io_status_sum(csr_io_status_sum), .io_status_mprv(csr_io_status_mprv), .io_status_xs(csr_io_status_xs), .io_status_fs(csr_io_status_fs), .io_status_mpp(csr_io_status_mpp), .io_status_hpp(csr_io_status_hpp), .io_status_spp(csr_io_status_spp), .io_status_mpie(csr_io_status_mpie), .io_status_hpie(csr_io_status_hpie), .io_status_spie(csr_io_status_spie), .io_status_upie(csr_io_status_upie), .io_status_mie(csr_io_status_mie), .io_status_hie(csr_io_status_hie), .io_status_sie(csr_io_status_sie), .io_status_uie(csr_io_status_uie), .io_evec(csr_io_evec), .io_exception(csr_io_exception), .io_retire(csr_io_retire), .io_cause(csr_io_cause), .io_pc(csr_io_pc), .io_tval(csr_io_tval), .io_time(csr_io_time), .io_interrupt(csr_io_interrupt), .io_interrupt_cause(csr_io_interrupt_cause), .io_bp_0_control_action(csr_io_bp_0_control_action), .io_bp_0_control_tmatch(csr_io_bp_0_control_tmatch), .io_bp_0_control_x(csr_io_bp_0_control_x), .io_bp_0_control_w(csr_io_bp_0_control_w), .io_bp_0_control_r(csr_io_bp_0_control_r), .io_bp_0_address(csr_io_bp_0_address), .io_pmp_0_cfg_l(csr_io_pmp_0_cfg_l), .io_pmp_0_cfg_a(csr_io_pmp_0_cfg_a), .io_pmp_0_cfg_x(csr_io_pmp_0_cfg_x), .io_pmp_0_cfg_w(csr_io_pmp_0_cfg_w), .io_pmp_0_cfg_r(csr_io_pmp_0_cfg_r), .io_pmp_0_addr(csr_io_pmp_0_addr), .io_pmp_0_mask(csr_io_pmp_0_mask), .io_pmp_1_cfg_l(csr_io_pmp_1_cfg_l), .io_pmp_1_cfg_a(csr_io_pmp_1_cfg_a), .io_pmp_1_cfg_x(csr_io_pmp_1_cfg_x), .io_pmp_1_cfg_w(csr_io_pmp_1_cfg_w), .io_pmp_1_cfg_r(csr_io_pmp_1_cfg_r), .io_pmp_1_addr(csr_io_pmp_1_addr), .io_pmp_1_mask(csr_io_pmp_1_mask), .io_pmp_2_cfg_l(csr_io_pmp_2_cfg_l), .io_pmp_2_cfg_a(csr_io_pmp_2_cfg_a), .io_pmp_2_cfg_x(csr_io_pmp_2_cfg_x), .io_pmp_2_cfg_w(csr_io_pmp_2_cfg_w), .io_pmp_2_cfg_r(csr_io_pmp_2_cfg_r), .io_pmp_2_addr(csr_io_pmp_2_addr), .io_pmp_2_mask(csr_io_pmp_2_mask), .io_pmp_3_cfg_l(csr_io_pmp_3_cfg_l), .io_pmp_3_cfg_a(csr_io_pmp_3_cfg_a), .io_pmp_3_cfg_x(csr_io_pmp_3_cfg_x), .io_pmp_3_cfg_w(csr_io_pmp_3_cfg_w), .io_pmp_3_cfg_r(csr_io_pmp_3_cfg_r), .io_pmp_3_addr(csr_io_pmp_3_addr), .io_pmp_3_mask(csr_io_pmp_3_mask), .io_pmp_4_cfg_l(csr_io_pmp_4_cfg_l), .io_pmp_4_cfg_a(csr_io_pmp_4_cfg_a), .io_pmp_4_cfg_x(csr_io_pmp_4_cfg_x), .io_pmp_4_cfg_w(csr_io_pmp_4_cfg_w), .io_pmp_4_cfg_r(csr_io_pmp_4_cfg_r), .io_pmp_4_addr(csr_io_pmp_4_addr), .io_pmp_4_mask(csr_io_pmp_4_mask), .io_pmp_5_cfg_l(csr_io_pmp_5_cfg_l), .io_pmp_5_cfg_a(csr_io_pmp_5_cfg_a), .io_pmp_5_cfg_x(csr_io_pmp_5_cfg_x), .io_pmp_5_cfg_w(csr_io_pmp_5_cfg_w), .io_pmp_5_cfg_r(csr_io_pmp_5_cfg_r), .io_pmp_5_addr(csr_io_pmp_5_addr), .io_pmp_5_mask(csr_io_pmp_5_mask), .io_pmp_6_cfg_l(csr_io_pmp_6_cfg_l), .io_pmp_6_cfg_a(csr_io_pmp_6_cfg_a), .io_pmp_6_cfg_x(csr_io_pmp_6_cfg_x), .io_pmp_6_cfg_w(csr_io_pmp_6_cfg_w), .io_pmp_6_cfg_r(csr_io_pmp_6_cfg_r), .io_pmp_6_addr(csr_io_pmp_6_addr), .io_pmp_6_mask(csr_io_pmp_6_mask), .io_pmp_7_cfg_l(csr_io_pmp_7_cfg_l), .io_pmp_7_cfg_a(csr_io_pmp_7_cfg_a), .io_pmp_7_cfg_x(csr_io_pmp_7_cfg_x), .io_pmp_7_cfg_w(csr_io_pmp_7_cfg_w), .io_pmp_7_cfg_r(csr_io_pmp_7_cfg_r), .io_pmp_7_addr(csr_io_pmp_7_addr), .io_pmp_7_mask(csr_io_pmp_7_mask), .io_inst_0(csr_io_inst_0), .io_trace_0_valid(csr_io_trace_0_valid), .io_trace_0_iaddr(csr_io_trace_0_iaddr), .io_trace_0_insn(csr_io_trace_0_insn), .io_trace_0_exception(csr_io_trace_0_exception) ); BreakpointUnit bpu ( // @[RocketCore.scala 298:19:freechips.rocketchip.system.TinyConfig.fir@124317.4] .io_status_debug(bpu_io_status_debug), .io_bp_0_control_action(bpu_io_bp_0_control_action), .io_bp_0_control_tmatch(bpu_io_bp_0_control_tmatch), .io_bp_0_control_x(bpu_io_bp_0_control_x), .io_bp_0_control_w(bpu_io_bp_0_control_w), .io_bp_0_control_r(bpu_io_bp_0_control_r), .io_bp_0_address(bpu_io_bp_0_address), .io_pc(bpu_io_pc), .io_ea(bpu_io_ea), .io_xcpt_if(bpu_io_xcpt_if), .io_xcpt_ld(bpu_io_xcpt_ld), .io_xcpt_st(bpu_io_xcpt_st), .io_debug_if(bpu_io_debug_if), .io_debug_ld(bpu_io_debug_ld), .io_debug_st(bpu_io_debug_st) ); ALU alu ( // @[RocketCore.scala 358:19:freechips.rocketchip.system.TinyConfig.fir@124467.4] .io_fn(alu_io_fn), .io_in2(alu_io_in2), .io_in1(alu_io_in1), .io_out(alu_io_out), .io_adder_out(alu_io_adder_out), .io_cmp_out(alu_io_cmp_out) ); MulDiv div ( // @[RocketCore.scala 382:19:freechips.rocketchip.system.TinyConfig.fir@124477.4] .clock(div_clock), .reset(div_reset), .io_req_ready(div_io_req_ready), .io_req_valid(div_io_req_valid), .io_req_bits_fn(div_io_req_bits_fn), .io_req_bits_in1(div_io_req_bits_in1), .io_req_bits_in2(div_io_req_bits_in2), .io_req_bits_tag(div_io_req_bits_tag), .io_kill(div_io_kill), .io_resp_ready(div_io_resp_ready), .io_resp_valid(div_io_resp_valid), .io_resp_bits_data(div_io_resp_bits_data), .io_resp_bits_tag(div_io_resp_bits_tag) ); PlusArgTimeout PlusArgTimeout ( // @[PlusArg.scala 53:11:freechips.rocketchip.system.TinyConfig.fir@125518.4] .clock(PlusArgTimeout_clock), .reset(PlusArgTimeout_reset), .io_count(PlusArgTimeout_io_count) ); assign _T_288__T_293_addr = ~ _T_291; `ifndef RANDOMIZE_GARBAGE_ASSIGN assign _T_288__T_293_data = _T_288[_T_288__T_293_addr]; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] `else assign _T_288__T_293_data = _T_288__T_293_addr >= 5'h1f ? _RAND_1[31:0] : _T_288[_T_288__T_293_addr]; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] `endif // RANDOMIZE_GARBAGE_ASSIGN assign _T_288__T_299_addr = ~ _T_297; `ifndef RANDOMIZE_GARBAGE_ASSIGN assign _T_288__T_299_data = _T_288[_T_288__T_299_addr]; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] `else assign _T_288__T_299_data = _T_288__T_299_addr >= 5'h1f ? _RAND_2[31:0] : _T_288[_T_288__T_299_addr]; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] `endif // RANDOMIZE_GARBAGE_ASSIGN assign _T_288__T_953_data = _T_944 ? io_dmem_resp_bits_data : _T_949; assign _T_288__T_953_addr = ~ rf_waddr; assign _T_288__T_953_mask = 1'h1; assign _T_288__T_953_en = rf_wen ? _T_950 : 1'h0; assign replay_wb_common = io_dmem_s2_nack | wb_reg_replay; // @[RocketCore.scala 604:42:freechips.rocketchip.system.TinyConfig.fir@125021.4] assign _T_898 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala 582:19:freechips.rocketchip.system.TinyConfig.fir@124984.4] assign _T_899 = _T_898 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala 582:34:freechips.rocketchip.system.TinyConfig.fir@124985.4] assign _T_910 = wb_reg_xcpt | _T_899; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124996.4] assign _T_901 = _T_898 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala 583:34:freechips.rocketchip.system.TinyConfig.fir@124987.4] assign _T_911 = _T_910 | _T_901; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124997.4] assign _T_903 = _T_898 & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala 584:34:freechips.rocketchip.system.TinyConfig.fir@124989.4] assign _T_912 = _T_911 | _T_903; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124998.4] assign _T_905 = _T_898 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala 585:34:freechips.rocketchip.system.TinyConfig.fir@124991.4] assign _T_913 = _T_912 | _T_905; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124999.4] assign _T_907 = _T_898 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala 586:34:freechips.rocketchip.system.TinyConfig.fir@124993.4] assign _T_914 = _T_913 | _T_907; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@125000.4] assign _T_909 = _T_898 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala 587:34:freechips.rocketchip.system.TinyConfig.fir@124995.4] assign wb_xcpt = _T_914 | _T_909; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@125001.4] assign _T_932 = replay_wb_common | wb_xcpt; // @[RocketCore.scala 607:27:freechips.rocketchip.system.TinyConfig.fir@125026.4] assign _T_933 = _T_932 | csr_io_eret; // @[RocketCore.scala 607:38:freechips.rocketchip.system.TinyConfig.fir@125027.4] assign take_pc_wb = _T_933 | wb_reg_flush_pipe; // @[RocketCore.scala 607:53:freechips.rocketchip.system.TinyConfig.fir@125028.4] assign _T_779 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala 488:40:freechips.rocketchip.system.TinyConfig.fir@124795.4] assign _T_780 = _T_779 | mem_ctrl_jalr; // @[RocketCore.scala 488:57:freechips.rocketchip.system.TinyConfig.fir@124796.4] assign mem_cfi_taken = _T_780 | mem_ctrl_jal; // @[RocketCore.scala 488:74:freechips.rocketchip.system.TinyConfig.fir@124797.4] assign take_pc_mem = mem_reg_valid & mem_cfi_taken; // @[RocketCore.scala 491:32:freechips.rocketchip.system.TinyConfig.fir@124802.4] assign take_pc_mem_wb = take_pc_wb | take_pc_mem; // @[RocketCore.scala 234:35:freechips.rocketchip.system.TinyConfig.fir@123809.4] assign _T = ibuf_io_inst_0_bits_inst_bits & 32'h505f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123818.4] assign _T_1 = _T == 32'h3; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123819.4] assign _T_2 = ibuf_io_inst_0_bits_inst_bits & 32'h207f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123820.4] assign _T_3 = _T_2 == 32'h3; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123821.4] assign _T_4 = ibuf_io_inst_0_bits_inst_bits & 32'h607f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123822.4] assign _T_5 = _T_4 == 32'hf; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123823.4] assign _T_6 = ibuf_io_inst_0_bits_inst_bits & 32'h5f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123824.4] assign _T_7 = _T_6 == 32'h17; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123825.4] assign _T_8 = ibuf_io_inst_0_bits_inst_bits & 32'hfc00007f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123826.4] assign _T_9 = _T_8 == 32'h33; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123827.4] assign _T_10 = ibuf_io_inst_0_bits_inst_bits & 32'hbe00707f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123828.4] assign _T_11 = _T_10 == 32'h33; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123829.4] assign _T_12 = ibuf_io_inst_0_bits_inst_bits & 32'h707b; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123830.4] assign _T_13 = _T_12 == 32'h63; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123831.4] assign _T_14 = ibuf_io_inst_0_bits_inst_bits & 32'h7f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123832.4] assign _T_15 = _T_14 == 32'h6f; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123833.4] assign _T_16 = ibuf_io_inst_0_bits_inst_bits & 32'hffefffff; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123834.4] assign _T_17 = _T_16 == 32'h73; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123835.4] assign _T_18 = ibuf_io_inst_0_bits_inst_bits & 32'hfe00305f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123836.4] assign _T_19 = _T_18 == 32'h1013; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123837.4] assign _T_21 = _T_2 == 32'h2013; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123839.4] assign _T_22 = ibuf_io_inst_0_bits_inst_bits & 32'h1800707f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123840.4] assign _T_23 = _T_22 == 32'h202f; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123841.4] assign _T_25 = _T_2 == 32'h2073; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123843.4] assign _T_26 = ibuf_io_inst_0_bits_inst_bits & 32'hbe00705f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123844.4] assign _T_27 = _T_26 == 32'h5013; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123845.4] assign _T_28 = ibuf_io_inst_0_bits_inst_bits & 32'he800707f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123846.4] assign _T_29 = _T_28 == 32'h800202f; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123847.4] assign _T_30 = ibuf_io_inst_0_bits_inst_bits & 32'hf9f0707f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123848.4] assign _T_31 = _T_30 == 32'h1000202f; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123849.4] assign _T_32 = ibuf_io_inst_0_bits_inst_bits & 32'hdfffffff; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123850.4] assign _T_33 = _T_32 == 32'h10500073; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123851.4] assign _T_34 = ibuf_io_inst_0_bits_inst_bits == 32'h30200073; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123852.4] assign _T_35 = ibuf_io_inst_0_bits_inst_bits == 32'h7b200073; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123853.4] assign _T_36 = ibuf_io_inst_0_bits_inst_bits & 32'h306f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123854.4] assign _T_37 = _T_36 == 32'h1063; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123855.4] assign _T_38 = ibuf_io_inst_0_bits_inst_bits & 32'h407f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123856.4] assign _T_39 = _T_38 == 32'h4063; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123857.4] assign _T_40 = ibuf_io_inst_0_bits_inst_bits & 32'h605f; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123858.4] assign _T_41 = _T_40 == 32'h3; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123859.4] assign _T_43 = _T_36 == 32'h3; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123861.4] assign _T_45 = _T_1 | _T_3; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123863.4] assign _T_46 = _T_45 | _T_5; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123864.4] assign _T_47 = _T_46 | _T_7; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123865.4] assign _T_48 = _T_47 | _T_9; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123866.4] assign _T_49 = _T_48 | _T_11; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123867.4] assign _T_50 = _T_49 | _T_13; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123868.4] assign _T_51 = _T_50 | _T_15; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123869.4] assign _T_52 = _T_51 | _T_17; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123870.4] assign _T_53 = _T_52 | _T_19; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123871.4] assign _T_54 = _T_53 | _T_21; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123872.4] assign _T_55 = _T_54 | _T_23; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123873.4] assign _T_56 = _T_55 | _T_25; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123874.4] assign _T_57 = _T_56 | _T_27; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123875.4] assign _T_58 = _T_57 | _T_29; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123876.4] assign _T_59 = _T_58 | _T_31; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123877.4] assign _T_60 = _T_59 | _T_33; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123878.4] assign _T_61 = _T_60 | _T_34; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123879.4] assign _T_62 = _T_61 | _T_35; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123880.4] assign _T_63 = _T_62 | _T_37; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123881.4] assign _T_64 = _T_63 | _T_39; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123882.4] assign _T_65 = _T_64 | _T_41; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123883.4] assign id_ctrl_legal = _T_65 | _T_43; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123884.4] assign _T_67 = ibuf_io_inst_0_bits_inst_bits & 32'h54; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123885.4] assign id_ctrl_branch = _T_67 == 32'h40; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123886.4] assign _T_70 = ibuf_io_inst_0_bits_inst_bits & 32'h48; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123888.4] assign id_ctrl_jal = _T_70 == 32'h48; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123889.4] assign _T_73 = ibuf_io_inst_0_bits_inst_bits & 32'h1c; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123891.4] assign id_ctrl_jalr = _T_73 == 32'h4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123892.4] assign _T_76 = ibuf_io_inst_0_bits_inst_bits & 32'h70; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123894.4] assign _T_77 = _T_76 == 32'h20; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123895.4] assign _T_78 = ibuf_io_inst_0_bits_inst_bits & 32'h64; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123896.4] assign _T_79 = _T_78 == 32'h20; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123897.4] assign _T_80 = ibuf_io_inst_0_bits_inst_bits & 32'h34; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123898.4] assign _T_81 = _T_80 == 32'h20; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123899.4] assign _T_83 = _T_77 | _T_79; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123901.4] assign id_ctrl_rxs2 = _T_83 | _T_81; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123902.4] assign _T_85 = ibuf_io_inst_0_bits_inst_bits & 32'h4004; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123903.4] assign _T_86 = _T_85 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123904.4] assign _T_87 = ibuf_io_inst_0_bits_inst_bits & 32'h44; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123905.4] assign _T_88 = _T_87 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123906.4] assign _T_89 = ibuf_io_inst_0_bits_inst_bits & 32'h18; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123907.4] assign _T_90 = _T_89 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123908.4] assign _T_91 = ibuf_io_inst_0_bits_inst_bits & 32'h2050; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123909.4] assign _T_92 = _T_91 == 32'h2000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123910.4] assign _T_94 = _T_86 | _T_88; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123912.4] assign _T_95 = _T_94 | _T_90; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123913.4] assign id_ctrl_rxs1 = _T_95 | _T_92; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123914.4] assign _T_97 = ibuf_io_inst_0_bits_inst_bits & 32'h58; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123915.4] assign _T_98 = _T_97 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123916.4] assign _T_99 = ibuf_io_inst_0_bits_inst_bits & 32'h20; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123917.4] assign _T_100 = _T_99 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123918.4] assign _T_101 = ibuf_io_inst_0_bits_inst_bits & 32'hc; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123919.4] assign _T_102 = _T_101 == 32'h4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123920.4] assign _T_103 = ibuf_io_inst_0_bits_inst_bits & 32'h4050; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123921.4] assign _T_104 = _T_103 == 32'h4050; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123922.4] assign _T_106 = _T_98 | _T_100; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123924.4] assign _T_107 = _T_106 | _T_102; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123925.4] assign _T_108 = _T_107 | id_ctrl_jal; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123926.4] assign _T_109 = _T_108 | _T_104; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123927.4] assign _T_111 = _T_70 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123929.4] assign _T_112 = ibuf_io_inst_0_bits_inst_bits & 32'h4008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123930.4] assign _T_113 = _T_112 == 32'h4000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123931.4] assign _T_115 = _T_111 | _T_90; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123933.4] assign _T_116 = _T_115 | _T_113; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123934.4] assign id_ctrl_sel_alu2 = {_T_116,_T_109}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123935.4] assign _T_118 = ibuf_io_inst_0_bits_inst_bits & 32'h50; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123936.4] assign _T_119 = _T_118 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123937.4] assign _T_121 = _T_86 | _T_119; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123939.4] assign _T_122 = _T_121 | _T_88; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123940.4] assign _T_123 = _T_122 | _T_90; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123941.4] assign _T_124 = ibuf_io_inst_0_bits_inst_bits & 32'h24; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123942.4] assign _T_125 = _T_124 == 32'h4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123943.4] assign _T_127 = _T_125 | id_ctrl_jal; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123945.4] assign id_ctrl_sel_alu1 = {_T_127,_T_123}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123946.4] assign _T_129 = ibuf_io_inst_0_bits_inst_bits & 32'h8; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123947.4] assign _T_130 = _T_129 == 32'h8; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123948.4] assign _T_132 = _T_87 == 32'h40; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123950.4] assign _T_134 = _T_130 | _T_132; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123952.4] assign _T_136 = _T_87 == 32'h4; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123954.4] assign _T_138 = _T_136 | _T_130; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123956.4] assign _T_139 = ibuf_io_inst_0_bits_inst_bits & 32'h14; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123957.4] assign _T_140 = _T_139 == 32'h10; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123958.4] assign _T_141 = ibuf_io_inst_0_bits_inst_bits & 32'h30; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123959.4] assign _T_142 = _T_141 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123960.4] assign _T_144 = id_ctrl_jalr | _T_140; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123962.4] assign _T_145 = _T_144 | _T_142; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123963.4] assign id_ctrl_sel_imm = {_T_145,_T_138,_T_134}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@123965.4] assign _T_151 = ibuf_io_inst_0_bits_inst_bits & 32'h3054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123969.4] assign _T_152 = _T_151 == 32'h1010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123970.4] assign _T_153 = ibuf_io_inst_0_bits_inst_bits & 32'h1058; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123971.4] assign _T_154 = _T_153 == 32'h1040; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123972.4] assign _T_155 = ibuf_io_inst_0_bits_inst_bits & 32'h7044; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123973.4] assign _T_156 = _T_155 == 32'h7000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123974.4] assign _T_157 = ibuf_io_inst_0_bits_inst_bits & 32'h2001074; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123975.4] assign _T_158 = _T_157 == 32'h2001030; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123976.4] assign _T_160 = _T_152 | _T_154; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123978.4] assign _T_161 = _T_160 | _T_156; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123979.4] assign _T_162 = _T_161 | _T_158; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123980.4] assign _T_163 = ibuf_io_inst_0_bits_inst_bits & 32'h4054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123981.4] assign _T_164 = _T_163 == 32'h40; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123982.4] assign _T_165 = ibuf_io_inst_0_bits_inst_bits & 32'h3044; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123983.4] assign _T_166 = _T_165 == 32'h3000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123984.4] assign _T_167 = ibuf_io_inst_0_bits_inst_bits & 32'h6044; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123985.4] assign _T_168 = _T_167 == 32'h6000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123986.4] assign _T_169 = ibuf_io_inst_0_bits_inst_bits & 32'h6018; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123987.4] assign _T_170 = _T_169 == 32'h6000; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123988.4] assign _T_171 = ibuf_io_inst_0_bits_inst_bits & 32'h2002074; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123989.4] assign _T_172 = _T_171 == 32'h2002030; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123990.4] assign _T_173 = ibuf_io_inst_0_bits_inst_bits & 32'h40003034; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123991.4] assign _T_174 = _T_173 == 32'h40000030; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123992.4] assign _T_175 = ibuf_io_inst_0_bits_inst_bits & 32'h40001054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@123993.4] assign _T_176 = _T_175 == 32'h40001010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@123994.4] assign _T_178 = _T_164 | _T_166; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123996.4] assign _T_179 = _T_178 | _T_168; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123997.4] assign _T_180 = _T_179 | _T_170; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123998.4] assign _T_181 = _T_180 | _T_172; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@123999.4] assign _T_182 = _T_181 | _T_174; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124000.4] assign _T_183 = _T_182 | _T_176; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124001.4] assign _T_184 = ibuf_io_inst_0_bits_inst_bits & 32'h2002054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124002.4] assign _T_185 = _T_184 == 32'h2010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124003.4] assign _T_186 = ibuf_io_inst_0_bits_inst_bits & 32'h2034; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124004.4] assign _T_187 = _T_186 == 32'h2010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124005.4] assign _T_188 = ibuf_io_inst_0_bits_inst_bits & 32'h40004054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124006.4] assign _T_189 = _T_188 == 32'h4010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124007.4] assign _T_190 = ibuf_io_inst_0_bits_inst_bits & 32'h5054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124008.4] assign _T_191 = _T_190 == 32'h4010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124009.4] assign _T_192 = ibuf_io_inst_0_bits_inst_bits & 32'h4058; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124010.4] assign _T_193 = _T_192 == 32'h4040; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124011.4] assign _T_195 = _T_185 | _T_187; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124013.4] assign _T_196 = _T_195 | _T_189; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124014.4] assign _T_197 = _T_196 | _T_191; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124015.4] assign _T_198 = _T_197 | _T_193; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124016.4] assign _T_199 = ibuf_io_inst_0_bits_inst_bits & 32'h2006054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124017.4] assign _T_200 = _T_199 == 32'h2010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124018.4] assign _T_201 = ibuf_io_inst_0_bits_inst_bits & 32'h6034; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124019.4] assign _T_202 = _T_201 == 32'h2010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124020.4] assign _T_203 = ibuf_io_inst_0_bits_inst_bits & 32'h40003054; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124021.4] assign _T_204 = _T_203 == 32'h40001010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124022.4] assign _T_206 = _T_200 | _T_202; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124024.4] assign _T_207 = _T_206 | _T_193; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124025.4] assign _T_208 = _T_207 | _T_174; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124026.4] assign _T_209 = _T_208 | _T_204; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124027.4] assign id_ctrl_alu_fn = {_T_209,_T_198,_T_183,_T_162}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124030.4] assign _T_214 = _T_41 | _T_1; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124032.4] assign _T_215 = _T_214 | _T_3; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124033.4] assign _T_216 = _T_215 | _T_23; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124034.4] assign _T_217 = _T_216 | _T_29; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124035.4] assign id_ctrl_mem = _T_217 | _T_31; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124036.4] assign _T_219 = ibuf_io_inst_0_bits_inst_bits & 32'h28; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124037.4] assign _T_220 = _T_219 == 32'h20; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124038.4] assign _T_221 = ibuf_io_inst_0_bits_inst_bits & 32'h18000020; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124039.4] assign _T_222 = _T_221 == 32'h18000020; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124040.4] assign _T_223 = ibuf_io_inst_0_bits_inst_bits & 32'h20000020; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124041.4] assign _T_224 = _T_223 == 32'h20000020; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124042.4] assign _T_226 = _T_220 | _T_222; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124044.4] assign _T_227 = _T_226 | _T_224; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124045.4] assign _T_228 = ibuf_io_inst_0_bits_inst_bits & 32'h10000008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124046.4] assign _T_229 = _T_228 == 32'h10000008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124047.4] assign _T_230 = ibuf_io_inst_0_bits_inst_bits & 32'h40000008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124048.4] assign _T_231 = _T_230 == 32'h40000008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124049.4] assign _T_233 = _T_229 | _T_231; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124051.4] assign _T_234 = ibuf_io_inst_0_bits_inst_bits & 32'h8000008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124052.4] assign _T_235 = _T_234 == 32'h8000008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124053.4] assign _T_236 = ibuf_io_inst_0_bits_inst_bits & 32'h80000008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124054.4] assign _T_237 = _T_236 == 32'h80000008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124055.4] assign _T_239 = _T_235 | _T_229; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124057.4] assign _T_240 = _T_239 | _T_237; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124058.4] assign _T_241 = ibuf_io_inst_0_bits_inst_bits & 32'h18000008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124059.4] assign _T_242 = _T_241 == 32'h8; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124060.4] assign id_ctrl_mem_cmd = {1'h0,_T_242,_T_240,_T_233,_T_227}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124065.4] assign _T_248 = ibuf_io_inst_0_bits_inst_bits & 32'h2000074; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124066.4] assign id_ctrl_div = _T_248 == 32'h2000030; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124067.4] assign _T_252 = _T_219 == 32'h0; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124070.4] assign _T_254 = _T_118 == 32'h10; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124072.4] assign _T_255 = ibuf_io_inst_0_bits_inst_bits & 32'h1010; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124073.4] assign _T_256 = _T_255 == 32'h1010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124074.4] assign _T_257 = ibuf_io_inst_0_bits_inst_bits & 32'h2008; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124075.4] assign _T_258 = _T_257 == 32'h2008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124076.4] assign _T_259 = ibuf_io_inst_0_bits_inst_bits & 32'h2010; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124077.4] assign _T_260 = _T_259 == 32'h2010; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124078.4] assign _T_262 = _T_252 | _T_102; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124080.4] assign _T_263 = _T_262 | _T_254; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124081.4] assign _T_264 = _T_263 | id_ctrl_jal; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124082.4] assign _T_265 = _T_264 | _T_256; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124083.4] assign _T_266 = _T_265 | _T_258; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124084.4] assign id_ctrl_wxd = _T_266 | _T_260; // @[Decode.scala 15:30:freechips.rocketchip.system.TinyConfig.fir@124085.4] assign _T_268 = ibuf_io_inst_0_bits_inst_bits & 32'h1050; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124086.4] assign _T_269 = _T_268 == 32'h1050; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124087.4] assign _T_272 = _T_91 == 32'h2050; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124090.4] assign _T_275 = _T_118 == 32'h50; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124093.4] assign id_ctrl_csr = {_T_275,_T_272,_T_269}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124096.4] assign _T_279 = ibuf_io_inst_0_bits_inst_bits & 32'h1048; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124097.4] assign id_ctrl_fence_i = _T_279 == 32'h1008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124098.4] assign _T_282 = ibuf_io_inst_0_bits_inst_bits & 32'h2048; // @[Decode.scala 14:65:freechips.rocketchip.system.TinyConfig.fir@124100.4] assign id_ctrl_fence = _T_282 == 32'h8; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124101.4] assign id_ctrl_amo = _T_282 == 32'h2008; // @[Decode.scala 14:121:freechips.rocketchip.system.TinyConfig.fir@124104.4] assign _T_289 = ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala 950:45:freechips.rocketchip.system.TinyConfig.fir@124140.4] assign _T_291 = ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 944:44:freechips.rocketchip.system.TinyConfig.fir@124142.4] assign _T_294 = _T_288__T_293_data; // @[RocketCore.scala 950:25:freechips.rocketchip.system.TinyConfig.fir@124145.4] assign _T_297 = ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 944:44:freechips.rocketchip.system.TinyConfig.fir@124151.4] assign _T_300 = _T_288__T_299_data; // @[RocketCore.scala 950:25:freechips.rocketchip.system.TinyConfig.fir@124154.4] assign _T_367 = id_ctrl_csr == 3'h6; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124229.4] assign _T_368 = id_ctrl_csr == 3'h7; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124230.4] assign _T_369 = id_ctrl_csr == 3'h5; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124231.4] assign _T_370 = _T_367 | _T_368; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124232.4] assign id_csr_en = _T_370 | _T_369; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124233.4] assign id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala 262:36:freechips.rocketchip.system.TinyConfig.fir@124234.4] assign id_csr_ren = _T_370 & _T_289; // @[RocketCore.scala 263:54:freechips.rocketchip.system.TinyConfig.fir@124239.4] assign _T_375 = id_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala 265:50:freechips.rocketchip.system.TinyConfig.fir@124241.4] assign id_sfence = id_ctrl_mem & _T_375; // @[RocketCore.scala 265:31:freechips.rocketchip.system.TinyConfig.fir@124242.4] assign _T_376 = id_sfence | id_system_insn; // @[RocketCore.scala 266:32:freechips.rocketchip.system.TinyConfig.fir@124243.4] assign _T_377 = id_csr_ren == 1'h0; // @[RocketCore.scala 266:67:freechips.rocketchip.system.TinyConfig.fir@124244.4] assign _T_378 = id_csr_en & _T_377; // @[RocketCore.scala 266:64:freechips.rocketchip.system.TinyConfig.fir@124245.4] assign _T_379 = _T_378 & csr_io_decode_0_write_flush; // @[RocketCore.scala 266:79:freechips.rocketchip.system.TinyConfig.fir@124246.4] assign id_csr_flush = _T_376 | _T_379; // @[RocketCore.scala 266:50:freechips.rocketchip.system.TinyConfig.fir@124247.4] assign _T_380 = id_ctrl_legal == 1'h0; // @[RocketCore.scala 274:25:freechips.rocketchip.system.TinyConfig.fir@124250.4] assign _T_382 = csr_io_status_isa[12]; // @[RocketCore.scala 275:55:freechips.rocketchip.system.TinyConfig.fir@124252.4] assign _T_383 = _T_382 == 1'h0; // @[RocketCore.scala 275:37:freechips.rocketchip.system.TinyConfig.fir@124253.4] assign _T_384 = id_ctrl_div & _T_383; // @[RocketCore.scala 275:34:freechips.rocketchip.system.TinyConfig.fir@124254.4] assign _T_385 = _T_380 | _T_384; // @[RocketCore.scala 274:40:freechips.rocketchip.system.TinyConfig.fir@124255.4] assign _T_386 = csr_io_status_isa[0]; // @[RocketCore.scala 276:38:freechips.rocketchip.system.TinyConfig.fir@124256.4] assign _T_387 = _T_386 == 1'h0; // @[RocketCore.scala 276:20:freechips.rocketchip.system.TinyConfig.fir@124257.4] assign _T_388 = id_ctrl_amo & _T_387; // @[RocketCore.scala 276:17:freechips.rocketchip.system.TinyConfig.fir@124258.4] assign _T_389 = _T_385 | _T_388; // @[RocketCore.scala 275:65:freechips.rocketchip.system.TinyConfig.fir@124259.4] assign _T_397 = csr_io_status_isa[2]; // @[RocketCore.scala 279:51:freechips.rocketchip.system.TinyConfig.fir@124267.4] assign _T_398 = _T_397 == 1'h0; // @[RocketCore.scala 279:33:freechips.rocketchip.system.TinyConfig.fir@124268.4] assign _T_399 = ibuf_io_inst_0_bits_rvc & _T_398; // @[RocketCore.scala 279:30:freechips.rocketchip.system.TinyConfig.fir@124269.4] assign _T_400 = _T_389 | _T_399; // @[RocketCore.scala 278:47:freechips.rocketchip.system.TinyConfig.fir@124270.4] assign _T_408 = _T_377 & csr_io_decode_0_write_illegal; // @[RocketCore.scala 282:64:freechips.rocketchip.system.TinyConfig.fir@124278.4] assign _T_409 = csr_io_decode_0_read_illegal | _T_408; // @[RocketCore.scala 282:49:freechips.rocketchip.system.TinyConfig.fir@124279.4] assign _T_410 = id_csr_en & _T_409; // @[RocketCore.scala 282:15:freechips.rocketchip.system.TinyConfig.fir@124280.4] assign id_illegal_insn = _T_400 | _T_410; // @[RocketCore.scala 281:81:freechips.rocketchip.system.TinyConfig.fir@124281.4] assign id_amo_aq = ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala 285:29:freechips.rocketchip.system.TinyConfig.fir@124287.4] assign id_amo_rl = ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala 286:29:freechips.rocketchip.system.TinyConfig.fir@124288.4] assign id_fence_succ = ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala 288:33:freechips.rocketchip.system.TinyConfig.fir@124290.4] assign _T_416 = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala 289:52:freechips.rocketchip.system.TinyConfig.fir@124291.4] assign id_fence_next = id_ctrl_fence | _T_416; // @[RocketCore.scala 289:37:freechips.rocketchip.system.TinyConfig.fir@124292.4] assign _T_417 = io_dmem_ordered == 1'h0; // @[RocketCore.scala 290:21:freechips.rocketchip.system.TinyConfig.fir@124293.4] assign id_mem_busy = _T_417 | io_dmem_req_valid; // @[RocketCore.scala 290:38:freechips.rocketchip.system.TinyConfig.fir@124294.4] assign _T_418 = id_mem_busy == 1'h0; // @[RocketCore.scala 291:9:freechips.rocketchip.system.TinyConfig.fir@124295.4] assign _T_426 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala 296:33:freechips.rocketchip.system.TinyConfig.fir@124307.4] assign _T_427 = _T_426 | id_ctrl_fence_i; // @[RocketCore.scala 296:46:freechips.rocketchip.system.TinyConfig.fir@124308.4] assign _T_429 = id_reg_fence & id_ctrl_mem; // @[RocketCore.scala 296:81:freechips.rocketchip.system.TinyConfig.fir@124310.4] assign _T_430 = _T_427 | _T_429; // @[RocketCore.scala 296:65:freechips.rocketchip.system.TinyConfig.fir@124311.4] assign id_do_fence = id_mem_busy & _T_430; // @[RocketCore.scala 296:17:freechips.rocketchip.system.TinyConfig.fir@124312.4] assign _T_433 = csr_io_interrupt | bpu_io_debug_if; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124325.4] assign _T_434 = _T_433 | bpu_io_xcpt_if; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124326.4] assign _T_436 = _T_434 | ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124328.4] assign _T_437 = _T_436 | ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124329.4] assign _T_438 = _T_437 | ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124330.4] assign id_xcpt = _T_438 | id_illegal_insn; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124331.4] assign _T_439 = ibuf_io_inst_0_bits_xcpt1_ae_inst ? 2'h1 : 2'h2; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124332.4] assign _T_440 = ibuf_io_inst_0_bits_xcpt1_pf_inst ? 4'hc : {{2'd0}, _T_439}; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124333.4] assign _T_441 = ibuf_io_inst_0_bits_xcpt0_ae_inst ? 4'h1 : _T_440; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124334.4] assign _T_443 = bpu_io_xcpt_if ? 4'h3 : _T_441; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124336.4] assign _T_444 = bpu_io_debug_if ? 4'he : _T_443; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124337.4] assign ex_waddr = ex_reg_inst[11:7]; // @[RocketCore.scala 332:29:freechips.rocketchip.system.TinyConfig.fir@124348.4] assign mem_waddr = mem_reg_inst[11:7]; // @[RocketCore.scala 333:31:freechips.rocketchip.system.TinyConfig.fir@124349.4] assign wb_waddr = wb_reg_inst[11:7]; // @[RocketCore.scala 334:29:freechips.rocketchip.system.TinyConfig.fir@124350.4] assign _T_453 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala 337:19:freechips.rocketchip.system.TinyConfig.fir@124351.4] assign _T_454 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala 338:20:freechips.rocketchip.system.TinyConfig.fir@124352.4] assign _T_455 = mem_ctrl_mem == 1'h0; // @[RocketCore.scala 338:39:freechips.rocketchip.system.TinyConfig.fir@124353.4] assign _T_456 = _T_454 & _T_455; // @[RocketCore.scala 338:36:freechips.rocketchip.system.TinyConfig.fir@124354.4] assign id_bypass_src_0_0 = 5'h0 == ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124356.4] assign _T_459 = ex_waddr == ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124358.4] assign id_bypass_src_0_1 = _T_453 & _T_459; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124359.4] assign _T_460 = mem_waddr == ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124360.4] assign id_bypass_src_0_2 = _T_456 & _T_460; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124361.4] assign id_bypass_src_0_3 = _T_454 & _T_460; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124363.4] assign id_bypass_src_1_0 = 5'h0 == ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124364.4] assign _T_463 = ex_waddr == ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124366.4] assign id_bypass_src_1_1 = _T_453 & _T_463; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124367.4] assign _T_464 = mem_waddr == ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 340:82:freechips.rocketchip.system.TinyConfig.fir@124368.4] assign id_bypass_src_1_2 = _T_456 & _T_464; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124369.4] assign id_bypass_src_1_3 = _T_454 & _T_464; // @[RocketCore.scala 340:74:freechips.rocketchip.system.TinyConfig.fir@124371.4] assign _T_466 = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124375.4] assign _T_467 = _T_466 ? mem_reg_wdata : 32'h0; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124376.4] assign _T_468 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124377.4] assign _T_469 = _T_468 ? wb_reg_wdata : _T_467; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124378.4] assign _T_470 = ex_reg_rs_lsb_0 == 2'h3; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124379.4] assign _T_471 = _T_470 ? io_dmem_resp_bits_data_word_bypass : _T_469; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124380.4] assign _T_472 = {ex_reg_rs_msb_0,ex_reg_rs_lsb_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124381.4] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _T_471 : _T_472; // @[RocketCore.scala 348:14:freechips.rocketchip.system.TinyConfig.fir@124382.4] assign _T_473 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124383.4] assign _T_474 = _T_473 ? mem_reg_wdata : 32'h0; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124384.4] assign _T_475 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124385.4] assign _T_476 = _T_475 ? wb_reg_wdata : _T_474; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124386.4] assign _T_477 = ex_reg_rs_lsb_1 == 2'h3; // @[package.scala 32:81:freechips.rocketchip.system.TinyConfig.fir@124387.4] assign _T_478 = _T_477 ? io_dmem_resp_bits_data_word_bypass : _T_476; // @[package.scala 32:71:freechips.rocketchip.system.TinyConfig.fir@124388.4] assign _T_479 = {ex_reg_rs_msb_1,ex_reg_rs_lsb_1}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124389.4] assign ex_rs_1 = ex_reg_rs_bypass_1 ? _T_478 : _T_479; // @[RocketCore.scala 348:14:freechips.rocketchip.system.TinyConfig.fir@124390.4] assign _T_480 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala 965:24:freechips.rocketchip.system.TinyConfig.fir@124391.4] assign _T_481 = ex_reg_inst[31]; // @[RocketCore.scala 965:48:freechips.rocketchip.system.TinyConfig.fir@124392.4] assign _T_482 = $signed(_T_481); // @[RocketCore.scala 965:53:freechips.rocketchip.system.TinyConfig.fir@124393.4] assign _T_483 = _T_480 ? $signed(1'sh0) : $signed(_T_482); // @[RocketCore.scala 965:19:freechips.rocketchip.system.TinyConfig.fir@124394.4] assign _T_484 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala 966:26:freechips.rocketchip.system.TinyConfig.fir@124395.4] assign _T_485 = ex_reg_inst[30:20]; // @[RocketCore.scala 966:41:freechips.rocketchip.system.TinyConfig.fir@124396.4] assign _T_486 = $signed(_T_485); // @[RocketCore.scala 966:49:freechips.rocketchip.system.TinyConfig.fir@124397.4] assign _T_487 = _T_484 ? $signed(_T_486) : $signed({11{_T_483}}); // @[RocketCore.scala 966:21:freechips.rocketchip.system.TinyConfig.fir@124398.4] assign _T_488 = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala 967:26:freechips.rocketchip.system.TinyConfig.fir@124399.4] assign _T_489 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala 967:43:freechips.rocketchip.system.TinyConfig.fir@124400.4] assign _T_490 = _T_488 & _T_489; // @[RocketCore.scala 967:36:freechips.rocketchip.system.TinyConfig.fir@124401.4] assign _T_491 = ex_reg_inst[19:12]; // @[RocketCore.scala 967:65:freechips.rocketchip.system.TinyConfig.fir@124402.4] assign _T_492 = $signed(_T_491); // @[RocketCore.scala 967:73:freechips.rocketchip.system.TinyConfig.fir@124403.4] assign _T_493 = _T_490 ? $signed({8{_T_483}}) : $signed(_T_492); // @[RocketCore.scala 967:21:freechips.rocketchip.system.TinyConfig.fir@124404.4] assign _T_496 = _T_484 | _T_480; // @[RocketCore.scala 968:33:freechips.rocketchip.system.TinyConfig.fir@124407.4] assign _T_497 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala 969:23:freechips.rocketchip.system.TinyConfig.fir@124408.4] assign _T_498 = ex_reg_inst[20]; // @[RocketCore.scala 969:39:freechips.rocketchip.system.TinyConfig.fir@124409.4] assign _T_499 = $signed(_T_498); // @[RocketCore.scala 969:44:freechips.rocketchip.system.TinyConfig.fir@124410.4] assign _T_500 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala 970:23:freechips.rocketchip.system.TinyConfig.fir@124411.4] assign _T_501 = ex_reg_inst[7]; // @[RocketCore.scala 970:39:freechips.rocketchip.system.TinyConfig.fir@124412.4] assign _T_502 = $signed(_T_501); // @[RocketCore.scala 970:43:freechips.rocketchip.system.TinyConfig.fir@124413.4] assign _T_503 = _T_500 ? $signed(_T_502) : $signed(_T_483); // @[RocketCore.scala 970:18:freechips.rocketchip.system.TinyConfig.fir@124414.4] assign _T_504 = _T_497 ? $signed(_T_499) : $signed(_T_503); // @[RocketCore.scala 969:18:freechips.rocketchip.system.TinyConfig.fir@124415.4] assign _T_505 = _T_496 ? $signed(1'sh0) : $signed(_T_504); // @[RocketCore.scala 968:18:freechips.rocketchip.system.TinyConfig.fir@124416.4] assign _T_509 = ex_reg_inst[30:25]; // @[RocketCore.scala 971:66:freechips.rocketchip.system.TinyConfig.fir@124420.4] assign _T_510 = _T_496 ? 6'h0 : _T_509; // @[RocketCore.scala 971:20:freechips.rocketchip.system.TinyConfig.fir@124421.4] assign _T_512 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala 973:24:freechips.rocketchip.system.TinyConfig.fir@124423.4] assign _T_514 = _T_512 | _T_500; // @[RocketCore.scala 973:34:freechips.rocketchip.system.TinyConfig.fir@124425.4] assign _T_515 = ex_reg_inst[11:8]; // @[RocketCore.scala 973:57:freechips.rocketchip.system.TinyConfig.fir@124426.4] assign _T_517 = ex_reg_inst[19:16]; // @[RocketCore.scala 974:39:freechips.rocketchip.system.TinyConfig.fir@124428.4] assign _T_518 = ex_reg_inst[24:21]; // @[RocketCore.scala 974:52:freechips.rocketchip.system.TinyConfig.fir@124429.4] assign _T_519 = _T_480 ? _T_517 : _T_518; // @[RocketCore.scala 974:19:freechips.rocketchip.system.TinyConfig.fir@124430.4] assign _T_520 = _T_514 ? _T_515 : _T_519; // @[RocketCore.scala 973:19:freechips.rocketchip.system.TinyConfig.fir@124431.4] assign _T_521 = _T_484 ? 4'h0 : _T_520; // @[RocketCore.scala 972:19:freechips.rocketchip.system.TinyConfig.fir@124432.4] assign _T_524 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala 976:22:freechips.rocketchip.system.TinyConfig.fir@124435.4] assign _T_527 = ex_reg_inst[15]; // @[RocketCore.scala 977:37:freechips.rocketchip.system.TinyConfig.fir@124438.4] assign _T_528 = _T_480 ? _T_527 : 1'h0; // @[RocketCore.scala 977:17:freechips.rocketchip.system.TinyConfig.fir@124439.4] assign _T_529 = _T_524 ? _T_498 : _T_528; // @[RocketCore.scala 976:17:freechips.rocketchip.system.TinyConfig.fir@124440.4] assign _T_530 = _T_512 ? _T_501 : _T_529; // @[RocketCore.scala 975:17:freechips.rocketchip.system.TinyConfig.fir@124441.4] assign _T_533 = $unsigned(_T_505); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124444.4] assign _T_534 = $unsigned(_T_493); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124445.4] assign _T_536 = $unsigned(_T_487); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124447.4] assign _T_537 = $unsigned(_T_483); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124448.4] assign _T_540 = {_T_537,_T_536,_T_534,_T_533,_T_510,_T_521,_T_530}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124451.4] assign ex_imm = $signed(_T_540); // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124452.4] assign _T_541 = $signed(ex_rs_0); // @[RocketCore.scala 351:24:freechips.rocketchip.system.TinyConfig.fir@124453.4] assign _T_542 = $signed(ex_reg_pc); // @[RocketCore.scala 352:24:freechips.rocketchip.system.TinyConfig.fir@124454.4] assign _T_543 = 2'h2 == ex_ctrl_sel_alu1; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124455.4] assign _T_544 = _T_543 ? $signed(_T_542) : $signed(32'sh0); // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124456.4] assign _T_545 = 2'h1 == ex_ctrl_sel_alu1; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124457.4] assign ex_op1 = _T_545 ? $signed(_T_541) : $signed(_T_544); // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124458.4] assign _T_546 = $signed(ex_rs_1); // @[RocketCore.scala 354:24:freechips.rocketchip.system.TinyConfig.fir@124459.4] assign _T_547 = ex_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 356:19:freechips.rocketchip.system.TinyConfig.fir@124460.4] assign _T_548 = 2'h1 == ex_ctrl_sel_alu2; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124461.4] assign _T_549 = _T_548 ? $signed(_T_547) : $signed(4'sh0); // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124462.4] assign _T_550 = 2'h3 == ex_ctrl_sel_alu2; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124463.4] assign _T_551 = _T_550 ? $signed(ex_imm) : $signed({{28{_T_549[3]}},_T_549}); // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124464.4] assign _T_552 = 2'h2 == ex_ctrl_sel_alu2; // @[Mux.scala 69:19:freechips.rocketchip.system.TinyConfig.fir@124465.4] assign ex_op2 = _T_552 ? $signed(_T_546) : $signed(_T_551); // @[Mux.scala 69:16:freechips.rocketchip.system.TinyConfig.fir@124466.4] assign _T_1147 = ibuf_io_inst_0_valid == 1'h0; // @[RocketCore.scala 745:17:freechips.rocketchip.system.TinyConfig.fir@125330.4] assign _T_1148 = _T_1147 | ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 745:40:freechips.rocketchip.system.TinyConfig.fir@125331.4] assign _T_1149 = _T_1148 | take_pc_mem_wb; // @[RocketCore.scala 745:71:freechips.rocketchip.system.TinyConfig.fir@125332.4] assign _T_987 = ibuf_io_inst_0_bits_inst_rs1 != 5'h0; // @[RocketCore.scala 676:55:freechips.rocketchip.system.TinyConfig.fir@125144.4] assign _T_988 = id_ctrl_rxs1 & _T_987; // @[RocketCore.scala 676:42:freechips.rocketchip.system.TinyConfig.fir@125145.4] assign _T_1035 = ibuf_io_inst_0_bits_inst_rs1 == ex_waddr; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125200.4] assign _T_1036 = _T_988 & _T_1035; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125201.4] assign _T_989 = ibuf_io_inst_0_bits_inst_rs2 != 5'h0; // @[RocketCore.scala 677:55:freechips.rocketchip.system.TinyConfig.fir@125146.4] assign _T_990 = id_ctrl_rxs2 & _T_989; // @[RocketCore.scala 677:42:freechips.rocketchip.system.TinyConfig.fir@125147.4] assign _T_1037 = ibuf_io_inst_0_bits_inst_rs2 == ex_waddr; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125202.4] assign _T_1038 = _T_990 & _T_1037; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125203.4] assign _T_1041 = _T_1036 | _T_1038; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125206.4] assign _T_991 = ibuf_io_inst_0_bits_inst_rd != 5'h0; // @[RocketCore.scala 678:55:freechips.rocketchip.system.TinyConfig.fir@125148.4] assign _T_992 = id_ctrl_wxd & _T_991; // @[RocketCore.scala 678:42:freechips.rocketchip.system.TinyConfig.fir@125149.4] assign _T_1039 = ibuf_io_inst_0_bits_inst_rd == ex_waddr; // @[RocketCore.scala 696:70:freechips.rocketchip.system.TinyConfig.fir@125204.4] assign _T_1040 = _T_992 & _T_1039; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125205.4] assign _T_1042 = _T_1041 | _T_1040; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125207.4] assign data_hazard_ex = ex_ctrl_wxd & _T_1042; // @[RocketCore.scala 696:36:freechips.rocketchip.system.TinyConfig.fir@125208.4] assign _T_1028 = ex_ctrl_csr != 3'h0; // @[RocketCore.scala 695:38:freechips.rocketchip.system.TinyConfig.fir@125192.4] assign _T_1029 = _T_1028 | ex_ctrl_jalr; // @[RocketCore.scala 695:48:freechips.rocketchip.system.TinyConfig.fir@125193.4] assign _T_1030 = _T_1029 | ex_ctrl_mem; // @[RocketCore.scala 695:64:freechips.rocketchip.system.TinyConfig.fir@125194.4] assign ex_cannot_bypass = _T_1030 | ex_ctrl_div; // @[RocketCore.scala 695:94:freechips.rocketchip.system.TinyConfig.fir@125196.4] assign _T_1054 = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala 698:54:freechips.rocketchip.system.TinyConfig.fir@125221.4] assign id_ex_hazard = ex_reg_valid & _T_1054; // @[RocketCore.scala 698:35:freechips.rocketchip.system.TinyConfig.fir@125223.4] assign _T_1062 = ibuf_io_inst_0_bits_inst_rs1 == mem_waddr; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125232.4] assign _T_1063 = _T_988 & _T_1062; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125233.4] assign _T_1064 = ibuf_io_inst_0_bits_inst_rs2 == mem_waddr; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125234.4] assign _T_1065 = _T_990 & _T_1064; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125235.4] assign _T_1068 = _T_1063 | _T_1065; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125238.4] assign _T_1066 = ibuf_io_inst_0_bits_inst_rd == mem_waddr; // @[RocketCore.scala 705:72:freechips.rocketchip.system.TinyConfig.fir@125236.4] assign _T_1067 = _T_992 & _T_1066; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125237.4] assign _T_1069 = _T_1068 | _T_1067; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125239.4] assign data_hazard_mem = mem_ctrl_wxd & _T_1069; // @[RocketCore.scala 705:38:freechips.rocketchip.system.TinyConfig.fir@125240.4] assign _T_1056 = mem_ctrl_csr != 3'h0; // @[RocketCore.scala 704:40:freechips.rocketchip.system.TinyConfig.fir@125225.4] assign _T_1057 = mem_ctrl_mem & mem_reg_slow_bypass; // @[RocketCore.scala 704:66:freechips.rocketchip.system.TinyConfig.fir@125226.4] assign _T_1058 = _T_1056 | _T_1057; // @[RocketCore.scala 704:50:freechips.rocketchip.system.TinyConfig.fir@125227.4] assign mem_cannot_bypass = _T_1058 | mem_ctrl_div; // @[RocketCore.scala 704:100:freechips.rocketchip.system.TinyConfig.fir@125229.4] assign _T_1081 = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala 707:57:freechips.rocketchip.system.TinyConfig.fir@125253.4] assign id_mem_hazard = mem_reg_valid & _T_1081; // @[RocketCore.scala 707:37:freechips.rocketchip.system.TinyConfig.fir@125255.4] assign _T_1119 = id_ex_hazard | id_mem_hazard; // @[RocketCore.scala 734:18:freechips.rocketchip.system.TinyConfig.fir@125301.4] assign _T_1085 = ibuf_io_inst_0_bits_inst_rs1 == wb_waddr; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125259.4] assign _T_1086 = _T_988 & _T_1085; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125260.4] assign _T_1087 = ibuf_io_inst_0_bits_inst_rs2 == wb_waddr; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125261.4] assign _T_1088 = _T_990 & _T_1087; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125262.4] assign _T_1091 = _T_1086 | _T_1088; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125265.4] assign _T_1089 = ibuf_io_inst_0_bits_inst_rd == wb_waddr; // @[RocketCore.scala 711:70:freechips.rocketchip.system.TinyConfig.fir@125263.4] assign _T_1090 = _T_992 & _T_1089; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125264.4] assign _T_1092 = _T_1091 | _T_1090; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125266.4] assign data_hazard_wb = wb_ctrl_wxd & _T_1092; // @[RocketCore.scala 711:36:freechips.rocketchip.system.TinyConfig.fir@125267.4] assign _T_606 = io_dmem_resp_valid == 1'h0; // @[RocketCore.scala 459:39:freechips.rocketchip.system.TinyConfig.fir@124607.4] assign wb_dcache_miss = wb_ctrl_mem & _T_606; // @[RocketCore.scala 459:36:freechips.rocketchip.system.TinyConfig.fir@124608.4] assign wb_set_sboard = wb_ctrl_div | wb_dcache_miss; // @[RocketCore.scala 603:35:freechips.rocketchip.system.TinyConfig.fir@125019.4] assign _T_1104 = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala 713:54:freechips.rocketchip.system.TinyConfig.fir@125280.4] assign id_wb_hazard = wb_reg_valid & _T_1104; // @[RocketCore.scala 713:35:freechips.rocketchip.system.TinyConfig.fir@125282.4] assign _T_1120 = _T_1119 | id_wb_hazard; // @[RocketCore.scala 734:35:freechips.rocketchip.system.TinyConfig.fir@125302.4] assign _T_994 = _T_993[31:1]; // @[RocketCore.scala 930:35:freechips.rocketchip.system.TinyConfig.fir@125151.4] assign _T_995 = {_T_994, 1'h0}; // @[RocketCore.scala 930:40:freechips.rocketchip.system.TinyConfig.fir@125152.4] assign _T_1001 = _T_995 >> ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125161.4] assign _T_1002 = _T_1001[0]; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125162.4] assign dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala 613:44:freechips.rocketchip.system.TinyConfig.fir@125036.4] assign dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala 614:42:freechips.rocketchip.system.TinyConfig.fir@125037.4] assign _T_935 = io_dmem_resp_bits_tag[0]; // @[RocketCore.scala 610:45:freechips.rocketchip.system.TinyConfig.fir@125030.4] assign dmem_resp_xpu = _T_935 == 1'h0; // @[RocketCore.scala 610:23:freechips.rocketchip.system.TinyConfig.fir@125032.4] assign _T_940 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala 629:26:freechips.rocketchip.system.TinyConfig.fir@125050.4] assign _T_939 = div_io_resp_ready & div_io_resp_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@125046.4] assign ll_wen = _T_940 ? 1'h1 : _T_939; // @[RocketCore.scala 629:44:freechips.rocketchip.system.TinyConfig.fir@125051.4] assign dmem_resp_waddr = io_dmem_resp_bits_tag[5:1]; // @[RocketCore.scala 612:46:freechips.rocketchip.system.TinyConfig.fir@125035.4] assign ll_waddr = _T_940 ? dmem_resp_waddr : div_io_resp_bits_tag; // @[RocketCore.scala 629:44:freechips.rocketchip.system.TinyConfig.fir@125051.4] assign _T_1003 = ll_waddr == ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125163.4] assign _T_1004 = ll_wen & _T_1003; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125164.4] assign _T_1005 = _T_1004 == 1'h0; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125165.4] assign _T_1006 = _T_1002 & _T_1005; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125166.4] assign _T_1007 = _T_988 & _T_1006; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125167.4] assign _T_1008 = _T_995 >> ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125168.4] assign _T_1009 = _T_1008[0]; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125169.4] assign _T_1010 = ll_waddr == ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125170.4] assign _T_1011 = ll_wen & _T_1010; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125171.4] assign _T_1012 = _T_1011 == 1'h0; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125172.4] assign _T_1013 = _T_1009 & _T_1012; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125173.4] assign _T_1014 = _T_990 & _T_1013; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125174.4] assign _T_1022 = _T_1007 | _T_1014; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125182.4] assign _T_1015 = _T_995 >> ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125175.4] assign _T_1016 = _T_1015[0]; // @[RocketCore.scala 926:35:freechips.rocketchip.system.TinyConfig.fir@125176.4] assign _T_1017 = ll_waddr == ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 688:70:freechips.rocketchip.system.TinyConfig.fir@125177.4] assign _T_1018 = ll_wen & _T_1017; // @[RocketCore.scala 688:58:freechips.rocketchip.system.TinyConfig.fir@125178.4] assign _T_1019 = _T_1018 == 1'h0; // @[RocketCore.scala 691:80:freechips.rocketchip.system.TinyConfig.fir@125179.4] assign _T_1020 = _T_1016 & _T_1019; // @[RocketCore.scala 691:77:freechips.rocketchip.system.TinyConfig.fir@125180.4] assign _T_1021 = _T_992 & _T_1020; // @[RocketCore.scala 912:27:freechips.rocketchip.system.TinyConfig.fir@125181.4] assign id_sboard_hazard = _T_1022 | _T_1021; // @[RocketCore.scala 912:50:freechips.rocketchip.system.TinyConfig.fir@125183.4] assign _T_1121 = _T_1120 | id_sboard_hazard; // @[RocketCore.scala 734:51:freechips.rocketchip.system.TinyConfig.fir@125303.4] assign _T_1122 = ex_reg_valid | mem_reg_valid; // @[RocketCore.scala 735:40:freechips.rocketchip.system.TinyConfig.fir@125304.4] assign _T_1123 = _T_1122 | wb_reg_valid; // @[RocketCore.scala 735:57:freechips.rocketchip.system.TinyConfig.fir@125305.4] assign _T_1124 = csr_io_singleStep & _T_1123; // @[RocketCore.scala 735:23:freechips.rocketchip.system.TinyConfig.fir@125306.4] assign _T_1125 = _T_1121 | _T_1124; // @[RocketCore.scala 734:71:freechips.rocketchip.system.TinyConfig.fir@125307.4] assign _T_1113 = io_dmem_perf_grant == 1'h0; // @[RocketCore.scala 728:16:freechips.rocketchip.system.TinyConfig.fir@125292.4] assign dcache_blocked = blocked & _T_1113; // @[RocketCore.scala 728:13:freechips.rocketchip.system.TinyConfig.fir@125293.4] assign _T_1132 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala 738:17:freechips.rocketchip.system.TinyConfig.fir@125314.4] assign _T_1133 = _T_1125 | _T_1132; // @[RocketCore.scala 737:32:freechips.rocketchip.system.TinyConfig.fir@125315.4] assign wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala 602:29:freechips.rocketchip.system.TinyConfig.fir@125018.4] assign _T_1136 = wb_wxd == 1'h0; // @[RocketCore.scala 740:65:freechips.rocketchip.system.TinyConfig.fir@125318.4] assign _T_1137 = div_io_resp_valid & _T_1136; // @[RocketCore.scala 740:62:freechips.rocketchip.system.TinyConfig.fir@125319.4] assign _T_1138 = div_io_req_ready | _T_1137; // @[RocketCore.scala 740:40:freechips.rocketchip.system.TinyConfig.fir@125320.4] assign _T_1139 = _T_1138 == 1'h0; // @[RocketCore.scala 740:21:freechips.rocketchip.system.TinyConfig.fir@125321.4] assign _T_1140 = _T_1139 | div_io_req_valid; // @[RocketCore.scala 740:75:freechips.rocketchip.system.TinyConfig.fir@125322.4] assign _T_1141 = id_ctrl_div & _T_1140; // @[RocketCore.scala 740:17:freechips.rocketchip.system.TinyConfig.fir@125323.4] assign _T_1142 = _T_1133 | _T_1141; // @[RocketCore.scala 739:34:freechips.rocketchip.system.TinyConfig.fir@125324.4] assign _T_1145 = _T_1142 | id_do_fence; // @[RocketCore.scala 741:15:freechips.rocketchip.system.TinyConfig.fir@125327.4] assign _T_1146 = _T_1145 | csr_io_csr_stall; // @[RocketCore.scala 742:17:freechips.rocketchip.system.TinyConfig.fir@125328.4] assign ctrl_stalld = _T_1146 | id_reg_pause; // @[RocketCore.scala 743:22:freechips.rocketchip.system.TinyConfig.fir@125329.4] assign _T_1150 = _T_1149 | ctrl_stalld; // @[RocketCore.scala 745:89:freechips.rocketchip.system.TinyConfig.fir@125333.4] assign ctrl_killd = _T_1150 | csr_io_interrupt; // @[RocketCore.scala 745:104:freechips.rocketchip.system.TinyConfig.fir@125334.4] assign _T_556 = ctrl_killd == 1'h0; // @[RocketCore.scala 396:19:freechips.rocketchip.system.TinyConfig.fir@124488.4] assign _T_557 = take_pc_mem_wb == 1'h0; // @[RocketCore.scala 397:20:freechips.rocketchip.system.TinyConfig.fir@124490.4] assign _T_558 = _T_557 & ibuf_io_inst_0_valid; // @[RocketCore.scala 397:29:freechips.rocketchip.system.TinyConfig.fir@124491.4] assign _T_568 = id_fence_succ == 4'h0; // @[RocketCore.scala 407:42:freechips.rocketchip.system.TinyConfig.fir@124510.6] assign _T_569 = id_ctrl_fence & _T_568; // @[RocketCore.scala 407:25:freechips.rocketchip.system.TinyConfig.fir@124511.6] assign _T_570 = {ibuf_io_inst_0_bits_xcpt1_pf_inst,ibuf_io_inst_0_bits_xcpt1_ae_inst}; // @[RocketCore.scala 414:22:freechips.rocketchip.system.TinyConfig.fir@124523.8] assign _T_571 = _T_570 != 2'h0; // @[RocketCore.scala 414:29:freechips.rocketchip.system.TinyConfig.fir@124524.8] assign _T_572 = {1'h0,ibuf_io_inst_0_bits_xcpt0_ae_inst}; // @[RocketCore.scala 419:40:freechips.rocketchip.system.TinyConfig.fir@124530.8] assign _T_573 = _T_572 != 2'h0; // @[RocketCore.scala 419:47:freechips.rocketchip.system.TinyConfig.fir@124531.8] assign _T_574 = bpu_io_xcpt_if | _T_573; // @[RocketCore.scala 419:28:freechips.rocketchip.system.TinyConfig.fir@124532.8] assign _T_575 = id_ctrl_fence_i | id_csr_flush; // @[RocketCore.scala 424:42:freechips.rocketchip.system.TinyConfig.fir@124538.6] assign _T_576 = ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala 426:34:freechips.rocketchip.system.TinyConfig.fir@124541.6] assign _T_578 = id_ctrl_mem_cmd == 5'h5; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124544.6] assign _T_579 = _T_375 | _T_578; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124545.6] assign _T_582 = {_T_989,_T_987}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124549.8] assign _T_583 = id_bypass_src_0_0 | id_bypass_src_0_1; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124552.6] assign _T_584 = _T_583 | id_bypass_src_0_2; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124553.6] assign do_bypass = _T_584 | id_bypass_src_0_3; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124554.6] assign _T_587 = do_bypass == 1'h0; // @[RocketCore.scala 436:26:freechips.rocketchip.system.TinyConfig.fir@124560.6] assign _T_588 = id_ctrl_rxs1 & _T_587; // @[RocketCore.scala 436:23:freechips.rocketchip.system.TinyConfig.fir@124561.6] assign _T_941 = replay_wb_common == 1'h0; // @[RocketCore.scala 637:34:freechips.rocketchip.system.TinyConfig.fir@125056.4] assign _T_942 = wb_reg_valid & _T_941; // @[RocketCore.scala 637:31:freechips.rocketchip.system.TinyConfig.fir@125057.4] assign _T_943 = wb_xcpt == 1'h0; // @[RocketCore.scala 637:48:freechips.rocketchip.system.TinyConfig.fir@125058.4] assign wb_valid = _T_942 & _T_943; // @[RocketCore.scala 637:45:freechips.rocketchip.system.TinyConfig.fir@125059.4] assign wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala 638:25:freechips.rocketchip.system.TinyConfig.fir@125060.4] assign rf_wen = wb_wen | ll_wen; // @[RocketCore.scala 639:23:freechips.rocketchip.system.TinyConfig.fir@125061.4] assign rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala 640:21:freechips.rocketchip.system.TinyConfig.fir@125062.4] assign _T_950 = rf_waddr != 5'h0; // @[RocketCore.scala 955:16:freechips.rocketchip.system.TinyConfig.fir@125071.6] assign _T_954 = rf_waddr == ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 958:20:freechips.rocketchip.system.TinyConfig.fir@125077.8] assign _T_944 = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala 641:38:freechips.rocketchip.system.TinyConfig.fir@125063.4] assign ll_wdata = div_io_resp_bits_data; // @[:freechips.rocketchip.system.TinyConfig.fir@125040.4 :freechips.rocketchip.system.TinyConfig.fir@125042.4] assign _T_946 = wb_ctrl_csr != 3'h0; // @[RocketCore.scala 643:34:freechips.rocketchip.system.TinyConfig.fir@125065.4] assign _T_948 = _T_946 ? csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala 643:21:freechips.rocketchip.system.TinyConfig.fir@125067.4] assign _T_949 = ll_wen ? ll_wdata : _T_948; // @[RocketCore.scala 642:21:freechips.rocketchip.system.TinyConfig.fir@125068.4] assign rf_wdata = _T_944 ? io_dmem_resp_bits_data : _T_949; // @[RocketCore.scala 641:21:freechips.rocketchip.system.TinyConfig.fir@125069.4] assign _GEN_230 = _T_954 ? rf_wdata : _T_294; // @[RocketCore.scala 958:31:freechips.rocketchip.system.TinyConfig.fir@125078.8] assign _GEN_237 = _T_950 ? _GEN_230 : _T_294; // @[RocketCore.scala 955:29:freechips.rocketchip.system.TinyConfig.fir@125072.6] assign id_rs_0 = rf_wen ? _GEN_237 : _T_294; // @[RocketCore.scala 646:17:freechips.rocketchip.system.TinyConfig.fir@125070.4] assign _T_589 = id_rs_0[1:0]; // @[RocketCore.scala 437:37:freechips.rocketchip.system.TinyConfig.fir@124563.8] assign _T_590 = id_rs_0[31:2]; // @[RocketCore.scala 438:38:freechips.rocketchip.system.TinyConfig.fir@124565.8] assign _T_591 = id_bypass_src_1_0 | id_bypass_src_1_1; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124568.6] assign _T_592 = _T_591 | id_bypass_src_1_2; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124569.6] assign do_bypass_1 = _T_592 | id_bypass_src_1_3; // @[RocketCore.scala 432:48:freechips.rocketchip.system.TinyConfig.fir@124570.6] assign _T_595 = do_bypass_1 == 1'h0; // @[RocketCore.scala 436:26:freechips.rocketchip.system.TinyConfig.fir@124576.6] assign _T_596 = id_ctrl_rxs2 & _T_595; // @[RocketCore.scala 436:23:freechips.rocketchip.system.TinyConfig.fir@124577.6] assign _T_955 = rf_waddr == ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 958:20:freechips.rocketchip.system.TinyConfig.fir@125081.8] assign _GEN_231 = _T_955 ? rf_wdata : _T_300; // @[RocketCore.scala 958:31:freechips.rocketchip.system.TinyConfig.fir@125082.8] assign _GEN_238 = _T_950 ? _GEN_231 : _T_300; // @[RocketCore.scala 955:29:freechips.rocketchip.system.TinyConfig.fir@125072.6] assign id_rs_1 = rf_wen ? _GEN_238 : _T_300; // @[RocketCore.scala 646:17:freechips.rocketchip.system.TinyConfig.fir@125070.4] assign _T_597 = id_rs_1[1:0]; // @[RocketCore.scala 437:37:freechips.rocketchip.system.TinyConfig.fir@124579.8] assign _T_598 = id_rs_1[31:2]; // @[RocketCore.scala 438:38:freechips.rocketchip.system.TinyConfig.fir@124581.8] assign _T_599 = ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala 442:62:freechips.rocketchip.system.TinyConfig.fir@124585.8] assign inst = ibuf_io_inst_0_bits_rvc ? {{16'd0}, _T_599} : ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 442:21:freechips.rocketchip.system.TinyConfig.fir@124586.8] assign _T_600 = inst[1:0]; // @[RocketCore.scala 444:31:freechips.rocketchip.system.TinyConfig.fir@124588.8] assign _T_601 = inst[31:2]; // @[RocketCore.scala 445:32:freechips.rocketchip.system.TinyConfig.fir@124590.8] assign _T_1083 = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala 708:32:freechips.rocketchip.system.TinyConfig.fir@125256.4] assign id_load_use = _T_1083 & mem_ctrl_mem; // @[RocketCore.scala 708:51:freechips.rocketchip.system.TinyConfig.fir@125257.4] assign _T_603 = _T_556 | csr_io_interrupt; // @[RocketCore.scala 448:21:freechips.rocketchip.system.TinyConfig.fir@124595.4] assign _T_604 = _T_603 | ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 448:41:freechips.rocketchip.system.TinyConfig.fir@124596.4] assign _T_605 = ex_reg_valid | ex_reg_replay; // @[RocketCore.scala 458:34:freechips.rocketchip.system.TinyConfig.fir@124605.4] assign ex_pc_valid = _T_605 | ex_reg_xcpt_interrupt; // @[RocketCore.scala 458:51:freechips.rocketchip.system.TinyConfig.fir@124606.4] assign _T_607 = io_dmem_req_ready == 1'h0; // @[RocketCore.scala 460:45:freechips.rocketchip.system.TinyConfig.fir@124609.4] assign _T_608 = ex_ctrl_mem & _T_607; // @[RocketCore.scala 460:42:freechips.rocketchip.system.TinyConfig.fir@124610.4] assign _T_609 = div_io_req_ready == 1'h0; // @[RocketCore.scala 461:45:freechips.rocketchip.system.TinyConfig.fir@124611.4] assign _T_610 = ex_ctrl_div & _T_609; // @[RocketCore.scala 461:42:freechips.rocketchip.system.TinyConfig.fir@124612.4] assign replay_ex_structural = _T_608 | _T_610; // @[RocketCore.scala 460:64:freechips.rocketchip.system.TinyConfig.fir@124613.4] assign replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala 462:43:freechips.rocketchip.system.TinyConfig.fir@124614.4] assign _T_611 = replay_ex_structural | replay_ex_load_use; // @[RocketCore.scala 463:75:freechips.rocketchip.system.TinyConfig.fir@124615.4] assign _T_612 = ex_reg_valid & _T_611; // @[RocketCore.scala 463:50:freechips.rocketchip.system.TinyConfig.fir@124616.4] assign replay_ex = ex_reg_replay | _T_612; // @[RocketCore.scala 463:33:freechips.rocketchip.system.TinyConfig.fir@124617.4] assign _T_613 = take_pc_mem_wb | replay_ex; // @[RocketCore.scala 464:35:freechips.rocketchip.system.TinyConfig.fir@124618.4] assign _T_614 = ex_reg_valid == 1'h0; // @[RocketCore.scala 464:51:freechips.rocketchip.system.TinyConfig.fir@124619.4] assign ctrl_killx = _T_613 | _T_614; // @[RocketCore.scala 464:48:freechips.rocketchip.system.TinyConfig.fir@124620.4] assign _T_615 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala 466:40:freechips.rocketchip.system.TinyConfig.fir@124621.4] assign _T_616 = ex_reg_mem_size < 2'h2; // @[RocketCore.scala 466:69:freechips.rocketchip.system.TinyConfig.fir@124622.4] assign ex_slow_bypass = _T_615 | _T_616; // @[RocketCore.scala 466:50:freechips.rocketchip.system.TinyConfig.fir@124623.4] assign ex_xcpt = ex_reg_xcpt_interrupt | ex_reg_xcpt; // @[RocketCore.scala 470:28:freechips.rocketchip.system.TinyConfig.fir@124627.4] assign _T_627 = mem_reg_valid | mem_reg_replay; // @[RocketCore.scala 476:36:freechips.rocketchip.system.TinyConfig.fir@124636.4] assign mem_pc_valid = _T_627 | mem_reg_xcpt_interrupt; // @[RocketCore.scala 476:54:freechips.rocketchip.system.TinyConfig.fir@124637.4] assign _T_628 = $signed(mem_reg_pc); // @[RocketCore.scala 477:34:freechips.rocketchip.system.TinyConfig.fir@124638.4] assign _T_631 = mem_reg_inst[31]; // @[RocketCore.scala 965:48:freechips.rocketchip.system.TinyConfig.fir@124641.4] assign _T_632 = $signed(_T_631); // @[RocketCore.scala 965:53:freechips.rocketchip.system.TinyConfig.fir@124642.4] assign _T_637 = {11{_T_632}}; // @[RocketCore.scala 966:21:freechips.rocketchip.system.TinyConfig.fir@124647.4] assign _T_641 = mem_reg_inst[19:12]; // @[RocketCore.scala 967:65:freechips.rocketchip.system.TinyConfig.fir@124651.4] assign _T_642 = $signed(_T_641); // @[RocketCore.scala 967:73:freechips.rocketchip.system.TinyConfig.fir@124652.4] assign _T_643 = {8{_T_632}}; // @[RocketCore.scala 967:21:freechips.rocketchip.system.TinyConfig.fir@124653.4] assign _T_648 = mem_reg_inst[20]; // @[RocketCore.scala 969:39:freechips.rocketchip.system.TinyConfig.fir@124658.4] assign _T_649 = $signed(_T_648); // @[RocketCore.scala 969:44:freechips.rocketchip.system.TinyConfig.fir@124659.4] assign _T_651 = mem_reg_inst[7]; // @[RocketCore.scala 970:39:freechips.rocketchip.system.TinyConfig.fir@124661.4] assign _T_652 = $signed(_T_651); // @[RocketCore.scala 970:43:freechips.rocketchip.system.TinyConfig.fir@124662.4] assign _T_659 = mem_reg_inst[30:25]; // @[RocketCore.scala 971:66:freechips.rocketchip.system.TinyConfig.fir@124669.4] assign _T_665 = mem_reg_inst[11:8]; // @[RocketCore.scala 973:57:freechips.rocketchip.system.TinyConfig.fir@124675.4] assign _T_668 = mem_reg_inst[24:21]; // @[RocketCore.scala 974:52:freechips.rocketchip.system.TinyConfig.fir@124678.4] assign _T_683 = $unsigned(_T_652); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124693.4] assign _T_684 = $unsigned(_T_643); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124694.4] assign _T_686 = $unsigned(_T_637); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124696.4] assign _T_687 = $unsigned(_T_632); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124697.4] assign _T_690 = {_T_687,_T_686,_T_684,_T_683,_T_659,_T_665,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124700.4] assign _T_691 = $signed(_T_690); // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124701.4] assign _T_745 = $unsigned(_T_649); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124755.4] assign _T_746 = $unsigned(_T_642); // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124756.4] assign _T_752 = {_T_687,_T_686,_T_746,_T_745,_T_659,_T_668,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124762.4] assign _T_753 = $signed(_T_752); // @[RocketCore.scala 979:53:freechips.rocketchip.system.TinyConfig.fir@124763.4] assign _T_754 = mem_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 480:8:freechips.rocketchip.system.TinyConfig.fir@124764.4] assign _T_755 = mem_ctrl_jal ? $signed(_T_753) : $signed({{28{_T_754[3]}},_T_754}); // @[RocketCore.scala 479:8:freechips.rocketchip.system.TinyConfig.fir@124765.4] assign _T_756 = _T_779 ? $signed(_T_691) : $signed(_T_755); // @[RocketCore.scala 478:8:freechips.rocketchip.system.TinyConfig.fir@124766.4] assign _T_758 = $signed(_T_628) + $signed(_T_756); // @[RocketCore.scala 477:41:freechips.rocketchip.system.TinyConfig.fir@124768.4] assign mem_br_target = $signed(_T_758); // @[RocketCore.scala 477:41:freechips.rocketchip.system.TinyConfig.fir@124769.4] assign _T_760 = $signed(mem_reg_wdata); // @[RocketCore.scala 481:106:freechips.rocketchip.system.TinyConfig.fir@124771.4] assign _T_761 = mem_ctrl_jalr ? $signed(_T_760) : $signed(mem_br_target); // @[RocketCore.scala 481:21:freechips.rocketchip.system.TinyConfig.fir@124772.4] assign _T_762 = $signed(_T_761) & $signed(-32'sh2); // @[RocketCore.scala 481:129:freechips.rocketchip.system.TinyConfig.fir@124773.4] assign _T_763 = $signed(_T_762); // @[RocketCore.scala 481:129:freechips.rocketchip.system.TinyConfig.fir@124774.4] assign mem_npc = $unsigned(_T_763); // @[RocketCore.scala 481:141:freechips.rocketchip.system.TinyConfig.fir@124775.4] assign _T_764 = mem_npc != ex_reg_pc; // @[RocketCore.scala 483:30:freechips.rocketchip.system.TinyConfig.fir@124776.4] assign _T_765 = ibuf_io_inst_0_valid | ibuf_io_imem_valid; // @[RocketCore.scala 484:31:freechips.rocketchip.system.TinyConfig.fir@124777.4] assign _T_766 = mem_npc != ibuf_io_pc; // @[RocketCore.scala 484:62:freechips.rocketchip.system.TinyConfig.fir@124778.4] assign _T_767 = _T_765 ? _T_766 : 1'h1; // @[RocketCore.scala 484:8:freechips.rocketchip.system.TinyConfig.fir@124779.4] assign mem_wrong_npc = ex_pc_valid ? _T_764 : _T_767; // @[RocketCore.scala 483:8:freechips.rocketchip.system.TinyConfig.fir@124780.4] assign _T_770 = mem_npc[1]; // @[RocketCore.scala 485:66:freechips.rocketchip.system.TinyConfig.fir@124783.4] assign mem_npc_misaligned = _T_398 & _T_770; // @[RocketCore.scala 485:56:freechips.rocketchip.system.TinyConfig.fir@124784.4] assign _T_773 = mem_reg_xcpt == 1'h0; // @[RocketCore.scala 486:27:freechips.rocketchip.system.TinyConfig.fir@124787.4] assign _T_774 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala 486:59:freechips.rocketchip.system.TinyConfig.fir@124788.4] assign _T_775 = _T_773 & _T_774; // @[RocketCore.scala 486:41:freechips.rocketchip.system.TinyConfig.fir@124789.4] assign _T_777 = _T_775 ? $signed(mem_br_target) : $signed(_T_760); // @[RocketCore.scala 486:26:freechips.rocketchip.system.TinyConfig.fir@124791.4] assign mem_int_wdata = $unsigned(_T_777); // @[RocketCore.scala 486:119:freechips.rocketchip.system.TinyConfig.fir@124792.4] assign _T_778 = mem_ctrl_branch | mem_ctrl_jalr; // @[RocketCore.scala 487:33:freechips.rocketchip.system.TinyConfig.fir@124793.4] assign mem_cfi = _T_778 | mem_ctrl_jal; // @[RocketCore.scala 487:50:freechips.rocketchip.system.TinyConfig.fir@124794.4] assign _T_785 = ctrl_killx == 1'h0; // @[RocketCore.scala 493:20:freechips.rocketchip.system.TinyConfig.fir@124804.4] assign _T_792 = mem_reg_valid & mem_reg_flush_pipe; // @[RocketCore.scala 500:23:freechips.rocketchip.system.TinyConfig.fir@124815.4] assign _T_793 = ex_ctrl_mem_cmd == 5'h0; // @[Consts.scala 81:31:freechips.rocketchip.system.TinyConfig.fir@124825.8] assign _T_794 = ex_ctrl_mem_cmd == 5'h6; // @[Consts.scala 81:48:freechips.rocketchip.system.TinyConfig.fir@124826.8] assign _T_795 = _T_793 | _T_794; // @[Consts.scala 81:41:freechips.rocketchip.system.TinyConfig.fir@124827.8] assign _T_797 = _T_795 | _T_615; // @[Consts.scala 81:58:freechips.rocketchip.system.TinyConfig.fir@124829.8] assign _T_798 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124830.8] assign _T_799 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124831.8] assign _T_800 = ex_ctrl_mem_cmd == 5'ha; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124832.8] assign _T_801 = ex_ctrl_mem_cmd == 5'hb; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124833.8] assign _T_802 = _T_798 | _T_799; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124834.8] assign _T_803 = _T_802 | _T_800; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124835.8] assign _T_804 = _T_803 | _T_801; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124836.8] assign _T_805 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124837.8] assign _T_806 = ex_ctrl_mem_cmd == 5'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124838.8] assign _T_807 = ex_ctrl_mem_cmd == 5'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124839.8] assign _T_808 = ex_ctrl_mem_cmd == 5'he; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124840.8] assign _T_809 = ex_ctrl_mem_cmd == 5'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@124841.8] assign _T_810 = _T_805 | _T_806; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124842.8] assign _T_811 = _T_810 | _T_807; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124843.8] assign _T_812 = _T_811 | _T_808; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124844.8] assign _T_813 = _T_812 | _T_809; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@124845.8] assign _T_814 = _T_804 | _T_813; // @[Consts.scala 79:44:freechips.rocketchip.system.TinyConfig.fir@124846.8] assign _T_815 = _T_797 | _T_814; // @[Consts.scala 81:75:freechips.rocketchip.system.TinyConfig.fir@124847.8] assign _T_816 = ex_ctrl_mem & _T_815; // @[RocketCore.scala 507:33:freechips.rocketchip.system.TinyConfig.fir@124848.8] assign _T_817 = ex_ctrl_mem_cmd == 5'h1; // @[Consts.scala 82:32:freechips.rocketchip.system.TinyConfig.fir@124850.8] assign _T_818 = ex_ctrl_mem_cmd == 5'h11; // @[Consts.scala 82:49:freechips.rocketchip.system.TinyConfig.fir@124851.8] assign _T_819 = _T_817 | _T_818; // @[Consts.scala 82:42:freechips.rocketchip.system.TinyConfig.fir@124852.8] assign _T_821 = _T_819 | _T_615; // @[Consts.scala 82:59:freechips.rocketchip.system.TinyConfig.fir@124854.8] assign _T_839 = _T_821 | _T_814; // @[Consts.scala 82:76:freechips.rocketchip.system.TinyConfig.fir@124872.8] assign _T_840 = ex_ctrl_mem & _T_839; // @[RocketCore.scala 508:34:freechips.rocketchip.system.TinyConfig.fir@124873.8] assign _T_841 = alu_io_out; // @[RocketCore.scala 520:25:freechips.rocketchip.system.TinyConfig.fir@124885.8] assign _T_844 = ex_ctrl_rxs2 & ex_ctrl_mem; // @[RocketCore.scala 523:24:freechips.rocketchip.system.TinyConfig.fir@124890.8] assign _T_846 = ex_reg_mem_size == 2'h0; // @[AMOALU.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@124894.10] assign _T_847 = ex_rs_1[7:0]; // @[AMOALU.scala 26:66:freechips.rocketchip.system.TinyConfig.fir@124895.10] assign _T_849 = {_T_847,_T_847,_T_847,_T_847}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124897.10] assign _T_850 = ex_reg_mem_size == 2'h1; // @[AMOALU.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@124898.10] assign _T_851 = ex_rs_1[15:0]; // @[AMOALU.scala 26:66:freechips.rocketchip.system.TinyConfig.fir@124899.10] assign _T_852 = {_T_851,_T_851}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@124900.10] assign _T_855 = ex_ctrl_jalr & csr_io_status_debug; // @[RocketCore.scala 527:24:freechips.rocketchip.system.TinyConfig.fir@124905.8] assign _T_856 = mem_reg_load & bpu_io_xcpt_ld; // @[RocketCore.scala 534:38:freechips.rocketchip.system.TinyConfig.fir@124911.4] assign _T_857 = mem_reg_store & bpu_io_xcpt_st; // @[RocketCore.scala 534:75:freechips.rocketchip.system.TinyConfig.fir@124912.4] assign mem_breakpoint = _T_856 | _T_857; // @[RocketCore.scala 534:57:freechips.rocketchip.system.TinyConfig.fir@124913.4] assign _T_858 = mem_reg_load & bpu_io_debug_ld; // @[RocketCore.scala 535:44:freechips.rocketchip.system.TinyConfig.fir@124914.4] assign _T_859 = mem_reg_store & bpu_io_debug_st; // @[RocketCore.scala 535:82:freechips.rocketchip.system.TinyConfig.fir@124915.4] assign mem_debug_breakpoint = _T_858 | _T_859; // @[RocketCore.scala 535:64:freechips.rocketchip.system.TinyConfig.fir@124916.4] assign mem_ldst_xcpt = mem_debug_breakpoint | mem_breakpoint; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124917.4] assign mem_ldst_cause = mem_debug_breakpoint ? 4'he : 4'h3; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124918.4] assign _T_860 = mem_reg_xcpt_interrupt | mem_reg_xcpt; // @[RocketCore.scala 541:29:freechips.rocketchip.system.TinyConfig.fir@124919.4] assign _T_861 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala 542:20:freechips.rocketchip.system.TinyConfig.fir@124920.4] assign _T_862 = mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala 543:20:freechips.rocketchip.system.TinyConfig.fir@124921.4] assign _T_863 = _T_860 | _T_861; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124922.4] assign mem_xcpt = _T_863 | _T_862; // @[RocketCore.scala 903:26:freechips.rocketchip.system.TinyConfig.fir@124923.4] assign _T_864 = _T_861 ? 4'h0 : mem_ldst_cause; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@124924.4] assign dcache_kill_mem = _T_454 & io_dmem_replay_next; // @[RocketCore.scala 552:55:freechips.rocketchip.system.TinyConfig.fir@124937.4] assign replay_mem = dcache_kill_mem | mem_reg_replay; // @[RocketCore.scala 554:37:freechips.rocketchip.system.TinyConfig.fir@124940.4] assign _T_878 = dcache_kill_mem | take_pc_wb; // @[RocketCore.scala 555:38:freechips.rocketchip.system.TinyConfig.fir@124942.4] assign _T_879 = _T_878 | mem_reg_xcpt; // @[RocketCore.scala 555:52:freechips.rocketchip.system.TinyConfig.fir@124943.4] assign _T_880 = mem_reg_valid == 1'h0; // @[RocketCore.scala 555:71:freechips.rocketchip.system.TinyConfig.fir@124944.4] assign killm_common = _T_879 | _T_880; // @[RocketCore.scala 555:68:freechips.rocketchip.system.TinyConfig.fir@124945.4] assign ctrl_killm = killm_common | mem_xcpt; // @[RocketCore.scala 557:33:freechips.rocketchip.system.TinyConfig.fir@124951.4] assign _T_885 = ctrl_killm == 1'h0; // @[RocketCore.scala 560:19:freechips.rocketchip.system.TinyConfig.fir@124953.4] assign _T_886 = take_pc_wb == 1'h0; // @[RocketCore.scala 561:34:freechips.rocketchip.system.TinyConfig.fir@124955.4] assign _T_915 = _T_907 ? 3'h7 : 3'h5; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125002.4] assign _T_916 = _T_905 ? 4'hd : {{1'd0}, _T_915}; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125003.4] assign _T_917 = _T_903 ? 4'hf : _T_916; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125004.4] assign _T_918 = _T_901 ? 4'h4 : _T_917; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125005.4] assign _T_919 = _T_899 ? 4'h6 : _T_918; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125006.4] assign wb_cause = wb_reg_xcpt ? wb_reg_cause : {{28'd0}, _T_919}; // @[Mux.scala 48:69:freechips.rocketchip.system.TinyConfig.fir@125007.4] assign _T_920 = wb_cause == 32'h6; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125008.4] assign _T_922 = wb_cause == 32'h4; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125010.4] assign _T_924 = wb_cause == 32'h7; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125012.4] assign _T_926 = wb_cause == 32'h5; // @[RocketCore.scala 907:38:freechips.rocketchip.system.TinyConfig.fir@125014.4] assign _T_957 = wb_reg_raw_inst[1:0]; // @[RocketCore.scala 654:66:freechips.rocketchip.system.TinyConfig.fir@125093.4] assign _T_958 = _T_957 == 2'h3; // @[RocketCore.scala 654:73:freechips.rocketchip.system.TinyConfig.fir@125094.4] assign _T_959 = wb_reg_inst[31:16]; // @[RocketCore.scala 654:91:freechips.rocketchip.system.TinyConfig.fir@125095.4] assign _T_960 = _T_958 ? _T_959 : 16'h0; // @[RocketCore.scala 654:50:freechips.rocketchip.system.TinyConfig.fir@125096.4] assign _T_961 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala 654:119:freechips.rocketchip.system.TinyConfig.fir@125097.4] assign _T_963 = wb_cause == 32'h2; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125106.4] assign _T_964 = wb_cause == 32'h3; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125107.4] assign _T_969 = wb_cause == 32'h1; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125112.4] assign _T_970 = wb_cause == 32'hd; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125113.4] assign _T_971 = wb_cause == 32'hf; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125114.4] assign _T_972 = wb_cause == 32'hc; // @[package.scala 15:47:freechips.rocketchip.system.TinyConfig.fir@125115.4] assign _T_973 = _T_963 | _T_964; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125116.4] assign _T_974 = _T_973 | _T_922; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125117.4] assign _T_975 = _T_974 | _T_920; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125118.4] assign _T_976 = _T_975 | _T_926; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125119.4] assign _T_977 = _T_976 | _T_924; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125120.4] assign _T_978 = _T_977 | _T_969; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125121.4] assign _T_979 = _T_978 | _T_970; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125122.4] assign _T_980 = _T_979 | _T_971; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125123.4] assign _T_981 = _T_980 | _T_972; // @[package.scala 15:62:freechips.rocketchip.system.TinyConfig.fir@125124.4] assign tval_valid = wb_xcpt & _T_981; // @[RocketCore.scala 661:28:freechips.rocketchip.system.TinyConfig.fir@125125.4] assign _T_984 = wb_reg_valid ? 3'h0 : 3'h4; // @[CSR.scala 130:15:freechips.rocketchip.system.TinyConfig.fir@125137.4] assign _T_985 = ~ _T_984; // @[CSR.scala 130:11:freechips.rocketchip.system.TinyConfig.fir@125138.4] assign _T_996 = 32'h1 << ll_waddr; // @[RocketCore.scala 933:62:freechips.rocketchip.system.TinyConfig.fir@125153.4] assign _T_997 = ll_wen ? _T_996 : 32'h0; // @[RocketCore.scala 933:49:freechips.rocketchip.system.TinyConfig.fir@125154.4] assign _T_998 = ~ _T_997; // @[RocketCore.scala 925:64:freechips.rocketchip.system.TinyConfig.fir@125155.4] assign _T_999 = _T_995 & _T_998; // @[RocketCore.scala 925:62:freechips.rocketchip.system.TinyConfig.fir@125156.4] assign _T_1023 = wb_set_sboard & wb_wen; // @[RocketCore.scala 692:28:freechips.rocketchip.system.TinyConfig.fir@125184.4] assign _T_1024 = 32'h1 << wb_waddr; // @[RocketCore.scala 933:62:freechips.rocketchip.system.TinyConfig.fir@125185.4] assign _T_1025 = _T_1023 ? _T_1024 : 32'h0; // @[RocketCore.scala 933:49:freechips.rocketchip.system.TinyConfig.fir@125186.4] assign _T_1026 = _T_999 | _T_1025; // @[RocketCore.scala 924:60:freechips.rocketchip.system.TinyConfig.fir@125187.4] assign _T_1027 = ll_wen | _T_1023; // @[RocketCore.scala 936:17:freechips.rocketchip.system.TinyConfig.fir@125188.4] assign _T_1109 = _T_607 & _T_1113; // @[RocketCore.scala 727:60:freechips.rocketchip.system.TinyConfig.fir@125287.4] assign _T_1110 = blocked | io_dmem_req_valid; // @[RocketCore.scala 727:95:freechips.rocketchip.system.TinyConfig.fir@125288.4] assign _T_1111 = _T_1110 | io_dmem_s2_nack; // @[RocketCore.scala 727:116:freechips.rocketchip.system.TinyConfig.fir@125289.4] assign _T_1153 = wb_xcpt | csr_io_eret; // @[RocketCore.scala 750:17:freechips.rocketchip.system.TinyConfig.fir@125339.4] assign _T_1154 = replay_wb_common ? wb_reg_pc : mem_npc; // @[RocketCore.scala 751:8:freechips.rocketchip.system.TinyConfig.fir@125340.4] assign _T_1156 = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala 753:40:freechips.rocketchip.system.TinyConfig.fir@125343.4] assign _T_1157 = io_dmem_s2_nack == 1'h0; // @[RocketCore.scala 753:62:freechips.rocketchip.system.TinyConfig.fir@125344.4] assign _T_1159 = ex_pc_valid | mem_pc_valid; // @[RocketCore.scala 755:43:freechips.rocketchip.system.TinyConfig.fir@125347.4] assign _T_1160 = io_ptw_customCSRs_csrs_0_value[1]; // @[CustomCSRs.scala 38:61:freechips.rocketchip.system.TinyConfig.fir@125348.4] assign _T_1167 = mem_reg_valid & _T_886; // @[RocketCore.scala 767:45:freechips.rocketchip.system.TinyConfig.fir@125364.4] assign _T_1168 = _T_1167 & mem_wrong_npc; // @[RocketCore.scala 767:60:freechips.rocketchip.system.TinyConfig.fir@125365.4] assign _T_1169 = mem_cfi == 1'h0; // @[RocketCore.scala 767:81:freechips.rocketchip.system.TinyConfig.fir@125366.4] assign _T_1170 = _T_1169 | mem_cfi_taken; // @[RocketCore.scala 767:90:freechips.rocketchip.system.TinyConfig.fir@125367.4] assign ex_dcache_tag = {ex_waddr,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@125417.4] assign _T_1196 = ex_reg_inst[14]; // @[RocketCore.scala 803:42:freechips.rocketchip.system.TinyConfig.fir@125421.4] assign _T_1213 = wb_reg_inst[19:15]; // @[RocketCore.scala 815:58:freechips.rocketchip.system.TinyConfig.fir@125456.4] assign _T_1214 = wb_reg_inst[24:20]; // @[RocketCore.scala 815:58:freechips.rocketchip.system.TinyConfig.fir@125458.4] assign _T_1216 = csr_io_time[4:0]; // @[RocketCore.scala 820:28:freechips.rocketchip.system.TinyConfig.fir@125465.4] assign _T_1217 = _T_1216 == 5'h0; // @[RocketCore.scala 820:62:freechips.rocketchip.system.TinyConfig.fir@125466.4] assign unpause = _T_1217 | take_pc_mem_wb; // @[RocketCore.scala 820:92:freechips.rocketchip.system.TinyConfig.fir@125468.4] assign coreMonitorBundle_timer = csr_io_time; // @[RocketCore.scala 846:41:freechips.rocketchip.system.TinyConfig.fir@125484.4] assign _T_1224 = csr_io_trace_0_exception == 1'h0; // @[RocketCore.scala 847:55:freechips.rocketchip.system.TinyConfig.fir@125486.4] assign coreMonitorBundle_valid = csr_io_trace_0_valid & _T_1224; // @[RocketCore.scala 847:52:freechips.rocketchip.system.TinyConfig.fir@125487.4] assign coreMonitorBundle_pc = csr_io_trace_0_iaddr; // @[RocketCore.scala 848:48:freechips.rocketchip.system.TinyConfig.fir@125489.4] assign _T_1228 = _T_1023 == 1'h0; // @[RocketCore.scala 849:44:freechips.rocketchip.system.TinyConfig.fir@125492.4] assign _T_1229 = rf_wen & _T_1228; // @[RocketCore.scala 849:41:freechips.rocketchip.system.TinyConfig.fir@125493.4] assign coreMonitorBundle_wrdst = _T_1229 ? rf_waddr : 5'h0; // @[RocketCore.scala 849:33:freechips.rocketchip.system.TinyConfig.fir@125494.4] assign _T_1238 = reset == 1'h0; // @[RocketCore.scala 885:11:freechips.rocketchip.system.TinyConfig.fir@125514.4] assign coreMonitorBundle_inst = csr_io_trace_0_insn; // @[RocketCore.scala 841:31:freechips.rocketchip.system.TinyConfig.fir@125479.4 RocketCore.scala 856:26:freechips.rocketchip.system.TinyConfig.fir@125512.4] assign io_imem_might_request = imem_might_request_reg; // @[RocketCore.scala 754:25:freechips.rocketchip.system.TinyConfig.fir@125351.4] assign io_imem_req_valid = take_pc_wb | take_pc_mem; // @[RocketCore.scala 747:21:freechips.rocketchip.system.TinyConfig.fir@125336.4] assign io_imem_req_bits_pc = _T_1153 ? csr_io_evec : _T_1154; // @[RocketCore.scala 749:23:freechips.rocketchip.system.TinyConfig.fir@125342.4] assign io_imem_req_bits_speculative = take_pc_wb == 1'h0; // @[RocketCore.scala 748:32:freechips.rocketchip.system.TinyConfig.fir@125338.4] assign io_imem_resp_ready = ibuf_io_imem_ready; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign io_imem_btb_update_valid = _T_1168 & _T_1170; // @[RocketCore.scala 767:28:freechips.rocketchip.system.TinyConfig.fir@125369.4] assign io_imem_bht_update_valid = mem_reg_valid & _T_886; // @[RocketCore.scala 779:28:freechips.rocketchip.system.TinyConfig.fir@125395.4] assign io_imem_flush_icache = _T_1156 & _T_1157; // @[RocketCore.scala 753:24:freechips.rocketchip.system.TinyConfig.fir@125346.4] assign io_dmem_req_valid = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala 797:25:freechips.rocketchip.system.TinyConfig.fir@125416.4] assign io_dmem_req_bits_addr = alu_io_adder_out; // @[RocketCore.scala 805:25:freechips.rocketchip.system.TinyConfig.fir@125425.4] assign io_dmem_req_bits_tag = {{1'd0}, ex_dcache_tag}; // @[RocketCore.scala 800:25:freechips.rocketchip.system.TinyConfig.fir@125418.4] assign io_dmem_req_bits_cmd = ex_ctrl_mem_cmd; // @[RocketCore.scala 801:25:freechips.rocketchip.system.TinyConfig.fir@125419.4] assign io_dmem_req_bits_size = ex_reg_mem_size; // @[RocketCore.scala 802:25:freechips.rocketchip.system.TinyConfig.fir@125420.4] assign io_dmem_req_bits_signed = _T_1196 == 1'h0; // @[RocketCore.scala 803:27:freechips.rocketchip.system.TinyConfig.fir@125423.4] assign io_dmem_s1_kill = killm_common | mem_ldst_xcpt; // @[RocketCore.scala 807:19:freechips.rocketchip.system.TinyConfig.fir@125429.4] assign io_dmem_s1_data_data = mem_reg_rs2; // @[RocketCore.scala 806:24:freechips.rocketchip.system.TinyConfig.fir@125426.4] assign io_ptw_pmp_0_cfg_l = csr_io_pmp_0_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_cfg_a = csr_io_pmp_0_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_cfg_x = csr_io_pmp_0_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_cfg_w = csr_io_pmp_0_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_cfg_r = csr_io_pmp_0_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_addr = csr_io_pmp_0_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_0_mask = csr_io_pmp_0_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_cfg_l = csr_io_pmp_1_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_cfg_a = csr_io_pmp_1_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_cfg_x = csr_io_pmp_1_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_cfg_w = csr_io_pmp_1_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_cfg_r = csr_io_pmp_1_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_addr = csr_io_pmp_1_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_1_mask = csr_io_pmp_1_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_cfg_l = csr_io_pmp_2_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_cfg_a = csr_io_pmp_2_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_cfg_x = csr_io_pmp_2_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_cfg_w = csr_io_pmp_2_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_cfg_r = csr_io_pmp_2_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_addr = csr_io_pmp_2_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_2_mask = csr_io_pmp_2_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_cfg_l = csr_io_pmp_3_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_cfg_a = csr_io_pmp_3_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_cfg_x = csr_io_pmp_3_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_cfg_w = csr_io_pmp_3_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_cfg_r = csr_io_pmp_3_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_addr = csr_io_pmp_3_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_3_mask = csr_io_pmp_3_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_cfg_l = csr_io_pmp_4_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_cfg_a = csr_io_pmp_4_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_cfg_x = csr_io_pmp_4_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_cfg_w = csr_io_pmp_4_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_cfg_r = csr_io_pmp_4_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_addr = csr_io_pmp_4_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_4_mask = csr_io_pmp_4_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_cfg_l = csr_io_pmp_5_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_cfg_a = csr_io_pmp_5_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_cfg_x = csr_io_pmp_5_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_cfg_w = csr_io_pmp_5_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_cfg_r = csr_io_pmp_5_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_addr = csr_io_pmp_5_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_5_mask = csr_io_pmp_5_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_cfg_l = csr_io_pmp_6_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_cfg_a = csr_io_pmp_6_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_cfg_x = csr_io_pmp_6_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_cfg_w = csr_io_pmp_6_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_cfg_r = csr_io_pmp_6_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_addr = csr_io_pmp_6_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_6_mask = csr_io_pmp_6_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_cfg_l = csr_io_pmp_7_cfg_l; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_cfg_a = csr_io_pmp_7_cfg_a; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_cfg_x = csr_io_pmp_7_cfg_x; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_cfg_w = csr_io_pmp_7_cfg_w; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_cfg_r = csr_io_pmp_7_cfg_r; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_addr = csr_io_pmp_7_addr; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_pmp_7_mask = csr_io_pmp_7_mask; // @[RocketCore.scala 669:14:freechips.rocketchip.system.TinyConfig.fir@125134.4] assign io_ptw_customCSRs_csrs_0_value = 32'h0; // @[RocketCore.scala 667:79:freechips.rocketchip.system.TinyConfig.fir@125129.4] assign ibuf_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@123812.4] assign ibuf_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@123813.4] assign ibuf_io_imem_valid = io_imem_resp_valid; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign ibuf_io_imem_bits_pc = io_imem_resp_bits_pc; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign ibuf_io_imem_bits_data = io_imem_resp_bits_data; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign ibuf_io_imem_bits_xcpt_ae_inst = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign ibuf_io_imem_bits_replay = io_imem_resp_bits_replay; // @[RocketCore.scala 242:16:freechips.rocketchip.system.TinyConfig.fir@123814.4] assign ibuf_io_kill = take_pc_wb | take_pc_mem; // @[RocketCore.scala 243:16:freechips.rocketchip.system.TinyConfig.fir@123815.4] assign ibuf_io_inst_0_ready = ctrl_stalld == 1'h0; // @[RocketCore.scala 765:25:freechips.rocketchip.system.TinyConfig.fir@125362.4] assign csr_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@124227.4] assign csr_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@124228.4] assign csr_io_ungated_clock = clock; // @[RocketCore.scala 649:24:freechips.rocketchip.system.TinyConfig.fir@125087.4] assign csr_io_interrupts_debug = io_interrupts_debug; // @[RocketCore.scala 655:21:freechips.rocketchip.system.TinyConfig.fir@125100.4] assign csr_io_interrupts_mtip = io_interrupts_mtip; // @[RocketCore.scala 655:21:freechips.rocketchip.system.TinyConfig.fir@125100.4] assign csr_io_interrupts_msip = io_interrupts_msip; // @[RocketCore.scala 655:21:freechips.rocketchip.system.TinyConfig.fir@125100.4] assign csr_io_interrupts_meip = io_interrupts_meip; // @[RocketCore.scala 655:21:freechips.rocketchip.system.TinyConfig.fir@125100.4] assign csr_io_rw_addr = wb_reg_inst[31:20]; // @[RocketCore.scala 670:18:freechips.rocketchip.system.TinyConfig.fir@125136.4] assign csr_io_rw_cmd = wb_ctrl_csr & _T_985; // @[RocketCore.scala 671:17:freechips.rocketchip.system.TinyConfig.fir@125140.4] assign csr_io_rw_wdata = wb_reg_wdata; // @[RocketCore.scala 672:19:freechips.rocketchip.system.TinyConfig.fir@125141.4] assign csr_io_decode_0_csr = ibuf_io_inst_0_bits_raw[31:20]; // @[RocketCore.scala 650:24:freechips.rocketchip.system.TinyConfig.fir@125089.4] assign csr_io_exception = _T_914 | _T_909; // @[RocketCore.scala 651:20:freechips.rocketchip.system.TinyConfig.fir@125090.4] assign csr_io_retire = _T_942 & _T_943; // @[RocketCore.scala 653:17:freechips.rocketchip.system.TinyConfig.fir@125092.4] assign csr_io_cause = wb_reg_xcpt ? wb_reg_cause : {{28'd0}, _T_919}; // @[RocketCore.scala 652:16:freechips.rocketchip.system.TinyConfig.fir@125091.4] assign csr_io_pc = wb_reg_pc; // @[RocketCore.scala 660:13:freechips.rocketchip.system.TinyConfig.fir@125105.4] assign csr_io_tval = tval_valid ? wb_reg_wdata : 32'h0; // @[RocketCore.scala 665:15:freechips.rocketchip.system.TinyConfig.fir@125127.4] assign csr_io_inst_0 = {_T_960,_T_961}; // @[RocketCore.scala 654:18:freechips.rocketchip.system.TinyConfig.fir@125099.4] assign bpu_io_status_debug = csr_io_status_debug; // @[RocketCore.scala 299:17:freechips.rocketchip.system.TinyConfig.fir@124321.4] assign bpu_io_bp_0_control_action = csr_io_bp_0_control_action; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_bp_0_control_tmatch = csr_io_bp_0_control_tmatch; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_bp_0_control_x = csr_io_bp_0_control_x; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_bp_0_control_w = csr_io_bp_0_control_w; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_bp_0_control_r = csr_io_bp_0_control_r; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_bp_0_address = csr_io_bp_0_address; // @[RocketCore.scala 300:13:freechips.rocketchip.system.TinyConfig.fir@124322.4] assign bpu_io_pc = ibuf_io_pc; // @[RocketCore.scala 301:13:freechips.rocketchip.system.TinyConfig.fir@124323.4] assign bpu_io_ea = mem_reg_wdata; // @[RocketCore.scala 302:13:freechips.rocketchip.system.TinyConfig.fir@124324.4] assign alu_io_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 360:13:freechips.rocketchip.system.TinyConfig.fir@124472.4] assign alu_io_in2 = $unsigned(ex_op2); // @[RocketCore.scala 361:14:freechips.rocketchip.system.TinyConfig.fir@124474.4] assign alu_io_in1 = $unsigned(ex_op1); // @[RocketCore.scala 362:14:freechips.rocketchip.system.TinyConfig.fir@124476.4] assign div_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@124479.4] assign div_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@124480.4] assign div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala 383:20:freechips.rocketchip.system.TinyConfig.fir@124482.4] assign div_io_req_bits_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 385:22:freechips.rocketchip.system.TinyConfig.fir@124484.4] assign div_io_req_bits_in1 = ex_reg_rs_bypass_0 ? _T_471 : _T_472; // @[RocketCore.scala 386:23:freechips.rocketchip.system.TinyConfig.fir@124485.4] assign div_io_req_bits_in2 = ex_reg_rs_bypass_1 ? _T_478 : _T_479; // @[RocketCore.scala 387:23:freechips.rocketchip.system.TinyConfig.fir@124486.4] assign div_io_req_bits_tag = ex_reg_inst[11:7]; // @[RocketCore.scala 388:23:freechips.rocketchip.system.TinyConfig.fir@124487.4] assign div_io_kill = killm_common & _T_882; // @[RocketCore.scala 556:15:freechips.rocketchip.system.TinyConfig.fir@124950.4] assign div_io_resp_ready = _T_940 ? 1'h0 : _T_1136; // @[RocketCore.scala 616:21:freechips.rocketchip.system.TinyConfig.fir@125039.4 RocketCore.scala 630:23:freechips.rocketchip.system.TinyConfig.fir@125052.6] assign PlusArgTimeout_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125519.4] assign PlusArgTimeout_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125520.4] assign PlusArgTimeout_io_count = csr_io_time; // @[PlusArg.scala 53:82:freechips.rocketchip.system.TinyConfig.fir@125521.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 31; initvar = initvar+1) _T_288[initvar] = _RAND_0[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; id_reg_pause = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; imem_might_request_reg = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; ex_ctrl_branch = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; ex_ctrl_jal = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; ex_ctrl_jalr = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; ex_ctrl_rxs2 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; ex_ctrl_sel_alu2 = _RAND_9[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; ex_ctrl_sel_alu1 = _RAND_10[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; ex_ctrl_sel_imm = _RAND_11[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; ex_ctrl_alu_fn = _RAND_12[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; ex_ctrl_mem = _RAND_13[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; ex_ctrl_mem_cmd = _RAND_14[4:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; ex_ctrl_div = _RAND_15[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; ex_ctrl_wxd = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; ex_ctrl_csr = _RAND_17[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; ex_ctrl_fence_i = _RAND_18[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; mem_ctrl_branch = _RAND_19[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; mem_ctrl_jal = _RAND_20[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; mem_ctrl_jalr = _RAND_21[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; mem_ctrl_mem = _RAND_22[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; mem_ctrl_div = _RAND_23[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_24 = {1{`RANDOM}}; mem_ctrl_wxd = _RAND_24[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_25 = {1{`RANDOM}}; mem_ctrl_csr = _RAND_25[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_26 = {1{`RANDOM}}; mem_ctrl_fence_i = _RAND_26[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_27 = {1{`RANDOM}}; wb_ctrl_mem = _RAND_27[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_28 = {1{`RANDOM}}; wb_ctrl_div = _RAND_28[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_29 = {1{`RANDOM}}; wb_ctrl_wxd = _RAND_29[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_30 = {1{`RANDOM}}; wb_ctrl_csr = _RAND_30[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_31 = {1{`RANDOM}}; wb_ctrl_fence_i = _RAND_31[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_32 = {1{`RANDOM}}; ex_reg_xcpt_interrupt = _RAND_32[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_33 = {1{`RANDOM}}; ex_reg_valid = _RAND_33[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_34 = {1{`RANDOM}}; ex_reg_rvc = _RAND_34[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_35 = {1{`RANDOM}}; ex_reg_xcpt = _RAND_35[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_36 = {1{`RANDOM}}; ex_reg_flush_pipe = _RAND_36[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_37 = {1{`RANDOM}}; ex_reg_load_use = _RAND_37[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_38 = {1{`RANDOM}}; ex_reg_cause = _RAND_38[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_39 = {1{`RANDOM}}; ex_reg_replay = _RAND_39[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_40 = {1{`RANDOM}}; ex_reg_pc = _RAND_40[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_41 = {1{`RANDOM}}; ex_reg_mem_size = _RAND_41[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_42 = {1{`RANDOM}}; ex_reg_inst = _RAND_42[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_43 = {1{`RANDOM}}; ex_reg_raw_inst = _RAND_43[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_44 = {1{`RANDOM}}; mem_reg_xcpt_interrupt = _RAND_44[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_45 = {1{`RANDOM}}; mem_reg_valid = _RAND_45[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_46 = {1{`RANDOM}}; mem_reg_rvc = _RAND_46[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_47 = {1{`RANDOM}}; mem_reg_xcpt = _RAND_47[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_48 = {1{`RANDOM}}; mem_reg_replay = _RAND_48[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_49 = {1{`RANDOM}}; mem_reg_flush_pipe = _RAND_49[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_50 = {1{`RANDOM}}; mem_reg_cause = _RAND_50[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_51 = {1{`RANDOM}}; mem_reg_slow_bypass = _RAND_51[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_52 = {1{`RANDOM}}; mem_reg_load = _RAND_52[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_53 = {1{`RANDOM}}; mem_reg_store = _RAND_53[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_54 = {1{`RANDOM}}; mem_reg_pc = _RAND_54[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_55 = {1{`RANDOM}}; mem_reg_inst = _RAND_55[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_56 = {1{`RANDOM}}; mem_reg_raw_inst = _RAND_56[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_57 = {1{`RANDOM}}; mem_reg_wdata = _RAND_57[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_58 = {1{`RANDOM}}; mem_reg_rs2 = _RAND_58[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_59 = {1{`RANDOM}}; mem_br_taken = _RAND_59[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_60 = {1{`RANDOM}}; wb_reg_valid = _RAND_60[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_61 = {1{`RANDOM}}; wb_reg_xcpt = _RAND_61[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_62 = {1{`RANDOM}}; wb_reg_replay = _RAND_62[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_63 = {1{`RANDOM}}; wb_reg_flush_pipe = _RAND_63[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_64 = {1{`RANDOM}}; wb_reg_cause = _RAND_64[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_65 = {1{`RANDOM}}; wb_reg_pc = _RAND_65[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_66 = {1{`RANDOM}}; wb_reg_inst = _RAND_66[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_67 = {1{`RANDOM}}; wb_reg_raw_inst = _RAND_67[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_68 = {1{`RANDOM}}; wb_reg_wdata = _RAND_68[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_69 = {1{`RANDOM}}; id_reg_fence = _RAND_69[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_70 = {1{`RANDOM}}; ex_reg_rs_bypass_0 = _RAND_70[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_71 = {1{`RANDOM}}; ex_reg_rs_bypass_1 = _RAND_71[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_72 = {1{`RANDOM}}; ex_reg_rs_lsb_0 = _RAND_72[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_73 = {1{`RANDOM}}; ex_reg_rs_lsb_1 = _RAND_73[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_74 = {1{`RANDOM}}; ex_reg_rs_msb_0 = _RAND_74[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_75 = {1{`RANDOM}}; ex_reg_rs_msb_1 = _RAND_75[29:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_76 = {1{`RANDOM}}; _T_993 = _RAND_76[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_77 = {1{`RANDOM}}; blocked = _RAND_77[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_78 = {1{`RANDOM}}; _T_882 = _RAND_78[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_79 = {1{`RANDOM}}; _T_1232 = _RAND_79[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_80 = {1{`RANDOM}}; coreMonitorBundle_rd0val = _RAND_80[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_81 = {1{`RANDOM}}; _T_1235 = _RAND_81[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_82 = {1{`RANDOM}}; coreMonitorBundle_rd1val = _RAND_82[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_288__T_953_en & _T_288__T_953_mask) begin _T_288[_T_288__T_953_addr] <= _T_288__T_953_data; // @[RocketCore.scala 943:15:freechips.rocketchip.system.TinyConfig.fir@124137.4] end if (unpause) begin id_reg_pause <= 1'h0; end else begin if (_T_556) begin if (_T_569) begin id_reg_pause <= 1'h1; end end end imem_might_request_reg <= _T_1159 | _T_1160; if (_T_556) begin ex_ctrl_branch <= id_ctrl_branch; end if (_T_556) begin ex_ctrl_jal <= id_ctrl_jal; end if (_T_556) begin ex_ctrl_jalr <= id_ctrl_jalr; end if (_T_556) begin ex_ctrl_rxs2 <= id_ctrl_rxs2; end if (_T_556) begin if (id_xcpt) begin if (_T_574) begin ex_ctrl_sel_alu2 <= 2'h0; end else begin if (_T_571) begin ex_ctrl_sel_alu2 <= 2'h1; end else begin ex_ctrl_sel_alu2 <= 2'h0; end end end else begin ex_ctrl_sel_alu2 <= id_ctrl_sel_alu2; end end if (_T_556) begin if (id_xcpt) begin if (_T_574) begin ex_ctrl_sel_alu1 <= 2'h2; end else begin if (_T_571) begin ex_ctrl_sel_alu1 <= 2'h2; end else begin ex_ctrl_sel_alu1 <= 2'h1; end end end else begin ex_ctrl_sel_alu1 <= id_ctrl_sel_alu1; end end if (_T_556) begin ex_ctrl_sel_imm <= id_ctrl_sel_imm; end if (_T_556) begin if (id_xcpt) begin ex_ctrl_alu_fn <= 4'h0; end else begin ex_ctrl_alu_fn <= id_ctrl_alu_fn; end end if (_T_556) begin ex_ctrl_mem <= id_ctrl_mem; end if (_T_556) begin ex_ctrl_mem_cmd <= id_ctrl_mem_cmd; end if (_T_556) begin ex_ctrl_div <= id_ctrl_div; end if (_T_556) begin ex_ctrl_wxd <= id_ctrl_wxd; end if (_T_556) begin if (id_csr_ren) begin ex_ctrl_csr <= 3'h2; end else begin ex_ctrl_csr <= id_ctrl_csr; end end if (_T_556) begin ex_ctrl_fence_i <= id_ctrl_fence_i; end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_branch <= ex_ctrl_branch; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_jal <= ex_ctrl_jal; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_jalr <= ex_ctrl_jalr; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_mem <= ex_ctrl_mem; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_div <= ex_ctrl_div; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_wxd <= ex_ctrl_wxd; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_ctrl_csr <= ex_ctrl_csr; end end if (!(_T_792)) begin if (ex_pc_valid) begin if (_T_855) begin mem_ctrl_fence_i <= 1'h1; end else begin mem_ctrl_fence_i <= ex_ctrl_fence_i; end end end if (mem_pc_valid) begin wb_ctrl_mem <= mem_ctrl_mem; end if (mem_pc_valid) begin wb_ctrl_div <= mem_ctrl_div; end if (mem_pc_valid) begin wb_ctrl_wxd <= mem_ctrl_wxd; end if (mem_pc_valid) begin wb_ctrl_csr <= mem_ctrl_csr; end if (mem_pc_valid) begin wb_ctrl_fence_i <= mem_ctrl_fence_i; end ex_reg_xcpt_interrupt <= _T_558 & csr_io_interrupt; ex_reg_valid <= ctrl_killd == 1'h0; if (_T_556) begin if (id_xcpt) begin if (_T_571) begin ex_reg_rvc <= 1'h1; end else begin ex_reg_rvc <= ibuf_io_inst_0_bits_rvc; end end else begin ex_reg_rvc <= ibuf_io_inst_0_bits_rvc; end end ex_reg_xcpt <= _T_556 & id_xcpt; if (_T_556) begin ex_reg_flush_pipe <= _T_575; end if (_T_556) begin ex_reg_load_use <= id_load_use; end if (_T_604) begin if (csr_io_interrupt) begin ex_reg_cause <= csr_io_interrupt_cause; end else begin ex_reg_cause <= {{28'd0}, _T_444}; end end ex_reg_replay <= _T_558 & ibuf_io_inst_0_bits_replay; if (_T_604) begin ex_reg_pc <= ibuf_io_pc; end if (_T_556) begin if (_T_579) begin ex_reg_mem_size <= _T_582; end else begin ex_reg_mem_size <= _T_576; end end if (_T_604) begin ex_reg_inst <= ibuf_io_inst_0_bits_inst_bits; end if (_T_604) begin ex_reg_raw_inst <= ibuf_io_inst_0_bits_raw; end mem_reg_xcpt_interrupt <= _T_557 & ex_reg_xcpt_interrupt; mem_reg_valid <= ctrl_killx == 1'h0; if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_rvc <= ex_reg_rvc; end end mem_reg_xcpt <= _T_785 & ex_xcpt; mem_reg_replay <= _T_557 & replay_ex; if (!(_T_792)) begin if (ex_pc_valid) begin if (_T_855) begin mem_reg_flush_pipe <= 1'h1; end else begin mem_reg_flush_pipe <= ex_reg_flush_pipe; end end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_cause <= ex_reg_cause; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_slow_bypass <= ex_slow_bypass; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_load <= _T_816; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_store <= _T_840; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_pc <= ex_reg_pc; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_inst <= ex_reg_inst; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_raw_inst <= ex_reg_raw_inst; end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_reg_wdata <= _T_841; end end if (!(_T_792)) begin if (ex_pc_valid) begin if (_T_844) begin if (_T_846) begin mem_reg_rs2 <= _T_849; end else begin if (_T_850) begin mem_reg_rs2 <= _T_852; end else begin if (ex_reg_rs_bypass_1) begin if (_T_477) begin mem_reg_rs2 <= io_dmem_resp_bits_data_word_bypass; end else begin if (_T_475) begin mem_reg_rs2 <= wb_reg_wdata; end else begin if (_T_473) begin mem_reg_rs2 <= mem_reg_wdata; end else begin mem_reg_rs2 <= 32'h0; end end end end else begin mem_reg_rs2 <= _T_479; end end end end end end if (!(_T_792)) begin if (ex_pc_valid) begin mem_br_taken <= alu_io_cmp_out; end end wb_reg_valid <= ctrl_killm == 1'h0; wb_reg_xcpt <= mem_xcpt & _T_886; wb_reg_replay <= replay_mem & _T_886; wb_reg_flush_pipe <= _T_885 & mem_reg_flush_pipe; if (mem_pc_valid) begin if (_T_860) begin wb_reg_cause <= mem_reg_cause; end else begin wb_reg_cause <= {{28'd0}, _T_864}; end end if (mem_pc_valid) begin wb_reg_pc <= mem_reg_pc; end if (mem_pc_valid) begin wb_reg_inst <= mem_reg_inst; end if (mem_pc_valid) begin wb_reg_raw_inst <= mem_reg_raw_inst; end if (mem_pc_valid) begin wb_reg_wdata <= mem_int_wdata; end if (reset) begin id_reg_fence <= 1'h0; end else begin if (_T_556) begin if (id_fence_next) begin id_reg_fence <= 1'h1; end else begin if (_T_418) begin id_reg_fence <= 1'h0; end end end else begin if (_T_418) begin id_reg_fence <= 1'h0; end end end if (_T_556) begin if (id_illegal_insn) begin ex_reg_rs_bypass_0 <= 1'h0; end else begin ex_reg_rs_bypass_0 <= do_bypass; end end if (_T_556) begin ex_reg_rs_bypass_1 <= do_bypass_1; end if (_T_556) begin if (id_illegal_insn) begin ex_reg_rs_lsb_0 <= _T_600; end else begin if (_T_588) begin ex_reg_rs_lsb_0 <= _T_589; end else begin if (id_bypass_src_0_0) begin ex_reg_rs_lsb_0 <= 2'h0; end else begin if (id_bypass_src_0_1) begin ex_reg_rs_lsb_0 <= 2'h1; end else begin if (id_bypass_src_0_2) begin ex_reg_rs_lsb_0 <= 2'h2; end else begin ex_reg_rs_lsb_0 <= 2'h3; end end end end end end if (_T_556) begin if (_T_596) begin ex_reg_rs_lsb_1 <= _T_597; end else begin if (id_bypass_src_1_0) begin ex_reg_rs_lsb_1 <= 2'h0; end else begin if (id_bypass_src_1_1) begin ex_reg_rs_lsb_1 <= 2'h1; end else begin if (id_bypass_src_1_2) begin ex_reg_rs_lsb_1 <= 2'h2; end else begin ex_reg_rs_lsb_1 <= 2'h3; end end end end end if (_T_556) begin if (id_illegal_insn) begin ex_reg_rs_msb_0 <= _T_601; end else begin if (_T_588) begin ex_reg_rs_msb_0 <= _T_590; end end end if (_T_556) begin if (_T_596) begin ex_reg_rs_msb_1 <= _T_598; end end if (reset) begin _T_993 <= 32'h0; end else begin if (_T_1027) begin _T_993 <= _T_1026; end else begin if (ll_wen) begin _T_993 <= _T_999; end end end blocked <= _T_1109 & _T_1111; _T_882 <= div_io_req_ready & div_io_req_valid; if (ex_reg_rs_bypass_0) begin if (_T_470) begin _T_1232 <= io_dmem_resp_bits_data_word_bypass; end else begin if (_T_468) begin _T_1232 <= wb_reg_wdata; end else begin if (_T_466) begin _T_1232 <= mem_reg_wdata; end else begin _T_1232 <= 32'h0; end end end end else begin _T_1232 <= _T_472; end coreMonitorBundle_rd0val <= _T_1232; if (ex_reg_rs_bypass_1) begin if (_T_477) begin _T_1235 <= io_dmem_resp_bits_data_word_bypass; end else begin if (_T_475) begin _T_1235 <= wb_reg_wdata; end else begin if (_T_473) begin _T_1235 <= mem_reg_wdata; end else begin _T_1235 <= 32'h0; end end end end else begin _T_1235 <= _T_479; end coreMonitorBundle_rd1val <= _T_1235; `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_1238) begin $fwrite(32'h80000002,"C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",1'h0,coreMonitorBundle_timer,coreMonitorBundle_valid,coreMonitorBundle_pc,coreMonitorBundle_wrdst,rf_wdata,rf_wen,_T_1213,coreMonitorBundle_rd0val,_T_1214,coreMonitorBundle_rd1val,coreMonitorBundle_inst,coreMonitorBundle_inst); // @[RocketCore.scala 885:11:freechips.rocketchip.system.TinyConfig.fir@125516.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS end endmodule module RocketTile( // @[:freechips.rocketchip.system.TinyConfig.fir@125523.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125524.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@125525.4] input auto_intsink_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_int_in_xing_in_1_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_int_in_xing_in_0_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_int_in_xing_in_0_sync_1, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_slave_xing_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_slave_xing_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [2:0] auto_tl_slave_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [2:0] auto_tl_slave_xing_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [2:0] auto_tl_slave_xing_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [4:0] auto_tl_slave_xing_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [31:0] auto_tl_slave_xing_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [3:0] auto_tl_slave_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [31:0] auto_tl_slave_xing_in_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_slave_xing_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_slave_xing_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [2:0] auto_tl_slave_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [1:0] auto_tl_slave_xing_in_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [2:0] auto_tl_slave_xing_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [4:0] auto_tl_slave_xing_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_slave_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_slave_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [31:0] auto_tl_slave_xing_in_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_slave_xing_in_d_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_master_xing_out_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [2:0] auto_tl_master_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [2:0] auto_tl_master_xing_out_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [3:0] auto_tl_master_xing_out_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_master_xing_out_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [31:0] auto_tl_master_xing_out_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [3:0] auto_tl_master_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output [31:0] auto_tl_master_xing_out_a_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_master_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] output auto_tl_master_xing_out_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [2:0] auto_tl_master_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [1:0] auto_tl_master_xing_out_d_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [3:0] auto_tl_master_xing_out_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input [31:0] auto_tl_master_xing_out_d_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] input auto_tl_master_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.TinyConfig.fir@125526.4] ); wire tlMasterXbar_clock; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_reset; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_1_a_ready; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_1_a_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_in_1_a_bits_address; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_1_d_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_in_1_d_bits_opcode; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_in_1_d_bits_size; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_in_1_d_bits_data; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_1_d_bits_corrupt; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_0_a_ready; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_0_a_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_in_0_a_bits_opcode; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_in_0_a_bits_param; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_in_0_a_bits_size; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_in_0_a_bits_address; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_in_0_a_bits_mask; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_in_0_a_bits_data; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_0_d_ready; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_0_d_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_in_0_d_bits_opcode; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_in_0_d_bits_size; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_in_0_d_bits_denied; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_in_0_d_bits_data; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_a_ready; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_a_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_out_a_bits_param; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_out_a_bits_size; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_a_bits_source; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_out_a_bits_address; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_out_a_bits_mask; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_out_a_bits_data; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_a_bits_corrupt; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_ready; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_valid; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [2:0] tlMasterXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [1:0] tlMasterXbar_auto_out_d_bits_param; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [3:0] tlMasterXbar_auto_out_d_bits_size; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_bits_source; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_bits_sink; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_bits_denied; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire [31:0] tlMasterXbar_auto_out_d_bits_data; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlMasterXbar_auto_out_d_bits_corrupt; // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] wire tlSlaveXbar_auto_in_a_ready; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_in_a_valid; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_in_a_bits_opcode; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_in_a_bits_param; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_in_a_bits_size; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [4:0] tlSlaveXbar_auto_in_a_bits_source; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_in_a_bits_address; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [3:0] tlSlaveXbar_auto_in_a_bits_mask; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_in_a_bits_data; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_in_d_ready; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_in_d_valid; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_in_d_bits_opcode; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_in_d_bits_size; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [4:0] tlSlaveXbar_auto_in_d_bits_source; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_in_d_bits_data; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_out_a_ready; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_out_a_valid; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_out_a_bits_param; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_out_a_bits_size; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [4:0] tlSlaveXbar_auto_out_a_bits_source; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_out_a_bits_address; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [3:0] tlSlaveXbar_auto_out_a_bits_mask; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_out_a_bits_data; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_out_d_ready; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire tlSlaveXbar_auto_out_d_valid; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [2:0] tlSlaveXbar_auto_out_d_bits_size; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [4:0] tlSlaveXbar_auto_out_d_bits_source; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire [31:0] tlSlaveXbar_auto_out_d_bits_data; // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] wire intXbar_auto_int_in_2_0; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_in_1_0; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_in_1_1; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_in_0_0; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_out_0; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_out_1; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_out_2; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire intXbar_auto_int_out_3; // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] wire dcache_gated_clock; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_reset; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_auto_out_a_ready; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_auto_out_a_valid; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [2:0] dcache_auto_out_a_bits_opcode; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [2:0] dcache_auto_out_a_bits_param; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [3:0] dcache_auto_out_a_bits_size; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_auto_out_a_bits_address; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [3:0] dcache_auto_out_a_bits_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_auto_out_a_bits_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_auto_out_d_ready; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_auto_out_d_valid; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [2:0] dcache_auto_out_d_bits_opcode; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [3:0] dcache_auto_out_d_bits_size; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_auto_out_d_bits_denied; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_auto_out_d_bits_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_req_ready; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_req_valid; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_req_bits_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [6:0] dcache_io_cpu_req_bits_tag; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [4:0] dcache_io_cpu_req_bits_cmd; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_cpu_req_bits_size; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_req_bits_signed; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_req_bits_phys; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s1_kill; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_s1_data_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [3:0] dcache_io_cpu_s1_data_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_nack; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_resp_valid; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [6:0] dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [4:0] dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_cpu_resp_bits_size; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_replay_next; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_ordered; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_cpu_perf_grant; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_0_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_0_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_0_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_0_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_0_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_0_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_0_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_1_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_1_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_1_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_1_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_1_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_1_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_1_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_2_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_2_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_2_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_2_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_2_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_2_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_2_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_3_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_3_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_3_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_3_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_3_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_3_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_3_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_4_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_4_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_4_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_4_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_4_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_4_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_4_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_5_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_5_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_5_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_5_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_5_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_5_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_5_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_6_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_6_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_6_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_6_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_6_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_6_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_6_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_7_cfg_l; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [1:0] dcache_io_ptw_pmp_7_cfg_a; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_7_cfg_x; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_7_cfg_w; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire dcache_io_ptw_pmp_7_cfg_r; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [29:0] dcache_io_ptw_pmp_7_addr; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire [31:0] dcache_io_ptw_pmp_7_mask; // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] wire frontend_gated_clock; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_reset; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_auto_icache_master_out_a_ready; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_auto_icache_master_out_a_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_auto_icache_master_out_a_bits_address; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_auto_icache_master_out_d_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [2:0] frontend_auto_icache_master_out_d_bits_opcode; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [3:0] frontend_auto_icache_master_out_d_bits_size; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_auto_icache_master_out_d_bits_data; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_might_request; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_req_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_cpu_req_bits_pc; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_req_bits_speculative; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_resp_ready; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_resp_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_cpu_resp_bits_pc; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_cpu_resp_bits_data; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_resp_bits_replay; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_btb_update_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_bht_update_valid; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_cpu_flush_icache; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_cpu_npc; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_0_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_0_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_0_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_0_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_1_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_1_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_1_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_1_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_2_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_2_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_2_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_2_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_3_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_3_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_3_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_3_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_4_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_4_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_4_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_4_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_5_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_5_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_5_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_5_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_6_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_6_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_6_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_6_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [1:0] frontend_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_7_cfg_w; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire frontend_io_ptw_pmp_7_cfg_r; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [29:0] frontend_io_ptw_pmp_7_addr; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire [31:0] frontend_io_ptw_pmp_7_mask; // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] wire dtim_adapter_clock; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_reset; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_auto_in_a_ready; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_auto_in_a_valid; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [2:0] dtim_adapter_auto_in_a_bits_opcode; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [2:0] dtim_adapter_auto_in_a_bits_param; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [1:0] dtim_adapter_auto_in_a_bits_size; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [10:0] dtim_adapter_auto_in_a_bits_source; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_auto_in_a_bits_address; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [3:0] dtim_adapter_auto_in_a_bits_mask; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_auto_in_a_bits_data; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_auto_in_d_ready; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_auto_in_d_valid; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [2:0] dtim_adapter_auto_in_d_bits_opcode; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [1:0] dtim_adapter_auto_in_d_bits_size; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [10:0] dtim_adapter_auto_in_d_bits_source; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_auto_in_d_bits_data; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_io_dmem_req_ready; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_io_dmem_req_valid; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_io_dmem_req_bits_addr; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [4:0] dtim_adapter_io_dmem_req_bits_cmd; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [1:0] dtim_adapter_io_dmem_req_bits_size; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_io_dmem_s1_kill; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_io_dmem_s1_data_data; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [3:0] dtim_adapter_io_dmem_s1_data_mask; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_io_dmem_s2_nack; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire dtim_adapter_io_dmem_resp_valid; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire [31:0] dtim_adapter_io_dmem_resp_bits_data_raw; // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] wire fragmenter_1_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [4:0] fragmenter_1_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [3:0] fragmenter_1_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [4:0] fragmenter_1_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [1:0] fragmenter_1_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [10:0] fragmenter_1_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [3:0] fragmenter_1_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire fragmenter_1_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [2:0] fragmenter_1_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [1:0] fragmenter_1_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [10:0] fragmenter_1_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire [31:0] fragmenter_1_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] wire buffer_1_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [4:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [3:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [4:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [4:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [3:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire buffer_1_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [4:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire [31:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] wire intsink_clock; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125608.4] wire intsink_auto_in_sync_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125608.4] wire intsink_auto_out_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125608.4] wire intsink_1_auto_in_sync_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125614.4] wire intsink_1_auto_in_sync_1; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125614.4] wire intsink_1_auto_out_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125614.4] wire intsink_1_auto_out_1; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125614.4] wire intsink_2_auto_in_sync_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125620.4] wire intsink_2_auto_out_0; // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125620.4] wire dcacheArb_clock; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_req_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_0_req_bits_addr; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [6:0] dcacheArb_io_requestor_0_req_bits_tag; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [4:0] dcacheArb_io_requestor_0_req_bits_cmd; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [1:0] dcacheArb_io_requestor_0_req_bits_size; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_req_bits_signed; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s1_kill; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_0_s1_data_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [6:0] dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_1_req_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_1_req_bits_addr; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [4:0] dcacheArb_io_requestor_1_req_bits_cmd; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [1:0] dcacheArb_io_requestor_1_req_bits_size; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_1_s1_kill; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_1_s1_data_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [3:0] dcacheArb_io_requestor_1_s1_data_mask; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_req_ready; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_req_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [6:0] dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [4:0] dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [1:0] dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [3:0] dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_nack; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_resp_valid; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [6:0] dcacheArb_io_mem_resp_bits_tag; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_mem_resp_bits_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_resp_bits_replay; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_resp_bits_has_data; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_mem_resp_bits_data_word_bypass; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire [31:0] dcacheArb_io_mem_resp_bits_data_raw; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_replay_next; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_ma_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_ma_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_pf_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_pf_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_ae_ld; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_s2_xcpt_ae_st; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_ordered; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire dcacheArb_io_mem_perf_grant; // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] wire ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_0_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_0_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_0_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_0_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_0_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_0_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_0_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_1_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_1_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_1_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_1_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_1_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_1_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_1_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_2_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_2_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_2_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_2_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_2_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_2_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_2_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_3_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_3_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_3_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_3_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_3_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_3_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_3_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_4_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_4_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_4_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_4_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_4_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_4_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_4_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_5_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_5_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_5_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_5_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_5_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_5_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_5_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_6_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_6_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_6_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_6_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_6_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_6_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_6_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_7_cfg_l; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [1:0] ptw_io_dpath_pmp_7_cfg_a; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_7_cfg_x; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_7_cfg_w; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire ptw_io_dpath_pmp_7_cfg_r; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [29:0] ptw_io_dpath_pmp_7_addr; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire [31:0] ptw_io_dpath_pmp_7_mask; // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] wire core_clock; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_reset; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_interrupts_debug; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_interrupts_mtip; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_interrupts_msip; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_interrupts_meip; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_might_request; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_req_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_imem_req_bits_pc; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_req_bits_speculative; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_resp_ready; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_resp_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_imem_resp_bits_pc; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_imem_resp_bits_data; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_resp_bits_replay; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_btb_update_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_bht_update_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_imem_flush_icache; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_req_ready; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_req_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_dmem_req_bits_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [6:0] core_io_dmem_req_bits_tag; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [4:0] core_io_dmem_req_bits_cmd; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_dmem_req_bits_size; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_req_bits_signed; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s1_kill; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_dmem_s1_data_data; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_nack; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_resp_valid; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [6:0] core_io_dmem_resp_bits_tag; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_dmem_resp_bits_data; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_resp_bits_replay; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_resp_bits_has_data; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_dmem_resp_bits_data_word_bypass; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_replay_next; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_ma_ld; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_ma_st; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_pf_ld; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_pf_st; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_ae_ld; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_s2_xcpt_ae_st; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_ordered; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_dmem_perf_grant; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_0_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_0_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_1_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_1_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_2_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_2_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_3_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_3_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_4_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_4_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_5_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_5_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_6_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_6_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [1:0] core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [29:0] core_io_ptw_pmp_7_addr; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_pmp_7_mask; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] wire [31:0] core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] TLXbar_8 tlMasterXbar ( // @[BaseTile.scala 169:42:freechips.rocketchip.system.TinyConfig.fir@125533.4] .clock(tlMasterXbar_clock), .reset(tlMasterXbar_reset), .auto_in_1_a_ready(tlMasterXbar_auto_in_1_a_ready), .auto_in_1_a_valid(tlMasterXbar_auto_in_1_a_valid), .auto_in_1_a_bits_address(tlMasterXbar_auto_in_1_a_bits_address), .auto_in_1_d_valid(tlMasterXbar_auto_in_1_d_valid), .auto_in_1_d_bits_opcode(tlMasterXbar_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_size(tlMasterXbar_auto_in_1_d_bits_size), .auto_in_1_d_bits_data(tlMasterXbar_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt(tlMasterXbar_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready(tlMasterXbar_auto_in_0_a_ready), .auto_in_0_a_valid(tlMasterXbar_auto_in_0_a_valid), .auto_in_0_a_bits_opcode(tlMasterXbar_auto_in_0_a_bits_opcode), .auto_in_0_a_bits_param(tlMasterXbar_auto_in_0_a_bits_param), .auto_in_0_a_bits_size(tlMasterXbar_auto_in_0_a_bits_size), .auto_in_0_a_bits_address(tlMasterXbar_auto_in_0_a_bits_address), .auto_in_0_a_bits_mask(tlMasterXbar_auto_in_0_a_bits_mask), .auto_in_0_a_bits_data(tlMasterXbar_auto_in_0_a_bits_data), .auto_in_0_d_ready(tlMasterXbar_auto_in_0_d_ready), .auto_in_0_d_valid(tlMasterXbar_auto_in_0_d_valid), .auto_in_0_d_bits_opcode(tlMasterXbar_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size(tlMasterXbar_auto_in_0_d_bits_size), .auto_in_0_d_bits_denied(tlMasterXbar_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data(tlMasterXbar_auto_in_0_d_bits_data), .auto_out_a_ready(tlMasterXbar_auto_out_a_ready), .auto_out_a_valid(tlMasterXbar_auto_out_a_valid), .auto_out_a_bits_opcode(tlMasterXbar_auto_out_a_bits_opcode), .auto_out_a_bits_param(tlMasterXbar_auto_out_a_bits_param), .auto_out_a_bits_size(tlMasterXbar_auto_out_a_bits_size), .auto_out_a_bits_source(tlMasterXbar_auto_out_a_bits_source), .auto_out_a_bits_address(tlMasterXbar_auto_out_a_bits_address), .auto_out_a_bits_mask(tlMasterXbar_auto_out_a_bits_mask), .auto_out_a_bits_data(tlMasterXbar_auto_out_a_bits_data), .auto_out_a_bits_corrupt(tlMasterXbar_auto_out_a_bits_corrupt), .auto_out_d_ready(tlMasterXbar_auto_out_d_ready), .auto_out_d_valid(tlMasterXbar_auto_out_d_valid), .auto_out_d_bits_opcode(tlMasterXbar_auto_out_d_bits_opcode), .auto_out_d_bits_param(tlMasterXbar_auto_out_d_bits_param), .auto_out_d_bits_size(tlMasterXbar_auto_out_d_bits_size), .auto_out_d_bits_source(tlMasterXbar_auto_out_d_bits_source), .auto_out_d_bits_sink(tlMasterXbar_auto_out_d_bits_sink), .auto_out_d_bits_denied(tlMasterXbar_auto_out_d_bits_denied), .auto_out_d_bits_data(tlMasterXbar_auto_out_d_bits_data), .auto_out_d_bits_corrupt(tlMasterXbar_auto_out_d_bits_corrupt) ); TLXbar_9 tlSlaveXbar ( // @[BaseTile.scala 170:41:freechips.rocketchip.system.TinyConfig.fir@125539.4] .auto_in_a_ready(tlSlaveXbar_auto_in_a_ready), .auto_in_a_valid(tlSlaveXbar_auto_in_a_valid), .auto_in_a_bits_opcode(tlSlaveXbar_auto_in_a_bits_opcode), .auto_in_a_bits_param(tlSlaveXbar_auto_in_a_bits_param), .auto_in_a_bits_size(tlSlaveXbar_auto_in_a_bits_size), .auto_in_a_bits_source(tlSlaveXbar_auto_in_a_bits_source), .auto_in_a_bits_address(tlSlaveXbar_auto_in_a_bits_address), .auto_in_a_bits_mask(tlSlaveXbar_auto_in_a_bits_mask), .auto_in_a_bits_data(tlSlaveXbar_auto_in_a_bits_data), .auto_in_d_ready(tlSlaveXbar_auto_in_d_ready), .auto_in_d_valid(tlSlaveXbar_auto_in_d_valid), .auto_in_d_bits_opcode(tlSlaveXbar_auto_in_d_bits_opcode), .auto_in_d_bits_size(tlSlaveXbar_auto_in_d_bits_size), .auto_in_d_bits_source(tlSlaveXbar_auto_in_d_bits_source), .auto_in_d_bits_data(tlSlaveXbar_auto_in_d_bits_data), .auto_out_a_ready(tlSlaveXbar_auto_out_a_ready), .auto_out_a_valid(tlSlaveXbar_auto_out_a_valid), .auto_out_a_bits_opcode(tlSlaveXbar_auto_out_a_bits_opcode), .auto_out_a_bits_param(tlSlaveXbar_auto_out_a_bits_param), .auto_out_a_bits_size(tlSlaveXbar_auto_out_a_bits_size), .auto_out_a_bits_source(tlSlaveXbar_auto_out_a_bits_source), .auto_out_a_bits_address(tlSlaveXbar_auto_out_a_bits_address), .auto_out_a_bits_mask(tlSlaveXbar_auto_out_a_bits_mask), .auto_out_a_bits_data(tlSlaveXbar_auto_out_a_bits_data), .auto_out_d_ready(tlSlaveXbar_auto_out_d_ready), .auto_out_d_valid(tlSlaveXbar_auto_out_d_valid), .auto_out_d_bits_opcode(tlSlaveXbar_auto_out_d_bits_opcode), .auto_out_d_bits_size(tlSlaveXbar_auto_out_d_bits_size), .auto_out_d_bits_source(tlSlaveXbar_auto_out_d_bits_source), .auto_out_d_bits_data(tlSlaveXbar_auto_out_d_bits_data) ); IntXbar_4 intXbar ( // @[BaseTile.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@125545.4] .auto_int_in_2_0(intXbar_auto_int_in_2_0), .auto_int_in_1_0(intXbar_auto_int_in_1_0), .auto_int_in_1_1(intXbar_auto_int_in_1_1), .auto_int_in_0_0(intXbar_auto_int_in_0_0), .auto_int_out_0(intXbar_auto_int_out_0), .auto_int_out_1(intXbar_auto_int_out_1), .auto_int_out_2(intXbar_auto_int_out_2), .auto_int_out_3(intXbar_auto_int_out_3) ); DCache dcache ( // @[HellaCache.scala 232:43:freechips.rocketchip.system.TinyConfig.fir@125563.4] .gated_clock(dcache_gated_clock), .reset(dcache_reset), .auto_out_a_ready(dcache_auto_out_a_ready), .auto_out_a_valid(dcache_auto_out_a_valid), .auto_out_a_bits_opcode(dcache_auto_out_a_bits_opcode), .auto_out_a_bits_param(dcache_auto_out_a_bits_param), .auto_out_a_bits_size(dcache_auto_out_a_bits_size), .auto_out_a_bits_address(dcache_auto_out_a_bits_address), .auto_out_a_bits_mask(dcache_auto_out_a_bits_mask), .auto_out_a_bits_data(dcache_auto_out_a_bits_data), .auto_out_d_ready(dcache_auto_out_d_ready), .auto_out_d_valid(dcache_auto_out_d_valid), .auto_out_d_bits_opcode(dcache_auto_out_d_bits_opcode), .auto_out_d_bits_size(dcache_auto_out_d_bits_size), .auto_out_d_bits_denied(dcache_auto_out_d_bits_denied), .auto_out_d_bits_data(dcache_auto_out_d_bits_data), .io_cpu_req_ready(dcache_io_cpu_req_ready), .io_cpu_req_valid(dcache_io_cpu_req_valid), .io_cpu_req_bits_addr(dcache_io_cpu_req_bits_addr), .io_cpu_req_bits_tag(dcache_io_cpu_req_bits_tag), .io_cpu_req_bits_cmd(dcache_io_cpu_req_bits_cmd), .io_cpu_req_bits_size(dcache_io_cpu_req_bits_size), .io_cpu_req_bits_signed(dcache_io_cpu_req_bits_signed), .io_cpu_req_bits_phys(dcache_io_cpu_req_bits_phys), .io_cpu_s1_kill(dcache_io_cpu_s1_kill), .io_cpu_s1_data_data(dcache_io_cpu_s1_data_data), .io_cpu_s1_data_mask(dcache_io_cpu_s1_data_mask), .io_cpu_s2_nack(dcache_io_cpu_s2_nack), .io_cpu_resp_valid(dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr(dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag(dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd(dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size(dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed(dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_data(dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_replay(dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data(dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass(dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw(dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data(dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next(dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld(dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st(dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld(dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st(dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld(dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st(dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_ordered(dcache_io_cpu_ordered), .io_cpu_perf_grant(dcache_io_cpu_perf_grant), .io_ptw_pmp_0_cfg_l(dcache_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a(dcache_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x(dcache_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w(dcache_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r(dcache_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr(dcache_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask(dcache_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l(dcache_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a(dcache_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x(dcache_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w(dcache_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r(dcache_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr(dcache_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask(dcache_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l(dcache_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a(dcache_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x(dcache_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w(dcache_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r(dcache_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr(dcache_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask(dcache_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l(dcache_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a(dcache_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x(dcache_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w(dcache_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r(dcache_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr(dcache_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask(dcache_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l(dcache_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a(dcache_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x(dcache_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w(dcache_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r(dcache_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr(dcache_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask(dcache_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l(dcache_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a(dcache_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x(dcache_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w(dcache_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r(dcache_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr(dcache_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask(dcache_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l(dcache_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a(dcache_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x(dcache_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w(dcache_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r(dcache_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr(dcache_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask(dcache_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l(dcache_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a(dcache_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x(dcache_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w(dcache_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r(dcache_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr(dcache_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask(dcache_io_ptw_pmp_7_mask) ); Frontend frontend ( // @[Frontend.scala 349:28:freechips.rocketchip.system.TinyConfig.fir@125570.4] .gated_clock(frontend_gated_clock), .reset(frontend_reset), .auto_icache_master_out_a_ready(frontend_auto_icache_master_out_a_ready), .auto_icache_master_out_a_valid(frontend_auto_icache_master_out_a_valid), .auto_icache_master_out_a_bits_address(frontend_auto_icache_master_out_a_bits_address), .auto_icache_master_out_d_valid(frontend_auto_icache_master_out_d_valid), .auto_icache_master_out_d_bits_opcode(frontend_auto_icache_master_out_d_bits_opcode), .auto_icache_master_out_d_bits_size(frontend_auto_icache_master_out_d_bits_size), .auto_icache_master_out_d_bits_data(frontend_auto_icache_master_out_d_bits_data), .auto_icache_master_out_d_bits_corrupt(frontend_auto_icache_master_out_d_bits_corrupt), .io_cpu_might_request(frontend_io_cpu_might_request), .io_cpu_req_valid(frontend_io_cpu_req_valid), .io_cpu_req_bits_pc(frontend_io_cpu_req_bits_pc), .io_cpu_req_bits_speculative(frontend_io_cpu_req_bits_speculative), .io_cpu_resp_ready(frontend_io_cpu_resp_ready), .io_cpu_resp_valid(frontend_io_cpu_resp_valid), .io_cpu_resp_bits_pc(frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data(frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_xcpt_ae_inst(frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay(frontend_io_cpu_resp_bits_replay), .io_cpu_btb_update_valid(frontend_io_cpu_btb_update_valid), .io_cpu_bht_update_valid(frontend_io_cpu_bht_update_valid), .io_cpu_flush_icache(frontend_io_cpu_flush_icache), .io_cpu_npc(frontend_io_cpu_npc), .io_ptw_pmp_0_cfg_l(frontend_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a(frontend_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x(frontend_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w(frontend_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r(frontend_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr(frontend_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask(frontend_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l(frontend_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a(frontend_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x(frontend_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w(frontend_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r(frontend_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr(frontend_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask(frontend_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l(frontend_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a(frontend_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x(frontend_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w(frontend_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r(frontend_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr(frontend_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask(frontend_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l(frontend_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a(frontend_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x(frontend_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w(frontend_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r(frontend_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr(frontend_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask(frontend_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l(frontend_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a(frontend_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x(frontend_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w(frontend_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r(frontend_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr(frontend_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask(frontend_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l(frontend_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a(frontend_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x(frontend_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w(frontend_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r(frontend_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr(frontend_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask(frontend_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l(frontend_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a(frontend_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x(frontend_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w(frontend_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r(frontend_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr(frontend_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask(frontend_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l(frontend_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a(frontend_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x(frontend_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w(frontend_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r(frontend_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr(frontend_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask(frontend_io_ptw_pmp_7_mask) ); ScratchpadSlavePort dtim_adapter ( // @[RocketTile.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@125583.4] .clock(dtim_adapter_clock), .reset(dtim_adapter_reset), .auto_in_a_ready(dtim_adapter_auto_in_a_ready), .auto_in_a_valid(dtim_adapter_auto_in_a_valid), .auto_in_a_bits_opcode(dtim_adapter_auto_in_a_bits_opcode), .auto_in_a_bits_param(dtim_adapter_auto_in_a_bits_param), .auto_in_a_bits_size(dtim_adapter_auto_in_a_bits_size), .auto_in_a_bits_source(dtim_adapter_auto_in_a_bits_source), .auto_in_a_bits_address(dtim_adapter_auto_in_a_bits_address), .auto_in_a_bits_mask(dtim_adapter_auto_in_a_bits_mask), .auto_in_a_bits_data(dtim_adapter_auto_in_a_bits_data), .auto_in_d_ready(dtim_adapter_auto_in_d_ready), .auto_in_d_valid(dtim_adapter_auto_in_d_valid), .auto_in_d_bits_opcode(dtim_adapter_auto_in_d_bits_opcode), .auto_in_d_bits_size(dtim_adapter_auto_in_d_bits_size), .auto_in_d_bits_source(dtim_adapter_auto_in_d_bits_source), .auto_in_d_bits_data(dtim_adapter_auto_in_d_bits_data), .io_dmem_req_ready(dtim_adapter_io_dmem_req_ready), .io_dmem_req_valid(dtim_adapter_io_dmem_req_valid), .io_dmem_req_bits_addr(dtim_adapter_io_dmem_req_bits_addr), .io_dmem_req_bits_cmd(dtim_adapter_io_dmem_req_bits_cmd), .io_dmem_req_bits_size(dtim_adapter_io_dmem_req_bits_size), .io_dmem_s1_kill(dtim_adapter_io_dmem_s1_kill), .io_dmem_s1_data_data(dtim_adapter_io_dmem_s1_data_data), .io_dmem_s1_data_mask(dtim_adapter_io_dmem_s1_data_mask), .io_dmem_s2_nack(dtim_adapter_io_dmem_s2_nack), .io_dmem_resp_valid(dtim_adapter_io_dmem_resp_valid), .io_dmem_resp_bits_data_raw(dtim_adapter_io_dmem_resp_bits_data_raw) ); TLFragmenter_5 fragmenter_1 ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.TinyConfig.fir@125590.4] .clock(fragmenter_1_clock), .reset(fragmenter_1_reset), .auto_in_a_ready(fragmenter_1_auto_in_a_ready), .auto_in_a_valid(fragmenter_1_auto_in_a_valid), .auto_in_a_bits_opcode(fragmenter_1_auto_in_a_bits_opcode), .auto_in_a_bits_param(fragmenter_1_auto_in_a_bits_param), .auto_in_a_bits_size(fragmenter_1_auto_in_a_bits_size), .auto_in_a_bits_source(fragmenter_1_auto_in_a_bits_source), .auto_in_a_bits_address(fragmenter_1_auto_in_a_bits_address), .auto_in_a_bits_mask(fragmenter_1_auto_in_a_bits_mask), .auto_in_a_bits_data(fragmenter_1_auto_in_a_bits_data), .auto_in_d_ready(fragmenter_1_auto_in_d_ready), .auto_in_d_valid(fragmenter_1_auto_in_d_valid), .auto_in_d_bits_opcode(fragmenter_1_auto_in_d_bits_opcode), .auto_in_d_bits_size(fragmenter_1_auto_in_d_bits_size), .auto_in_d_bits_source(fragmenter_1_auto_in_d_bits_source), .auto_in_d_bits_data(fragmenter_1_auto_in_d_bits_data), .auto_out_a_ready(fragmenter_1_auto_out_a_ready), .auto_out_a_valid(fragmenter_1_auto_out_a_valid), .auto_out_a_bits_opcode(fragmenter_1_auto_out_a_bits_opcode), .auto_out_a_bits_param(fragmenter_1_auto_out_a_bits_param), .auto_out_a_bits_size(fragmenter_1_auto_out_a_bits_size), .auto_out_a_bits_source(fragmenter_1_auto_out_a_bits_source), .auto_out_a_bits_address(fragmenter_1_auto_out_a_bits_address), .auto_out_a_bits_mask(fragmenter_1_auto_out_a_bits_mask), .auto_out_a_bits_data(fragmenter_1_auto_out_a_bits_data), .auto_out_d_ready(fragmenter_1_auto_out_d_ready), .auto_out_d_valid(fragmenter_1_auto_out_d_valid), .auto_out_d_bits_opcode(fragmenter_1_auto_out_d_bits_opcode), .auto_out_d_bits_size(fragmenter_1_auto_out_d_bits_size), .auto_out_d_bits_source(fragmenter_1_auto_out_d_bits_source), .auto_out_d_bits_data(fragmenter_1_auto_out_d_bits_data) ); TLBuffer_10 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125596.4] .clock(buffer_clock), .reset(buffer_reset), .auto_in_a_ready(buffer_auto_in_a_ready), .auto_in_a_valid(buffer_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_auto_in_a_bits_data), .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt), .auto_in_d_ready(buffer_auto_in_d_ready), .auto_in_d_valid(buffer_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_auto_out_a_ready), .auto_out_a_valid(buffer_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt), .auto_out_d_ready(buffer_auto_out_d_ready), .auto_out_d_valid(buffer_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode), .auto_out_d_bits_param(buffer_auto_out_d_bits_param), .auto_out_d_bits_size(buffer_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_auto_out_d_bits_source), .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink), .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied), .auto_out_d_bits_data(buffer_auto_out_d_bits_data), .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt) ); TLBuffer_11 buffer_1 ( // @[Buffer.scala 69:28:freechips.rocketchip.system.TinyConfig.fir@125602.4] .clock(buffer_1_clock), .reset(buffer_1_reset), .auto_in_a_ready(buffer_1_auto_in_a_ready), .auto_in_a_valid(buffer_1_auto_in_a_valid), .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode), .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param), .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size), .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source), .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address), .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask), .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data), .auto_in_d_ready(buffer_1_auto_in_d_ready), .auto_in_d_valid(buffer_1_auto_in_d_valid), .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode), .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param), .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size), .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source), .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink), .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied), .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data), .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt), .auto_out_a_ready(buffer_1_auto_out_a_ready), .auto_out_a_valid(buffer_1_auto_out_a_valid), .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode), .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param), .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size), .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source), .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address), .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask), .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data), .auto_out_d_ready(buffer_1_auto_out_d_ready), .auto_out_d_valid(buffer_1_auto_out_d_valid), .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode), .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size), .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source), .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data) ); IntSyncCrossingSink intsink ( // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125608.4] .clock(intsink_clock), .auto_in_sync_0(intsink_auto_in_sync_0), .auto_out_0(intsink_auto_out_0) ); IntSyncCrossingSink_1 intsink_1 ( // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125614.4] .auto_in_sync_0(intsink_1_auto_in_sync_0), .auto_in_sync_1(intsink_1_auto_in_sync_1), .auto_out_0(intsink_1_auto_out_0), .auto_out_1(intsink_1_auto_out_1) ); IntSyncCrossingSink_2 intsink_2 ( // @[Crossing.scala 63:29:freechips.rocketchip.system.TinyConfig.fir@125620.4] .auto_in_sync_0(intsink_2_auto_in_sync_0), .auto_out_0(intsink_2_auto_out_0) ); HellaCacheArbiter dcacheArb ( // @[HellaCache.scala 244:25:freechips.rocketchip.system.TinyConfig.fir@125718.4] .clock(dcacheArb_clock), .io_requestor_0_req_ready(dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid(dcacheArb_io_requestor_0_req_valid), .io_requestor_0_req_bits_addr(dcacheArb_io_requestor_0_req_bits_addr), .io_requestor_0_req_bits_tag(dcacheArb_io_requestor_0_req_bits_tag), .io_requestor_0_req_bits_cmd(dcacheArb_io_requestor_0_req_bits_cmd), .io_requestor_0_req_bits_size(dcacheArb_io_requestor_0_req_bits_size), .io_requestor_0_req_bits_signed(dcacheArb_io_requestor_0_req_bits_signed), .io_requestor_0_s1_kill(dcacheArb_io_requestor_0_s1_kill), .io_requestor_0_s1_data_data(dcacheArb_io_requestor_0_s1_data_data), .io_requestor_0_s2_nack(dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_resp_valid(dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_tag(dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_data(dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_replay(dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data(dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass(dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_replay_next(dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld(dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st(dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld(dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st(dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld(dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st(dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_ordered(dcacheArb_io_requestor_0_ordered), .io_requestor_0_perf_grant(dcacheArb_io_requestor_0_perf_grant), .io_requestor_1_req_ready(dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid(dcacheArb_io_requestor_1_req_valid), .io_requestor_1_req_bits_addr(dcacheArb_io_requestor_1_req_bits_addr), .io_requestor_1_req_bits_cmd(dcacheArb_io_requestor_1_req_bits_cmd), .io_requestor_1_req_bits_size(dcacheArb_io_requestor_1_req_bits_size), .io_requestor_1_s1_kill(dcacheArb_io_requestor_1_s1_kill), .io_requestor_1_s1_data_data(dcacheArb_io_requestor_1_s1_data_data), .io_requestor_1_s1_data_mask(dcacheArb_io_requestor_1_s1_data_mask), .io_requestor_1_s2_nack(dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_resp_valid(dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_data_raw(dcacheArb_io_requestor_1_resp_bits_data_raw), .io_mem_req_ready(dcacheArb_io_mem_req_ready), .io_mem_req_valid(dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr(dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag(dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd(dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size(dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed(dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_phys(dcacheArb_io_mem_req_bits_phys), .io_mem_s1_kill(dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data(dcacheArb_io_mem_s1_data_data), .io_mem_s1_data_mask(dcacheArb_io_mem_s1_data_mask), .io_mem_s2_nack(dcacheArb_io_mem_s2_nack), .io_mem_resp_valid(dcacheArb_io_mem_resp_valid), .io_mem_resp_bits_tag(dcacheArb_io_mem_resp_bits_tag), .io_mem_resp_bits_data(dcacheArb_io_mem_resp_bits_data), .io_mem_resp_bits_replay(dcacheArb_io_mem_resp_bits_replay), .io_mem_resp_bits_has_data(dcacheArb_io_mem_resp_bits_has_data), .io_mem_resp_bits_data_word_bypass(dcacheArb_io_mem_resp_bits_data_word_bypass), .io_mem_resp_bits_data_raw(dcacheArb_io_mem_resp_bits_data_raw), .io_mem_replay_next(dcacheArb_io_mem_replay_next), .io_mem_s2_xcpt_ma_ld(dcacheArb_io_mem_s2_xcpt_ma_ld), .io_mem_s2_xcpt_ma_st(dcacheArb_io_mem_s2_xcpt_ma_st), .io_mem_s2_xcpt_pf_ld(dcacheArb_io_mem_s2_xcpt_pf_ld), .io_mem_s2_xcpt_pf_st(dcacheArb_io_mem_s2_xcpt_pf_st), .io_mem_s2_xcpt_ae_ld(dcacheArb_io_mem_s2_xcpt_ae_ld), .io_mem_s2_xcpt_ae_st(dcacheArb_io_mem_s2_xcpt_ae_st), .io_mem_ordered(dcacheArb_io_mem_ordered), .io_mem_perf_grant(dcacheArb_io_mem_perf_grant) ); PTW ptw ( // @[PTW.scala 391:19:freechips.rocketchip.system.TinyConfig.fir@125723.4] .io_requestor_0_pmp_0_cfg_l(ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a(ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x(ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w(ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r(ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr(ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask(ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l(ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a(ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x(ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w(ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r(ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr(ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask(ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l(ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a(ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x(ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w(ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r(ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr(ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask(ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l(ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a(ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x(ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w(ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r(ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr(ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask(ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l(ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a(ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x(ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w(ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r(ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr(ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask(ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l(ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a(ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x(ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w(ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r(ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr(ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask(ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l(ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a(ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x(ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w(ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r(ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr(ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask(ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l(ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a(ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x(ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w(ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r(ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr(ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask(ptw_io_requestor_0_pmp_7_mask), .io_requestor_1_pmp_0_cfg_l(ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a(ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x(ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w(ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r(ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr(ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask(ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l(ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a(ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x(ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w(ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r(ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr(ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask(ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l(ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a(ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x(ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w(ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r(ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr(ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask(ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l(ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a(ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x(ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w(ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r(ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr(ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask(ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l(ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a(ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x(ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w(ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r(ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr(ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask(ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l(ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a(ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x(ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w(ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r(ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr(ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask(ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l(ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a(ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x(ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w(ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r(ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr(ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask(ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l(ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a(ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x(ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w(ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r(ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr(ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask(ptw_io_requestor_1_pmp_7_mask), .io_dpath_pmp_0_cfg_l(ptw_io_dpath_pmp_0_cfg_l), .io_dpath_pmp_0_cfg_a(ptw_io_dpath_pmp_0_cfg_a), .io_dpath_pmp_0_cfg_x(ptw_io_dpath_pmp_0_cfg_x), .io_dpath_pmp_0_cfg_w(ptw_io_dpath_pmp_0_cfg_w), .io_dpath_pmp_0_cfg_r(ptw_io_dpath_pmp_0_cfg_r), .io_dpath_pmp_0_addr(ptw_io_dpath_pmp_0_addr), .io_dpath_pmp_0_mask(ptw_io_dpath_pmp_0_mask), .io_dpath_pmp_1_cfg_l(ptw_io_dpath_pmp_1_cfg_l), .io_dpath_pmp_1_cfg_a(ptw_io_dpath_pmp_1_cfg_a), .io_dpath_pmp_1_cfg_x(ptw_io_dpath_pmp_1_cfg_x), .io_dpath_pmp_1_cfg_w(ptw_io_dpath_pmp_1_cfg_w), .io_dpath_pmp_1_cfg_r(ptw_io_dpath_pmp_1_cfg_r), .io_dpath_pmp_1_addr(ptw_io_dpath_pmp_1_addr), .io_dpath_pmp_1_mask(ptw_io_dpath_pmp_1_mask), .io_dpath_pmp_2_cfg_l(ptw_io_dpath_pmp_2_cfg_l), .io_dpath_pmp_2_cfg_a(ptw_io_dpath_pmp_2_cfg_a), .io_dpath_pmp_2_cfg_x(ptw_io_dpath_pmp_2_cfg_x), .io_dpath_pmp_2_cfg_w(ptw_io_dpath_pmp_2_cfg_w), .io_dpath_pmp_2_cfg_r(ptw_io_dpath_pmp_2_cfg_r), .io_dpath_pmp_2_addr(ptw_io_dpath_pmp_2_addr), .io_dpath_pmp_2_mask(ptw_io_dpath_pmp_2_mask), .io_dpath_pmp_3_cfg_l(ptw_io_dpath_pmp_3_cfg_l), .io_dpath_pmp_3_cfg_a(ptw_io_dpath_pmp_3_cfg_a), .io_dpath_pmp_3_cfg_x(ptw_io_dpath_pmp_3_cfg_x), .io_dpath_pmp_3_cfg_w(ptw_io_dpath_pmp_3_cfg_w), .io_dpath_pmp_3_cfg_r(ptw_io_dpath_pmp_3_cfg_r), .io_dpath_pmp_3_addr(ptw_io_dpath_pmp_3_addr), .io_dpath_pmp_3_mask(ptw_io_dpath_pmp_3_mask), .io_dpath_pmp_4_cfg_l(ptw_io_dpath_pmp_4_cfg_l), .io_dpath_pmp_4_cfg_a(ptw_io_dpath_pmp_4_cfg_a), .io_dpath_pmp_4_cfg_x(ptw_io_dpath_pmp_4_cfg_x), .io_dpath_pmp_4_cfg_w(ptw_io_dpath_pmp_4_cfg_w), .io_dpath_pmp_4_cfg_r(ptw_io_dpath_pmp_4_cfg_r), .io_dpath_pmp_4_addr(ptw_io_dpath_pmp_4_addr), .io_dpath_pmp_4_mask(ptw_io_dpath_pmp_4_mask), .io_dpath_pmp_5_cfg_l(ptw_io_dpath_pmp_5_cfg_l), .io_dpath_pmp_5_cfg_a(ptw_io_dpath_pmp_5_cfg_a), .io_dpath_pmp_5_cfg_x(ptw_io_dpath_pmp_5_cfg_x), .io_dpath_pmp_5_cfg_w(ptw_io_dpath_pmp_5_cfg_w), .io_dpath_pmp_5_cfg_r(ptw_io_dpath_pmp_5_cfg_r), .io_dpath_pmp_5_addr(ptw_io_dpath_pmp_5_addr), .io_dpath_pmp_5_mask(ptw_io_dpath_pmp_5_mask), .io_dpath_pmp_6_cfg_l(ptw_io_dpath_pmp_6_cfg_l), .io_dpath_pmp_6_cfg_a(ptw_io_dpath_pmp_6_cfg_a), .io_dpath_pmp_6_cfg_x(ptw_io_dpath_pmp_6_cfg_x), .io_dpath_pmp_6_cfg_w(ptw_io_dpath_pmp_6_cfg_w), .io_dpath_pmp_6_cfg_r(ptw_io_dpath_pmp_6_cfg_r), .io_dpath_pmp_6_addr(ptw_io_dpath_pmp_6_addr), .io_dpath_pmp_6_mask(ptw_io_dpath_pmp_6_mask), .io_dpath_pmp_7_cfg_l(ptw_io_dpath_pmp_7_cfg_l), .io_dpath_pmp_7_cfg_a(ptw_io_dpath_pmp_7_cfg_a), .io_dpath_pmp_7_cfg_x(ptw_io_dpath_pmp_7_cfg_x), .io_dpath_pmp_7_cfg_w(ptw_io_dpath_pmp_7_cfg_w), .io_dpath_pmp_7_cfg_r(ptw_io_dpath_pmp_7_cfg_r), .io_dpath_pmp_7_addr(ptw_io_dpath_pmp_7_addr), .io_dpath_pmp_7_mask(ptw_io_dpath_pmp_7_mask) ); Rocket core ( // @[RocketTile.scala 122:20:freechips.rocketchip.system.TinyConfig.fir@125727.4] .clock(core_clock), .reset(core_reset), .io_interrupts_debug(core_io_interrupts_debug), .io_interrupts_mtip(core_io_interrupts_mtip), .io_interrupts_msip(core_io_interrupts_msip), .io_interrupts_meip(core_io_interrupts_meip), .io_imem_might_request(core_io_imem_might_request), .io_imem_req_valid(core_io_imem_req_valid), .io_imem_req_bits_pc(core_io_imem_req_bits_pc), .io_imem_req_bits_speculative(core_io_imem_req_bits_speculative), .io_imem_resp_ready(core_io_imem_resp_ready), .io_imem_resp_valid(core_io_imem_resp_valid), .io_imem_resp_bits_pc(core_io_imem_resp_bits_pc), .io_imem_resp_bits_data(core_io_imem_resp_bits_data), .io_imem_resp_bits_xcpt_ae_inst(core_io_imem_resp_bits_xcpt_ae_inst), .io_imem_resp_bits_replay(core_io_imem_resp_bits_replay), .io_imem_btb_update_valid(core_io_imem_btb_update_valid), .io_imem_bht_update_valid(core_io_imem_bht_update_valid), .io_imem_flush_icache(core_io_imem_flush_icache), .io_dmem_req_ready(core_io_dmem_req_ready), .io_dmem_req_valid(core_io_dmem_req_valid), .io_dmem_req_bits_addr(core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag(core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd(core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size(core_io_dmem_req_bits_size), .io_dmem_req_bits_signed(core_io_dmem_req_bits_signed), .io_dmem_s1_kill(core_io_dmem_s1_kill), .io_dmem_s1_data_data(core_io_dmem_s1_data_data), .io_dmem_s2_nack(core_io_dmem_s2_nack), .io_dmem_resp_valid(core_io_dmem_resp_valid), .io_dmem_resp_bits_tag(core_io_dmem_resp_bits_tag), .io_dmem_resp_bits_data(core_io_dmem_resp_bits_data), .io_dmem_resp_bits_replay(core_io_dmem_resp_bits_replay), .io_dmem_resp_bits_has_data(core_io_dmem_resp_bits_has_data), .io_dmem_resp_bits_data_word_bypass(core_io_dmem_resp_bits_data_word_bypass), .io_dmem_replay_next(core_io_dmem_replay_next), .io_dmem_s2_xcpt_ma_ld(core_io_dmem_s2_xcpt_ma_ld), .io_dmem_s2_xcpt_ma_st(core_io_dmem_s2_xcpt_ma_st), .io_dmem_s2_xcpt_pf_ld(core_io_dmem_s2_xcpt_pf_ld), .io_dmem_s2_xcpt_pf_st(core_io_dmem_s2_xcpt_pf_st), .io_dmem_s2_xcpt_ae_ld(core_io_dmem_s2_xcpt_ae_ld), .io_dmem_s2_xcpt_ae_st(core_io_dmem_s2_xcpt_ae_st), .io_dmem_ordered(core_io_dmem_ordered), .io_dmem_perf_grant(core_io_dmem_perf_grant), .io_ptw_pmp_0_cfg_l(core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a(core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x(core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w(core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r(core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr(core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask(core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l(core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a(core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x(core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w(core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r(core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr(core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask(core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l(core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a(core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x(core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w(core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r(core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr(core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask(core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l(core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a(core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x(core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w(core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r(core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr(core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask(core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l(core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a(core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x(core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w(core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r(core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr(core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask(core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l(core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a(core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x(core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w(core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r(core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr(core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask(core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l(core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a(core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x(core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w(core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r(core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr(core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask(core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l(core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a(core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x(core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w(core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r(core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr(core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask(core_io_ptw_pmp_7_mask), .io_ptw_customCSRs_csrs_0_value(core_io_ptw_customCSRs_csrs_0_value) ); assign auto_tl_slave_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_slave_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125714.4] assign auto_tl_master_xing_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign auto_tl_master_xing_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125713.4] assign tlMasterXbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125537.4] assign tlMasterXbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125538.4] assign tlMasterXbar_auto_in_1_a_valid = frontend_auto_icache_master_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign tlMasterXbar_auto_in_1_a_bits_address = frontend_auto_icache_master_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign tlMasterXbar_auto_in_0_a_valid = dcache_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_opcode = dcache_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_param = dcache_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_size = dcache_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_address = dcache_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_mask = dcache_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_a_bits_data = dcache_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_in_0_d_ready = dcache_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign tlMasterXbar_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlMasterXbar_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125690.4] assign tlSlaveXbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125700.4] assign tlSlaveXbar_auto_out_a_ready = fragmenter_1_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign tlSlaveXbar_auto_out_d_valid = fragmenter_1_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign tlSlaveXbar_auto_out_d_bits_opcode = fragmenter_1_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign tlSlaveXbar_auto_out_d_bits_size = fragmenter_1_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign tlSlaveXbar_auto_out_d_bits_source = fragmenter_1_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign tlSlaveXbar_auto_out_d_bits_data = fragmenter_1_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign intXbar_auto_int_in_2_0 = intsink_2_auto_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125697.4] assign intXbar_auto_int_in_1_0 = intsink_1_auto_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125696.4] assign intXbar_auto_int_in_1_1 = intsink_1_auto_out_1; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125696.4] assign intXbar_auto_int_in_0_0 = intsink_auto_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125695.4] assign dcache_gated_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125568.4] assign dcache_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125569.4] assign dcache_auto_out_a_ready = tlMasterXbar_auto_in_0_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_auto_out_d_valid = tlMasterXbar_auto_in_0_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_auto_out_d_bits_opcode = tlMasterXbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_auto_out_d_bits_size = tlMasterXbar_auto_in_0_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_auto_out_d_bits_denied = tlMasterXbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_auto_out_d_bits_data = tlMasterXbar_auto_in_0_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125698.4] assign dcache_io_cpu_req_valid = dcacheArb_io_mem_req_valid; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_addr = dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_tag = dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_cmd = dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_size = dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_signed = dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_req_bits_phys = dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_s1_kill = dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_s1_data_data = dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_cpu_s1_data_mask = dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcache_io_ptw_pmp_0_cfg_l = ptw_io_requestor_0_pmp_0_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_cfg_a = ptw_io_requestor_0_pmp_0_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_cfg_x = ptw_io_requestor_0_pmp_0_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_cfg_w = ptw_io_requestor_0_pmp_0_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_cfg_r = ptw_io_requestor_0_pmp_0_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_addr = ptw_io_requestor_0_pmp_0_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_0_mask = ptw_io_requestor_0_pmp_0_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_cfg_l = ptw_io_requestor_0_pmp_1_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_cfg_a = ptw_io_requestor_0_pmp_1_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_cfg_x = ptw_io_requestor_0_pmp_1_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_cfg_w = ptw_io_requestor_0_pmp_1_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_cfg_r = ptw_io_requestor_0_pmp_1_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_addr = ptw_io_requestor_0_pmp_1_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_1_mask = ptw_io_requestor_0_pmp_1_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_cfg_l = ptw_io_requestor_0_pmp_2_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_cfg_a = ptw_io_requestor_0_pmp_2_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_cfg_x = ptw_io_requestor_0_pmp_2_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_cfg_w = ptw_io_requestor_0_pmp_2_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_cfg_r = ptw_io_requestor_0_pmp_2_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_addr = ptw_io_requestor_0_pmp_2_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_2_mask = ptw_io_requestor_0_pmp_2_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_cfg_l = ptw_io_requestor_0_pmp_3_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_cfg_a = ptw_io_requestor_0_pmp_3_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_cfg_x = ptw_io_requestor_0_pmp_3_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_cfg_w = ptw_io_requestor_0_pmp_3_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_cfg_r = ptw_io_requestor_0_pmp_3_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_addr = ptw_io_requestor_0_pmp_3_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_3_mask = ptw_io_requestor_0_pmp_3_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_cfg_l = ptw_io_requestor_0_pmp_4_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_cfg_a = ptw_io_requestor_0_pmp_4_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_cfg_x = ptw_io_requestor_0_pmp_4_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_cfg_w = ptw_io_requestor_0_pmp_4_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_cfg_r = ptw_io_requestor_0_pmp_4_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_addr = ptw_io_requestor_0_pmp_4_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_4_mask = ptw_io_requestor_0_pmp_4_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_cfg_l = ptw_io_requestor_0_pmp_5_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_cfg_a = ptw_io_requestor_0_pmp_5_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_cfg_x = ptw_io_requestor_0_pmp_5_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_cfg_w = ptw_io_requestor_0_pmp_5_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_cfg_r = ptw_io_requestor_0_pmp_5_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_addr = ptw_io_requestor_0_pmp_5_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_5_mask = ptw_io_requestor_0_pmp_5_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_cfg_l = ptw_io_requestor_0_pmp_6_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_cfg_a = ptw_io_requestor_0_pmp_6_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_cfg_x = ptw_io_requestor_0_pmp_6_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_cfg_w = ptw_io_requestor_0_pmp_6_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_cfg_r = ptw_io_requestor_0_pmp_6_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_addr = ptw_io_requestor_0_pmp_6_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_6_mask = ptw_io_requestor_0_pmp_6_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_cfg_l = ptw_io_requestor_0_pmp_7_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_cfg_a = ptw_io_requestor_0_pmp_7_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_cfg_x = ptw_io_requestor_0_pmp_7_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_cfg_w = ptw_io_requestor_0_pmp_7_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_cfg_r = ptw_io_requestor_0_pmp_7_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_addr = ptw_io_requestor_0_pmp_7_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign dcache_io_ptw_pmp_7_mask = ptw_io_requestor_0_pmp_7_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125748.4] assign frontend_gated_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125575.4] assign frontend_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125576.4] assign frontend_auto_icache_master_out_a_ready = tlMasterXbar_auto_in_1_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_auto_icache_master_out_d_valid = tlMasterXbar_auto_in_1_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_auto_icache_master_out_d_bits_opcode = tlMasterXbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_auto_icache_master_out_d_bits_size = tlMasterXbar_auto_in_1_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_auto_icache_master_out_d_bits_data = tlMasterXbar_auto_in_1_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_auto_icache_master_out_d_bits_corrupt = tlMasterXbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125699.4] assign frontend_io_cpu_might_request = core_io_imem_might_request; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_req_valid = core_io_imem_req_valid; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_req_bits_pc = core_io_imem_req_bits_pc; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_req_bits_speculative = core_io_imem_req_bits_speculative; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_resp_ready = core_io_imem_resp_ready; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_btb_update_valid = core_io_imem_btb_update_valid; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_bht_update_valid = core_io_imem_bht_update_valid; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_cpu_flush_icache = core_io_imem_flush_icache; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign frontend_io_ptw_pmp_0_cfg_l = ptw_io_requestor_1_pmp_0_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_cfg_a = ptw_io_requestor_1_pmp_0_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_cfg_x = ptw_io_requestor_1_pmp_0_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_cfg_w = ptw_io_requestor_1_pmp_0_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_cfg_r = ptw_io_requestor_1_pmp_0_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_addr = ptw_io_requestor_1_pmp_0_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_0_mask = ptw_io_requestor_1_pmp_0_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_cfg_l = ptw_io_requestor_1_pmp_1_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_cfg_a = ptw_io_requestor_1_pmp_1_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_cfg_x = ptw_io_requestor_1_pmp_1_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_cfg_w = ptw_io_requestor_1_pmp_1_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_cfg_r = ptw_io_requestor_1_pmp_1_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_addr = ptw_io_requestor_1_pmp_1_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_1_mask = ptw_io_requestor_1_pmp_1_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_cfg_l = ptw_io_requestor_1_pmp_2_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_cfg_a = ptw_io_requestor_1_pmp_2_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_cfg_x = ptw_io_requestor_1_pmp_2_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_cfg_w = ptw_io_requestor_1_pmp_2_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_cfg_r = ptw_io_requestor_1_pmp_2_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_addr = ptw_io_requestor_1_pmp_2_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_2_mask = ptw_io_requestor_1_pmp_2_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_cfg_l = ptw_io_requestor_1_pmp_3_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_cfg_a = ptw_io_requestor_1_pmp_3_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_cfg_x = ptw_io_requestor_1_pmp_3_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_cfg_w = ptw_io_requestor_1_pmp_3_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_cfg_r = ptw_io_requestor_1_pmp_3_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_addr = ptw_io_requestor_1_pmp_3_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_3_mask = ptw_io_requestor_1_pmp_3_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_cfg_l = ptw_io_requestor_1_pmp_4_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_cfg_a = ptw_io_requestor_1_pmp_4_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_cfg_x = ptw_io_requestor_1_pmp_4_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_cfg_w = ptw_io_requestor_1_pmp_4_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_cfg_r = ptw_io_requestor_1_pmp_4_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_addr = ptw_io_requestor_1_pmp_4_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_4_mask = ptw_io_requestor_1_pmp_4_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_cfg_l = ptw_io_requestor_1_pmp_5_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_cfg_a = ptw_io_requestor_1_pmp_5_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_cfg_x = ptw_io_requestor_1_pmp_5_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_cfg_w = ptw_io_requestor_1_pmp_5_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_cfg_r = ptw_io_requestor_1_pmp_5_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_addr = ptw_io_requestor_1_pmp_5_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_5_mask = ptw_io_requestor_1_pmp_5_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_cfg_l = ptw_io_requestor_1_pmp_6_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_cfg_a = ptw_io_requestor_1_pmp_6_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_cfg_x = ptw_io_requestor_1_pmp_6_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_cfg_w = ptw_io_requestor_1_pmp_6_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_cfg_r = ptw_io_requestor_1_pmp_6_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_addr = ptw_io_requestor_1_pmp_6_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_6_mask = ptw_io_requestor_1_pmp_6_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_cfg_l = ptw_io_requestor_1_pmp_7_cfg_l; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_cfg_a = ptw_io_requestor_1_pmp_7_cfg_a; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_cfg_x = ptw_io_requestor_1_pmp_7_cfg_x; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_cfg_w = ptw_io_requestor_1_pmp_7_cfg_w; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_cfg_r = ptw_io_requestor_1_pmp_7_cfg_r; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_addr = ptw_io_requestor_1_pmp_7_addr; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign frontend_io_ptw_pmp_7_mask = ptw_io_requestor_1_pmp_7_mask; // @[RocketTile.scala 178:20:freechips.rocketchip.system.TinyConfig.fir@125749.4] assign dtim_adapter_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125588.4] assign dtim_adapter_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125589.4] assign dtim_adapter_auto_in_a_valid = fragmenter_1_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_opcode = fragmenter_1_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_param = fragmenter_1_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_size = fragmenter_1_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_source = fragmenter_1_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_address = fragmenter_1_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_mask = fragmenter_1_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_a_bits_data = fragmenter_1_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_auto_in_d_ready = fragmenter_1_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign dtim_adapter_io_dmem_req_ready = dcacheArb_io_requestor_1_req_ready; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dtim_adapter_io_dmem_s2_nack = dcacheArb_io_requestor_1_s2_nack; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dtim_adapter_io_dmem_resp_valid = dcacheArb_io_requestor_1_resp_valid; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dtim_adapter_io_dmem_resp_bits_data_raw = dcacheArb_io_requestor_1_resp_bits_data_raw; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign fragmenter_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125594.4] assign fragmenter_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125595.4] assign fragmenter_1_auto_in_a_valid = tlSlaveXbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_opcode = tlSlaveXbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_param = tlSlaveXbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_size = tlSlaveXbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_source = tlSlaveXbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_address = tlSlaveXbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_mask = tlSlaveXbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_a_bits_data = tlSlaveXbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_in_d_ready = tlSlaveXbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125691.4] assign fragmenter_1_auto_out_a_ready = dtim_adapter_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign fragmenter_1_auto_out_d_valid = dtim_adapter_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign fragmenter_1_auto_out_d_bits_opcode = dtim_adapter_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign fragmenter_1_auto_out_d_bits_size = dtim_adapter_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign fragmenter_1_auto_out_d_bits_source = dtim_adapter_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign fragmenter_1_auto_out_d_bits_data = dtim_adapter_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125701.4] assign buffer_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125600.4] assign buffer_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125601.4] assign buffer_auto_in_a_valid = tlMasterXbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_opcode = tlMasterXbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_param = tlMasterXbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_size = tlMasterXbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_source = tlMasterXbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_address = tlMasterXbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_mask = tlMasterXbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_data = tlMasterXbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_a_bits_corrupt = tlMasterXbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_in_d_ready = tlMasterXbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125689.4] assign buffer_auto_out_a_ready = auto_tl_master_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_valid = auto_tl_master_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_opcode = auto_tl_master_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_param = auto_tl_master_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_size = auto_tl_master_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_source = auto_tl_master_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_sink = auto_tl_master_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_denied = auto_tl_master_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_data = auto_tl_master_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_auto_out_d_bits_corrupt = auto_tl_master_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125702.4] assign buffer_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125606.4] assign buffer_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125607.4] assign buffer_1_auto_in_a_valid = auto_tl_slave_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_opcode = auto_tl_slave_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_param = auto_tl_slave_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_size = auto_tl_slave_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_source = auto_tl_slave_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_address = auto_tl_slave_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_mask = auto_tl_slave_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_a_bits_data = auto_tl_slave_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_in_d_ready = auto_tl_slave_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125704.4] assign buffer_1_auto_out_a_ready = tlSlaveXbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign buffer_1_auto_out_d_valid = tlSlaveXbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign buffer_1_auto_out_d_bits_opcode = tlSlaveXbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign buffer_1_auto_out_d_bits_size = tlSlaveXbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign buffer_1_auto_out_d_bits_source = tlSlaveXbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign buffer_1_auto_out_d_bits_data = tlSlaveXbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@125703.4] assign intsink_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125612.4] assign intsink_auto_in_sync_0 = auto_intsink_in_sync_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@125717.4] assign intsink_1_auto_in_sync_0 = auto_int_in_xing_in_0_sync_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125707.4] assign intsink_1_auto_in_sync_1 = auto_int_in_xing_in_0_sync_1; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125707.4] assign intsink_2_auto_in_sync_0 = auto_int_in_xing_in_1_sync_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@125709.4] assign dcacheArb_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125720.4] assign dcacheArb_io_requestor_0_req_valid = core_io_dmem_req_valid; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_req_bits_addr = core_io_dmem_req_bits_addr; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_req_bits_tag = core_io_dmem_req_bits_tag; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_req_bits_cmd = core_io_dmem_req_bits_cmd; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_req_bits_size = core_io_dmem_req_bits_size; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_req_bits_signed = core_io_dmem_req_bits_signed; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_s1_kill = core_io_dmem_s1_kill; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_0_s1_data_data = core_io_dmem_s1_data_data; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign dcacheArb_io_requestor_1_req_valid = dtim_adapter_io_dmem_req_valid; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_req_bits_addr = dtim_adapter_io_dmem_req_bits_addr; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_req_bits_cmd = dtim_adapter_io_dmem_req_bits_cmd; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_req_bits_size = dtim_adapter_io_dmem_req_bits_size; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_s1_kill = dtim_adapter_io_dmem_s1_kill; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_s1_data_data = dtim_adapter_io_dmem_s1_data_data; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_requestor_1_s1_data_mask = dtim_adapter_io_dmem_s1_data_mask; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125747.4] assign dcacheArb_io_mem_req_ready = dcache_io_cpu_req_ready; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_nack = dcache_io_cpu_s2_nack; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_valid = dcache_io_cpu_resp_valid; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_tag = dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_data = dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_replay = dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_has_data = dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_data_word_bypass = dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_resp_bits_data_raw = dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_replay_next = dcache_io_cpu_replay_next; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_ma_ld = dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_ma_st = dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_pf_ld = dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_pf_st = dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_ae_ld = dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_s2_xcpt_ae_st = dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_ordered = dcache_io_cpu_ordered; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign dcacheArb_io_mem_perf_grant = dcache_io_cpu_perf_grant; // @[HellaCache.scala 245:30:freechips.rocketchip.system.TinyConfig.fir@125722.4] assign ptw_io_dpath_pmp_0_cfg_l = core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_cfg_a = core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_cfg_x = core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_cfg_w = core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_cfg_r = core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_addr = core_io_ptw_pmp_0_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_0_mask = core_io_ptw_pmp_0_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_cfg_l = core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_cfg_a = core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_cfg_x = core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_cfg_w = core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_cfg_r = core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_addr = core_io_ptw_pmp_1_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_1_mask = core_io_ptw_pmp_1_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_cfg_l = core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_cfg_a = core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_cfg_x = core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_cfg_w = core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_cfg_r = core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_addr = core_io_ptw_pmp_2_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_2_mask = core_io_ptw_pmp_2_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_cfg_l = core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_cfg_a = core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_cfg_x = core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_cfg_w = core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_cfg_r = core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_addr = core_io_ptw_pmp_3_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_3_mask = core_io_ptw_pmp_3_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_cfg_l = core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_cfg_a = core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_cfg_x = core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_cfg_w = core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_cfg_r = core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_addr = core_io_ptw_pmp_4_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_4_mask = core_io_ptw_pmp_4_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_cfg_l = core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_cfg_a = core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_cfg_x = core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_cfg_w = core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_cfg_r = core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_addr = core_io_ptw_pmp_5_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_5_mask = core_io_ptw_pmp_5_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_cfg_l = core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_cfg_a = core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_cfg_x = core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_cfg_w = core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_cfg_r = core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_addr = core_io_ptw_pmp_6_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_6_mask = core_io_ptw_pmp_6_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_cfg_l = core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_cfg_a = core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_cfg_x = core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_cfg_w = core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_cfg_r = core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_addr = core_io_ptw_pmp_7_addr; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign ptw_io_dpath_pmp_7_mask = core_io_ptw_pmp_7_mask; // @[RocketTile.scala 156:15:freechips.rocketchip.system.TinyConfig.fir@125745.4] assign core_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125729.4] assign core_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125730.4] assign core_io_interrupts_debug = intXbar_auto_int_out_0; // @[Interrupts.scala 75:93:freechips.rocketchip.system.TinyConfig.fir@125734.4] assign core_io_interrupts_mtip = intXbar_auto_int_out_2; // @[Interrupts.scala 75:93:freechips.rocketchip.system.TinyConfig.fir@125736.4] assign core_io_interrupts_msip = intXbar_auto_int_out_1; // @[Interrupts.scala 75:93:freechips.rocketchip.system.TinyConfig.fir@125735.4] assign core_io_interrupts_meip = intXbar_auto_int_out_3; // @[Interrupts.scala 75:93:freechips.rocketchip.system.TinyConfig.fir@125737.4] assign core_io_imem_resp_valid = frontend_io_cpu_resp_valid; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign core_io_imem_resp_bits_pc = frontend_io_cpu_resp_bits_pc; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign core_io_imem_resp_bits_data = frontend_io_cpu_resp_bits_data; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign core_io_imem_resp_bits_xcpt_ae_inst = frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign core_io_imem_resp_bits_replay = frontend_io_cpu_resp_bits_replay; // @[RocketTile.scala 153:32:freechips.rocketchip.system.TinyConfig.fir@125744.4] assign core_io_dmem_req_ready = dcacheArb_io_requestor_0_req_ready; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_nack = dcacheArb_io_requestor_0_s2_nack; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_valid = dcacheArb_io_requestor_0_resp_valid; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_bits_tag = dcacheArb_io_requestor_0_resp_bits_tag; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_bits_data = dcacheArb_io_requestor_0_resp_bits_data; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_bits_replay = dcacheArb_io_requestor_0_resp_bits_replay; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_bits_has_data = dcacheArb_io_requestor_0_resp_bits_has_data; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_resp_bits_data_word_bypass = dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_replay_next = dcacheArb_io_requestor_0_replay_next; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_ma_ld = dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_ma_st = dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_pf_ld = dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_pf_st = dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_ae_ld = dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_s2_xcpt_ae_st = dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_ordered = dcacheArb_io_requestor_0_ordered; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] assign core_io_dmem_perf_grant = dcacheArb_io_requestor_0_perf_grant; // @[RocketTile.scala 177:26:freechips.rocketchip.system.TinyConfig.fir@125746.4] endmodule module AsyncResetRegVec_w2_i0( // @[:freechips.rocketchip.system.TinyConfig.fir@125771.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125772.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@125773.4] input [1:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@125774.4] output [1:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@125774.4] ); wire reg_0_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] wire reg_0_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] wire reg_0_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] wire reg_0_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] wire reg_0_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] wire reg_1_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] wire reg_1_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] wire reg_1_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] wire reg_1_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] wire reg_1_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] AsyncResetReg #(.RESET_VALUE(0)) reg_0 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125779.4] .d(reg_0_d), .q(reg_0_q), .en(reg_0_en), .clk(reg_0_clk), .rst(reg_0_rst) ); AsyncResetReg #(.RESET_VALUE(0)) reg_1 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.TinyConfig.fir@125785.4] .d(reg_1_d), .q(reg_1_q), .en(reg_1_en), .clk(reg_1_clk), .rst(reg_1_rst) ); assign io_q = {reg_1_q,reg_0_q}; // @[AsyncResetReg.scala 73:8:freechips.rocketchip.system.TinyConfig.fir@125802.4] assign reg_0_d = io_d[0]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@125794.4] assign reg_0_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@125795.4] assign reg_0_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@125791.4] assign reg_0_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@125792.4] assign reg_1_d = io_d[1]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.TinyConfig.fir@125799.4] assign reg_1_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@125800.4] assign reg_1_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.TinyConfig.fir@125796.4] assign reg_1_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.TinyConfig.fir@125797.4] endmodule module IntSyncCrossingSource_2( // @[:freechips.rocketchip.system.TinyConfig.fir@125804.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125805.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@125806.4] input auto_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125807.4] input auto_in_1, // @[:freechips.rocketchip.system.TinyConfig.fir@125807.4] output auto_out_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125807.4] output auto_out_sync_1 // @[:freechips.rocketchip.system.TinyConfig.fir@125807.4] ); wire AsyncResetRegVec_w2_i0_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125819.4] wire AsyncResetRegVec_w2_i0_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125819.4] wire [1:0] AsyncResetRegVec_w2_i0_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125819.4] wire [1:0] AsyncResetRegVec_w2_i0_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125819.4] AsyncResetRegVec_w2_i0 AsyncResetRegVec_w2_i0 ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125819.4] .clock(AsyncResetRegVec_w2_i0_clock), .reset(AsyncResetRegVec_w2_i0_reset), .io_d(AsyncResetRegVec_w2_i0_io_d), .io_q(AsyncResetRegVec_w2_i0_io_q) ); assign auto_out_sync_0 = AsyncResetRegVec_w2_i0_io_q[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125816.4] assign auto_out_sync_1 = AsyncResetRegVec_w2_i0_io_q[1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125816.4] assign AsyncResetRegVec_w2_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125821.4] assign AsyncResetRegVec_w2_i0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125822.4] assign AsyncResetRegVec_w2_i0_io_d = {auto_in_1,auto_in_0}; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@125823.4] endmodule module IntSyncCrossingSource_3( // @[:freechips.rocketchip.system.TinyConfig.fir@125861.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125862.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@125863.4] input auto_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125864.4] output auto_out_sync_0 // @[:freechips.rocketchip.system.TinyConfig.fir@125864.4] ); wire AsyncResetRegVec_w1_i0_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] wire AsyncResetRegVec_w1_i0_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] wire AsyncResetRegVec_w1_i0_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] wire AsyncResetRegVec_w1_i0_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] wire AsyncResetRegVec_w1_i0_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] AsyncResetRegVec_w1_i0 AsyncResetRegVec_w1_i0 ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.TinyConfig.fir@125875.4] .clock(AsyncResetRegVec_w1_i0_clock), .reset(AsyncResetRegVec_w1_i0_reset), .io_d(AsyncResetRegVec_w1_i0_io_d), .io_q(AsyncResetRegVec_w1_i0_io_q), .io_en(AsyncResetRegVec_w1_i0_io_en) ); assign auto_out_sync_0 = AsyncResetRegVec_w1_i0_io_q; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125873.4] assign AsyncResetRegVec_w1_i0_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125877.4] assign AsyncResetRegVec_w1_i0_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@125878.4] assign AsyncResetRegVec_w1_i0_io_d = auto_in_0; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@125879.4] assign AsyncResetRegVec_w1_i0_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.TinyConfig.fir@125880.4] endmodule module SynchronizerShiftReg_w2_d3( // @[:freechips.rocketchip.system.TinyConfig.fir@125920.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125921.4] input [1:0] io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@125923.4] output [1:0] io_q // @[:freechips.rocketchip.system.TinyConfig.fir@125923.4] ); reg [1:0] sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@125928.4] reg [31:0] _RAND_0; reg [1:0] sync_1; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@125929.4] reg [31:0] _RAND_1; reg [1:0] sync_2; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@125930.4] reg [31:0] _RAND_2; assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@125934.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; sync_0 = _RAND_0[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; sync_1 = _RAND_1[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; sync_2 = _RAND_2[1:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin sync_0 <= sync_1; sync_1 <= sync_2; sync_2 <= io_d; end endmodule module IntXing( // @[:freechips.rocketchip.system.TinyConfig.fir@125936.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125937.4] input auto_int_in_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125939.4] input auto_int_in_1, // @[:freechips.rocketchip.system.TinyConfig.fir@125939.4] output auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@125939.4] output auto_int_out_1 // @[:freechips.rocketchip.system.TinyConfig.fir@125939.4] ); wire SynchronizerShiftReg_w2_d3_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@125950.4] wire [1:0] SynchronizerShiftReg_w2_d3_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@125950.4] wire [1:0] SynchronizerShiftReg_w2_d3_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@125950.4] wire [1:0] _T_4; // @[:freechips.rocketchip.system.TinyConfig.fir@125958.4 :freechips.rocketchip.system.TinyConfig.fir@125960.4] SynchronizerShiftReg_w2_d3 SynchronizerShiftReg_w2_d3 ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.TinyConfig.fir@125950.4] .clock(SynchronizerShiftReg_w2_d3_clock), .io_d(SynchronizerShiftReg_w2_d3_io_d), .io_q(SynchronizerShiftReg_w2_d3_io_q) ); assign _T_4 = SynchronizerShiftReg_w2_d3_io_q; // @[:freechips.rocketchip.system.TinyConfig.fir@125958.4 :freechips.rocketchip.system.TinyConfig.fir@125960.4] assign auto_int_out_0 = _T_4[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125948.4] assign auto_int_out_1 = _T_4[1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@125948.4] assign SynchronizerShiftReg_w2_d3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@125952.4] assign SynchronizerShiftReg_w2_d3_io_d = {auto_int_in_1,auto_int_in_0}; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.TinyConfig.fir@125955.4] endmodule module TLMonitor_38( // @[:freechips.rocketchip.system.TinyConfig.fir@125975.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@125976.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@125977.4] input io_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input io_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [9:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [16:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input io_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input io_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] input [9:0] io_in_d_bits_source // @[:freechips.rocketchip.system.TinyConfig.fir@125978.4] ); wire [31:0] plusarg_reader_out; // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@127095.4] wire _T_11; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@125999.6] wire [4:0] _T_15; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@126005.6] wire [1:0] _T_16; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@126006.6] wire [1:0] _T_17; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@126007.6] wire [16:0] _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@126008.6] wire [16:0] _T_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@126008.6] wire _T_19; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@126009.6] wire _T_21; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@126011.6] wire [1:0] _T_22; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@126012.6] wire [1:0] _T_24; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@126014.6] wire _T_25; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@126015.6] wire _T_26; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@126016.6] wire _T_27; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@126017.6] wire _T_28; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@126018.6] wire _T_30; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126020.6] wire _T_31; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126021.6] wire _T_33; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126023.6] wire _T_34; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126024.6] wire _T_35; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@126025.6] wire _T_36; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@126026.6] wire _T_37; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@126027.6] wire _T_38; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126028.6] wire _T_39; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126029.6] wire _T_40; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126030.6] wire _T_41; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126031.6] wire _T_42; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126032.6] wire _T_43; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126033.6] wire _T_44; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126034.6] wire _T_45; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126035.6] wire _T_46; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126036.6] wire _T_47; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126037.6] wire _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126038.6] wire _T_49; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126039.6] wire [3:0] _T_52; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@126042.6] wire _T_71; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@126065.6] wire [16:0] _T_73; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@126068.8] wire [17:0] _T_74; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@126069.8] wire [17:0] _T_75; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126070.8] wire [17:0] _T_76; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126071.8] wire _T_77; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@126072.8] wire _T_82; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126077.8] wire _T_87; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126090.8] wire _T_88; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126091.8] wire _T_91; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126098.8] wire _T_92; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126099.8] wire _T_94; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126105.8] wire _T_95; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126106.8] wire _T_96; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@126111.8] wire _T_98; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126113.8] wire _T_99; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126114.8] wire [3:0] _T_100; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@126119.8] wire _T_101; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@126120.8] wire _T_103; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126122.8] wire _T_104; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126123.8] wire _T_105; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@126128.8] wire _T_107; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126130.8] wire _T_108; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126131.8] wire _T_109; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@126137.6] wire _T_138; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@126191.8] wire _T_140; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126193.8] wire _T_141; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126194.8] wire _T_151; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@126217.6] wire _T_153; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@126220.8] wire _T_161; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@126228.8] wire _T_164; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126231.8] wire _T_165; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126232.8] wire _T_172; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@126251.8] wire _T_174; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126253.8] wire _T_175; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126254.8] wire _T_176; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@126259.8] wire _T_178; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126261.8] wire _T_179; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126262.8] wire _T_184; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@126276.6] wire _T_210; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@126324.6] wire [3:0] _T_232; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@126363.8] wire [3:0] _T_233; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@126364.8] wire _T_234; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@126365.8] wire _T_236; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126367.8] wire _T_237; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126368.8] wire _T_238; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@126374.6] wire _T_256; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@126405.8] wire _T_258; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126407.8] wire _T_259; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126408.8] wire _T_264; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@126422.6] wire _T_282; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@126453.8] wire _T_284; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126455.8] wire _T_285; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126456.8] wire _T_290; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@126470.6] wire _T_326; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@126534.6] wire _T_332; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@126543.8] wire _T_333; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@126544.8] wire _T_471; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@126830.4] reg _T_480; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@126839.4] reg [31:0] _RAND_0; wire _T_482; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@126841.4] wire _T_483; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@126842.4] reg [2:0] _T_491; // @[Monitor.scala 349:22:freechips.rocketchip.system.TinyConfig.fir@126853.4] reg [31:0] _RAND_1; reg [2:0] _T_492; // @[Monitor.scala 350:22:freechips.rocketchip.system.TinyConfig.fir@126854.4] reg [31:0] _RAND_2; reg [1:0] _T_493; // @[Monitor.scala 351:22:freechips.rocketchip.system.TinyConfig.fir@126855.4] reg [31:0] _RAND_3; reg [9:0] _T_494; // @[Monitor.scala 352:22:freechips.rocketchip.system.TinyConfig.fir@126856.4] reg [31:0] _RAND_4; reg [16:0] _T_495; // @[Monitor.scala 353:22:freechips.rocketchip.system.TinyConfig.fir@126857.4] reg [31:0] _RAND_5; wire _T_496; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@126858.4] wire _T_497; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@126859.4] wire _T_498; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@126861.6] wire _T_500; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126863.6] wire _T_501; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126864.6] wire _T_502; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@126869.6] wire _T_504; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126871.6] wire _T_505; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126872.6] wire _T_506; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@126877.6] wire _T_508; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126879.6] wire _T_509; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126880.6] wire _T_510; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@126885.6] wire _T_512; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126887.6] wire _T_513; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126888.6] wire _T_514; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@126893.6] wire _T_516; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126895.6] wire _T_517; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126896.6] wire _T_519; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@126903.4] wire _T_520; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@126911.4] reg _T_528; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@126919.4] reg [31:0] _RAND_6; wire _T_530; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@126921.4] wire _T_531; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@126922.4] reg [1:0] _T_541; // @[Monitor.scala 420:22:freechips.rocketchip.system.TinyConfig.fir@126935.4] reg [31:0] _RAND_7; reg [9:0] _T_542; // @[Monitor.scala 421:22:freechips.rocketchip.system.TinyConfig.fir@126936.4] reg [31:0] _RAND_8; wire _T_545; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@126939.4] wire _T_546; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@126940.4] wire _T_555; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@126958.6] wire _T_557; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126960.6] wire _T_558; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126961.6] wire _T_559; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@126966.6] wire _T_561; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126968.6] wire _T_562; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126969.6] wire _T_572; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@126992.4] reg [575:0] _T_573; // @[Monitor.scala 452:27:freechips.rocketchip.system.TinyConfig.fir@127001.4] reg [575:0] _RAND_9; reg _T_583; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@127011.4] reg [31:0] _RAND_10; wire _T_585; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@127013.4] wire _T_586; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@127014.4] reg _T_602; // @[Edges.scala 230:27:freechips.rocketchip.system.TinyConfig.fir@127033.4] reg [31:0] _RAND_11; wire _T_604; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@127035.4] wire _T_605; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@127036.4] wire _T_615; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@127051.4] wire [1023:0] _T_617; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@127054.6] wire [575:0] _T_618; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@127056.6] wire _T_619; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@127057.6] wire _T_620; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@127058.6] wire _T_622; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127060.6] wire _T_623; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127061.6] wire [1023:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@127053.4] wire _T_627; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@127072.4] wire [1023:0] _T_631; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@127077.6] wire [575:0] _T_613; // @[:freechips.rocketchip.system.TinyConfig.fir@127047.4 :freechips.rocketchip.system.TinyConfig.fir@127049.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@127055.6] wire [575:0] _T_632; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@127079.6] wire [575:0] _T_633; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@127080.6] wire _T_634; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@127081.6] wire _T_636; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127083.6] wire _T_637; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127084.6] wire [1023:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@127076.4] wire [575:0] _T_638; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@127090.4] wire [575:0] _T_624; // @[:freechips.rocketchip.system.TinyConfig.fir@127067.4 :freechips.rocketchip.system.TinyConfig.fir@127069.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@127078.6] wire [575:0] _T_639; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@127091.4] wire [575:0] _T_640; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@127092.4] reg [31:0] _T_641; // @[Monitor.scala 476:27:freechips.rocketchip.system.TinyConfig.fir@127094.4] reg [31:0] _RAND_12; wire _T_642; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@127097.4] wire _T_643; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@127098.4] wire _T_644; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@127099.4] wire _T_645; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@127100.4] wire _T_646; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@127101.4] wire _T_647; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@127102.4] wire _T_649; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127104.4] wire _T_650; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127105.4] wire [31:0] _T_652; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@127111.4] wire _T_655; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@127115.4] wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126079.10] wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@126151.10] wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126234.10] wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@126290.10] wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@126338.10] wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@126388.10] wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@126436.10] wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@126484.10] plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 44:11:freechips.rocketchip.system.TinyConfig.fir@127095.4] .out(plusarg_reader_out) ); assign _T_11 = io_in_a_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@125999.6] assign _T_15 = 5'h3 << io_in_a_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@126005.6] assign _T_16 = _T_15[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@126006.6] assign _T_17 = ~ _T_16; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@126007.6] assign _GEN_18 = {{15'd0}, _T_17}; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@126008.6] assign _T_18 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 22:16:freechips.rocketchip.system.TinyConfig.fir@126008.6] assign _T_19 = _T_18 == 17'h0; // @[Edges.scala 22:24:freechips.rocketchip.system.TinyConfig.fir@126009.6] assign _T_21 = io_in_a_bits_size[0]; // @[OneHot.scala 64:49:freechips.rocketchip.system.TinyConfig.fir@126011.6] assign _T_22 = 2'h1 << _T_21; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@126012.6] assign _T_24 = _T_22 | 2'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.TinyConfig.fir@126014.6] assign _T_25 = io_in_a_bits_size >= 2'h2; // @[Misc.scala 204:21:freechips.rocketchip.system.TinyConfig.fir@126015.6] assign _T_26 = _T_24[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@126016.6] assign _T_27 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@126017.6] assign _T_28 = _T_27 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@126018.6] assign _T_30 = _T_26 & _T_28; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126020.6] assign _T_31 = _T_25 | _T_30; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126021.6] assign _T_33 = _T_26 & _T_27; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126023.6] assign _T_34 = _T_25 | _T_33; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126024.6] assign _T_35 = _T_24[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.TinyConfig.fir@126025.6] assign _T_36 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.TinyConfig.fir@126026.6] assign _T_37 = _T_36 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.TinyConfig.fir@126027.6] assign _T_38 = _T_28 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126028.6] assign _T_39 = _T_35 & _T_38; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126029.6] assign _T_40 = _T_31 | _T_39; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126030.6] assign _T_41 = _T_28 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126031.6] assign _T_42 = _T_35 & _T_41; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126032.6] assign _T_43 = _T_31 | _T_42; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126033.6] assign _T_44 = _T_27 & _T_37; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126034.6] assign _T_45 = _T_35 & _T_44; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126035.6] assign _T_46 = _T_34 | _T_45; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126036.6] assign _T_47 = _T_27 & _T_36; // @[Misc.scala 212:27:freechips.rocketchip.system.TinyConfig.fir@126037.6] assign _T_48 = _T_35 & _T_47; // @[Misc.scala 213:38:freechips.rocketchip.system.TinyConfig.fir@126038.6] assign _T_49 = _T_34 | _T_48; // @[Misc.scala 213:29:freechips.rocketchip.system.TinyConfig.fir@126039.6] assign _T_52 = {_T_49,_T_46,_T_43,_T_40}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@126042.6] assign _T_71 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.TinyConfig.fir@126065.6] assign _T_73 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 123:31:freechips.rocketchip.system.TinyConfig.fir@126068.8] assign _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@126069.8] assign _T_75 = $signed(_T_74) & $signed(-18'sh10000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126070.8] assign _T_76 = $signed(_T_75); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@126071.8] assign _T_77 = $signed(_T_76) == $signed(18'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@126072.8] assign _T_82 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126077.8] assign _T_87 = _T_11 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126090.8] assign _T_88 = _T_87 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126091.8] assign _T_91 = _T_25 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126098.8] assign _T_92 = _T_91 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126099.8] assign _T_94 = _T_19 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126105.8] assign _T_95 = _T_94 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126106.8] assign _T_96 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 110:27:freechips.rocketchip.system.TinyConfig.fir@126111.8] assign _T_98 = _T_96 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126113.8] assign _T_99 = _T_98 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126114.8] assign _T_100 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.TinyConfig.fir@126119.8] assign _T_101 = _T_100 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.TinyConfig.fir@126120.8] assign _T_103 = _T_101 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126122.8] assign _T_104 = _T_103 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126123.8] assign _T_105 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.TinyConfig.fir@126128.8] assign _T_107 = _T_105 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126130.8] assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126131.8] assign _T_109 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@126137.6] assign _T_138 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.TinyConfig.fir@126191.8] assign _T_140 = _T_138 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126193.8] assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126194.8] assign _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.TinyConfig.fir@126217.6] assign _T_153 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42:freechips.rocketchip.system.TinyConfig.fir@126220.8] assign _T_161 = _T_153 & _T_77; // @[Parameters.scala 180:56:freechips.rocketchip.system.TinyConfig.fir@126228.8] assign _T_164 = _T_161 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126231.8] assign _T_165 = _T_164 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126232.8] assign _T_172 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.TinyConfig.fir@126251.8] assign _T_174 = _T_172 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126253.8] assign _T_175 = _T_174 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126254.8] assign _T_176 = io_in_a_bits_mask == _T_52; // @[Monitor.scala 76:27:freechips.rocketchip.system.TinyConfig.fir@126259.8] assign _T_178 = _T_176 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126261.8] assign _T_179 = _T_178 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126262.8] assign _T_184 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.TinyConfig.fir@126276.6] assign _T_210 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@126324.6] assign _T_232 = ~ _T_52; // @[Monitor.scala 93:30:freechips.rocketchip.system.TinyConfig.fir@126363.8] assign _T_233 = io_in_a_bits_mask & _T_232; // @[Monitor.scala 93:28:freechips.rocketchip.system.TinyConfig.fir@126364.8] assign _T_234 = _T_233 == 4'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.TinyConfig.fir@126365.8] assign _T_236 = _T_234 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126367.8] assign _T_237 = _T_236 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126368.8] assign _T_238 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.TinyConfig.fir@126374.6] assign _T_256 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 140:33:freechips.rocketchip.system.TinyConfig.fir@126405.8] assign _T_258 = _T_256 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126407.8] assign _T_259 = _T_258 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126408.8] assign _T_264 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.TinyConfig.fir@126422.6] assign _T_282 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 147:30:freechips.rocketchip.system.TinyConfig.fir@126453.8] assign _T_284 = _T_282 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126455.8] assign _T_285 = _T_284 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126456.8] assign _T_290 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.TinyConfig.fir@126470.6] assign _T_326 = io_in_d_bits_source <= 10'h23f; // @[Parameters.scala 57:20:freechips.rocketchip.system.TinyConfig.fir@126534.6] assign _T_332 = _T_326 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@126543.8] assign _T_333 = _T_332 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.TinyConfig.fir@126544.8] assign _T_471 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@126830.4] assign _T_482 = _T_480 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@126841.4] assign _T_483 = _T_480 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@126842.4] assign _T_496 = _T_483 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.TinyConfig.fir@126858.4] assign _T_497 = io_in_a_valid & _T_496; // @[Monitor.scala 354:19:freechips.rocketchip.system.TinyConfig.fir@126859.4] assign _T_498 = io_in_a_bits_opcode == _T_491; // @[Monitor.scala 355:29:freechips.rocketchip.system.TinyConfig.fir@126861.6] assign _T_500 = _T_498 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126863.6] assign _T_501 = _T_500 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126864.6] assign _T_502 = io_in_a_bits_param == _T_492; // @[Monitor.scala 356:29:freechips.rocketchip.system.TinyConfig.fir@126869.6] assign _T_504 = _T_502 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126871.6] assign _T_505 = _T_504 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126872.6] assign _T_506 = io_in_a_bits_size == _T_493; // @[Monitor.scala 357:29:freechips.rocketchip.system.TinyConfig.fir@126877.6] assign _T_508 = _T_506 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126879.6] assign _T_509 = _T_508 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126880.6] assign _T_510 = io_in_a_bits_source == _T_494; // @[Monitor.scala 358:29:freechips.rocketchip.system.TinyConfig.fir@126885.6] assign _T_512 = _T_510 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126887.6] assign _T_513 = _T_512 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126888.6] assign _T_514 = io_in_a_bits_address == _T_495; // @[Monitor.scala 359:29:freechips.rocketchip.system.TinyConfig.fir@126893.6] assign _T_516 = _T_514 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126895.6] assign _T_517 = _T_516 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126896.6] assign _T_519 = _T_471 & _T_483; // @[Monitor.scala 361:20:freechips.rocketchip.system.TinyConfig.fir@126903.4] assign _T_520 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 293:22:freechips.rocketchip.system.TinyConfig.fir@126911.4] assign _T_530 = _T_528 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@126921.4] assign _T_531 = _T_528 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@126922.4] assign _T_545 = _T_531 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.TinyConfig.fir@126939.4] assign _T_546 = io_in_d_valid & _T_545; // @[Monitor.scala 424:19:freechips.rocketchip.system.TinyConfig.fir@126940.4] assign _T_555 = io_in_d_bits_size == _T_541; // @[Monitor.scala 427:29:freechips.rocketchip.system.TinyConfig.fir@126958.6] assign _T_557 = _T_555 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126960.6] assign _T_558 = _T_557 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126961.6] assign _T_559 = io_in_d_bits_source == _T_542; // @[Monitor.scala 428:29:freechips.rocketchip.system.TinyConfig.fir@126966.6] assign _T_561 = _T_559 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126968.6] assign _T_562 = _T_561 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126969.6] assign _T_572 = _T_520 & _T_531; // @[Monitor.scala 432:20:freechips.rocketchip.system.TinyConfig.fir@126992.4] assign _T_585 = _T_583 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@127013.4] assign _T_586 = _T_583 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@127014.4] assign _T_604 = _T_602 - 1'h1; // @[Edges.scala 231:28:freechips.rocketchip.system.TinyConfig.fir@127035.4] assign _T_605 = _T_602 == 1'h0; // @[Edges.scala 232:25:freechips.rocketchip.system.TinyConfig.fir@127036.4] assign _T_615 = _T_471 & _T_586; // @[Monitor.scala 458:27:freechips.rocketchip.system.TinyConfig.fir@127051.4] assign _T_617 = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@127054.6] assign _T_618 = _T_573 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@127056.6] assign _T_619 = _T_618[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.TinyConfig.fir@127057.6] assign _T_620 = _T_619 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.TinyConfig.fir@127058.6] assign _T_622 = _T_620 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127060.6] assign _T_623 = _T_622 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127061.6] assign _GEN_15 = _T_615 ? _T_617 : 1024'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.TinyConfig.fir@127053.4] assign _T_627 = _T_520 & _T_605; // @[Monitor.scala 465:27:freechips.rocketchip.system.TinyConfig.fir@127072.4] assign _T_631 = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 58:35:freechips.rocketchip.system.TinyConfig.fir@127077.6] assign _T_613 = _GEN_15[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@127047.4 :freechips.rocketchip.system.TinyConfig.fir@127049.4 Monitor.scala 459:13:freechips.rocketchip.system.TinyConfig.fir@127055.6] assign _T_632 = _T_613 | _T_573; // @[Monitor.scala 467:21:freechips.rocketchip.system.TinyConfig.fir@127079.6] assign _T_633 = _T_632 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@127080.6] assign _T_634 = _T_633[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.TinyConfig.fir@127081.6] assign _T_636 = _T_634 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127083.6] assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127084.6] assign _GEN_16 = _T_627 ? _T_631 : 1024'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.TinyConfig.fir@127076.4] assign _T_638 = _T_573 | _T_613; // @[Monitor.scala 474:27:freechips.rocketchip.system.TinyConfig.fir@127090.4] assign _T_624 = _GEN_16[575:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@127067.4 :freechips.rocketchip.system.TinyConfig.fir@127069.4 Monitor.scala 466:13:freechips.rocketchip.system.TinyConfig.fir@127078.6] assign _T_639 = ~ _T_624; // @[Monitor.scala 474:38:freechips.rocketchip.system.TinyConfig.fir@127091.4] assign _T_640 = _T_638 & _T_639; // @[Monitor.scala 474:36:freechips.rocketchip.system.TinyConfig.fir@127092.4] assign _T_642 = _T_573 != 576'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.TinyConfig.fir@127097.4] assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.TinyConfig.fir@127098.4] assign _T_644 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.TinyConfig.fir@127099.4] assign _T_645 = _T_643 | _T_644; // @[Monitor.scala 479:27:freechips.rocketchip.system.TinyConfig.fir@127100.4] assign _T_646 = _T_641 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.TinyConfig.fir@127101.4] assign _T_647 = _T_645 | _T_646; // @[Monitor.scala 479:48:freechips.rocketchip.system.TinyConfig.fir@127102.4] assign _T_649 = _T_647 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127104.4] assign _T_650 = _T_649 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127105.4] assign _T_652 = _T_641 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.TinyConfig.fir@127111.4] assign _T_655 = _T_471 | _T_520; // @[Monitor.scala 482:27:freechips.rocketchip.system.TinyConfig.fir@127115.4] assign _GEN_19 = io_in_a_valid & _T_71; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126079.10] assign _GEN_35 = io_in_a_valid & _T_109; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@126151.10] assign _GEN_53 = io_in_a_valid & _T_151; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126234.10] assign _GEN_65 = io_in_a_valid & _T_184; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@126290.10] assign _GEN_75 = io_in_a_valid & _T_210; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@126338.10] assign _GEN_85 = io_in_a_valid & _T_238; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@126388.10] assign _GEN_95 = io_in_a_valid & _T_264; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@126436.10] assign _GEN_105 = io_in_a_valid & _T_290; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@126484.10] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_480 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_491 = _RAND_1[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_492 = _RAND_2[2:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_493 = _RAND_3[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_494 = _RAND_4[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_495 = _RAND_5[16:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_528 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_541 = _RAND_7[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_542 = _RAND_8[9:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {18{`RANDOM}}; _T_573 = _RAND_9[575:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_583 = _RAND_10[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_602 = _RAND_11[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_641 = _RAND_12[31:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_480 <= 1'h0; end else begin if (_T_471) begin if (_T_483) begin _T_480 <= 1'h0; end else begin _T_480 <= _T_482; end end end if (_T_519) begin _T_491 <= io_in_a_bits_opcode; end if (_T_519) begin _T_492 <= io_in_a_bits_param; end if (_T_519) begin _T_493 <= io_in_a_bits_size; end if (_T_519) begin _T_494 <= io_in_a_bits_source; end if (_T_519) begin _T_495 <= io_in_a_bits_address; end if (reset) begin _T_528 <= 1'h0; end else begin if (_T_520) begin if (_T_531) begin _T_528 <= 1'h0; end else begin _T_528 <= _T_530; end end end if (_T_572) begin _T_541 <= io_in_d_bits_size; end if (_T_572) begin _T_542 <= io_in_d_bits_source; end if (reset) begin _T_573 <= 576'h0; end else begin _T_573 <= _T_640; end if (reset) begin _T_583 <= 1'h0; end else begin if (_T_471) begin if (_T_586) begin _T_583 <= 1'h0; end else begin _T_583 <= _T_585; end end end if (reset) begin _T_602 <= 1'h0; end else begin if (_T_520) begin if (_T_605) begin _T_602 <= 1'h0; end else begin _T_602 <= _T_604; end end end if (reset) begin _T_641 <= 32'h0; end else begin if (_T_655) begin _T_641 <= 32'h0; end else begin _T_641 <= _T_652; end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126079.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.TinyConfig.fir@126080.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:74:16)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@126086.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_82) begin $fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.TinyConfig.fir@126087.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126093.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_88) begin $fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.TinyConfig.fir@126094.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:74:16)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126101.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_92) begin $fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.TinyConfig.fir@126102.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126108.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_95) begin $fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.TinyConfig.fir@126109.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:74:16)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126116.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_99) begin $fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.TinyConfig.fir@126117.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126125.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_104) begin $fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.TinyConfig.fir@126126.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_19 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:74:16)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126133.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_19 & _T_108) begin $fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.TinyConfig.fir@126134.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@126151.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.TinyConfig.fir@126152.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:74:16)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@126158.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_82) begin $fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.TinyConfig.fir@126159.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@126165.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_88) begin $fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.TinyConfig.fir@126166.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_92) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:74:16)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@126173.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_92) begin $fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.TinyConfig.fir@126174.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@126180.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_95) begin $fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.TinyConfig.fir@126181.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_99) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:74:16)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@126188.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_99) begin $fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.TinyConfig.fir@126189.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_141) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:74:16)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126196.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_141) begin $fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.TinyConfig.fir@126197.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_104) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@126205.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_104) begin $fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.TinyConfig.fir@126206.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_35 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:74:16)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@126213.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_35 & _T_108) begin $fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.TinyConfig.fir@126214.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_165) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126234.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_165) begin $fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.TinyConfig.fir@126235.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@126241.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_88) begin $fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.TinyConfig.fir@126242.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@126248.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_95) begin $fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.TinyConfig.fir@126249.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:74:16)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126256.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_175) begin $fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.TinyConfig.fir@126257.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126264.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_179) begin $fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.TinyConfig.fir@126265.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_53 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:74:16)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@126272.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_53 & _T_108) begin $fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.TinyConfig.fir@126273.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@126290.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_82) begin $fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.TinyConfig.fir@126291.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@126297.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_88) begin $fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.TinyConfig.fir@126298.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@126304.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_95) begin $fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.TinyConfig.fir@126305.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:74:16)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@126312.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_175) begin $fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.TinyConfig.fir@126313.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_65 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@126320.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_65 & _T_179) begin $fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.TinyConfig.fir@126321.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@126338.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_82) begin $fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.TinyConfig.fir@126339.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@126345.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_88) begin $fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.TinyConfig.fir@126346.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@126352.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_95) begin $fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.TinyConfig.fir@126353.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_175) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:74:16)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@126360.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_175) begin $fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.TinyConfig.fir@126361.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_75 & _T_237) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126370.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_75 & _T_237) begin $fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.TinyConfig.fir@126371.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@126388.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_82) begin $fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.TinyConfig.fir@126389.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@126395.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_88) begin $fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.TinyConfig.fir@126396.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@126402.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_95) begin $fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.TinyConfig.fir@126403.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_259) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:74:16)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126410.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_259) begin $fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.TinyConfig.fir@126411.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_85 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@126418.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_85 & _T_179) begin $fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.TinyConfig.fir@126419.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@126436.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_82) begin $fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.TinyConfig.fir@126437.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@126443.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_88) begin $fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.TinyConfig.fir@126444.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@126450.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_95) begin $fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.TinyConfig.fir@126451.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_285) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:74:16)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126458.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_285) begin $fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.TinyConfig.fir@126459.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_95 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@126466.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_95 & _T_179) begin $fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.TinyConfig.fir@126467.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_82) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BootROM.scala:74:16)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@126484.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_82) begin $fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.TinyConfig.fir@126485.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_88) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@126491.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_88) begin $fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.TinyConfig.fir@126492.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_95) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:74:16)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@126498.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_95) begin $fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.TinyConfig.fir@126499.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_179) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:74:16)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@126506.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_179) begin $fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.TinyConfig.fir@126507.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_GEN_105 & _T_108) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:74:16)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@126514.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_GEN_105 & _T_108) begin $fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.TinyConfig.fir@126515.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (io_in_d_valid & _T_333) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@126740.10] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (io_in_d_valid & _T_333) begin $fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.TinyConfig.fir@126741.10] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_497 & _T_501) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126866.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_497 & _T_501) begin $fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.TinyConfig.fir@126867.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_497 & _T_505) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126874.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_497 & _T_505) begin $fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.TinyConfig.fir@126875.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_497 & _T_509) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126882.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_497 & _T_509) begin $fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.TinyConfig.fir@126883.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_497 & _T_513) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126890.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_497 & _T_513) begin $fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.TinyConfig.fir@126891.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_497 & _T_517) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126898.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_497 & _T_517) begin $fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.TinyConfig.fir@126899.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_546 & _T_558) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126963.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_546 & _T_558) begin $fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.TinyConfig.fir@126964.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_546 & _T_562) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:74:16)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126971.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_546 & _T_562) begin $fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.TinyConfig.fir@126972.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_615 & _T_623) begin $fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:74:16)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127063.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_615 & _T_623) begin $fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.TinyConfig.fir@127064.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_627 & _T_637) begin $fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:74:16)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127086.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_627 & _T_637) begin $fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.TinyConfig.fir@127087.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_650) begin $fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BootROM.scala:74:16)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127107.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_650) begin $fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.TinyConfig.fir@127108.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module TLROM( // @[:freechips.rocketchip.system.TinyConfig.fir@127120.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@127121.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@127122.4] output auto_in_a_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input auto_in_a_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [9:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [16:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] input auto_in_d_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] output auto_in_d_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] output [9:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] output [31:0] auto_in_d_bits_data // @[:freechips.rocketchip.system.TinyConfig.fir@127123.4] ); wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [9:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [16:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [9:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] wire [9:0] index; // @[BootROM.scala 50:34:freechips.rocketchip.system.TinyConfig.fir@128208.4] wire [3:0] high; // @[BootROM.scala 51:68:freechips.rocketchip.system.TinyConfig.fir@128209.4] wire _T_12; // @[BootROM.scala 52:53:freechips.rocketchip.system.TinyConfig.fir@128210.4] wire [31:0] _GEN_1; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_2; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_3; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_4; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_5; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_6; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_7; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_8; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_9; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_10; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_11; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_12; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_13; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_14; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_15; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_16; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_17; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_18; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_19; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_20; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_21; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_22; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_23; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_24; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_25; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_26; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_27; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_28; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_29; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_30; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_31; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_32; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_33; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_34; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_35; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_36; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_37; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_38; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_39; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_40; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_41; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_42; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_43; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_44; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_45; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_46; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_47; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_48; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_49; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_50; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_51; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_52; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_53; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_54; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_55; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_56; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_57; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_58; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_59; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_60; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_61; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_62; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_63; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_64; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_65; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_66; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_67; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_68; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_69; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_70; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_71; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_72; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_73; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_74; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_75; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_76; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_77; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_78; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_79; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_80; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_81; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_82; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_83; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_84; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_85; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_86; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_87; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_88; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_89; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_90; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_91; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_92; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_93; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_94; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_95; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_96; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_97; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_98; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_99; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_100; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_101; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_102; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_103; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_104; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_105; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_106; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_107; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_108; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_109; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_110; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_111; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_112; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_113; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_114; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_115; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_116; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_117; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_118; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_119; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_120; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_121; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_122; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_123; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_124; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_125; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_126; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_127; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_128; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_129; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_130; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_131; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_132; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_133; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_134; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_135; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_136; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_137; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_138; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_139; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_140; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_141; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_142; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_143; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_144; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_145; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_146; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_147; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_148; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_149; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_150; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_151; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_152; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_153; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_154; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_155; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_156; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_157; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_158; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_159; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_160; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_161; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_162; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_163; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_164; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_165; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_166; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_167; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_168; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_169; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_170; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_171; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_172; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_173; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_174; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_175; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_176; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_177; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_178; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_179; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_180; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_181; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_182; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_183; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_184; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_185; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_186; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_187; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_188; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_189; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_190; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_191; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_192; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_193; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_194; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_195; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_196; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_197; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_198; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_199; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_200; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_201; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_202; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_203; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_204; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_205; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_206; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_207; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_208; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_209; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_210; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_211; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_212; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_213; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_214; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_215; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_216; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_217; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_218; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_219; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_220; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_221; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_222; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_223; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_224; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_225; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_226; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_227; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_228; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_229; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_230; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_231; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_232; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_233; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_234; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_235; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_236; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_237; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_238; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_239; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_240; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_241; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_242; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_243; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_244; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_245; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_246; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_247; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_248; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_249; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_250; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_251; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_252; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_253; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_254; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_255; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_256; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_257; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_258; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_259; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_260; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_261; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_262; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_263; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_264; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_265; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_266; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_267; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_268; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_269; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_270; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_271; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_272; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_273; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_274; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_275; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_276; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_277; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_278; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_279; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_280; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_281; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_282; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_283; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_284; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_285; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_286; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_287; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_288; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_289; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_290; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_291; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_292; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_293; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_294; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_295; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_296; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_297; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_298; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_299; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_300; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_301; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_302; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_303; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_304; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_305; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_306; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_307; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_308; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_309; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_310; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_311; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_312; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_313; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_314; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_315; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_316; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_317; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_318; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_319; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_320; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_321; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_322; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_323; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_324; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_325; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_326; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_327; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_328; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_329; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_330; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_331; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_332; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_333; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_334; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_335; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_336; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_337; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_338; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_339; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_340; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_341; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_342; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_343; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_344; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_345; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_346; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_347; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_348; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_349; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_350; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_351; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_352; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_353; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_354; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_355; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_356; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_357; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_358; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_359; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_360; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_361; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_362; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_363; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_364; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_365; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_366; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_367; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_368; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_369; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_370; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_371; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_372; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_373; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_374; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_375; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_376; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_377; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_378; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_379; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_380; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_381; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_382; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_383; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_384; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_385; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_386; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_387; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_388; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_389; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_390; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_391; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_392; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_393; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_394; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_395; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_396; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_397; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_398; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_399; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_400; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_401; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_402; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_403; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_404; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_405; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_406; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_407; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_408; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_409; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_410; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_411; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_412; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_413; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_414; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_415; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_416; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_417; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_418; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_419; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_420; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_421; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_422; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_423; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_424; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_425; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_426; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_427; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_428; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_429; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_430; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_431; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_432; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_433; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_434; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_435; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_436; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_437; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_438; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_439; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_440; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_441; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_442; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_443; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_444; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_445; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_446; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_447; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_448; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_449; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_450; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_451; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_452; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_453; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_454; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_455; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_456; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_457; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_458; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_459; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_460; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_461; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_462; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_463; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_464; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_465; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_466; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_467; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_468; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_469; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_470; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_471; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_472; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_473; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_474; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_475; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_476; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_477; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_478; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_479; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_480; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_481; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_482; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_483; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_484; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_485; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_486; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_487; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_488; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_489; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_490; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_491; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_492; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_493; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_494; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_495; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_496; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_497; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_498; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_499; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_500; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_501; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_502; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_503; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_504; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_505; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_506; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_507; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_508; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_509; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_510; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_511; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_512; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_513; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_514; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_515; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_516; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_517; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_518; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_519; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_520; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_521; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_522; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_523; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_524; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_525; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_526; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_527; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_528; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_529; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_530; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_531; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_532; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_533; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_534; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_535; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_536; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_537; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_538; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_539; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_540; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_541; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_542; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_543; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_544; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_545; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_546; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_547; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_548; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_549; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_550; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_551; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_552; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_553; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_554; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_555; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_556; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_557; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_558; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_559; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_560; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_561; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_562; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_563; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_564; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_565; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_566; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_567; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_568; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_569; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_570; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_571; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_572; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_573; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_574; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_575; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_576; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_577; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_578; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_579; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_580; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_581; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_582; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_583; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_584; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_585; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_586; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_587; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_588; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_589; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_590; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_591; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_592; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_593; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_594; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_595; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_596; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_597; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_598; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_599; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_600; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_601; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_602; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_603; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_604; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_605; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_606; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_607; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_608; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_609; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_610; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_611; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_612; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_613; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_614; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_615; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_616; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_617; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_618; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_619; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_620; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_621; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_622; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_623; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_624; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_625; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_626; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_627; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_628; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_629; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_630; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_631; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_632; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_633; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_634; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_635; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_636; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_637; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_638; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_639; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_640; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_641; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_642; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_643; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_644; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_645; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_646; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_647; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_648; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_649; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_650; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_651; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_652; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_653; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_654; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_655; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_656; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_657; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_658; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_659; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_660; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_661; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_662; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_663; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_664; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_665; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_666; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_667; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_668; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_669; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_670; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_671; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_672; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_673; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_674; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_675; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_676; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_677; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_678; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_679; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_680; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_681; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_682; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_683; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_684; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_685; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_686; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_687; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_688; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_689; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_690; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_691; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_692; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_693; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_694; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_695; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_696; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_697; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_698; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_699; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_700; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_701; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_702; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_703; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_704; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_705; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_706; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_707; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_708; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_709; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_710; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_711; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_712; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_713; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_714; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_715; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_716; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_717; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_718; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_719; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_720; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_721; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_722; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_723; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_724; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_725; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_726; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_727; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_728; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_729; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_730; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_731; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_732; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_733; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_734; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_735; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_736; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_737; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_738; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_739; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_740; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_741; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_742; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_743; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_744; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_745; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_746; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_747; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_748; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_749; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_750; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_751; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_752; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_753; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_754; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_755; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_756; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_757; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_758; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_759; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_760; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_761; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_762; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_763; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_764; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_765; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_766; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_767; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_768; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_769; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_770; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_771; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_772; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_773; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_774; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_775; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_776; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_777; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_778; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_779; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_780; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_781; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_782; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_783; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_784; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_785; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_786; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_787; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_788; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_789; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_790; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_791; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_792; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_793; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_794; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_795; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_796; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_797; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_798; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_799; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_800; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_801; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_802; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_803; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_804; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_805; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_806; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_807; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_808; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_809; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_810; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_811; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_812; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_813; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_814; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_815; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_816; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_817; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_818; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_819; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_820; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_821; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_822; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_823; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_824; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_825; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_826; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_827; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_828; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_829; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_830; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_831; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_832; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_833; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_834; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_835; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_836; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_837; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_838; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_839; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_840; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_841; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_842; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_843; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_844; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_845; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_846; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_847; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_848; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_849; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_850; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_851; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_852; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_853; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_854; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_855; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_856; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_857; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_858; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_859; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_860; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_861; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_862; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_863; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_864; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_865; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_866; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_867; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_868; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_869; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_870; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_871; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_872; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_873; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_874; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_875; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_876; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_877; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_878; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_879; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_880; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_881; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_882; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_883; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_884; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_885; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_886; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_887; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_888; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_889; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_890; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_891; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_892; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_893; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_894; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_895; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_896; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_897; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_898; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_899; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_900; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_901; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_902; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_903; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_904; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_905; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_906; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_907; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_908; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_909; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_910; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_911; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_912; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_913; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_914; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_915; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_916; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_917; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_918; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_919; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_920; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_921; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_922; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_923; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_924; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_925; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_926; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_927; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_928; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_929; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_930; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_931; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_932; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_933; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_934; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_935; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_936; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_937; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_938; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_939; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_940; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_941; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_942; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_943; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_944; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_945; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_946; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_947; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_948; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_949; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_950; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_951; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_952; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_953; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_954; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_955; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_956; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_957; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_958; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_959; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_960; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_961; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_962; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_963; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_964; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_965; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_966; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_967; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_968; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_969; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_970; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_971; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_972; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_973; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_974; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_975; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_976; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_977; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_978; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_979; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_980; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_981; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_982; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_983; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_984; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_985; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_986; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_987; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_988; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_989; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_990; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_991; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_992; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_993; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_994; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_995; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_996; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_997; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_998; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_999; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1000; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1001; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1002; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1003; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1004; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1005; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1006; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1007; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1008; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1009; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1010; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1011; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1012; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1013; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1014; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1015; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1016; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1017; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1018; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1019; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1020; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1021; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1022; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] wire [31:0] _GEN_1023; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] TLMonitor_38 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.TinyConfig.fir@127130.4] .clock(TLMonitor_clock), .reset(TLMonitor_reset), .io_in_a_ready(TLMonitor_io_in_a_ready), .io_in_a_valid(TLMonitor_io_in_a_valid), .io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode), .io_in_a_bits_param(TLMonitor_io_in_a_bits_param), .io_in_a_bits_size(TLMonitor_io_in_a_bits_size), .io_in_a_bits_source(TLMonitor_io_in_a_bits_source), .io_in_a_bits_address(TLMonitor_io_in_a_bits_address), .io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask), .io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt), .io_in_d_ready(TLMonitor_io_in_d_ready), .io_in_d_valid(TLMonitor_io_in_d_valid), .io_in_d_bits_size(TLMonitor_io_in_d_bits_size), .io_in_d_bits_source(TLMonitor_io_in_d_bits_source) ); assign index = auto_in_a_bits_address[11:2]; // @[BootROM.scala 50:34:freechips.rocketchip.system.TinyConfig.fir@128208.4] assign high = auto_in_a_bits_address[15:12]; // @[BootROM.scala 51:68:freechips.rocketchip.system.TinyConfig.fir@128209.4] assign _T_12 = high != 4'h0; // @[BootROM.scala 52:53:freechips.rocketchip.system.TinyConfig.fir@128210.4] assign _GEN_1 = 10'h1 == index ? 32'h10041b : 32'h7c105073; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_2 = 10'h2 == index ? 32'h1f41413 : _GEN_1; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_3 = 10'h3 == index ? 32'hf1402573 : _GEN_2; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_4 = 10'h4 == index ? 32'h597 : _GEN_3; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_5 = 10'h5 == index ? 32'h7058593 : _GEN_4; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_6 = 10'h6 == index ? 32'h8402 : _GEN_5; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_7 = 10'h7 == index ? 32'h0 : _GEN_6; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_8 = 10'h8 == index ? 32'h0 : _GEN_7; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_9 = 10'h9 == index ? 32'h0 : _GEN_8; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_10 = 10'ha == index ? 32'h0 : _GEN_9; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_11 = 10'hb == index ? 32'h0 : _GEN_10; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_12 = 10'hc == index ? 32'h0 : _GEN_11; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_13 = 10'hd == index ? 32'h0 : _GEN_12; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_14 = 10'he == index ? 32'h0 : _GEN_13; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_15 = 10'hf == index ? 32'h0 : _GEN_14; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_16 = 10'h10 == index ? 32'h7c105073 : _GEN_15; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_17 = 10'h11 == index ? 32'hf1402573 : _GEN_16; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_18 = 10'h12 == index ? 32'h597 : _GEN_17; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_19 = 10'h13 == index ? 32'h3858593 : _GEN_18; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_20 = 10'h14 == index ? 32'h30405073 : _GEN_19; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_21 = 10'h15 == index ? 32'h10500073 : _GEN_20; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_22 = 10'h16 == index ? 32'hbff5 : _GEN_21; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_23 = 10'h17 == index ? 32'h0 : _GEN_22; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_24 = 10'h18 == index ? 32'h0 : _GEN_23; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_25 = 10'h19 == index ? 32'h0 : _GEN_24; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_26 = 10'h1a == index ? 32'h0 : _GEN_25; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_27 = 10'h1b == index ? 32'h0 : _GEN_26; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_28 = 10'h1c == index ? 32'h0 : _GEN_27; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_29 = 10'h1d == index ? 32'h0 : _GEN_28; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_30 = 10'h1e == index ? 32'h0 : _GEN_29; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_31 = 10'h1f == index ? 32'h0 : _GEN_30; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_32 = 10'h20 == index ? 32'hedfe0dd0 : _GEN_31; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_33 = 10'h21 == index ? 32'he4070000 : _GEN_32; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_34 = 10'h22 == index ? 32'h38000000 : _GEN_33; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_35 = 10'h23 == index ? 32'h78060000 : _GEN_34; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_36 = 10'h24 == index ? 32'h28000000 : _GEN_35; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_37 = 10'h25 == index ? 32'h11000000 : _GEN_36; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_38 = 10'h26 == index ? 32'h10000000 : _GEN_37; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_39 = 10'h27 == index ? 32'h0 : _GEN_38; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_40 = 10'h28 == index ? 32'h6c010000 : _GEN_39; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_41 = 10'h29 == index ? 32'h40060000 : _GEN_40; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_42 = 10'h2a == index ? 32'h0 : _GEN_41; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_43 = 10'h2b == index ? 32'h0 : _GEN_42; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_44 = 10'h2c == index ? 32'h0 : _GEN_43; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_45 = 10'h2d == index ? 32'h0 : _GEN_44; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_46 = 10'h2e == index ? 32'h1000000 : _GEN_45; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_47 = 10'h2f == index ? 32'h0 : _GEN_46; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_48 = 10'h30 == index ? 32'h3000000 : _GEN_47; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_49 = 10'h31 == index ? 32'h4000000 : _GEN_48; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_50 = 10'h32 == index ? 32'h0 : _GEN_49; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_51 = 10'h33 == index ? 32'h1000000 : _GEN_50; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_52 = 10'h34 == index ? 32'h3000000 : _GEN_51; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_53 = 10'h35 == index ? 32'h4000000 : _GEN_52; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_54 = 10'h36 == index ? 32'hf000000 : _GEN_53; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_55 = 10'h37 == index ? 32'h1000000 : _GEN_54; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_56 = 10'h38 == index ? 32'h3000000 : _GEN_55; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_57 = 10'h39 == index ? 32'h21000000 : _GEN_56; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_58 = 10'h3a == index ? 32'h1b000000 : _GEN_57; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_59 = 10'h3b == index ? 32'h65657266 : _GEN_58; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_60 = 10'h3c == index ? 32'h70696863 : _GEN_59; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_61 = 10'h3d == index ? 32'h6f722c73 : _GEN_60; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_62 = 10'h3e == index ? 32'h74656b63 : _GEN_61; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_63 = 10'h3f == index ? 32'h70696863 : _GEN_62; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_64 = 10'h40 == index ? 32'h6b6e752d : _GEN_63; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_65 = 10'h41 == index ? 32'h6e776f6e : _GEN_64; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_66 = 10'h42 == index ? 32'h7665642d : _GEN_65; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_67 = 10'h43 == index ? 32'h0 : _GEN_66; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_68 = 10'h44 == index ? 32'h3000000 : _GEN_67; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_69 = 10'h45 == index ? 32'h1d000000 : _GEN_68; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_70 = 10'h46 == index ? 32'h26000000 : _GEN_69; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_71 = 10'h47 == index ? 32'h65657266 : _GEN_70; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_72 = 10'h48 == index ? 32'h70696863 : _GEN_71; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_73 = 10'h49 == index ? 32'h6f722c73 : _GEN_72; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_74 = 10'h4a == index ? 32'h74656b63 : _GEN_73; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_75 = 10'h4b == index ? 32'h70696863 : _GEN_74; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_76 = 10'h4c == index ? 32'h6b6e752d : _GEN_75; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_77 = 10'h4d == index ? 32'h6e776f6e : _GEN_76; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_78 = 10'h4e == index ? 32'h0 : _GEN_77; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_79 = 10'h4f == index ? 32'h1000000 : _GEN_78; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_80 = 10'h50 == index ? 32'h73757063 : _GEN_79; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_81 = 10'h51 == index ? 32'h0 : _GEN_80; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_82 = 10'h52 == index ? 32'h3000000 : _GEN_81; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_83 = 10'h53 == index ? 32'h4000000 : _GEN_82; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_84 = 10'h54 == index ? 32'h0 : _GEN_83; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_85 = 10'h55 == index ? 32'h1000000 : _GEN_84; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_86 = 10'h56 == index ? 32'h3000000 : _GEN_85; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_87 = 10'h57 == index ? 32'h4000000 : _GEN_86; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_88 = 10'h58 == index ? 32'hf000000 : _GEN_87; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_89 = 10'h59 == index ? 32'h0 : _GEN_88; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_90 = 10'h5a == index ? 32'h1000000 : _GEN_89; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_91 = 10'h5b == index ? 32'h40757063 : _GEN_90; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_92 = 10'h5c == index ? 32'h30 : _GEN_91; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_93 = 10'h5d == index ? 32'h3000000 : _GEN_92; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_94 = 10'h5e == index ? 32'h4000000 : _GEN_93; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_95 = 10'h5f == index ? 32'h2c000000 : _GEN_94; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_96 = 10'h60 == index ? 32'h0 : _GEN_95; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_97 = 10'h61 == index ? 32'h3000000 : _GEN_96; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_98 = 10'h62 == index ? 32'h15000000 : _GEN_97; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_99 = 10'h63 == index ? 32'h1b000000 : _GEN_98; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_100 = 10'h64 == index ? 32'h69666973 : _GEN_99; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_101 = 10'h65 == index ? 32'h722c6576 : _GEN_100; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_102 = 10'h66 == index ? 32'h656b636f : _GEN_101; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_103 = 10'h67 == index ? 32'h72003074 : _GEN_102; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_104 = 10'h68 == index ? 32'h76637369 : _GEN_103; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_105 = 10'h69 == index ? 32'h0 : _GEN_104; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_106 = 10'h6a == index ? 32'h3000000 : _GEN_105; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_107 = 10'h6b == index ? 32'h4000000 : _GEN_106; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_108 = 10'h6c == index ? 32'h3c000000 : _GEN_107; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_109 = 10'h6d == index ? 32'h757063 : _GEN_108; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_110 = 10'h6e == index ? 32'h3000000 : _GEN_109; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_111 = 10'h6f == index ? 32'h4000000 : _GEN_110; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_112 = 10'h70 == index ? 32'h48000000 : _GEN_111; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_113 = 10'h71 == index ? 32'h1000000 : _GEN_112; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_114 = 10'h72 == index ? 32'h3000000 : _GEN_113; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_115 = 10'h73 == index ? 32'h4000000 : _GEN_114; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_116 = 10'h74 == index ? 32'h67000000 : _GEN_115; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_117 = 10'h75 == index ? 32'h40000000 : _GEN_116; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_118 = 10'h76 == index ? 32'h3000000 : _GEN_117; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_119 = 10'h77 == index ? 32'h4000000 : _GEN_118; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_120 = 10'h78 == index ? 32'h7a000000 : _GEN_119; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_121 = 10'h79 == index ? 32'h4000000 : _GEN_120; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_122 = 10'h7a == index ? 32'h3000000 : _GEN_121; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_123 = 10'h7b == index ? 32'h4000000 : _GEN_122; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_124 = 10'h7c == index ? 32'h87000000 : _GEN_123; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_125 = 10'h7d == index ? 32'h10000 : _GEN_124; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_126 = 10'h7e == index ? 32'h3000000 : _GEN_125; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_127 = 10'h7f == index ? 32'h4000000 : _GEN_126; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_128 = 10'h80 == index ? 32'h94000000 : _GEN_127; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_129 = 10'h81 == index ? 32'h0 : _GEN_128; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_130 = 10'h82 == index ? 32'h3000000 : _GEN_129; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_131 = 10'h83 == index ? 32'h9000000 : _GEN_130; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_132 = 10'h84 == index ? 32'h98000000 : _GEN_131; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_133 = 10'h85 == index ? 32'h32337672 : _GEN_132; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_134 = 10'h86 == index ? 32'h63616d69 : _GEN_133; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_135 = 10'h87 == index ? 32'h0 : _GEN_134; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_136 = 10'h88 == index ? 32'h3000000 : _GEN_135; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_137 = 10'h89 == index ? 32'h4000000 : _GEN_136; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_138 = 10'h8a == index ? 32'ha2000000 : _GEN_137; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_139 = 10'h8b == index ? 32'h8000000 : _GEN_138; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_140 = 10'h8c == index ? 32'h3000000 : _GEN_139; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_141 = 10'h8d == index ? 32'h4000000 : _GEN_140; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_142 = 10'h8e == index ? 32'hb3000000 : _GEN_141; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_143 = 10'h8f == index ? 32'h1000000 : _GEN_142; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_144 = 10'h90 == index ? 32'h3000000 : _GEN_143; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_145 = 10'h91 == index ? 32'h5000000 : _GEN_144; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_146 = 10'h92 == index ? 32'hbf000000 : _GEN_145; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_147 = 10'h93 == index ? 32'h79616b6f : _GEN_146; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_148 = 10'h94 == index ? 32'h0 : _GEN_147; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_149 = 10'h95 == index ? 32'h3000000 : _GEN_148; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_150 = 10'h96 == index ? 32'h4000000 : _GEN_149; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_151 = 10'h97 == index ? 32'hc6000000 : _GEN_150; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_152 = 10'h98 == index ? 32'h40420f00 : _GEN_151; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_153 = 10'h99 == index ? 32'h1000000 : _GEN_152; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_154 = 10'h9a == index ? 32'h65746e69 : _GEN_153; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_155 = 10'h9b == index ? 32'h70757272 : _GEN_154; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_156 = 10'h9c == index ? 32'h6f632d74 : _GEN_155; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_157 = 10'h9d == index ? 32'h6f72746e : _GEN_156; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_158 = 10'h9e == index ? 32'h72656c6c : _GEN_157; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_159 = 10'h9f == index ? 32'h0 : _GEN_158; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_160 = 10'ha0 == index ? 32'h3000000 : _GEN_159; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_161 = 10'ha1 == index ? 32'h4000000 : _GEN_160; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_162 = 10'ha2 == index ? 32'hd9000000 : _GEN_161; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_163 = 10'ha3 == index ? 32'h1000000 : _GEN_162; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_164 = 10'ha4 == index ? 32'h3000000 : _GEN_163; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_165 = 10'ha5 == index ? 32'hf000000 : _GEN_164; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_166 = 10'ha6 == index ? 32'h1b000000 : _GEN_165; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_167 = 10'ha7 == index ? 32'h63736972 : _GEN_166; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_168 = 10'ha8 == index ? 32'h70632c76 : _GEN_167; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_169 = 10'ha9 == index ? 32'h6e692d75 : _GEN_168; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_170 = 10'haa == index ? 32'h6374 : _GEN_169; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_171 = 10'hab == index ? 32'h3000000 : _GEN_170; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_172 = 10'hac == index ? 32'h0 : _GEN_171; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_173 = 10'had == index ? 32'hea000000 : _GEN_172; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_174 = 10'hae == index ? 32'h3000000 : _GEN_173; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_175 = 10'haf == index ? 32'h4000000 : _GEN_174; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_176 = 10'hb0 == index ? 32'hff000000 : _GEN_175; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_177 = 10'hb1 == index ? 32'h2000000 : _GEN_176; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_178 = 10'hb2 == index ? 32'h3000000 : _GEN_177; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_179 = 10'hb3 == index ? 32'h4000000 : _GEN_178; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_180 = 10'hb4 == index ? 32'h5010000 : _GEN_179; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_181 = 10'hb5 == index ? 32'h2000000 : _GEN_180; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_182 = 10'hb6 == index ? 32'h2000000 : _GEN_181; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_183 = 10'hb7 == index ? 32'h2000000 : _GEN_182; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_184 = 10'hb8 == index ? 32'h2000000 : _GEN_183; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_185 = 10'hb9 == index ? 32'h1000000 : _GEN_184; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_186 = 10'hba == index ? 32'h636f73 : _GEN_185; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_187 = 10'hbb == index ? 32'h3000000 : _GEN_186; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_188 = 10'hbc == index ? 32'h4000000 : _GEN_187; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_189 = 10'hbd == index ? 32'h0 : _GEN_188; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_190 = 10'hbe == index ? 32'h1000000 : _GEN_189; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_191 = 10'hbf == index ? 32'h3000000 : _GEN_190; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_192 = 10'hc0 == index ? 32'h4000000 : _GEN_191; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_193 = 10'hc1 == index ? 32'hf000000 : _GEN_192; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_194 = 10'hc2 == index ? 32'h1000000 : _GEN_193; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_195 = 10'hc3 == index ? 32'h3000000 : _GEN_194; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_196 = 10'hc4 == index ? 32'h2c000000 : _GEN_195; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_197 = 10'hc5 == index ? 32'h1b000000 : _GEN_196; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_198 = 10'hc6 == index ? 32'h65657266 : _GEN_197; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_199 = 10'hc7 == index ? 32'h70696863 : _GEN_198; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_200 = 10'hc8 == index ? 32'h6f722c73 : _GEN_199; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_201 = 10'hc9 == index ? 32'h74656b63 : _GEN_200; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_202 = 10'hca == index ? 32'h70696863 : _GEN_201; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_203 = 10'hcb == index ? 32'h6b6e752d : _GEN_202; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_204 = 10'hcc == index ? 32'h6e776f6e : _GEN_203; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_205 = 10'hcd == index ? 32'h636f732d : _GEN_204; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_206 = 10'hce == index ? 32'h6d697300 : _GEN_205; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_207 = 10'hcf == index ? 32'h2d656c70 : _GEN_206; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_208 = 10'hd0 == index ? 32'h737562 : _GEN_207; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_209 = 10'hd1 == index ? 32'h3000000 : _GEN_208; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_210 = 10'hd2 == index ? 32'h0 : _GEN_209; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_211 = 10'hd3 == index ? 32'hd010000 : _GEN_210; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_212 = 10'hd4 == index ? 32'h1000000 : _GEN_211; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_213 = 10'hd5 == index ? 32'h6e696c63 : _GEN_212; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_214 = 10'hd6 == index ? 32'h30324074 : _GEN_213; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_215 = 10'hd7 == index ? 32'h30303030 : _GEN_214; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_216 = 10'hd8 == index ? 32'h30 : _GEN_215; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_217 = 10'hd9 == index ? 32'h3000000 : _GEN_216; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_218 = 10'hda == index ? 32'hd000000 : _GEN_217; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_219 = 10'hdb == index ? 32'h1b000000 : _GEN_218; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_220 = 10'hdc == index ? 32'h63736972 : _GEN_219; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_221 = 10'hdd == index ? 32'h6c632c76 : _GEN_220; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_222 = 10'hde == index ? 32'h30746e69 : _GEN_221; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_223 = 10'hdf == index ? 32'h0 : _GEN_222; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_224 = 10'he0 == index ? 32'h3000000 : _GEN_223; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_225 = 10'he1 == index ? 32'h10000000 : _GEN_224; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_226 = 10'he2 == index ? 32'h14010000 : _GEN_225; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_227 = 10'he3 == index ? 32'h2000000 : _GEN_226; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_228 = 10'he4 == index ? 32'h3000000 : _GEN_227; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_229 = 10'he5 == index ? 32'h2000000 : _GEN_228; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_230 = 10'he6 == index ? 32'h7000000 : _GEN_229; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_231 = 10'he7 == index ? 32'h3000000 : _GEN_230; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_232 = 10'he8 == index ? 32'h8000000 : _GEN_231; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_233 = 10'he9 == index ? 32'h94000000 : _GEN_232; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_234 = 10'hea == index ? 32'h2 : _GEN_233; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_235 = 10'heb == index ? 32'h100 : _GEN_234; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_236 = 10'hec == index ? 32'h3000000 : _GEN_235; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_237 = 10'hed == index ? 32'h8000000 : _GEN_236; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_238 = 10'hee == index ? 32'h28010000 : _GEN_237; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_239 = 10'hef == index ? 32'h746e6f63 : _GEN_238; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_240 = 10'hf0 == index ? 32'h6c6f72 : _GEN_239; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_241 = 10'hf1 == index ? 32'h2000000 : _GEN_240; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_242 = 10'hf2 == index ? 32'h1000000 : _GEN_241; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_243 = 10'hf3 == index ? 32'h75626564 : _GEN_242; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_244 = 10'hf4 == index ? 32'h6f632d67 : _GEN_243; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_245 = 10'hf5 == index ? 32'h6f72746e : _GEN_244; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_246 = 10'hf6 == index ? 32'h72656c6c : _GEN_245; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_247 = 10'hf7 == index ? 32'h3040 : _GEN_246; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_248 = 10'hf8 == index ? 32'h3000000 : _GEN_247; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_249 = 10'hf9 == index ? 32'h21000000 : _GEN_248; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_250 = 10'hfa == index ? 32'h1b000000 : _GEN_249; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_251 = 10'hfb == index ? 32'h69666973 : _GEN_250; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_252 = 10'hfc == index ? 32'h642c6576 : _GEN_251; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_253 = 10'hfd == index ? 32'h67756265 : _GEN_252; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_254 = 10'hfe == index ? 32'h3331302d : _GEN_253; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_255 = 10'hff == index ? 32'h73697200 : _GEN_254; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_256 = 10'h100 == index ? 32'h642c7663 : _GEN_255; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_257 = 10'h101 == index ? 32'h67756265 : _GEN_256; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_258 = 10'h102 == index ? 32'h3331302d : _GEN_257; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_259 = 10'h103 == index ? 32'h0 : _GEN_258; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_260 = 10'h104 == index ? 32'h3000000 : _GEN_259; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_261 = 10'h105 == index ? 32'h8000000 : _GEN_260; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_262 = 10'h106 == index ? 32'h14010000 : _GEN_261; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_263 = 10'h107 == index ? 32'h2000000 : _GEN_262; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_264 = 10'h108 == index ? 32'hffff0000 : _GEN_263; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_265 = 10'h109 == index ? 32'h3000000 : _GEN_264; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_266 = 10'h10a == index ? 32'h8000000 : _GEN_265; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_267 = 10'h10b == index ? 32'h94000000 : _GEN_266; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_268 = 10'h10c == index ? 32'h0 : _GEN_267; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_269 = 10'h10d == index ? 32'h100000 : _GEN_268; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_270 = 10'h10e == index ? 32'h3000000 : _GEN_269; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_271 = 10'h10f == index ? 32'h8000000 : _GEN_270; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_272 = 10'h110 == index ? 32'h28010000 : _GEN_271; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_273 = 10'h111 == index ? 32'h746e6f63 : _GEN_272; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_274 = 10'h112 == index ? 32'h6c6f72 : _GEN_273; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_275 = 10'h113 == index ? 32'h2000000 : _GEN_274; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_276 = 10'h114 == index ? 32'h1000000 : _GEN_275; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_277 = 10'h115 == index ? 32'h6d697464 : _GEN_276; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_278 = 10'h116 == index ? 32'h30303840 : _GEN_277; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_279 = 10'h117 == index ? 32'h30303030 : _GEN_278; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_280 = 10'h118 == index ? 32'h30 : _GEN_279; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_281 = 10'h119 == index ? 32'h3000000 : _GEN_280; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_282 = 10'h11a == index ? 32'hd000000 : _GEN_281; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_283 = 10'h11b == index ? 32'h1b000000 : _GEN_282; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_284 = 10'h11c == index ? 32'h69666973 : _GEN_283; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_285 = 10'h11d == index ? 32'h642c6576 : _GEN_284; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_286 = 10'h11e == index ? 32'h306d6974 : _GEN_285; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_287 = 10'h11f == index ? 32'h0 : _GEN_286; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_288 = 10'h120 == index ? 32'h3000000 : _GEN_287; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_289 = 10'h121 == index ? 32'h8000000 : _GEN_288; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_290 = 10'h122 == index ? 32'h94000000 : _GEN_289; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_291 = 10'h123 == index ? 32'h80 : _GEN_290; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_292 = 10'h124 == index ? 32'h10000 : _GEN_291; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_293 = 10'h125 == index ? 32'h3000000 : _GEN_292; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_294 = 10'h126 == index ? 32'h4000000 : _GEN_293; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_295 = 10'h127 == index ? 32'h28010000 : _GEN_294; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_296 = 10'h128 == index ? 32'h6d656d : _GEN_295; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_297 = 10'h129 == index ? 32'h3000000 : _GEN_296; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_298 = 10'h12a == index ? 32'h4000000 : _GEN_297; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_299 = 10'h12b == index ? 32'hff000000 : _GEN_298; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_300 = 10'h12c == index ? 32'h1000000 : _GEN_299; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_301 = 10'h12d == index ? 32'h3000000 : _GEN_300; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_302 = 10'h12e == index ? 32'h4000000 : _GEN_301; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_303 = 10'h12f == index ? 32'h5010000 : _GEN_302; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_304 = 10'h130 == index ? 32'h1000000 : _GEN_303; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_305 = 10'h131 == index ? 32'h2000000 : _GEN_304; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_306 = 10'h132 == index ? 32'h1000000 : _GEN_305; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_307 = 10'h133 == index ? 32'h6f727265 : _GEN_306; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_308 = 10'h134 == index ? 32'h65642d72 : _GEN_307; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_309 = 10'h135 == index ? 32'h65636976 : _GEN_308; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_310 = 10'h136 == index ? 32'h30303340 : _GEN_309; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_311 = 10'h137 == index ? 32'h30 : _GEN_310; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_312 = 10'h138 == index ? 32'h3000000 : _GEN_311; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_313 = 10'h139 == index ? 32'he000000 : _GEN_312; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_314 = 10'h13a == index ? 32'h1b000000 : _GEN_313; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_315 = 10'h13b == index ? 32'h69666973 : _GEN_314; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_316 = 10'h13c == index ? 32'h652c6576 : _GEN_315; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_317 = 10'h13d == index ? 32'h726f7272 : _GEN_316; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_318 = 10'h13e == index ? 32'h30 : _GEN_317; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_319 = 10'h13f == index ? 32'h3000000 : _GEN_318; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_320 = 10'h140 == index ? 32'h8000000 : _GEN_319; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_321 = 10'h141 == index ? 32'h94000000 : _GEN_320; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_322 = 10'h142 == index ? 32'h300000 : _GEN_321; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_323 = 10'h143 == index ? 32'h100000 : _GEN_322; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_324 = 10'h144 == index ? 32'h2000000 : _GEN_323; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_325 = 10'h145 == index ? 32'h1000000 : _GEN_324; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_326 = 10'h146 == index ? 32'h65747865 : _GEN_325; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_327 = 10'h147 == index ? 32'h6c616e72 : _GEN_326; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_328 = 10'h148 == index ? 32'h746e692d : _GEN_327; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_329 = 10'h149 == index ? 32'h75727265 : _GEN_328; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_330 = 10'h14a == index ? 32'h737470 : _GEN_329; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_331 = 10'h14b == index ? 32'h3000000 : _GEN_330; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_332 = 10'h14c == index ? 32'h4000000 : _GEN_331; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_333 = 10'h14d == index ? 32'h32010000 : _GEN_332; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_334 = 10'h14e == index ? 32'h3000000 : _GEN_333; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_335 = 10'h14f == index ? 32'h3000000 : _GEN_334; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_336 = 10'h150 == index ? 32'h8000000 : _GEN_335; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_337 = 10'h151 == index ? 32'h43010000 : _GEN_336; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_338 = 10'h152 == index ? 32'h1000000 : _GEN_337; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_339 = 10'h153 == index ? 32'h2000000 : _GEN_338; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_340 = 10'h154 == index ? 32'h2000000 : _GEN_339; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_341 = 10'h155 == index ? 32'h1000000 : _GEN_340; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_342 = 10'h156 == index ? 32'h65746e69 : _GEN_341; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_343 = 10'h157 == index ? 32'h70757272 : _GEN_342; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_344 = 10'h158 == index ? 32'h6f632d74 : _GEN_343; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_345 = 10'h159 == index ? 32'h6f72746e : _GEN_344; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_346 = 10'h15a == index ? 32'h72656c6c : _GEN_345; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_347 = 10'h15b == index ? 32'h30306340 : _GEN_346; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_348 = 10'h15c == index ? 32'h30303030 : _GEN_347; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_349 = 10'h15d == index ? 32'h0 : _GEN_348; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_350 = 10'h15e == index ? 32'h3000000 : _GEN_349; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_351 = 10'h15f == index ? 32'h4000000 : _GEN_350; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_352 = 10'h160 == index ? 32'hd9000000 : _GEN_351; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_353 = 10'h161 == index ? 32'h1000000 : _GEN_352; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_354 = 10'h162 == index ? 32'h3000000 : _GEN_353; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_355 = 10'h163 == index ? 32'hc000000 : _GEN_354; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_356 = 10'h164 == index ? 32'h1b000000 : _GEN_355; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_357 = 10'h165 == index ? 32'h63736972 : _GEN_356; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_358 = 10'h166 == index ? 32'h6c702c76 : _GEN_357; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_359 = 10'h167 == index ? 32'h306369 : _GEN_358; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_360 = 10'h168 == index ? 32'h3000000 : _GEN_359; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_361 = 10'h169 == index ? 32'h0 : _GEN_360; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_362 = 10'h16a == index ? 32'hea000000 : _GEN_361; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_363 = 10'h16b == index ? 32'h3000000 : _GEN_362; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_364 = 10'h16c == index ? 32'h8000000 : _GEN_363; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_365 = 10'h16d == index ? 32'h14010000 : _GEN_364; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_366 = 10'h16e == index ? 32'h2000000 : _GEN_365; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_367 = 10'h16f == index ? 32'hb000000 : _GEN_366; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_368 = 10'h170 == index ? 32'h3000000 : _GEN_367; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_369 = 10'h171 == index ? 32'h8000000 : _GEN_368; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_370 = 10'h172 == index ? 32'h94000000 : _GEN_369; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_371 = 10'h173 == index ? 32'hc : _GEN_370; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_372 = 10'h174 == index ? 32'h4 : _GEN_371; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_373 = 10'h175 == index ? 32'h3000000 : _GEN_372; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_374 = 10'h176 == index ? 32'h8000000 : _GEN_373; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_375 = 10'h177 == index ? 32'h28010000 : _GEN_374; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_376 = 10'h178 == index ? 32'h746e6f63 : _GEN_375; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_377 = 10'h179 == index ? 32'h6c6f72 : _GEN_376; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_378 = 10'h17a == index ? 32'h3000000 : _GEN_377; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_379 = 10'h17b == index ? 32'h4000000 : _GEN_378; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_380 = 10'h17c == index ? 32'h4e010000 : _GEN_379; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_381 = 10'h17d == index ? 32'h3000000 : _GEN_380; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_382 = 10'h17e == index ? 32'h3000000 : _GEN_381; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_383 = 10'h17f == index ? 32'h4000000 : _GEN_382; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_384 = 10'h180 == index ? 32'h61010000 : _GEN_383; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_385 = 10'h181 == index ? 32'h2000000 : _GEN_384; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_386 = 10'h182 == index ? 32'h3000000 : _GEN_385; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_387 = 10'h183 == index ? 32'h4000000 : _GEN_386; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_388 = 10'h184 == index ? 32'hff000000 : _GEN_387; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_389 = 10'h185 == index ? 32'h3000000 : _GEN_388; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_390 = 10'h186 == index ? 32'h3000000 : _GEN_389; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_391 = 10'h187 == index ? 32'h4000000 : _GEN_390; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_392 = 10'h188 == index ? 32'h5010000 : _GEN_391; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_393 = 10'h189 == index ? 32'h3000000 : _GEN_392; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_394 = 10'h18a == index ? 32'h2000000 : _GEN_393; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_395 = 10'h18b == index ? 32'h1000000 : _GEN_394; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_396 = 10'h18c == index ? 32'h6f696d6d : _GEN_395; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_397 = 10'h18d == index ? 32'h726f702d : _GEN_396; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_398 = 10'h18e == index ? 32'h78612d74 : _GEN_397; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_399 = 10'h18f == index ? 32'h36403469 : _GEN_398; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_400 = 10'h190 == index ? 32'h30303030 : _GEN_399; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_401 = 10'h191 == index ? 32'h303030 : _GEN_400; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_402 = 10'h192 == index ? 32'h3000000 : _GEN_401; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_403 = 10'h193 == index ? 32'h4000000 : _GEN_402; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_404 = 10'h194 == index ? 32'h0 : _GEN_403; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_405 = 10'h195 == index ? 32'h1000000 : _GEN_404; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_406 = 10'h196 == index ? 32'h3000000 : _GEN_405; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_407 = 10'h197 == index ? 32'h4000000 : _GEN_406; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_408 = 10'h198 == index ? 32'hf000000 : _GEN_407; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_409 = 10'h199 == index ? 32'h1000000 : _GEN_408; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_410 = 10'h19a == index ? 32'h3000000 : _GEN_409; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_411 = 10'h19b == index ? 32'hb000000 : _GEN_410; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_412 = 10'h19c == index ? 32'h1b000000 : _GEN_411; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_413 = 10'h19d == index ? 32'h706d6973 : _GEN_412; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_414 = 10'h19e == index ? 32'h622d656c : _GEN_413; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_415 = 10'h19f == index ? 32'h7375 : _GEN_414; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_416 = 10'h1a0 == index ? 32'h3000000 : _GEN_415; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_417 = 10'h1a1 == index ? 32'hc000000 : _GEN_416; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_418 = 10'h1a2 == index ? 32'hd010000 : _GEN_417; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_419 = 10'h1a3 == index ? 32'h60 : _GEN_418; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_420 = 10'h1a4 == index ? 32'h60 : _GEN_419; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_421 = 10'h1a5 == index ? 32'h20 : _GEN_420; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_422 = 10'h1a6 == index ? 32'h2000000 : _GEN_421; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_423 = 10'h1a7 == index ? 32'h1000000 : _GEN_422; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_424 = 10'h1a8 == index ? 32'h406d6f72 : _GEN_423; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_425 = 10'h1a9 == index ? 32'h30303031 : _GEN_424; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_426 = 10'h1aa == index ? 32'h30 : _GEN_425; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_427 = 10'h1ab == index ? 32'h3000000 : _GEN_426; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_428 = 10'h1ac == index ? 32'hc000000 : _GEN_427; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_429 = 10'h1ad == index ? 32'h1b000000 : _GEN_428; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_430 = 10'h1ae == index ? 32'h69666973 : _GEN_429; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_431 = 10'h1af == index ? 32'h722c6576 : _GEN_430; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_432 = 10'h1b0 == index ? 32'h306d6f : _GEN_431; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_433 = 10'h1b1 == index ? 32'h3000000 : _GEN_432; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_434 = 10'h1b2 == index ? 32'h8000000 : _GEN_433; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_435 = 10'h1b3 == index ? 32'h94000000 : _GEN_434; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_436 = 10'h1b4 == index ? 32'h100 : _GEN_435; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_437 = 10'h1b5 == index ? 32'h100 : _GEN_436; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_438 = 10'h1b6 == index ? 32'h3000000 : _GEN_437; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_439 = 10'h1b7 == index ? 32'h4000000 : _GEN_438; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_440 = 10'h1b8 == index ? 32'h28010000 : _GEN_439; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_441 = 10'h1b9 == index ? 32'h6d656d : _GEN_440; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_442 = 10'h1ba == index ? 32'h2000000 : _GEN_441; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_443 = 10'h1bb == index ? 32'h2000000 : _GEN_442; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_444 = 10'h1bc == index ? 32'h2000000 : _GEN_443; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_445 = 10'h1bd == index ? 32'h9000000 : _GEN_444; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_446 = 10'h1be == index ? 32'h64646123 : _GEN_445; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_447 = 10'h1bf == index ? 32'h73736572 : _GEN_446; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_448 = 10'h1c0 == index ? 32'h6c65632d : _GEN_447; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_449 = 10'h1c1 == index ? 32'h2300736c : _GEN_448; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_450 = 10'h1c2 == index ? 32'h657a6973 : _GEN_449; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_451 = 10'h1c3 == index ? 32'h6c65632d : _GEN_450; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_452 = 10'h1c4 == index ? 32'h6300736c : _GEN_451; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_453 = 10'h1c5 == index ? 32'h61706d6f : _GEN_452; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_454 = 10'h1c6 == index ? 32'h6c626974 : _GEN_453; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_455 = 10'h1c7 == index ? 32'h6f6d0065 : _GEN_454; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_456 = 10'h1c8 == index ? 32'h6c6564 : _GEN_455; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_457 = 10'h1c9 == index ? 32'h636f6c63 : _GEN_456; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_458 = 10'h1ca == index ? 32'h72662d6b : _GEN_457; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_459 = 10'h1cb == index ? 32'h65757165 : _GEN_458; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_460 = 10'h1cc == index ? 32'h79636e : _GEN_459; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_461 = 10'h1cd == index ? 32'h69766564 : _GEN_460; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_462 = 10'h1ce == index ? 32'h745f6563 : _GEN_461; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_463 = 10'h1cf == index ? 32'h657079 : _GEN_462; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_464 = 10'h1d0 == index ? 32'h64726168 : _GEN_463; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_465 = 10'h1d1 == index ? 32'h65726177 : _GEN_464; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_466 = 10'h1d2 == index ? 32'h6578652d : _GEN_465; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_467 = 10'h1d3 == index ? 32'h72622d63 : _GEN_466; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_468 = 10'h1d4 == index ? 32'h706b6165 : _GEN_467; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_469 = 10'h1d5 == index ? 32'h746e696f : _GEN_468; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_470 = 10'h1d6 == index ? 32'h756f632d : _GEN_469; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_471 = 10'h1d7 == index ? 32'h6900746e : _GEN_470; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_472 = 10'h1d8 == index ? 32'h6361632d : _GEN_471; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_473 = 10'h1d9 == index ? 32'h622d6568 : _GEN_472; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_474 = 10'h1da == index ? 32'h6b636f6c : _GEN_473; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_475 = 10'h1db == index ? 32'h7a69732d : _GEN_474; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_476 = 10'h1dc == index ? 32'h2d690065 : _GEN_475; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_477 = 10'h1dd == index ? 32'h68636163 : _GEN_476; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_478 = 10'h1de == index ? 32'h65732d65 : _GEN_477; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_479 = 10'h1df == index ? 32'h69007374 : _GEN_478; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_480 = 10'h1e0 == index ? 32'h6361632d : _GEN_479; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_481 = 10'h1e1 == index ? 32'h732d6568 : _GEN_480; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_482 = 10'h1e2 == index ? 32'h657a69 : _GEN_481; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_483 = 10'h1e3 == index ? 32'h676572 : _GEN_482; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_484 = 10'h1e4 == index ? 32'h63736972 : _GEN_483; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_485 = 10'h1e5 == index ? 32'h73692c76 : _GEN_484; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_486 = 10'h1e6 == index ? 32'h69720061 : _GEN_485; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_487 = 10'h1e7 == index ? 32'h2c766373 : _GEN_486; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_488 = 10'h1e8 == index ? 32'h72706d70 : _GEN_487; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_489 = 10'h1e9 == index ? 32'h6f696765 : _GEN_488; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_490 = 10'h1ea == index ? 32'h7300736e : _GEN_489; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_491 = 10'h1eb == index ? 32'h76696669 : _GEN_490; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_492 = 10'h1ec == index ? 32'h74642c65 : _GEN_491; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_493 = 10'h1ed == index ? 32'h73006d69 : _GEN_492; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_494 = 10'h1ee == index ? 32'h75746174 : _GEN_493; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_495 = 10'h1ef == index ? 32'h69740073 : _GEN_494; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_496 = 10'h1f0 == index ? 32'h6162656d : _GEN_495; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_497 = 10'h1f1 == index ? 32'h662d6573 : _GEN_496; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_498 = 10'h1f2 == index ? 32'h75716572 : _GEN_497; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_499 = 10'h1f3 == index ? 32'h79636e65 : _GEN_498; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_500 = 10'h1f4 == index ? 32'h6e692300 : _GEN_499; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_501 = 10'h1f5 == index ? 32'h72726574 : _GEN_500; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_502 = 10'h1f6 == index ? 32'h2d747075 : _GEN_501; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_503 = 10'h1f7 == index ? 32'h6c6c6563 : _GEN_502; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_504 = 10'h1f8 == index ? 32'h6e690073 : _GEN_503; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_505 = 10'h1f9 == index ? 32'h72726574 : _GEN_504; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_506 = 10'h1fa == index ? 32'h2d747075 : _GEN_505; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_507 = 10'h1fb == index ? 32'h746e6f63 : _GEN_506; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_508 = 10'h1fc == index ? 32'h6c6c6f72 : _GEN_507; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_509 = 10'h1fd == index ? 32'h6c007265 : _GEN_508; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_510 = 10'h1fe == index ? 32'h78756e69 : _GEN_509; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_511 = 10'h1ff == index ? 32'h6168702c : _GEN_510; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_512 = 10'h200 == index ? 32'h656c646e : _GEN_511; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_513 = 10'h201 == index ? 32'h6e617200 : _GEN_512; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_514 = 10'h202 == index ? 32'h736567 : _GEN_513; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_515 = 10'h203 == index ? 32'h65746e69 : _GEN_514; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_516 = 10'h204 == index ? 32'h70757272 : _GEN_515; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_517 = 10'h205 == index ? 32'h652d7374 : _GEN_516; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_518 = 10'h206 == index ? 32'h6e657478 : _GEN_517; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_519 = 10'h207 == index ? 32'h646564 : _GEN_518; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_520 = 10'h208 == index ? 32'h2d676572 : _GEN_519; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_521 = 10'h209 == index ? 32'h656d616e : _GEN_520; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_522 = 10'h20a == index ? 32'h6e690073 : _GEN_521; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_523 = 10'h20b == index ? 32'h72726574 : _GEN_522; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_524 = 10'h20c == index ? 32'h2d747075 : _GEN_523; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_525 = 10'h20d == index ? 32'h65726170 : _GEN_524; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_526 = 10'h20e == index ? 32'h6900746e : _GEN_525; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_527 = 10'h20f == index ? 32'h7265746e : _GEN_526; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_528 = 10'h210 == index ? 32'h74707572 : _GEN_527; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_529 = 10'h211 == index ? 32'h69720073 : _GEN_528; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_530 = 10'h212 == index ? 32'h2c766373 : _GEN_529; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_531 = 10'h213 == index ? 32'h2d78616d : _GEN_530; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_532 = 10'h214 == index ? 32'h6f697270 : _GEN_531; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_533 = 10'h215 == index ? 32'h79746972 : _GEN_532; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_534 = 10'h216 == index ? 32'h73697200 : _GEN_533; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_535 = 10'h217 == index ? 32'h6e2c7663 : _GEN_534; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_536 = 10'h218 == index ? 32'h766564 : _GEN_535; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_537 = 10'h219 == index ? 32'h0 : _GEN_536; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_538 = 10'h21a == index ? 32'h0 : _GEN_537; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_539 = 10'h21b == index ? 32'h0 : _GEN_538; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_540 = 10'h21c == index ? 32'h0 : _GEN_539; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_541 = 10'h21d == index ? 32'h0 : _GEN_540; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_542 = 10'h21e == index ? 32'h0 : _GEN_541; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_543 = 10'h21f == index ? 32'h0 : _GEN_542; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_544 = 10'h220 == index ? 32'h0 : _GEN_543; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_545 = 10'h221 == index ? 32'h0 : _GEN_544; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_546 = 10'h222 == index ? 32'h0 : _GEN_545; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_547 = 10'h223 == index ? 32'h0 : _GEN_546; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_548 = 10'h224 == index ? 32'h0 : _GEN_547; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_549 = 10'h225 == index ? 32'h0 : _GEN_548; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_550 = 10'h226 == index ? 32'h0 : _GEN_549; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_551 = 10'h227 == index ? 32'h0 : _GEN_550; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_552 = 10'h228 == index ? 32'h0 : _GEN_551; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_553 = 10'h229 == index ? 32'h0 : _GEN_552; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_554 = 10'h22a == index ? 32'h0 : _GEN_553; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_555 = 10'h22b == index ? 32'h0 : _GEN_554; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_556 = 10'h22c == index ? 32'h0 : _GEN_555; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_557 = 10'h22d == index ? 32'h0 : _GEN_556; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_558 = 10'h22e == index ? 32'h0 : _GEN_557; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_559 = 10'h22f == index ? 32'h0 : _GEN_558; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_560 = 10'h230 == index ? 32'h0 : _GEN_559; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_561 = 10'h231 == index ? 32'h0 : _GEN_560; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_562 = 10'h232 == index ? 32'h0 : _GEN_561; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_563 = 10'h233 == index ? 32'h0 : _GEN_562; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_564 = 10'h234 == index ? 32'h0 : _GEN_563; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_565 = 10'h235 == index ? 32'h0 : _GEN_564; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_566 = 10'h236 == index ? 32'h0 : _GEN_565; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_567 = 10'h237 == index ? 32'h0 : _GEN_566; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_568 = 10'h238 == index ? 32'h0 : _GEN_567; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_569 = 10'h239 == index ? 32'h0 : _GEN_568; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_570 = 10'h23a == index ? 32'h0 : _GEN_569; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_571 = 10'h23b == index ? 32'h0 : _GEN_570; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_572 = 10'h23c == index ? 32'h0 : _GEN_571; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_573 = 10'h23d == index ? 32'h0 : _GEN_572; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_574 = 10'h23e == index ? 32'h0 : _GEN_573; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_575 = 10'h23f == index ? 32'h0 : _GEN_574; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_576 = 10'h240 == index ? 32'h0 : _GEN_575; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_577 = 10'h241 == index ? 32'h0 : _GEN_576; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_578 = 10'h242 == index ? 32'h0 : _GEN_577; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_579 = 10'h243 == index ? 32'h0 : _GEN_578; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_580 = 10'h244 == index ? 32'h0 : _GEN_579; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_581 = 10'h245 == index ? 32'h0 : _GEN_580; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_582 = 10'h246 == index ? 32'h0 : _GEN_581; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_583 = 10'h247 == index ? 32'h0 : _GEN_582; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_584 = 10'h248 == index ? 32'h0 : _GEN_583; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_585 = 10'h249 == index ? 32'h0 : _GEN_584; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_586 = 10'h24a == index ? 32'h0 : _GEN_585; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_587 = 10'h24b == index ? 32'h0 : _GEN_586; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_588 = 10'h24c == index ? 32'h0 : _GEN_587; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_589 = 10'h24d == index ? 32'h0 : _GEN_588; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_590 = 10'h24e == index ? 32'h0 : _GEN_589; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_591 = 10'h24f == index ? 32'h0 : _GEN_590; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_592 = 10'h250 == index ? 32'h0 : _GEN_591; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_593 = 10'h251 == index ? 32'h0 : _GEN_592; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_594 = 10'h252 == index ? 32'h0 : _GEN_593; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_595 = 10'h253 == index ? 32'h0 : _GEN_594; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_596 = 10'h254 == index ? 32'h0 : _GEN_595; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_597 = 10'h255 == index ? 32'h0 : _GEN_596; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_598 = 10'h256 == index ? 32'h0 : _GEN_597; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_599 = 10'h257 == index ? 32'h0 : _GEN_598; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_600 = 10'h258 == index ? 32'h0 : _GEN_599; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_601 = 10'h259 == index ? 32'h0 : _GEN_600; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_602 = 10'h25a == index ? 32'h0 : _GEN_601; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_603 = 10'h25b == index ? 32'h0 : _GEN_602; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_604 = 10'h25c == index ? 32'h0 : _GEN_603; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_605 = 10'h25d == index ? 32'h0 : _GEN_604; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_606 = 10'h25e == index ? 32'h0 : _GEN_605; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_607 = 10'h25f == index ? 32'h0 : _GEN_606; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_608 = 10'h260 == index ? 32'h0 : _GEN_607; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_609 = 10'h261 == index ? 32'h0 : _GEN_608; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_610 = 10'h262 == index ? 32'h0 : _GEN_609; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_611 = 10'h263 == index ? 32'h0 : _GEN_610; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_612 = 10'h264 == index ? 32'h0 : _GEN_611; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_613 = 10'h265 == index ? 32'h0 : _GEN_612; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_614 = 10'h266 == index ? 32'h0 : _GEN_613; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_615 = 10'h267 == index ? 32'h0 : _GEN_614; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_616 = 10'h268 == index ? 32'h0 : _GEN_615; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_617 = 10'h269 == index ? 32'h0 : _GEN_616; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_618 = 10'h26a == index ? 32'h0 : _GEN_617; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_619 = 10'h26b == index ? 32'h0 : _GEN_618; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_620 = 10'h26c == index ? 32'h0 : _GEN_619; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_621 = 10'h26d == index ? 32'h0 : _GEN_620; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_622 = 10'h26e == index ? 32'h0 : _GEN_621; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_623 = 10'h26f == index ? 32'h0 : _GEN_622; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_624 = 10'h270 == index ? 32'h0 : _GEN_623; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_625 = 10'h271 == index ? 32'h0 : _GEN_624; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_626 = 10'h272 == index ? 32'h0 : _GEN_625; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_627 = 10'h273 == index ? 32'h0 : _GEN_626; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_628 = 10'h274 == index ? 32'h0 : _GEN_627; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_629 = 10'h275 == index ? 32'h0 : _GEN_628; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_630 = 10'h276 == index ? 32'h0 : _GEN_629; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_631 = 10'h277 == index ? 32'h0 : _GEN_630; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_632 = 10'h278 == index ? 32'h0 : _GEN_631; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_633 = 10'h279 == index ? 32'h0 : _GEN_632; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_634 = 10'h27a == index ? 32'h0 : _GEN_633; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_635 = 10'h27b == index ? 32'h0 : _GEN_634; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_636 = 10'h27c == index ? 32'h0 : _GEN_635; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_637 = 10'h27d == index ? 32'h0 : _GEN_636; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_638 = 10'h27e == index ? 32'h0 : _GEN_637; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_639 = 10'h27f == index ? 32'h0 : _GEN_638; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_640 = 10'h280 == index ? 32'h0 : _GEN_639; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_641 = 10'h281 == index ? 32'h0 : _GEN_640; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_642 = 10'h282 == index ? 32'h0 : _GEN_641; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_643 = 10'h283 == index ? 32'h0 : _GEN_642; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_644 = 10'h284 == index ? 32'h0 : _GEN_643; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_645 = 10'h285 == index ? 32'h0 : _GEN_644; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_646 = 10'h286 == index ? 32'h0 : _GEN_645; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_647 = 10'h287 == index ? 32'h0 : _GEN_646; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_648 = 10'h288 == index ? 32'h0 : _GEN_647; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_649 = 10'h289 == index ? 32'h0 : _GEN_648; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_650 = 10'h28a == index ? 32'h0 : _GEN_649; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_651 = 10'h28b == index ? 32'h0 : _GEN_650; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_652 = 10'h28c == index ? 32'h0 : _GEN_651; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_653 = 10'h28d == index ? 32'h0 : _GEN_652; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_654 = 10'h28e == index ? 32'h0 : _GEN_653; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_655 = 10'h28f == index ? 32'h0 : _GEN_654; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_656 = 10'h290 == index ? 32'h0 : _GEN_655; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_657 = 10'h291 == index ? 32'h0 : _GEN_656; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_658 = 10'h292 == index ? 32'h0 : _GEN_657; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_659 = 10'h293 == index ? 32'h0 : _GEN_658; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_660 = 10'h294 == index ? 32'h0 : _GEN_659; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_661 = 10'h295 == index ? 32'h0 : _GEN_660; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_662 = 10'h296 == index ? 32'h0 : _GEN_661; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_663 = 10'h297 == index ? 32'h0 : _GEN_662; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_664 = 10'h298 == index ? 32'h0 : _GEN_663; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_665 = 10'h299 == index ? 32'h0 : _GEN_664; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_666 = 10'h29a == index ? 32'h0 : _GEN_665; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_667 = 10'h29b == index ? 32'h0 : _GEN_666; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_668 = 10'h29c == index ? 32'h0 : _GEN_667; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_669 = 10'h29d == index ? 32'h0 : _GEN_668; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_670 = 10'h29e == index ? 32'h0 : _GEN_669; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_671 = 10'h29f == index ? 32'h0 : _GEN_670; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_672 = 10'h2a0 == index ? 32'h0 : _GEN_671; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_673 = 10'h2a1 == index ? 32'h0 : _GEN_672; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_674 = 10'h2a2 == index ? 32'h0 : _GEN_673; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_675 = 10'h2a3 == index ? 32'h0 : _GEN_674; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_676 = 10'h2a4 == index ? 32'h0 : _GEN_675; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_677 = 10'h2a5 == index ? 32'h0 : _GEN_676; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_678 = 10'h2a6 == index ? 32'h0 : _GEN_677; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_679 = 10'h2a7 == index ? 32'h0 : _GEN_678; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_680 = 10'h2a8 == index ? 32'h0 : _GEN_679; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_681 = 10'h2a9 == index ? 32'h0 : _GEN_680; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_682 = 10'h2aa == index ? 32'h0 : _GEN_681; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_683 = 10'h2ab == index ? 32'h0 : _GEN_682; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_684 = 10'h2ac == index ? 32'h0 : _GEN_683; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_685 = 10'h2ad == index ? 32'h0 : _GEN_684; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_686 = 10'h2ae == index ? 32'h0 : _GEN_685; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_687 = 10'h2af == index ? 32'h0 : _GEN_686; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_688 = 10'h2b0 == index ? 32'h0 : _GEN_687; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_689 = 10'h2b1 == index ? 32'h0 : _GEN_688; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_690 = 10'h2b2 == index ? 32'h0 : _GEN_689; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_691 = 10'h2b3 == index ? 32'h0 : _GEN_690; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_692 = 10'h2b4 == index ? 32'h0 : _GEN_691; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_693 = 10'h2b5 == index ? 32'h0 : _GEN_692; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_694 = 10'h2b6 == index ? 32'h0 : _GEN_693; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_695 = 10'h2b7 == index ? 32'h0 : _GEN_694; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_696 = 10'h2b8 == index ? 32'h0 : _GEN_695; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_697 = 10'h2b9 == index ? 32'h0 : _GEN_696; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_698 = 10'h2ba == index ? 32'h0 : _GEN_697; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_699 = 10'h2bb == index ? 32'h0 : _GEN_698; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_700 = 10'h2bc == index ? 32'h0 : _GEN_699; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_701 = 10'h2bd == index ? 32'h0 : _GEN_700; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_702 = 10'h2be == index ? 32'h0 : _GEN_701; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_703 = 10'h2bf == index ? 32'h0 : _GEN_702; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_704 = 10'h2c0 == index ? 32'h0 : _GEN_703; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_705 = 10'h2c1 == index ? 32'h0 : _GEN_704; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_706 = 10'h2c2 == index ? 32'h0 : _GEN_705; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_707 = 10'h2c3 == index ? 32'h0 : _GEN_706; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_708 = 10'h2c4 == index ? 32'h0 : _GEN_707; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_709 = 10'h2c5 == index ? 32'h0 : _GEN_708; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_710 = 10'h2c6 == index ? 32'h0 : _GEN_709; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_711 = 10'h2c7 == index ? 32'h0 : _GEN_710; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_712 = 10'h2c8 == index ? 32'h0 : _GEN_711; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_713 = 10'h2c9 == index ? 32'h0 : _GEN_712; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_714 = 10'h2ca == index ? 32'h0 : _GEN_713; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_715 = 10'h2cb == index ? 32'h0 : _GEN_714; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_716 = 10'h2cc == index ? 32'h0 : _GEN_715; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_717 = 10'h2cd == index ? 32'h0 : _GEN_716; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_718 = 10'h2ce == index ? 32'h0 : _GEN_717; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_719 = 10'h2cf == index ? 32'h0 : _GEN_718; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_720 = 10'h2d0 == index ? 32'h0 : _GEN_719; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_721 = 10'h2d1 == index ? 32'h0 : _GEN_720; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_722 = 10'h2d2 == index ? 32'h0 : _GEN_721; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_723 = 10'h2d3 == index ? 32'h0 : _GEN_722; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_724 = 10'h2d4 == index ? 32'h0 : _GEN_723; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_725 = 10'h2d5 == index ? 32'h0 : _GEN_724; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_726 = 10'h2d6 == index ? 32'h0 : _GEN_725; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_727 = 10'h2d7 == index ? 32'h0 : _GEN_726; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_728 = 10'h2d8 == index ? 32'h0 : _GEN_727; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_729 = 10'h2d9 == index ? 32'h0 : _GEN_728; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_730 = 10'h2da == index ? 32'h0 : _GEN_729; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_731 = 10'h2db == index ? 32'h0 : _GEN_730; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_732 = 10'h2dc == index ? 32'h0 : _GEN_731; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_733 = 10'h2dd == index ? 32'h0 : _GEN_732; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_734 = 10'h2de == index ? 32'h0 : _GEN_733; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_735 = 10'h2df == index ? 32'h0 : _GEN_734; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_736 = 10'h2e0 == index ? 32'h0 : _GEN_735; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_737 = 10'h2e1 == index ? 32'h0 : _GEN_736; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_738 = 10'h2e2 == index ? 32'h0 : _GEN_737; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_739 = 10'h2e3 == index ? 32'h0 : _GEN_738; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_740 = 10'h2e4 == index ? 32'h0 : _GEN_739; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_741 = 10'h2e5 == index ? 32'h0 : _GEN_740; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_742 = 10'h2e6 == index ? 32'h0 : _GEN_741; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_743 = 10'h2e7 == index ? 32'h0 : _GEN_742; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_744 = 10'h2e8 == index ? 32'h0 : _GEN_743; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_745 = 10'h2e9 == index ? 32'h0 : _GEN_744; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_746 = 10'h2ea == index ? 32'h0 : _GEN_745; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_747 = 10'h2eb == index ? 32'h0 : _GEN_746; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_748 = 10'h2ec == index ? 32'h0 : _GEN_747; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_749 = 10'h2ed == index ? 32'h0 : _GEN_748; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_750 = 10'h2ee == index ? 32'h0 : _GEN_749; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_751 = 10'h2ef == index ? 32'h0 : _GEN_750; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_752 = 10'h2f0 == index ? 32'h0 : _GEN_751; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_753 = 10'h2f1 == index ? 32'h0 : _GEN_752; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_754 = 10'h2f2 == index ? 32'h0 : _GEN_753; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_755 = 10'h2f3 == index ? 32'h0 : _GEN_754; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_756 = 10'h2f4 == index ? 32'h0 : _GEN_755; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_757 = 10'h2f5 == index ? 32'h0 : _GEN_756; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_758 = 10'h2f6 == index ? 32'h0 : _GEN_757; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_759 = 10'h2f7 == index ? 32'h0 : _GEN_758; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_760 = 10'h2f8 == index ? 32'h0 : _GEN_759; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_761 = 10'h2f9 == index ? 32'h0 : _GEN_760; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_762 = 10'h2fa == index ? 32'h0 : _GEN_761; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_763 = 10'h2fb == index ? 32'h0 : _GEN_762; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_764 = 10'h2fc == index ? 32'h0 : _GEN_763; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_765 = 10'h2fd == index ? 32'h0 : _GEN_764; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_766 = 10'h2fe == index ? 32'h0 : _GEN_765; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_767 = 10'h2ff == index ? 32'h0 : _GEN_766; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_768 = 10'h300 == index ? 32'h0 : _GEN_767; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_769 = 10'h301 == index ? 32'h0 : _GEN_768; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_770 = 10'h302 == index ? 32'h0 : _GEN_769; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_771 = 10'h303 == index ? 32'h0 : _GEN_770; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_772 = 10'h304 == index ? 32'h0 : _GEN_771; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_773 = 10'h305 == index ? 32'h0 : _GEN_772; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_774 = 10'h306 == index ? 32'h0 : _GEN_773; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_775 = 10'h307 == index ? 32'h0 : _GEN_774; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_776 = 10'h308 == index ? 32'h0 : _GEN_775; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_777 = 10'h309 == index ? 32'h0 : _GEN_776; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_778 = 10'h30a == index ? 32'h0 : _GEN_777; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_779 = 10'h30b == index ? 32'h0 : _GEN_778; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_780 = 10'h30c == index ? 32'h0 : _GEN_779; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_781 = 10'h30d == index ? 32'h0 : _GEN_780; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_782 = 10'h30e == index ? 32'h0 : _GEN_781; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_783 = 10'h30f == index ? 32'h0 : _GEN_782; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_784 = 10'h310 == index ? 32'h0 : _GEN_783; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_785 = 10'h311 == index ? 32'h0 : _GEN_784; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_786 = 10'h312 == index ? 32'h0 : _GEN_785; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_787 = 10'h313 == index ? 32'h0 : _GEN_786; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_788 = 10'h314 == index ? 32'h0 : _GEN_787; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_789 = 10'h315 == index ? 32'h0 : _GEN_788; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_790 = 10'h316 == index ? 32'h0 : _GEN_789; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_791 = 10'h317 == index ? 32'h0 : _GEN_790; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_792 = 10'h318 == index ? 32'h0 : _GEN_791; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_793 = 10'h319 == index ? 32'h0 : _GEN_792; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_794 = 10'h31a == index ? 32'h0 : _GEN_793; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_795 = 10'h31b == index ? 32'h0 : _GEN_794; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_796 = 10'h31c == index ? 32'h0 : _GEN_795; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_797 = 10'h31d == index ? 32'h0 : _GEN_796; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_798 = 10'h31e == index ? 32'h0 : _GEN_797; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_799 = 10'h31f == index ? 32'h0 : _GEN_798; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_800 = 10'h320 == index ? 32'h0 : _GEN_799; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_801 = 10'h321 == index ? 32'h0 : _GEN_800; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_802 = 10'h322 == index ? 32'h0 : _GEN_801; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_803 = 10'h323 == index ? 32'h0 : _GEN_802; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_804 = 10'h324 == index ? 32'h0 : _GEN_803; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_805 = 10'h325 == index ? 32'h0 : _GEN_804; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_806 = 10'h326 == index ? 32'h0 : _GEN_805; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_807 = 10'h327 == index ? 32'h0 : _GEN_806; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_808 = 10'h328 == index ? 32'h0 : _GEN_807; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_809 = 10'h329 == index ? 32'h0 : _GEN_808; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_810 = 10'h32a == index ? 32'h0 : _GEN_809; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_811 = 10'h32b == index ? 32'h0 : _GEN_810; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_812 = 10'h32c == index ? 32'h0 : _GEN_811; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_813 = 10'h32d == index ? 32'h0 : _GEN_812; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_814 = 10'h32e == index ? 32'h0 : _GEN_813; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_815 = 10'h32f == index ? 32'h0 : _GEN_814; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_816 = 10'h330 == index ? 32'h0 : _GEN_815; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_817 = 10'h331 == index ? 32'h0 : _GEN_816; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_818 = 10'h332 == index ? 32'h0 : _GEN_817; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_819 = 10'h333 == index ? 32'h0 : _GEN_818; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_820 = 10'h334 == index ? 32'h0 : _GEN_819; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_821 = 10'h335 == index ? 32'h0 : _GEN_820; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_822 = 10'h336 == index ? 32'h0 : _GEN_821; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_823 = 10'h337 == index ? 32'h0 : _GEN_822; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_824 = 10'h338 == index ? 32'h0 : _GEN_823; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_825 = 10'h339 == index ? 32'h0 : _GEN_824; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_826 = 10'h33a == index ? 32'h0 : _GEN_825; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_827 = 10'h33b == index ? 32'h0 : _GEN_826; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_828 = 10'h33c == index ? 32'h0 : _GEN_827; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_829 = 10'h33d == index ? 32'h0 : _GEN_828; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_830 = 10'h33e == index ? 32'h0 : _GEN_829; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_831 = 10'h33f == index ? 32'h0 : _GEN_830; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_832 = 10'h340 == index ? 32'h0 : _GEN_831; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_833 = 10'h341 == index ? 32'h0 : _GEN_832; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_834 = 10'h342 == index ? 32'h0 : _GEN_833; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_835 = 10'h343 == index ? 32'h0 : _GEN_834; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_836 = 10'h344 == index ? 32'h0 : _GEN_835; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_837 = 10'h345 == index ? 32'h0 : _GEN_836; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_838 = 10'h346 == index ? 32'h0 : _GEN_837; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_839 = 10'h347 == index ? 32'h0 : _GEN_838; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_840 = 10'h348 == index ? 32'h0 : _GEN_839; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_841 = 10'h349 == index ? 32'h0 : _GEN_840; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_842 = 10'h34a == index ? 32'h0 : _GEN_841; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_843 = 10'h34b == index ? 32'h0 : _GEN_842; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_844 = 10'h34c == index ? 32'h0 : _GEN_843; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_845 = 10'h34d == index ? 32'h0 : _GEN_844; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_846 = 10'h34e == index ? 32'h0 : _GEN_845; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_847 = 10'h34f == index ? 32'h0 : _GEN_846; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_848 = 10'h350 == index ? 32'h0 : _GEN_847; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_849 = 10'h351 == index ? 32'h0 : _GEN_848; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_850 = 10'h352 == index ? 32'h0 : _GEN_849; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_851 = 10'h353 == index ? 32'h0 : _GEN_850; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_852 = 10'h354 == index ? 32'h0 : _GEN_851; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_853 = 10'h355 == index ? 32'h0 : _GEN_852; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_854 = 10'h356 == index ? 32'h0 : _GEN_853; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_855 = 10'h357 == index ? 32'h0 : _GEN_854; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_856 = 10'h358 == index ? 32'h0 : _GEN_855; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_857 = 10'h359 == index ? 32'h0 : _GEN_856; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_858 = 10'h35a == index ? 32'h0 : _GEN_857; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_859 = 10'h35b == index ? 32'h0 : _GEN_858; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_860 = 10'h35c == index ? 32'h0 : _GEN_859; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_861 = 10'h35d == index ? 32'h0 : _GEN_860; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_862 = 10'h35e == index ? 32'h0 : _GEN_861; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_863 = 10'h35f == index ? 32'h0 : _GEN_862; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_864 = 10'h360 == index ? 32'h0 : _GEN_863; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_865 = 10'h361 == index ? 32'h0 : _GEN_864; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_866 = 10'h362 == index ? 32'h0 : _GEN_865; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_867 = 10'h363 == index ? 32'h0 : _GEN_866; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_868 = 10'h364 == index ? 32'h0 : _GEN_867; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_869 = 10'h365 == index ? 32'h0 : _GEN_868; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_870 = 10'h366 == index ? 32'h0 : _GEN_869; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_871 = 10'h367 == index ? 32'h0 : _GEN_870; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_872 = 10'h368 == index ? 32'h0 : _GEN_871; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_873 = 10'h369 == index ? 32'h0 : _GEN_872; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_874 = 10'h36a == index ? 32'h0 : _GEN_873; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_875 = 10'h36b == index ? 32'h0 : _GEN_874; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_876 = 10'h36c == index ? 32'h0 : _GEN_875; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_877 = 10'h36d == index ? 32'h0 : _GEN_876; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_878 = 10'h36e == index ? 32'h0 : _GEN_877; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_879 = 10'h36f == index ? 32'h0 : _GEN_878; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_880 = 10'h370 == index ? 32'h0 : _GEN_879; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_881 = 10'h371 == index ? 32'h0 : _GEN_880; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_882 = 10'h372 == index ? 32'h0 : _GEN_881; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_883 = 10'h373 == index ? 32'h0 : _GEN_882; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_884 = 10'h374 == index ? 32'h0 : _GEN_883; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_885 = 10'h375 == index ? 32'h0 : _GEN_884; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_886 = 10'h376 == index ? 32'h0 : _GEN_885; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_887 = 10'h377 == index ? 32'h0 : _GEN_886; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_888 = 10'h378 == index ? 32'h0 : _GEN_887; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_889 = 10'h379 == index ? 32'h0 : _GEN_888; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_890 = 10'h37a == index ? 32'h0 : _GEN_889; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_891 = 10'h37b == index ? 32'h0 : _GEN_890; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_892 = 10'h37c == index ? 32'h0 : _GEN_891; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_893 = 10'h37d == index ? 32'h0 : _GEN_892; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_894 = 10'h37e == index ? 32'h0 : _GEN_893; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_895 = 10'h37f == index ? 32'h0 : _GEN_894; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_896 = 10'h380 == index ? 32'h0 : _GEN_895; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_897 = 10'h381 == index ? 32'h0 : _GEN_896; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_898 = 10'h382 == index ? 32'h0 : _GEN_897; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_899 = 10'h383 == index ? 32'h0 : _GEN_898; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_900 = 10'h384 == index ? 32'h0 : _GEN_899; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_901 = 10'h385 == index ? 32'h0 : _GEN_900; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_902 = 10'h386 == index ? 32'h0 : _GEN_901; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_903 = 10'h387 == index ? 32'h0 : _GEN_902; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_904 = 10'h388 == index ? 32'h0 : _GEN_903; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_905 = 10'h389 == index ? 32'h0 : _GEN_904; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_906 = 10'h38a == index ? 32'h0 : _GEN_905; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_907 = 10'h38b == index ? 32'h0 : _GEN_906; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_908 = 10'h38c == index ? 32'h0 : _GEN_907; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_909 = 10'h38d == index ? 32'h0 : _GEN_908; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_910 = 10'h38e == index ? 32'h0 : _GEN_909; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_911 = 10'h38f == index ? 32'h0 : _GEN_910; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_912 = 10'h390 == index ? 32'h0 : _GEN_911; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_913 = 10'h391 == index ? 32'h0 : _GEN_912; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_914 = 10'h392 == index ? 32'h0 : _GEN_913; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_915 = 10'h393 == index ? 32'h0 : _GEN_914; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_916 = 10'h394 == index ? 32'h0 : _GEN_915; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_917 = 10'h395 == index ? 32'h0 : _GEN_916; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_918 = 10'h396 == index ? 32'h0 : _GEN_917; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_919 = 10'h397 == index ? 32'h0 : _GEN_918; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_920 = 10'h398 == index ? 32'h0 : _GEN_919; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_921 = 10'h399 == index ? 32'h0 : _GEN_920; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_922 = 10'h39a == index ? 32'h0 : _GEN_921; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_923 = 10'h39b == index ? 32'h0 : _GEN_922; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_924 = 10'h39c == index ? 32'h0 : _GEN_923; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_925 = 10'h39d == index ? 32'h0 : _GEN_924; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_926 = 10'h39e == index ? 32'h0 : _GEN_925; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_927 = 10'h39f == index ? 32'h0 : _GEN_926; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_928 = 10'h3a0 == index ? 32'h0 : _GEN_927; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_929 = 10'h3a1 == index ? 32'h0 : _GEN_928; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_930 = 10'h3a2 == index ? 32'h0 : _GEN_929; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_931 = 10'h3a3 == index ? 32'h0 : _GEN_930; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_932 = 10'h3a4 == index ? 32'h0 : _GEN_931; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_933 = 10'h3a5 == index ? 32'h0 : _GEN_932; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_934 = 10'h3a6 == index ? 32'h0 : _GEN_933; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_935 = 10'h3a7 == index ? 32'h0 : _GEN_934; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_936 = 10'h3a8 == index ? 32'h0 : _GEN_935; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_937 = 10'h3a9 == index ? 32'h0 : _GEN_936; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_938 = 10'h3aa == index ? 32'h0 : _GEN_937; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_939 = 10'h3ab == index ? 32'h0 : _GEN_938; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_940 = 10'h3ac == index ? 32'h0 : _GEN_939; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_941 = 10'h3ad == index ? 32'h0 : _GEN_940; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_942 = 10'h3ae == index ? 32'h0 : _GEN_941; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_943 = 10'h3af == index ? 32'h0 : _GEN_942; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_944 = 10'h3b0 == index ? 32'h0 : _GEN_943; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_945 = 10'h3b1 == index ? 32'h0 : _GEN_944; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_946 = 10'h3b2 == index ? 32'h0 : _GEN_945; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_947 = 10'h3b3 == index ? 32'h0 : _GEN_946; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_948 = 10'h3b4 == index ? 32'h0 : _GEN_947; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_949 = 10'h3b5 == index ? 32'h0 : _GEN_948; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_950 = 10'h3b6 == index ? 32'h0 : _GEN_949; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_951 = 10'h3b7 == index ? 32'h0 : _GEN_950; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_952 = 10'h3b8 == index ? 32'h0 : _GEN_951; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_953 = 10'h3b9 == index ? 32'h0 : _GEN_952; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_954 = 10'h3ba == index ? 32'h0 : _GEN_953; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_955 = 10'h3bb == index ? 32'h0 : _GEN_954; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_956 = 10'h3bc == index ? 32'h0 : _GEN_955; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_957 = 10'h3bd == index ? 32'h0 : _GEN_956; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_958 = 10'h3be == index ? 32'h0 : _GEN_957; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_959 = 10'h3bf == index ? 32'h0 : _GEN_958; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_960 = 10'h3c0 == index ? 32'h0 : _GEN_959; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_961 = 10'h3c1 == index ? 32'h0 : _GEN_960; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_962 = 10'h3c2 == index ? 32'h0 : _GEN_961; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_963 = 10'h3c3 == index ? 32'h0 : _GEN_962; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_964 = 10'h3c4 == index ? 32'h0 : _GEN_963; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_965 = 10'h3c5 == index ? 32'h0 : _GEN_964; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_966 = 10'h3c6 == index ? 32'h0 : _GEN_965; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_967 = 10'h3c7 == index ? 32'h0 : _GEN_966; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_968 = 10'h3c8 == index ? 32'h0 : _GEN_967; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_969 = 10'h3c9 == index ? 32'h0 : _GEN_968; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_970 = 10'h3ca == index ? 32'h0 : _GEN_969; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_971 = 10'h3cb == index ? 32'h0 : _GEN_970; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_972 = 10'h3cc == index ? 32'h0 : _GEN_971; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_973 = 10'h3cd == index ? 32'h0 : _GEN_972; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_974 = 10'h3ce == index ? 32'h0 : _GEN_973; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_975 = 10'h3cf == index ? 32'h0 : _GEN_974; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_976 = 10'h3d0 == index ? 32'h0 : _GEN_975; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_977 = 10'h3d1 == index ? 32'h0 : _GEN_976; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_978 = 10'h3d2 == index ? 32'h0 : _GEN_977; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_979 = 10'h3d3 == index ? 32'h0 : _GEN_978; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_980 = 10'h3d4 == index ? 32'h0 : _GEN_979; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_981 = 10'h3d5 == index ? 32'h0 : _GEN_980; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_982 = 10'h3d6 == index ? 32'h0 : _GEN_981; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_983 = 10'h3d7 == index ? 32'h0 : _GEN_982; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_984 = 10'h3d8 == index ? 32'h0 : _GEN_983; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_985 = 10'h3d9 == index ? 32'h0 : _GEN_984; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_986 = 10'h3da == index ? 32'h0 : _GEN_985; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_987 = 10'h3db == index ? 32'h0 : _GEN_986; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_988 = 10'h3dc == index ? 32'h0 : _GEN_987; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_989 = 10'h3dd == index ? 32'h0 : _GEN_988; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_990 = 10'h3de == index ? 32'h0 : _GEN_989; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_991 = 10'h3df == index ? 32'h0 : _GEN_990; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_992 = 10'h3e0 == index ? 32'h0 : _GEN_991; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_993 = 10'h3e1 == index ? 32'h0 : _GEN_992; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_994 = 10'h3e2 == index ? 32'h0 : _GEN_993; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_995 = 10'h3e3 == index ? 32'h0 : _GEN_994; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_996 = 10'h3e4 == index ? 32'h0 : _GEN_995; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_997 = 10'h3e5 == index ? 32'h0 : _GEN_996; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_998 = 10'h3e6 == index ? 32'h0 : _GEN_997; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_999 = 10'h3e7 == index ? 32'h0 : _GEN_998; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1000 = 10'h3e8 == index ? 32'h0 : _GEN_999; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1001 = 10'h3e9 == index ? 32'h0 : _GEN_1000; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1002 = 10'h3ea == index ? 32'h0 : _GEN_1001; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1003 = 10'h3eb == index ? 32'h0 : _GEN_1002; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1004 = 10'h3ec == index ? 32'h0 : _GEN_1003; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1005 = 10'h3ed == index ? 32'h0 : _GEN_1004; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1006 = 10'h3ee == index ? 32'h0 : _GEN_1005; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1007 = 10'h3ef == index ? 32'h0 : _GEN_1006; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1008 = 10'h3f0 == index ? 32'h0 : _GEN_1007; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1009 = 10'h3f1 == index ? 32'h0 : _GEN_1008; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1010 = 10'h3f2 == index ? 32'h0 : _GEN_1009; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1011 = 10'h3f3 == index ? 32'h0 : _GEN_1010; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1012 = 10'h3f4 == index ? 32'h0 : _GEN_1011; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1013 = 10'h3f5 == index ? 32'h0 : _GEN_1012; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1014 = 10'h3f6 == index ? 32'h0 : _GEN_1013; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1015 = 10'h3f7 == index ? 32'h0 : _GEN_1014; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1016 = 10'h3f8 == index ? 32'h0 : _GEN_1015; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1017 = 10'h3f9 == index ? 32'h0 : _GEN_1016; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1018 = 10'h3fa == index ? 32'h0 : _GEN_1017; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1019 = 10'h3fb == index ? 32'h0 : _GEN_1018; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1020 = 10'h3fc == index ? 32'h0 : _GEN_1019; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1021 = 10'h3fd == index ? 32'h0 : _GEN_1020; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1022 = 10'h3fe == index ? 32'h0 : _GEN_1021; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign _GEN_1023 = 10'h3ff == index ? 32'h0 : _GEN_1022; // @[BootROM.scala 52:47:freechips.rocketchip.system.TinyConfig.fir@128211.4] assign auto_in_a_ready = auto_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@127179.4] assign auto_in_d_valid = auto_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@127179.4] assign auto_in_d_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@127179.4] assign auto_in_d_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@127179.4] assign auto_in_d_bits_data = _T_12 ? 32'h0 : _GEN_1023; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@127179.4] assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@127132.4] assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@127133.4] assign TLMonitor_io_in_a_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_d_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] assign TLMonitor_io_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.TinyConfig.fir@127178.4] endmodule module ExampleRocketSystem( // @[:freechips.rocketchip.system.TinyConfig.fir@128233.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@128234.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@128235.4] output debug_clockeddmi_dmi_req_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input debug_clockeddmi_dmi_req_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input [6:0] debug_clockeddmi_dmi_req_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input [31:0] debug_clockeddmi_dmi_req_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input [1:0] debug_clockeddmi_dmi_req_bits_op, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input debug_clockeddmi_dmi_resp_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] output debug_clockeddmi_dmi_resp_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] output [31:0] debug_clockeddmi_dmi_resp_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] output [1:0] debug_clockeddmi_dmi_resp_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input debug_clockeddmi_dmiClock, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input debug_clockeddmi_dmiReset, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] output debug_ndreset, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] output debug_dmactive, // @[:freechips.rocketchip.system.TinyConfig.fir@128237.4] input [1:0] interrupts, // @[:freechips.rocketchip.system.TinyConfig.fir@128238.4] input mmio_axi4_0_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [30:0] mmio_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [7:0] mmio_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [2:0] mmio_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [1:0] mmio_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [2:0] mmio_axi4_0_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input mmio_axi4_0_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [31:0] mmio_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input mmio_axi4_0_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input [3:0] mmio_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input [1:0] mmio_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input mmio_axi4_0_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [30:0] mmio_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [7:0] mmio_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [2:0] mmio_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [1:0] mmio_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [2:0] mmio_axi4_0_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output [3:0] mmio_axi4_0_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output mmio_axi4_0_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input mmio_axi4_0_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input [3:0] mmio_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input [31:0] mmio_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input [1:0] mmio_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] input mmio_axi4_0_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128239.4] output l2_frontend_bus_axi4_0_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [7:0] l2_frontend_bus_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [31:0] l2_frontend_bus_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [7:0] l2_frontend_bus_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [2:0] l2_frontend_bus_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [1:0] l2_frontend_bus_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_aw_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [3:0] l2_frontend_bus_axi4_0_aw_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [2:0] l2_frontend_bus_axi4_0_aw_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [3:0] l2_frontend_bus_axi4_0_aw_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output l2_frontend_bus_axi4_0_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [63:0] l2_frontend_bus_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [7:0] l2_frontend_bus_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output l2_frontend_bus_axi4_0_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output [7:0] l2_frontend_bus_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output [1:0] l2_frontend_bus_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output l2_frontend_bus_axi4_0_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [7:0] l2_frontend_bus_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [31:0] l2_frontend_bus_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [7:0] l2_frontend_bus_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [2:0] l2_frontend_bus_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [1:0] l2_frontend_bus_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_ar_bits_lock, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [3:0] l2_frontend_bus_axi4_0_ar_bits_cache, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [2:0] l2_frontend_bus_axi4_0_ar_bits_prot, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input [3:0] l2_frontend_bus_axi4_0_ar_bits_qos, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] input l2_frontend_bus_axi4_0_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output l2_frontend_bus_axi4_0_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output [7:0] l2_frontend_bus_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output [63:0] l2_frontend_bus_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output [1:0] l2_frontend_bus_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] output l2_frontend_bus_axi4_0_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@128240.4] ); wire int_bus_auto_int_in_0; // @[InterruptBus.scala 13:27:freechips.rocketchip.system.TinyConfig.fir@128249.4] wire int_bus_auto_int_in_1; // @[InterruptBus.scala 13:27:freechips.rocketchip.system.TinyConfig.fir@128249.4] wire int_bus_auto_int_out_0; // @[InterruptBus.scala 13:27:freechips.rocketchip.system.TinyConfig.fir@128249.4] wire int_bus_auto_int_out_1; // @[InterruptBus.scala 13:27:freechips.rocketchip.system.TinyConfig.fir@128249.4] wire sbus_clock; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_reset; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [30:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [7:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [30:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [7:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [4:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [4:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [2:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [1:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [3:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire [31:0] sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt; // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] wire fbus_clock; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_reset; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [31:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [2:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [1:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [63:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [1:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [31:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [2:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [1:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [7:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [63:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [1:0] fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_a_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_a_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [2:0] fbus_auto_bus_xing_out_a_bits_opcode; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [2:0] fbus_auto_bus_xing_out_a_bits_param; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [3:0] fbus_auto_bus_xing_out_a_bits_size; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [3:0] fbus_auto_bus_xing_out_a_bits_source; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [31:0] fbus_auto_bus_xing_out_a_bits_address; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [3:0] fbus_auto_bus_xing_out_a_bits_mask; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [31:0] fbus_auto_bus_xing_out_a_bits_data; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_a_bits_corrupt; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_d_ready; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_d_valid; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [2:0] fbus_auto_bus_xing_out_d_bits_opcode; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [1:0] fbus_auto_bus_xing_out_d_bits_param; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [3:0] fbus_auto_bus_xing_out_d_bits_size; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [3:0] fbus_auto_bus_xing_out_d_bits_source; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_d_bits_sink; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_d_bits_denied; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire [31:0] fbus_auto_bus_xing_out_d_bits_data; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire fbus_auto_bus_xing_out_d_bits_corrupt; // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] wire cbus_clock; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_reset; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [16:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [4:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [4:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_debug_fragmenter_out_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [11:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_debug_fragmenter_out_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_clint_fragmenter_out_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [25:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_clint_fragmenter_out_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_plic_fragmenter_out_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [27:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_coupler_to_plic_fragmenter_out_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [9:0] cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_a_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_a_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_bus_xing_in_a_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_bus_xing_in_a_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_bus_xing_in_a_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [4:0] cbus_auto_bus_xing_in_a_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_bus_xing_in_a_bits_address; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_bus_xing_in_a_bits_mask; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_bus_xing_in_a_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_a_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_d_ready; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_d_valid; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [2:0] cbus_auto_bus_xing_in_d_bits_opcode; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [1:0] cbus_auto_bus_xing_in_d_bits_param; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [3:0] cbus_auto_bus_xing_in_d_bits_size; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [4:0] cbus_auto_bus_xing_in_d_bits_source; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_d_bits_sink; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_d_bits_denied; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire [31:0] cbus_auto_bus_xing_in_d_bits_data; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire cbus_auto_bus_xing_in_d_bits_corrupt; // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] wire plic_clock; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_reset; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_int_in_0; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_int_in_1; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_int_out_0; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_in_a_ready; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_in_a_valid; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [2:0] plic_auto_in_a_bits_opcode; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [2:0] plic_auto_in_a_bits_param; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [1:0] plic_auto_in_a_bits_size; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [9:0] plic_auto_in_a_bits_source; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [27:0] plic_auto_in_a_bits_address; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [3:0] plic_auto_in_a_bits_mask; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [31:0] plic_auto_in_a_bits_data; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_in_a_bits_corrupt; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_in_d_ready; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire plic_auto_in_d_valid; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [2:0] plic_auto_in_d_bits_opcode; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [1:0] plic_auto_in_d_bits_size; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [9:0] plic_auto_in_d_bits_source; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire [31:0] plic_auto_in_d_bits_data; // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] wire clint_clock; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_reset; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_int_out_0; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_int_out_1; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_in_a_ready; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_in_a_valid; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [2:0] clint_auto_in_a_bits_opcode; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [2:0] clint_auto_in_a_bits_param; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [1:0] clint_auto_in_a_bits_size; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [9:0] clint_auto_in_a_bits_source; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [25:0] clint_auto_in_a_bits_address; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [3:0] clint_auto_in_a_bits_mask; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [31:0] clint_auto_in_a_bits_data; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_in_a_bits_corrupt; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_in_d_ready; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_auto_in_d_valid; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [2:0] clint_auto_in_d_bits_opcode; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [1:0] clint_auto_in_d_bits_size; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [9:0] clint_auto_in_d_bits_source; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire [31:0] clint_auto_in_d_bits_data; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire clint_io_rtcTick; // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] wire debug_1_clock; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_reset; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmInner_dmInner_tl_in_a_valid; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_param; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_size; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [9:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_source; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [11:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_address; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [3:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [31:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_data; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmInner_dmInner_tl_in_d_ready; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [9:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [31:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_auto_dmOuter_intsource_out_sync_0; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_ctrl_ndreset; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_ctrl_dmactive; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmi_req_valid; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [6:0] debug_1_io_dmi_dmi_req_bits_addr; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [31:0] debug_1_io_dmi_dmi_req_bits_data; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [1:0] debug_1_io_dmi_dmi_req_bits_op; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmi_resp_ready; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [31:0] debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire [1:0] debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmiClock; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire debug_1_io_dmi_dmiReset; // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] wire tile_clock; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_reset; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_intsink_in_sync_0; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_int_in_xing_in_1_sync_0; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_int_in_xing_in_0_sync_0; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_int_in_xing_in_0_sync_1; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_a_ready; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_a_valid; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_slave_xing_in_a_bits_opcode; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_slave_xing_in_a_bits_param; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_slave_xing_in_a_bits_size; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [4:0] tile_auto_tl_slave_xing_in_a_bits_source; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_slave_xing_in_a_bits_address; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [3:0] tile_auto_tl_slave_xing_in_a_bits_mask; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_slave_xing_in_a_bits_data; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_d_ready; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_d_valid; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_slave_xing_in_d_bits_opcode; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [1:0] tile_auto_tl_slave_xing_in_d_bits_param; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_slave_xing_in_d_bits_size; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [4:0] tile_auto_tl_slave_xing_in_d_bits_source; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_d_bits_sink; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_d_bits_denied; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_slave_xing_in_d_bits_data; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_slave_xing_in_d_bits_corrupt; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_a_ready; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_a_valid; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_master_xing_out_a_bits_opcode; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_master_xing_out_a_bits_param; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [3:0] tile_auto_tl_master_xing_out_a_bits_size; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_a_bits_source; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_master_xing_out_a_bits_address; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [3:0] tile_auto_tl_master_xing_out_a_bits_mask; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_master_xing_out_a_bits_data; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_a_bits_corrupt; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_ready; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_valid; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [2:0] tile_auto_tl_master_xing_out_d_bits_opcode; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [1:0] tile_auto_tl_master_xing_out_d_bits_param; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [3:0] tile_auto_tl_master_xing_out_d_bits_size; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_bits_source; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_bits_sink; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_bits_denied; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire [31:0] tile_auto_tl_master_xing_out_d_bits_data; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire tile_auto_tl_master_xing_out_d_bits_corrupt; // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] wire intsource_clock; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_reset; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_auto_in_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_auto_in_1; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_auto_out_sync_1; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] wire intsource_1_clock; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128342.4] wire intsource_1_reset; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128342.4] wire intsource_1_auto_in_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128342.4] wire intsource_1_auto_out_sync_0; // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128342.4] wire asyncXing_clock; // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] wire asyncXing_auto_int_in_0; // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] wire asyncXing_auto_int_in_1; // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] wire asyncXing_auto_int_out_0; // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] wire asyncXing_auto_int_out_1; // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] wire bootrom_clock; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_reset; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_auto_in_a_ready; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_auto_in_a_valid; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [2:0] bootrom_auto_in_a_bits_opcode; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [2:0] bootrom_auto_in_a_bits_param; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [1:0] bootrom_auto_in_a_bits_size; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [9:0] bootrom_auto_in_a_bits_source; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [16:0] bootrom_auto_in_a_bits_address; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [3:0] bootrom_auto_in_a_bits_mask; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_auto_in_a_bits_corrupt; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_auto_in_d_ready; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire bootrom_auto_in_d_valid; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [1:0] bootrom_auto_in_d_bits_size; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [9:0] bootrom_auto_in_d_bits_source; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] wire [31:0] bootrom_auto_in_d_bits_data; // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] reg [6:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@128441.4] reg [31:0] _RAND_0; wire int_rtc_tick; // @[Counter.scala 34:24:freechips.rocketchip.system.TinyConfig.fir@128443.6] wire [6:0] _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@128445.6] IntXbar int_bus ( // @[InterruptBus.scala 13:27:freechips.rocketchip.system.TinyConfig.fir@128249.4] .auto_int_in_0(int_bus_auto_int_in_0), .auto_int_in_1(int_bus_auto_int_in_1), .auto_int_out_0(int_bus_auto_int_out_0), .auto_int_out_1(int_bus_auto_int_out_1) ); SystemBus sbus ( // @[BaseSubsystem.scala 46:24:freechips.rocketchip.system.TinyConfig.fir@128255.4] .clock(sbus_clock), .reset(sbus_reset), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp), .auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last(sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data), .auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt(sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data), .auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt(sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data), .auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data), .auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt(sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt) ); FrontBus fbus ( // @[BaseSubsystem.scala 48:24:freechips.rocketchip.system.TinyConfig.fir@128267.4] .clock(fbus_clock), .reset(fbus_reset), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp), .auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last(fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last), .auto_bus_xing_out_a_ready(fbus_auto_bus_xing_out_a_ready), .auto_bus_xing_out_a_valid(fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode(fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param(fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size(fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source(fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address(fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask(fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data(fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt(fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready(fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid(fbus_auto_bus_xing_out_d_valid), .auto_bus_xing_out_d_bits_opcode(fbus_auto_bus_xing_out_d_bits_opcode), .auto_bus_xing_out_d_bits_param(fbus_auto_bus_xing_out_d_bits_param), .auto_bus_xing_out_d_bits_size(fbus_auto_bus_xing_out_d_bits_size), .auto_bus_xing_out_d_bits_source(fbus_auto_bus_xing_out_d_bits_source), .auto_bus_xing_out_d_bits_sink(fbus_auto_bus_xing_out_d_bits_sink), .auto_bus_xing_out_d_bits_denied(fbus_auto_bus_xing_out_d_bits_denied), .auto_bus_xing_out_d_bits_data(fbus_auto_bus_xing_out_d_bits_data), .auto_bus_xing_out_d_bits_corrupt(fbus_auto_bus_xing_out_d_bits_corrupt) ); PeripheryBus_1 cbus ( // @[BaseSubsystem.scala 50:24:freechips.rocketchip.system.TinyConfig.fir@128279.4] .clock(cbus_clock), .reset(cbus_reset), .auto_coupler_to_bootrom_fragmenter_out_a_ready(cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready), .auto_coupler_to_bootrom_fragmenter_out_a_valid(cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid), .auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_out_a_bits_param(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_out_a_bits_size(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_out_a_bits_source(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_out_a_bits_address(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_out_a_bits_mask(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt(cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_out_d_ready(cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready), .auto_coupler_to_bootrom_fragmenter_out_d_valid(cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid), .auto_coupler_to_bootrom_fragmenter_out_d_bits_size(cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size), .auto_coupler_to_bootrom_fragmenter_out_d_bits_source(cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source), .auto_coupler_to_bootrom_fragmenter_out_d_bits_data(cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data), .auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt(cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt), .auto_coupler_to_debug_fragmenter_out_a_ready(cbus_auto_coupler_to_debug_fragmenter_out_a_ready), .auto_coupler_to_debug_fragmenter_out_a_valid(cbus_auto_coupler_to_debug_fragmenter_out_a_valid), .auto_coupler_to_debug_fragmenter_out_a_bits_opcode(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_out_a_bits_param(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param), .auto_coupler_to_debug_fragmenter_out_a_bits_size(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size), .auto_coupler_to_debug_fragmenter_out_a_bits_source(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source), .auto_coupler_to_debug_fragmenter_out_a_bits_address(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address), .auto_coupler_to_debug_fragmenter_out_a_bits_mask(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_out_a_bits_data(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data), .auto_coupler_to_debug_fragmenter_out_a_bits_corrupt(cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_out_d_ready(cbus_auto_coupler_to_debug_fragmenter_out_d_ready), .auto_coupler_to_debug_fragmenter_out_d_valid(cbus_auto_coupler_to_debug_fragmenter_out_d_valid), .auto_coupler_to_debug_fragmenter_out_d_bits_opcode(cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode), .auto_coupler_to_debug_fragmenter_out_d_bits_size(cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size), .auto_coupler_to_debug_fragmenter_out_d_bits_source(cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source), .auto_coupler_to_debug_fragmenter_out_d_bits_data(cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data), .auto_coupler_to_clint_fragmenter_out_a_ready(cbus_auto_coupler_to_clint_fragmenter_out_a_ready), .auto_coupler_to_clint_fragmenter_out_a_valid(cbus_auto_coupler_to_clint_fragmenter_out_a_valid), .auto_coupler_to_clint_fragmenter_out_a_bits_opcode(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_out_a_bits_param(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param), .auto_coupler_to_clint_fragmenter_out_a_bits_size(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size), .auto_coupler_to_clint_fragmenter_out_a_bits_source(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source), .auto_coupler_to_clint_fragmenter_out_a_bits_address(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address), .auto_coupler_to_clint_fragmenter_out_a_bits_mask(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_out_a_bits_data(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data), .auto_coupler_to_clint_fragmenter_out_a_bits_corrupt(cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_out_d_ready(cbus_auto_coupler_to_clint_fragmenter_out_d_ready), .auto_coupler_to_clint_fragmenter_out_d_valid(cbus_auto_coupler_to_clint_fragmenter_out_d_valid), .auto_coupler_to_clint_fragmenter_out_d_bits_opcode(cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode), .auto_coupler_to_clint_fragmenter_out_d_bits_size(cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size), .auto_coupler_to_clint_fragmenter_out_d_bits_source(cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source), .auto_coupler_to_clint_fragmenter_out_d_bits_data(cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data), .auto_coupler_to_plic_fragmenter_out_a_ready(cbus_auto_coupler_to_plic_fragmenter_out_a_ready), .auto_coupler_to_plic_fragmenter_out_a_valid(cbus_auto_coupler_to_plic_fragmenter_out_a_valid), .auto_coupler_to_plic_fragmenter_out_a_bits_opcode(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_out_a_bits_param(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param), .auto_coupler_to_plic_fragmenter_out_a_bits_size(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size), .auto_coupler_to_plic_fragmenter_out_a_bits_source(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source), .auto_coupler_to_plic_fragmenter_out_a_bits_address(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address), .auto_coupler_to_plic_fragmenter_out_a_bits_mask(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_out_a_bits_data(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data), .auto_coupler_to_plic_fragmenter_out_a_bits_corrupt(cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_out_d_ready(cbus_auto_coupler_to_plic_fragmenter_out_d_ready), .auto_coupler_to_plic_fragmenter_out_d_valid(cbus_auto_coupler_to_plic_fragmenter_out_d_valid), .auto_coupler_to_plic_fragmenter_out_d_bits_opcode(cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode), .auto_coupler_to_plic_fragmenter_out_d_bits_size(cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size), .auto_coupler_to_plic_fragmenter_out_d_bits_source(cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source), .auto_coupler_to_plic_fragmenter_out_d_bits_data(cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data), .auto_bus_xing_in_a_ready(cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid(cbus_auto_bus_xing_in_a_valid), .auto_bus_xing_in_a_bits_opcode(cbus_auto_bus_xing_in_a_bits_opcode), .auto_bus_xing_in_a_bits_param(cbus_auto_bus_xing_in_a_bits_param), .auto_bus_xing_in_a_bits_size(cbus_auto_bus_xing_in_a_bits_size), .auto_bus_xing_in_a_bits_source(cbus_auto_bus_xing_in_a_bits_source), .auto_bus_xing_in_a_bits_address(cbus_auto_bus_xing_in_a_bits_address), .auto_bus_xing_in_a_bits_mask(cbus_auto_bus_xing_in_a_bits_mask), .auto_bus_xing_in_a_bits_data(cbus_auto_bus_xing_in_a_bits_data), .auto_bus_xing_in_a_bits_corrupt(cbus_auto_bus_xing_in_a_bits_corrupt), .auto_bus_xing_in_d_ready(cbus_auto_bus_xing_in_d_ready), .auto_bus_xing_in_d_valid(cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode(cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param(cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size(cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source(cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink(cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied(cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data(cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt(cbus_auto_bus_xing_in_d_bits_corrupt) ); TLPLIC plic ( // @[Plic.scala 340:26:freechips.rocketchip.system.TinyConfig.fir@128303.4] .clock(plic_clock), .reset(plic_reset), .auto_int_in_0(plic_auto_int_in_0), .auto_int_in_1(plic_auto_int_in_1), .auto_int_out_0(plic_auto_int_out_0), .auto_in_a_ready(plic_auto_in_a_ready), .auto_in_a_valid(plic_auto_in_a_valid), .auto_in_a_bits_opcode(plic_auto_in_a_bits_opcode), .auto_in_a_bits_param(plic_auto_in_a_bits_param), .auto_in_a_bits_size(plic_auto_in_a_bits_size), .auto_in_a_bits_source(plic_auto_in_a_bits_source), .auto_in_a_bits_address(plic_auto_in_a_bits_address), .auto_in_a_bits_mask(plic_auto_in_a_bits_mask), .auto_in_a_bits_data(plic_auto_in_a_bits_data), .auto_in_a_bits_corrupt(plic_auto_in_a_bits_corrupt), .auto_in_d_ready(plic_auto_in_d_ready), .auto_in_d_valid(plic_auto_in_d_valid), .auto_in_d_bits_opcode(plic_auto_in_d_bits_opcode), .auto_in_d_bits_size(plic_auto_in_d_bits_size), .auto_in_d_bits_source(plic_auto_in_d_bits_source), .auto_in_d_bits_data(plic_auto_in_d_bits_data) ); CLINT clint ( // @[CLINT.scala 102:27:freechips.rocketchip.system.TinyConfig.fir@128309.4] .clock(clint_clock), .reset(clint_reset), .auto_int_out_0(clint_auto_int_out_0), .auto_int_out_1(clint_auto_int_out_1), .auto_in_a_ready(clint_auto_in_a_ready), .auto_in_a_valid(clint_auto_in_a_valid), .auto_in_a_bits_opcode(clint_auto_in_a_bits_opcode), .auto_in_a_bits_param(clint_auto_in_a_bits_param), .auto_in_a_bits_size(clint_auto_in_a_bits_size), .auto_in_a_bits_source(clint_auto_in_a_bits_source), .auto_in_a_bits_address(clint_auto_in_a_bits_address), .auto_in_a_bits_mask(clint_auto_in_a_bits_mask), .auto_in_a_bits_data(clint_auto_in_a_bits_data), .auto_in_a_bits_corrupt(clint_auto_in_a_bits_corrupt), .auto_in_d_ready(clint_auto_in_d_ready), .auto_in_d_valid(clint_auto_in_d_valid), .auto_in_d_bits_opcode(clint_auto_in_d_bits_opcode), .auto_in_d_bits_size(clint_auto_in_d_bits_size), .auto_in_d_bits_source(clint_auto_in_d_bits_source), .auto_in_d_bits_data(clint_auto_in_d_bits_data), .io_rtcTick(clint_io_rtcTick) ); TLDebugModule debug_1 ( // @[Periphery.scala 45:25:freechips.rocketchip.system.TinyConfig.fir@128316.4] .clock(debug_1_clock), .reset(debug_1_reset), .auto_dmInner_dmInner_tl_in_a_ready(debug_1_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid(debug_1_auto_dmInner_dmInner_tl_in_a_valid), .auto_dmInner_dmInner_tl_in_a_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode), .auto_dmInner_dmInner_tl_in_a_bits_param(debug_1_auto_dmInner_dmInner_tl_in_a_bits_param), .auto_dmInner_dmInner_tl_in_a_bits_size(debug_1_auto_dmInner_dmInner_tl_in_a_bits_size), .auto_dmInner_dmInner_tl_in_a_bits_source(debug_1_auto_dmInner_dmInner_tl_in_a_bits_source), .auto_dmInner_dmInner_tl_in_a_bits_address(debug_1_auto_dmInner_dmInner_tl_in_a_bits_address), .auto_dmInner_dmInner_tl_in_a_bits_mask(debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask), .auto_dmInner_dmInner_tl_in_a_bits_data(debug_1_auto_dmInner_dmInner_tl_in_a_bits_data), .auto_dmInner_dmInner_tl_in_a_bits_corrupt(debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt), .auto_dmInner_dmInner_tl_in_d_ready(debug_1_auto_dmInner_dmInner_tl_in_d_ready), .auto_dmInner_dmInner_tl_in_d_valid(debug_1_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size(debug_1_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source(debug_1_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data(debug_1_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_intsource_out_sync_0(debug_1_auto_dmOuter_intsource_out_sync_0), .io_ctrl_ndreset(debug_1_io_ctrl_ndreset), .io_ctrl_dmactive(debug_1_io_ctrl_dmactive), .io_dmi_dmi_req_ready(debug_1_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid(debug_1_io_dmi_dmi_req_valid), .io_dmi_dmi_req_bits_addr(debug_1_io_dmi_dmi_req_bits_addr), .io_dmi_dmi_req_bits_data(debug_1_io_dmi_dmi_req_bits_data), .io_dmi_dmi_req_bits_op(debug_1_io_dmi_dmi_req_bits_op), .io_dmi_dmi_resp_ready(debug_1_io_dmi_dmi_resp_ready), .io_dmi_dmi_resp_valid(debug_1_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data(debug_1_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp(debug_1_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock(debug_1_io_dmi_dmiClock), .io_dmi_dmiReset(debug_1_io_dmi_dmiReset) ); RocketTile tile ( // @[RocketSubsystem.scala 42:28:freechips.rocketchip.system.TinyConfig.fir@128329.4] .clock(tile_clock), .reset(tile_reset), .auto_intsink_in_sync_0(tile_auto_intsink_in_sync_0), .auto_int_in_xing_in_1_sync_0(tile_auto_int_in_xing_in_1_sync_0), .auto_int_in_xing_in_0_sync_0(tile_auto_int_in_xing_in_0_sync_0), .auto_int_in_xing_in_0_sync_1(tile_auto_int_in_xing_in_0_sync_1), .auto_tl_slave_xing_in_a_ready(tile_auto_tl_slave_xing_in_a_ready), .auto_tl_slave_xing_in_a_valid(tile_auto_tl_slave_xing_in_a_valid), .auto_tl_slave_xing_in_a_bits_opcode(tile_auto_tl_slave_xing_in_a_bits_opcode), .auto_tl_slave_xing_in_a_bits_param(tile_auto_tl_slave_xing_in_a_bits_param), .auto_tl_slave_xing_in_a_bits_size(tile_auto_tl_slave_xing_in_a_bits_size), .auto_tl_slave_xing_in_a_bits_source(tile_auto_tl_slave_xing_in_a_bits_source), .auto_tl_slave_xing_in_a_bits_address(tile_auto_tl_slave_xing_in_a_bits_address), .auto_tl_slave_xing_in_a_bits_mask(tile_auto_tl_slave_xing_in_a_bits_mask), .auto_tl_slave_xing_in_a_bits_data(tile_auto_tl_slave_xing_in_a_bits_data), .auto_tl_slave_xing_in_d_ready(tile_auto_tl_slave_xing_in_d_ready), .auto_tl_slave_xing_in_d_valid(tile_auto_tl_slave_xing_in_d_valid), .auto_tl_slave_xing_in_d_bits_opcode(tile_auto_tl_slave_xing_in_d_bits_opcode), .auto_tl_slave_xing_in_d_bits_param(tile_auto_tl_slave_xing_in_d_bits_param), .auto_tl_slave_xing_in_d_bits_size(tile_auto_tl_slave_xing_in_d_bits_size), .auto_tl_slave_xing_in_d_bits_source(tile_auto_tl_slave_xing_in_d_bits_source), .auto_tl_slave_xing_in_d_bits_sink(tile_auto_tl_slave_xing_in_d_bits_sink), .auto_tl_slave_xing_in_d_bits_denied(tile_auto_tl_slave_xing_in_d_bits_denied), .auto_tl_slave_xing_in_d_bits_data(tile_auto_tl_slave_xing_in_d_bits_data), .auto_tl_slave_xing_in_d_bits_corrupt(tile_auto_tl_slave_xing_in_d_bits_corrupt), .auto_tl_master_xing_out_a_ready(tile_auto_tl_master_xing_out_a_ready), .auto_tl_master_xing_out_a_valid(tile_auto_tl_master_xing_out_a_valid), .auto_tl_master_xing_out_a_bits_opcode(tile_auto_tl_master_xing_out_a_bits_opcode), .auto_tl_master_xing_out_a_bits_param(tile_auto_tl_master_xing_out_a_bits_param), .auto_tl_master_xing_out_a_bits_size(tile_auto_tl_master_xing_out_a_bits_size), .auto_tl_master_xing_out_a_bits_source(tile_auto_tl_master_xing_out_a_bits_source), .auto_tl_master_xing_out_a_bits_address(tile_auto_tl_master_xing_out_a_bits_address), .auto_tl_master_xing_out_a_bits_mask(tile_auto_tl_master_xing_out_a_bits_mask), .auto_tl_master_xing_out_a_bits_data(tile_auto_tl_master_xing_out_a_bits_data), .auto_tl_master_xing_out_a_bits_corrupt(tile_auto_tl_master_xing_out_a_bits_corrupt), .auto_tl_master_xing_out_d_ready(tile_auto_tl_master_xing_out_d_ready), .auto_tl_master_xing_out_d_valid(tile_auto_tl_master_xing_out_d_valid), .auto_tl_master_xing_out_d_bits_opcode(tile_auto_tl_master_xing_out_d_bits_opcode), .auto_tl_master_xing_out_d_bits_param(tile_auto_tl_master_xing_out_d_bits_param), .auto_tl_master_xing_out_d_bits_size(tile_auto_tl_master_xing_out_d_bits_size), .auto_tl_master_xing_out_d_bits_source(tile_auto_tl_master_xing_out_d_bits_source), .auto_tl_master_xing_out_d_bits_sink(tile_auto_tl_master_xing_out_d_bits_sink), .auto_tl_master_xing_out_d_bits_denied(tile_auto_tl_master_xing_out_d_bits_denied), .auto_tl_master_xing_out_d_bits_data(tile_auto_tl_master_xing_out_d_bits_data), .auto_tl_master_xing_out_d_bits_corrupt(tile_auto_tl_master_xing_out_d_bits_corrupt) ); IntSyncCrossingSource_2 intsource ( // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128336.4] .clock(intsource_clock), .reset(intsource_reset), .auto_in_0(intsource_auto_in_0), .auto_in_1(intsource_auto_in_1), .auto_out_sync_0(intsource_auto_out_sync_0), .auto_out_sync_1(intsource_auto_out_sync_1) ); IntSyncCrossingSource_3 intsource_1 ( // @[Crossing.scala 26:31:freechips.rocketchip.system.TinyConfig.fir@128342.4] .clock(intsource_1_clock), .reset(intsource_1_reset), .auto_in_0(intsource_1_auto_in_0), .auto_out_sync_0(intsource_1_auto_out_sync_0) ); IntXing asyncXing ( // @[InterruptBus.scala 16:31:freechips.rocketchip.system.TinyConfig.fir@128372.4] .clock(asyncXing_clock), .auto_int_in_0(asyncXing_auto_int_in_0), .auto_int_in_1(asyncXing_auto_int_in_1), .auto_int_out_0(asyncXing_auto_int_out_0), .auto_int_out_1(asyncXing_auto_int_out_1) ); TLROM bootrom ( // @[BootROM.scala 72:27:freechips.rocketchip.system.TinyConfig.fir@128378.4] .clock(bootrom_clock), .reset(bootrom_reset), .auto_in_a_ready(bootrom_auto_in_a_ready), .auto_in_a_valid(bootrom_auto_in_a_valid), .auto_in_a_bits_opcode(bootrom_auto_in_a_bits_opcode), .auto_in_a_bits_param(bootrom_auto_in_a_bits_param), .auto_in_a_bits_size(bootrom_auto_in_a_bits_size), .auto_in_a_bits_source(bootrom_auto_in_a_bits_source), .auto_in_a_bits_address(bootrom_auto_in_a_bits_address), .auto_in_a_bits_mask(bootrom_auto_in_a_bits_mask), .auto_in_a_bits_corrupt(bootrom_auto_in_a_bits_corrupt), .auto_in_d_ready(bootrom_auto_in_d_ready), .auto_in_d_valid(bootrom_auto_in_d_valid), .auto_in_d_bits_size(bootrom_auto_in_d_bits_size), .auto_in_d_bits_source(bootrom_auto_in_d_bits_source), .auto_in_d_bits_data(bootrom_auto_in_d_bits_data) ); assign int_rtc_tick = value == 7'h63; // @[Counter.scala 34:24:freechips.rocketchip.system.TinyConfig.fir@128443.6] assign _T_12 = value + 7'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@128445.6] assign debug_clockeddmi_dmi_req_ready = debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_clockeddmi_dmi_resp_valid = debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_clockeddmi_dmi_resp_bits_data = debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_clockeddmi_dmi_resp_bits_resp = debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_ndreset = debug_1_io_ctrl_ndreset; // @[Periphery.scala 92:18:freechips.rocketchip.system.TinyConfig.fir@128436.4] assign debug_dmactive = debug_1_io_ctrl_dmactive; // @[Periphery.scala 93:18:freechips.rocketchip.system.TinyConfig.fir@128437.4] assign mmio_axi4_0_aw_valid = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_id = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_addr = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_len = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_size = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_burst = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_lock = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_cache = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_prot = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_aw_bits_qos = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_w_valid = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_w_bits_data = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_w_bits_strb = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_w_bits_last = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_b_ready = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_valid = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_id = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_addr = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_len = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_size = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_burst = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_lock = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_cache = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_prot = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_ar_bits_qos = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign mmio_axi4_0_r_ready = sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready; // @[Ports.scala 115:80:freechips.rocketchip.system.TinyConfig.fir@128457.4] assign l2_frontend_bus_axi4_0_aw_ready = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_w_ready = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_b_valid = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_b_bits_id = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_b_bits_resp = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_ar_ready = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_r_valid = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_r_bits_id = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_r_bits_data = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_r_bits_resp = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign l2_frontend_bus_axi4_0_r_bits_last = fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last; // @[Ports.scala 154:102:freechips.rocketchip.system.TinyConfig.fir@128458.4] assign int_bus_auto_int_in_0 = asyncXing_auto_int_out_0; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128429.4] assign int_bus_auto_int_in_1 = asyncXing_auto_int_out_1; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128429.4] assign sbus_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128259.4] assign sbus_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128260.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready = mmio_axi4_0_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready = mmio_axi4_0_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid = mmio_axi4_0_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id = mmio_axi4_0_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp = mmio_axi4_0_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready = mmio_axi4_0_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid = mmio_axi4_0_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id = mmio_axi4_0_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data = mmio_axi4_0_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp = mmio_axi4_0_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last = mmio_axi4_0_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128430.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid = fbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode = fbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param = fbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size = fbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source = fbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address = fbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask = fbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data = fbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt = fbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready = fbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready = cbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid = cbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode = cbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param = cbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size = cbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source = cbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink = cbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied = cbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data = cbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt = cbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid = tile_auto_tl_master_xing_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode = tile_auto_tl_master_xing_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param = tile_auto_tl_master_xing_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size = tile_auto_tl_master_xing_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source = tile_auto_tl_master_xing_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address = tile_auto_tl_master_xing_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask = tile_auto_tl_master_xing_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data = tile_auto_tl_master_xing_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt = tile_auto_tl_master_xing_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready = tile_auto_tl_master_xing_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign fbus_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128271.4] assign fbus_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128272.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid = l2_frontend_bus_axi4_0_aw_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id = l2_frontend_bus_axi4_0_aw_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr = l2_frontend_bus_axi4_0_aw_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len = l2_frontend_bus_axi4_0_aw_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size = l2_frontend_bus_axi4_0_aw_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst = l2_frontend_bus_axi4_0_aw_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid = l2_frontend_bus_axi4_0_w_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data = l2_frontend_bus_axi4_0_w_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb = l2_frontend_bus_axi4_0_w_bits_strb; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last = l2_frontend_bus_axi4_0_w_bits_last; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready = l2_frontend_bus_axi4_0_b_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid = l2_frontend_bus_axi4_0_ar_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id = l2_frontend_bus_axi4_0_ar_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr = l2_frontend_bus_axi4_0_ar_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len = l2_frontend_bus_axi4_0_ar_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size = l2_frontend_bus_axi4_0_ar_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst = l2_frontend_bus_axi4_0_ar_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready = l2_frontend_bus_axi4_0_r_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128431.4] assign fbus_auto_bus_xing_out_a_ready = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_valid = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_opcode = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_param = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_size = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_source = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_sink = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_denied = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_data = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign fbus_auto_bus_xing_out_d_bits_corrupt = sbus_auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128427.4] assign cbus_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128283.4] assign cbus_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128284.4] assign cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready = bootrom_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid = bootrom_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size = bootrom_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source = bootrom_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data = bootrom_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_ready = tile_auto_tl_slave_xing_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_valid = tile_auto_tl_slave_xing_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_opcode = tile_auto_tl_slave_xing_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_param = tile_auto_tl_slave_xing_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_size = tile_auto_tl_slave_xing_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_source = tile_auto_tl_slave_xing_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_sink = tile_auto_tl_slave_xing_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_denied = tile_auto_tl_slave_xing_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_data = tile_auto_tl_slave_xing_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_bits_corrupt = tile_auto_tl_slave_xing_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign cbus_auto_coupler_to_debug_fragmenter_out_a_ready = debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_debug_fragmenter_out_d_valid = debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode = debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size = debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source = debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data = debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign cbus_auto_coupler_to_clint_fragmenter_out_a_ready = clint_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_clint_fragmenter_out_d_valid = clint_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode = clint_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size = clint_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source = clint_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data = clint_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign cbus_auto_coupler_to_plic_fragmenter_out_a_ready = plic_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_coupler_to_plic_fragmenter_out_d_valid = plic_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode = plic_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size = plic_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source = plic_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data = plic_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign cbus_auto_bus_xing_in_a_valid = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_opcode = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_param = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_size = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_source = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_address = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_mask = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_data = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_a_bits_corrupt = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign cbus_auto_bus_xing_in_d_ready = sbus_auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128426.4] assign plic_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128307.4] assign plic_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128308.4] assign plic_auto_int_in_0 = int_bus_auto_int_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128406.4] assign plic_auto_int_in_1 = int_bus_auto_int_out_1; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128406.4] assign plic_auto_in_a_valid = cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_opcode = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_param = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_size = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_source = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_address = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_mask = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_data = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_a_bits_corrupt = cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign plic_auto_in_d_ready = cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128411.4] assign clint_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128314.4] assign clint_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128315.4] assign clint_auto_in_a_valid = cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_opcode = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_param = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_size = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_source = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_address = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_mask = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_data = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_a_bits_corrupt = cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_auto_in_d_ready = cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128413.4] assign clint_io_rtcTick = value == 7'h63; // @[RTC.scala 24:29:freechips.rocketchip.system.TinyConfig.fir@128452.4] assign debug_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128321.4] assign debug_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128322.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_valid = cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_param = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_size = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_source = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_address = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_data = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt = cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_auto_dmInner_dmInner_tl_in_d_ready = cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128415.4] assign debug_1_io_dmi_dmi_req_valid = debug_clockeddmi_dmi_req_valid; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmi_req_bits_addr = debug_clockeddmi_dmi_req_bits_addr; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmi_req_bits_data = debug_clockeddmi_dmi_req_bits_data; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmi_req_bits_op = debug_clockeddmi_dmi_req_bits_op; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmi_resp_ready = debug_clockeddmi_dmi_resp_ready; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmiClock = debug_clockeddmi_dmiClock; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign debug_1_io_dmi_dmiReset = debug_clockeddmi_dmiReset; // @[Periphery.scala 78:67:freechips.rocketchip.system.TinyConfig.fir@128435.4] assign tile_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128334.4] assign tile_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128335.4] assign tile_auto_intsink_in_sync_0 = debug_1_auto_dmOuter_intsource_out_sync_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128414.4] assign tile_auto_int_in_xing_in_1_sync_0 = intsource_1_auto_out_sync_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128424.4] assign tile_auto_int_in_xing_in_0_sync_0 = intsource_auto_out_sync_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128422.4] assign tile_auto_int_in_xing_in_0_sync_1 = intsource_auto_out_sync_1; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128422.4] assign tile_auto_tl_slave_xing_in_a_valid = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_opcode = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_param = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_size = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_source = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_address = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_mask = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_a_bits_data = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_slave_xing_in_d_ready = cbus_auto_coupler_to_tile_named_tile_tl_slave_xing_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128421.4] assign tile_auto_tl_master_xing_out_a_ready = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_valid = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_opcode = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_param = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_size = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_source = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_sink = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_denied = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_data = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign tile_auto_tl_master_xing_out_d_bits_corrupt = sbus_auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@128420.4] assign intsource_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128340.4] assign intsource_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128341.4] assign intsource_auto_in_0 = clint_auto_int_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128412.4] assign intsource_auto_in_1 = clint_auto_int_out_1; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128412.4] assign intsource_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128346.4] assign intsource_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128347.4] assign intsource_1_auto_in_0 = plic_auto_int_out_0; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128410.4] assign asyncXing_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128376.4] assign asyncXing_auto_int_in_0 = interrupts[0]; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128428.4] assign asyncXing_auto_int_in_1 = interrupts[1]; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128428.4] assign bootrom_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128382.4] assign bootrom_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@128383.4] assign bootrom_auto_in_a_valid = cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_opcode = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_param = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_size = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_source = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_address = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_mask = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_a_bits_corrupt = cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] assign bootrom_auto_in_d_ready = cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@128432.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; value = _RAND_0[6:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin value <= 7'h0; end else begin if (int_rtc_tick) begin value <= 7'h0; end else begin value <= _T_12; end end end endmodule module AXI4RAM( // @[:freechips.rocketchip.system.TinyConfig.fir@128461.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@128462.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@128463.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [11:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input [11:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] output auto_in_r_bits_user // @[:freechips.rocketchip.system.TinyConfig.fir@128464.4] ); wire [9:0] mem_R0_addr; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_R0_en; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_R0_clk; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_R0_data_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_R0_data_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_R0_data_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_R0_data_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [9:0] mem_W0_addr; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_en; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_clk; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_W0_data_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_W0_data_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_W0_data_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [7:0] mem_W0_data_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_mask_0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_mask_1; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_mask_2; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire mem_W0_mask_3; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] wire [9:0] _T; // @[SRAM.scala 54:49:freechips.rocketchip.system.TinyConfig.fir@128473.4] wire _T_1; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128474.4] wire _T_2; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128475.4] wire _T_3; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128476.4] wire _T_4; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128477.4] wire _T_5; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128478.4] wire _T_6; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128479.4] wire _T_7; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128480.4] wire _T_8; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128481.4] wire _T_9; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128482.4] wire _T_10; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128483.4] wire [4:0] _T_14; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128487.4] wire [4:0] _T_18; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128491.4] wire [9:0] _T_19; // @[SRAM.scala 55:49:freechips.rocketchip.system.TinyConfig.fir@128493.4] wire _T_20; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128494.4] wire _T_21; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128495.4] wire _T_22; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128496.4] wire _T_23; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128497.4] wire _T_24; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128498.4] wire _T_25; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128499.4] wire _T_26; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128500.4] wire _T_27; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128501.4] wire _T_28; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128502.4] wire _T_29; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128503.4] wire [4:0] _T_33; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128507.4] wire [4:0] _T_37; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128511.4] wire [12:0] _T_39; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@128514.4] wire [12:0] _T_40; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128515.4] wire [12:0] _T_41; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128516.4] wire r_sel0; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128517.4] wire [12:0] _T_43; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@128519.4] wire [12:0] _T_44; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128520.4] wire [12:0] _T_45; // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128521.4] wire w_sel0; // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128522.4] reg w_full; // @[SRAM.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@128523.4] reg [31:0] _RAND_0; reg [3:0] w_id; // @[SRAM.scala 60:21:freechips.rocketchip.system.TinyConfig.fir@128524.4] reg [31:0] _RAND_1; reg w_user; // @[SRAM.scala 61:21:freechips.rocketchip.system.TinyConfig.fir@128525.4] reg [31:0] _RAND_2; reg r_sel1; // @[SRAM.scala 62:21:freechips.rocketchip.system.TinyConfig.fir@128526.4] reg [31:0] _RAND_3; reg w_sel1; // @[SRAM.scala 63:21:freechips.rocketchip.system.TinyConfig.fir@128527.4] reg [31:0] _RAND_4; wire _T_46; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128528.4] wire _T_60; // @[SRAM.scala 81:50:freechips.rocketchip.system.TinyConfig.fir@128574.4] wire _T_61; // @[SRAM.scala 81:47:freechips.rocketchip.system.TinyConfig.fir@128575.4] wire in_aw_ready; // @[SRAM.scala 81:32:freechips.rocketchip.system.TinyConfig.fir@128576.4] wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128532.4] reg r_full; // @[SRAM.scala 88:25:freechips.rocketchip.system.TinyConfig.fir@128586.4] reg [31:0] _RAND_5; reg [3:0] r_id; // @[SRAM.scala 89:21:freechips.rocketchip.system.TinyConfig.fir@128587.4] reg [31:0] _RAND_6; reg r_user; // @[SRAM.scala 90:21:freechips.rocketchip.system.TinyConfig.fir@128588.4] reg [31:0] _RAND_7; wire _T_67; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128589.4] wire _T_76; // @[SRAM.scala 106:34:freechips.rocketchip.system.TinyConfig.fir@128624.4] wire in_ar_ready; // @[SRAM.scala 106:31:freechips.rocketchip.system.TinyConfig.fir@128625.4] wire _T_68; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128593.4] reg _T_74; // @[package.scala 75:91:freechips.rocketchip.system.TinyConfig.fir@128613.4] reg [31:0] _RAND_8; reg [7:0] _T_75_0; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@128615.4] reg [31:0] _RAND_9; reg [7:0] _T_75_1; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@128615.4] reg [31:0] _RAND_10; reg [7:0] _T_75_2; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@128615.4] reg [31:0] _RAND_11; reg [7:0] _T_75_3; // @[Reg.scala 15:16:freechips.rocketchip.system.TinyConfig.fir@128615.4] reg [31:0] _RAND_12; wire [7:0] _GEN_33; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] wire [7:0] _GEN_34; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] wire [7:0] _GEN_35; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] wire [7:0] _GEN_36; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] wire [15:0] _T_80; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128631.4] wire [15:0] _T_81; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128632.4] mem mem ( // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4] .R0_addr(mem_R0_addr), .R0_en(mem_R0_en), .R0_clk(mem_R0_clk), .R0_data_0(mem_R0_data_0), .R0_data_1(mem_R0_data_1), .R0_data_2(mem_R0_data_2), .R0_data_3(mem_R0_data_3), .W0_addr(mem_W0_addr), .W0_en(mem_W0_en), .W0_clk(mem_W0_clk), .W0_data_0(mem_W0_data_0), .W0_data_1(mem_W0_data_1), .W0_data_2(mem_W0_data_2), .W0_data_3(mem_W0_data_3), .W0_mask_0(mem_W0_mask_0), .W0_mask_1(mem_W0_mask_1), .W0_mask_2(mem_W0_mask_2), .W0_mask_3(mem_W0_mask_3) ); assign _T = auto_in_ar_bits_addr[11:2]; // @[SRAM.scala 54:49:freechips.rocketchip.system.TinyConfig.fir@128473.4] assign _T_1 = _T[0]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128474.4] assign _T_2 = _T[1]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128475.4] assign _T_3 = _T[2]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128476.4] assign _T_4 = _T[3]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128477.4] assign _T_5 = _T[4]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128478.4] assign _T_6 = _T[5]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128479.4] assign _T_7 = _T[6]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128480.4] assign _T_8 = _T[7]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128481.4] assign _T_9 = _T[8]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128482.4] assign _T_10 = _T[9]; // @[SRAM.scala 54:73:freechips.rocketchip.system.TinyConfig.fir@128483.4] assign _T_14 = {_T_5,_T_4,_T_3,_T_2,_T_1}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128487.4] assign _T_18 = {_T_10,_T_9,_T_8,_T_7,_T_6}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128491.4] assign _T_19 = auto_in_aw_bits_addr[11:2]; // @[SRAM.scala 55:49:freechips.rocketchip.system.TinyConfig.fir@128493.4] assign _T_20 = _T_19[0]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128494.4] assign _T_21 = _T_19[1]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128495.4] assign _T_22 = _T_19[2]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128496.4] assign _T_23 = _T_19[3]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128497.4] assign _T_24 = _T_19[4]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128498.4] assign _T_25 = _T_19[5]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128499.4] assign _T_26 = _T_19[6]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128500.4] assign _T_27 = _T_19[7]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128501.4] assign _T_28 = _T_19[8]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128502.4] assign _T_29 = _T_19[9]; // @[SRAM.scala 55:73:freechips.rocketchip.system.TinyConfig.fir@128503.4] assign _T_33 = {_T_24,_T_23,_T_22,_T_21,_T_20}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128507.4] assign _T_37 = {_T_29,_T_28,_T_27,_T_26,_T_25}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128511.4] assign _T_39 = {1'b0,$signed(auto_in_ar_bits_addr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@128514.4] assign _T_40 = $signed(_T_39) & $signed(-13'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128515.4] assign _T_41 = $signed(_T_40); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128516.4] assign r_sel0 = $signed(_T_41) == $signed(13'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128517.4] assign _T_43 = {1'b0,$signed(auto_in_aw_bits_addr)}; // @[Parameters.scala 123:49:freechips.rocketchip.system.TinyConfig.fir@128519.4] assign _T_44 = $signed(_T_43) & $signed(-13'sh1000); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128520.4] assign _T_45 = $signed(_T_44); // @[Parameters.scala 123:52:freechips.rocketchip.system.TinyConfig.fir@128521.4] assign w_sel0 = $signed(_T_45) == $signed(13'sh0); // @[Parameters.scala 123:67:freechips.rocketchip.system.TinyConfig.fir@128522.4] assign _T_46 = auto_in_b_ready & w_full; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128528.4] assign _T_60 = w_full == 1'h0; // @[SRAM.scala 81:50:freechips.rocketchip.system.TinyConfig.fir@128574.4] assign _T_61 = auto_in_b_ready | _T_60; // @[SRAM.scala 81:47:freechips.rocketchip.system.TinyConfig.fir@128575.4] assign in_aw_ready = auto_in_w_valid & _T_61; // @[SRAM.scala 81:32:freechips.rocketchip.system.TinyConfig.fir@128576.4] assign _T_47 = in_aw_ready & auto_in_aw_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128532.4] assign _T_67 = auto_in_r_ready & r_full; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128589.4] assign _T_76 = r_full == 1'h0; // @[SRAM.scala 106:34:freechips.rocketchip.system.TinyConfig.fir@128624.4] assign in_ar_ready = auto_in_r_ready | _T_76; // @[SRAM.scala 106:31:freechips.rocketchip.system.TinyConfig.fir@128625.4] assign _T_68 = in_ar_ready & auto_in_ar_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@128593.4] assign _GEN_33 = _T_74 ? mem_R0_data_0 : _T_75_0; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] assign _GEN_34 = _T_74 ? mem_R0_data_1 : _T_75_1; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] assign _GEN_35 = _T_74 ? mem_R0_data_2 : _T_75_2; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] assign _GEN_36 = _T_74 ? mem_R0_data_3 : _T_75_3; // @[Reg.scala 16:19:freechips.rocketchip.system.TinyConfig.fir@128616.4] assign _T_80 = {_GEN_34,_GEN_33}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128631.4] assign _T_81 = {_GEN_36,_GEN_35}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@128632.4] assign auto_in_aw_ready = auto_in_w_valid & _T_61; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_w_ready = auto_in_aw_valid & _T_61; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_b_valid = w_full; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_b_bits_id = w_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_b_bits_resp = w_sel1 ? 2'h0 : 2'h3; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_b_bits_user = w_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_ar_ready = auto_in_r_ready | _T_76; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_r_valid = r_full; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_r_bits_id = r_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_r_bits_data = {_T_81,_T_80}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_r_bits_resp = r_sel1 ? 2'h0 : 2'h3; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign auto_in_r_bits_user = r_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128471.4] assign mem_R0_addr = {_T_18,_T_14}; // @[package.scala 75:58:freechips.rocketchip.system.TinyConfig.fir@128611.6] assign mem_R0_en = in_ar_ready & auto_in_ar_valid; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4 package.scala 75:58:freechips.rocketchip.system.TinyConfig.fir@128610.6] assign mem_R0_clk = clock; // @[package.scala 75:58:freechips.rocketchip.system.TinyConfig.fir@128611.6] assign mem_W0_addr = {_T_37,_T_33}; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6] assign mem_W0_en = _T_47 & w_sel0; // @[DescribedSRAM.scala 25:21:freechips.rocketchip.system.TinyConfig.fir@128472.4 :freechips.rocketchip.system.TinyConfig.fir@128559.6] assign mem_W0_clk = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6] assign mem_W0_data_0 = auto_in_w_bits_data[7:0]; // @[:freechips.rocketchip.system.TinyConfig.fir@128561.8] assign mem_W0_data_1 = auto_in_w_bits_data[15:8]; // @[:freechips.rocketchip.system.TinyConfig.fir@128564.8] assign mem_W0_data_2 = auto_in_w_bits_data[23:16]; // @[:freechips.rocketchip.system.TinyConfig.fir@128567.8] assign mem_W0_data_3 = auto_in_w_bits_data[31:24]; // @[:freechips.rocketchip.system.TinyConfig.fir@128570.8] assign mem_W0_mask_0 = auto_in_w_bits_strb[0]; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6 :freechips.rocketchip.system.TinyConfig.fir@128561.8] assign mem_W0_mask_1 = auto_in_w_bits_strb[1]; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6 :freechips.rocketchip.system.TinyConfig.fir@128564.8] assign mem_W0_mask_2 = auto_in_w_bits_strb[2]; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6 :freechips.rocketchip.system.TinyConfig.fir@128567.8] assign mem_W0_mask_3 = auto_in_w_bits_strb[3]; // @[:freechips.rocketchip.system.TinyConfig.fir@128559.6 :freechips.rocketchip.system.TinyConfig.fir@128570.8] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; w_full = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; w_id = _RAND_1[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; w_user = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; r_sel1 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; w_sel1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; r_full = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; r_id = _RAND_6[3:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; r_user = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_74 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_75_0 = _RAND_9[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_75_1 = _RAND_10[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_75_2 = _RAND_11[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_75_3 = _RAND_12[7:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin w_full <= 1'h0; end else begin if (_T_47) begin w_full <= 1'h1; end else begin if (_T_46) begin w_full <= 1'h0; end end end if (_T_47) begin w_id <= auto_in_aw_bits_id; end if (_T_47) begin w_user <= auto_in_aw_bits_user; end if (_T_68) begin r_sel1 <= r_sel0; end if (_T_47) begin w_sel1 <= w_sel0; end if (reset) begin r_full <= 1'h0; end else begin if (_T_68) begin r_full <= 1'h1; end else begin if (_T_67) begin r_full <= 1'h0; end end end if (_T_68) begin r_id <= auto_in_ar_bits_id; end if (_T_68) begin r_user <= auto_in_ar_bits_user; end _T_74 <= in_ar_ready & auto_in_ar_valid; if (_T_74) begin _T_75_0 <= mem_R0_data_0; end if (_T_74) begin _T_75_1 <= mem_R0_data_1; end if (_T_74) begin _T_75_2 <= mem_R0_data_2; end if (_T_74) begin _T_75_3 <= mem_R0_data_3; end end endmodule module AXI4Xbar( // @[:freechips.rocketchip.system.TinyConfig.fir@128768.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@128769.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@128770.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [11:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [11:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [11:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [11:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@128771.4] ); wire _T_44; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128877.4] wire _T_50; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128887.4] wire _T_52; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128889.4] wire _T_53; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128890.4] wire _T_65; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128923.4] wire _T_71; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128933.4] wire _T_73; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128935.4] wire _T_74; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128936.4] wire _T_88; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128973.4] wire _T_94; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128983.4] wire _T_96; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128985.4] wire _T_97; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128986.4] wire _T_109; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@129018.4] wire _T_115; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@129028.4] wire _T_117; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129030.4] wire _T_118; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129031.4] assign _T_44 = auto_in_aw_valid == 1'h0; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128877.4] assign _T_50 = _T_44 | auto_in_aw_valid; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128887.4] assign _T_52 = _T_50 | reset; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128889.4] assign _T_53 = _T_52 == 1'h0; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128890.4] assign _T_65 = auto_in_ar_valid == 1'h0; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128923.4] assign _T_71 = _T_65 | auto_in_ar_valid; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128933.4] assign _T_73 = _T_71 | reset; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128935.4] assign _T_74 = _T_73 == 1'h0; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128936.4] assign _T_88 = auto_out_r_valid == 1'h0; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@128973.4] assign _T_94 = _T_88 | auto_out_r_valid; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@128983.4] assign _T_96 = _T_94 | reset; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128985.4] assign _T_97 = _T_96 == 1'h0; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128986.4] assign _T_109 = auto_out_b_valid == 1'h0; // @[Xbar.scala 256:60:freechips.rocketchip.system.TinyConfig.fir@129018.4] assign _T_115 = _T_109 | auto_out_b_valid; // @[Xbar.scala 258:23:freechips.rocketchip.system.TinyConfig.fir@129028.4] assign _T_117 = _T_115 | reset; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129030.4] assign _T_118 = _T_117 == 1'h0; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129031.4] assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@128781.4] assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@128780.4] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_53) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:258 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128892.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_53) begin $fatal; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128893.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_74) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:258 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128938.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_74) begin $fatal; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128939.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_97) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:258 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128988.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_97) begin $fatal; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@128989.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_118) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:258 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129033.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_118) begin $fatal; // @[Xbar.scala 258:12:freechips.rocketchip.system.TinyConfig.fir@129034.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module Queue_44( // @[:freechips.rocketchip.system.TinyConfig.fir@129054.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129055.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129056.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] input [11:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] input io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] output [11:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] output io_deq_bits_user // @[:freechips.rocketchip.system.TinyConfig.fir@129057.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg [11:0] _T_addr [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg [31:0] _RAND_1; wire [11:0] _T_addr__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_addr__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire [11:0] _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_addr__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_addr__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_addr__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg _T_user [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg [31:0] _RAND_2; wire _T_user__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_user__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129060.4] reg [31:0] _RAND_3; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129061.4] reg [31:0] _RAND_4; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@129062.4] reg [31:0] _RAND_5; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129063.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129064.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129065.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129066.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129067.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129070.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129087.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129093.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129096.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_addr__T_18_addr = value_1; assign _T_addr__T_18_data = _T_addr[_T_addr__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] assign _T_addr__T_10_data = io_enq_bits_addr; assign _T_addr__T_10_addr = value; assign _T_addr__T_10_mask = 1'h1; assign _T_addr__T_10_en = io_enq_ready & io_enq_valid; assign _T_user__T_18_addr = value_1; assign _T_user__T_18_data = _T_user[_T_user__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = value; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129063.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129064.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129065.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129066.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129067.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129070.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129087.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129093.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129096.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@129103.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@129101.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129114.4] assign io_deq_bits_addr = _T_addr__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129113.4] assign io_deq_bits_user = _T_user__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129105.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_addr[initvar] = _RAND_1[11:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_user[initvar] = _RAND_2[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; value = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; value_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] end if(_T_addr__T_10_en & _T_addr__T_10_mask) begin _T_addr[_T_addr__T_10_addr] <= _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129059.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_46( // @[:freechips.rocketchip.system.TinyConfig.fir@129176.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129177.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129178.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] input io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] output io_deq_bits_user // @[:freechips.rocketchip.system.TinyConfig.fir@129179.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg [1:0] _T_resp [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg [31:0] _RAND_1; wire [1:0] _T_resp__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_resp__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg _T_user [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg [31:0] _RAND_2; wire _T_user__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_user__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129182.4] reg [31:0] _RAND_3; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129183.4] reg [31:0] _RAND_4; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@129184.4] reg [31:0] _RAND_5; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129185.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129186.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129187.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129188.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129189.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129192.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129202.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129208.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129211.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_resp__T_18_addr = value_1; assign _T_resp__T_18_data = _T_resp[_T_resp__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = value; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = io_enq_ready & io_enq_valid; assign _T_user__T_18_addr = value_1; assign _T_user__T_18_data = _T_user[_T_user__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = value; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129185.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129186.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129187.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129188.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129189.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129192.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129202.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129208.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129211.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@129218.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@129216.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129222.4] assign io_deq_bits_resp = _T_resp__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129221.4] assign io_deq_bits_user = _T_user__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129220.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_resp[initvar] = _RAND_1[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_user[initvar] = _RAND_2[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; value = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; value_1 = _RAND_4[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129181.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module Queue_48( // @[:freechips.rocketchip.system.TinyConfig.fir@129298.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129299.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129300.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input io_enq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output [31:0] io_deq_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output io_deq_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] output io_deq_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@129301.4] ); reg [3:0] _T_id [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_id__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _RAND_1; wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_data__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [1:0] _T_resp [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _RAND_2; wire [1:0] _T_resp__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_resp__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire [1:0] _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_resp__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_resp__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_resp__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg _T_user [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _RAND_3; wire _T_user__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_user__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_user__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_user__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_user__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg _T_last [0:1]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg [31:0] _RAND_4; wire _T_last__T_18_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_last__T_18_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_last__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_last__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] wire _T_last__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129304.4] reg [31:0] _RAND_5; reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.TinyConfig.fir@129305.4] reg [31:0] _RAND_6; reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@129306.4] reg [31:0] _RAND_7; wire _T_2; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129307.4] wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129308.4] wire _T_4; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129309.4] wire _T_5; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129310.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129311.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129314.4] wire _T_12; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129326.6] wire _T_14; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129332.6] wire _T_15; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129335.4] assign _T_id__T_18_addr = value_1; assign _T_id__T_18_data = _T_id[_T_id__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = value; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = io_enq_ready & io_enq_valid; assign _T_data__T_18_addr = value_1; assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] assign _T_data__T_10_data = io_enq_bits_data; assign _T_data__T_10_addr = value; assign _T_data__T_10_mask = 1'h1; assign _T_data__T_10_en = io_enq_ready & io_enq_valid; assign _T_resp__T_18_addr = value_1; assign _T_resp__T_18_data = _T_resp[_T_resp__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] assign _T_resp__T_10_data = io_enq_bits_resp; assign _T_resp__T_10_addr = value; assign _T_resp__T_10_mask = 1'h1; assign _T_resp__T_10_en = io_enq_ready & io_enq_valid; assign _T_user__T_18_addr = value_1; assign _T_user__T_18_data = _T_user[_T_user__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] assign _T_user__T_10_data = io_enq_bits_user; assign _T_user__T_10_addr = value; assign _T_user__T_10_mask = 1'h1; assign _T_user__T_10_en = io_enq_ready & io_enq_valid; assign _T_last__T_18_addr = value_1; assign _T_last__T_18_data = _T_last[_T_last__T_18_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] assign _T_last__T_10_data = 1'h1; assign _T_last__T_10_addr = value; assign _T_last__T_10_mask = 1'h1; assign _T_last__T_10_en = io_enq_ready & io_enq_valid; assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:freechips.rocketchip.system.TinyConfig.fir@129307.4] assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129308.4] assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:freechips.rocketchip.system.TinyConfig.fir@129309.4] assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:freechips.rocketchip.system.TinyConfig.fir@129310.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129311.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129314.4] assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129326.6] assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.TinyConfig.fir@129332.6] assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129335.4] assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@129342.4] assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@129340.4] assign io_deq_bits_id = _T_id__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129348.4] assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129347.4] assign io_deq_bits_resp = _T_resp__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129346.4] assign io_deq_bits_user = _T_user__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129345.4] assign io_deq_bits_last = _T_last__T_18_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129344.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_data[initvar] = _RAND_1[31:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_resp[initvar] = _RAND_2[1:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_user[initvar] = _RAND_3[0:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 2; initvar = initvar+1) _T_last[initvar] = _RAND_4[0:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; value = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; value_1 = _RAND_6[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_1 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] end if(_T_data__T_10_en & _T_data__T_10_mask) begin _T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] end if(_T_resp__T_10_en & _T_resp__T_10_mask) begin _T_resp[_T_resp__T_10_addr] <= _T_resp__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] end if(_T_user__T_10_en & _T_user__T_10_mask) begin _T_user[_T_user__T_10_addr] <= _T_user__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] end if(_T_last__T_10_en & _T_last__T_10_mask) begin _T_last[_T_last__T_10_addr] <= _T_last__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129303.4] end if (reset) begin value <= 1'h0; end else begin if (_T_6) begin value <= _T_12; end end if (reset) begin value_1 <= 1'h0; end else begin if (_T_8) begin value_1 <= _T_14; end end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_15) begin _T_1 <= _T_6; end end end endmodule module AXI4Buffer_1( // @[:freechips.rocketchip.system.TinyConfig.fir@129356.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129357.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129358.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [11:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [11:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [11:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output [11:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] input auto_out_r_bits_user // @[:freechips.rocketchip.system.TinyConfig.fir@129359.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire [3:0] Queue_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire [11:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire [3:0] Queue_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire [11:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire [31:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire [3:0] Queue_1_io_enq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire [31:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire [3:0] Queue_1_io_deq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_1_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] wire Queue_2_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire [3:0] Queue_2_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire [1:0] Queue_2_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire [3:0] Queue_2_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire [1:0] Queue_2_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_2_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] wire Queue_3_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire [3:0] Queue_3_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire [11:0] Queue_3_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire [3:0] Queue_3_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire [11:0] Queue_3_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_3_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] wire Queue_4_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [3:0] Queue_4_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [31:0] Queue_4_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [1:0] Queue_4_io_enq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_enq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [3:0] Queue_4_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [31:0] Queue_4_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire [1:0] Queue_4_io_deq_bits_resp; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_deq_bits_user; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] wire Queue_4_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] Queue_44 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129370.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_addr(Queue_io_enq_bits_addr), .io_enq_bits_user(Queue_io_enq_bits_user), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_addr(Queue_io_deq_bits_addr), .io_deq_bits_user(Queue_io_deq_bits_user) ); Queue_1 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129399.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_data(Queue_1_io_enq_bits_data), .io_enq_bits_strb(Queue_1_io_enq_bits_strb), .io_enq_bits_last(Queue_1_io_enq_bits_last), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_data(Queue_1_io_deq_bits_data), .io_deq_bits_strb(Queue_1_io_deq_bits_strb), .io_deq_bits_last(Queue_1_io_deq_bits_last) ); Queue_46 Queue_2 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129414.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits_id(Queue_2_io_enq_bits_id), .io_enq_bits_resp(Queue_2_io_enq_bits_resp), .io_enq_bits_user(Queue_2_io_enq_bits_user), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits_id(Queue_2_io_deq_bits_id), .io_deq_bits_resp(Queue_2_io_deq_bits_resp), .io_deq_bits_user(Queue_2_io_deq_bits_user) ); Queue_44 Queue_3 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129429.4] .clock(Queue_3_clock), .reset(Queue_3_reset), .io_enq_ready(Queue_3_io_enq_ready), .io_enq_valid(Queue_3_io_enq_valid), .io_enq_bits_id(Queue_3_io_enq_bits_id), .io_enq_bits_addr(Queue_3_io_enq_bits_addr), .io_enq_bits_user(Queue_3_io_enq_bits_user), .io_deq_ready(Queue_3_io_deq_ready), .io_deq_valid(Queue_3_io_deq_valid), .io_deq_bits_id(Queue_3_io_deq_bits_id), .io_deq_bits_addr(Queue_3_io_deq_bits_addr), .io_deq_bits_user(Queue_3_io_deq_bits_user) ); Queue_48 Queue_4 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129458.4] .clock(Queue_4_clock), .reset(Queue_4_reset), .io_enq_ready(Queue_4_io_enq_ready), .io_enq_valid(Queue_4_io_enq_valid), .io_enq_bits_id(Queue_4_io_enq_bits_id), .io_enq_bits_data(Queue_4_io_enq_bits_data), .io_enq_bits_resp(Queue_4_io_enq_bits_resp), .io_enq_bits_user(Queue_4_io_enq_bits_user), .io_deq_ready(Queue_4_io_deq_ready), .io_deq_valid(Queue_4_io_deq_valid), .io_deq_bits_id(Queue_4_io_deq_bits_id), .io_deq_bits_data(Queue_4_io_deq_bits_data), .io_deq_bits_resp(Queue_4_io_deq_bits_resp), .io_deq_bits_user(Queue_4_io_deq_bits_user), .io_deq_bits_last(Queue_4_io_deq_bits_last) ); assign auto_in_aw_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_w_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_b_valid = Queue_2_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_b_bits_id = Queue_2_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_b_bits_resp = Queue_2_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_b_bits_user = Queue_2_io_deq_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_ar_ready = Queue_3_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_valid = Queue_4_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_bits_id = Queue_4_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_bits_data = Queue_4_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_bits_resp = Queue_4_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_bits_user = Queue_4_io_deq_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_in_r_bits_last = Queue_4_io_deq_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129369.4] assign auto_out_aw_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_aw_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_aw_bits_addr = Queue_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_aw_bits_user = Queue_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_w_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_w_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_w_bits_strb = Queue_1_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_b_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_ar_valid = Queue_3_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_ar_bits_id = Queue_3_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_ar_bits_addr = Queue_3_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_ar_bits_user = Queue_3_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign auto_out_r_ready = Queue_4_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129368.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129371.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129372.4] assign Queue_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129373.4] assign Queue_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129383.4] assign Queue_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129382.4] assign Queue_io_enq_bits_user = auto_in_aw_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129374.4] assign Queue_io_deq_ready = auto_out_aw_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129397.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129400.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129401.4] assign Queue_1_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129402.4] assign Queue_1_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129405.4] assign Queue_1_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129404.4] assign Queue_1_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129403.4] assign Queue_1_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129412.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129415.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129416.4] assign Queue_2_io_enq_valid = auto_out_b_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129417.4] assign Queue_2_io_enq_bits_id = auto_out_b_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129420.4] assign Queue_2_io_enq_bits_resp = auto_out_b_bits_resp; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129419.4] assign Queue_2_io_enq_bits_user = auto_out_b_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129418.4] assign Queue_2_io_deq_ready = auto_in_b_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129427.4] assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129430.4] assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129431.4] assign Queue_3_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129432.4] assign Queue_3_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129442.4] assign Queue_3_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129441.4] assign Queue_3_io_enq_bits_user = auto_in_ar_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129433.4] assign Queue_3_io_deq_ready = auto_out_ar_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129456.4] assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129459.4] assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129460.4] assign Queue_4_io_enq_valid = auto_out_r_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129461.4] assign Queue_4_io_enq_bits_id = auto_out_r_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129466.4] assign Queue_4_io_enq_bits_data = auto_out_r_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129465.4] assign Queue_4_io_enq_bits_resp = auto_out_r_bits_resp; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129464.4] assign Queue_4_io_enq_bits_user = auto_out_r_bits_user; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129463.4] assign Queue_4_io_deq_ready = auto_in_r_ready; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129475.4] endmodule module Queue_49( // @[:freechips.rocketchip.system.TinyConfig.fir@129478.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129479.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129480.4] output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input io_enq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input [11:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input [1:0] io_enq_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] input io_deq_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output io_deq_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output [11:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] output [1:0] io_deq_bits_burst // @[:freechips.rocketchip.system.TinyConfig.fir@129481.4] ); reg [3:0] _T_id [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [31:0] _RAND_0; wire [3:0] _T_id__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_id__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire [3:0] _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_id__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_id__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_id__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [11:0] _T_addr [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [31:0] _RAND_1; wire [11:0] _T_addr__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_addr__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire [11:0] _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_addr__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_addr__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_addr__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [7:0] _T_len [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [31:0] _RAND_2; wire [7:0] _T_len__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_len__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire [7:0] _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_len__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_len__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_len__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [2:0] _T_size [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [31:0] _RAND_3; wire [2:0] _T_size__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_size__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_size__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [1:0] _T_burst [0:0]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg [31:0] _RAND_4; wire [1:0] _T_burst__T_14_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_burst__T_14_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire [1:0] _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_burst__T_10_addr; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_burst__T_10_mask; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] wire _T_burst__T_10_en; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] reg _T_1; // @[Decoupled.scala 218:35:freechips.rocketchip.system.TinyConfig.fir@129484.4] reg [31:0] _RAND_5; wire _T_3; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129486.4] wire _T_6; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129489.4] wire _T_8; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129492.4] wire _GEN_15; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@129541.6] wire _GEN_26; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@129530.4] wire _GEN_25; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@129530.4] wire _T_11; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129509.4] wire _T_12; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@129513.4] assign _T_id__T_14_addr = 1'h0; assign _T_id__T_14_data = _T_id[_T_id__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] assign _T_id__T_10_data = io_enq_bits_id; assign _T_id__T_10_addr = 1'h0; assign _T_id__T_10_mask = 1'h1; assign _T_id__T_10_en = _T_3 ? _GEN_15 : _T_6; assign _T_addr__T_14_addr = 1'h0; assign _T_addr__T_14_data = _T_addr[_T_addr__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] assign _T_addr__T_10_data = io_enq_bits_addr; assign _T_addr__T_10_addr = 1'h0; assign _T_addr__T_10_mask = 1'h1; assign _T_addr__T_10_en = _T_3 ? _GEN_15 : _T_6; assign _T_len__T_14_addr = 1'h0; assign _T_len__T_14_data = _T_len[_T_len__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] assign _T_len__T_10_data = io_enq_bits_len; assign _T_len__T_10_addr = 1'h0; assign _T_len__T_10_mask = 1'h1; assign _T_len__T_10_en = _T_3 ? _GEN_15 : _T_6; assign _T_size__T_14_addr = 1'h0; assign _T_size__T_14_data = _T_size[_T_size__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] assign _T_size__T_10_data = io_enq_bits_size; assign _T_size__T_10_addr = 1'h0; assign _T_size__T_10_mask = 1'h1; assign _T_size__T_10_en = _T_3 ? _GEN_15 : _T_6; assign _T_burst__T_14_addr = 1'h0; assign _T_burst__T_14_data = _T_burst[_T_burst__T_14_addr]; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] assign _T_burst__T_10_data = io_enq_bits_burst; assign _T_burst__T_10_addr = 1'h0; assign _T_burst__T_10_mask = 1'h1; assign _T_burst__T_10_en = _T_3 ? _GEN_15 : _T_6; assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:freechips.rocketchip.system.TinyConfig.fir@129486.4] assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129489.4] assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129492.4] assign _GEN_15 = io_deq_ready ? 1'h0 : _T_6; // @[Decoupled.scala 246:27:freechips.rocketchip.system.TinyConfig.fir@129541.6] assign _GEN_26 = _T_3 ? _GEN_15 : _T_6; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@129530.4] assign _GEN_25 = _T_3 ? 1'h0 : _T_8; // @[Decoupled.scala 243:18:freechips.rocketchip.system.TinyConfig.fir@129530.4] assign _T_11 = _GEN_26 != _GEN_25; // @[Decoupled.scala 233:16:freechips.rocketchip.system.TinyConfig.fir@129509.4] assign _T_12 = _T_3 == 1'h0; // @[Decoupled.scala 237:19:freechips.rocketchip.system.TinyConfig.fir@129513.4] assign io_enq_ready = _T_1 == 1'h0; // @[Decoupled.scala 238:16:freechips.rocketchip.system.TinyConfig.fir@129516.4] assign io_deq_valid = io_enq_valid ? 1'h1 : _T_12; // @[Decoupled.scala 237:16:freechips.rocketchip.system.TinyConfig.fir@129514.4 Decoupled.scala 242:40:freechips.rocketchip.system.TinyConfig.fir@129528.6] assign io_deq_bits_id = _T_3 ? io_enq_bits_id : _T_id__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129526.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@129539.6] assign io_deq_bits_addr = _T_3 ? io_enq_bits_addr : _T_addr__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129525.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@129538.6] assign io_deq_bits_len = _T_3 ? io_enq_bits_len : _T_len__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129524.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@129537.6] assign io_deq_bits_size = _T_3 ? io_enq_bits_size : _T_size__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129523.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@129536.6] assign io_deq_bits_burst = _T_3 ? io_enq_bits_burst : _T_burst__T_14_data; // @[Decoupled.scala 239:15:freechips.rocketchip.system.TinyConfig.fir@129522.4 Decoupled.scala 244:19:freechips.rocketchip.system.TinyConfig.fir@129535.6] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif _RAND_0 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_id[initvar] = _RAND_0[3:0]; `endif // RANDOMIZE_MEM_INIT _RAND_1 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_addr[initvar] = _RAND_1[11:0]; `endif // RANDOMIZE_MEM_INIT _RAND_2 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_len[initvar] = _RAND_2[7:0]; `endif // RANDOMIZE_MEM_INIT _RAND_3 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_size[initvar] = _RAND_3[2:0]; `endif // RANDOMIZE_MEM_INIT _RAND_4 = {1{`RANDOM}}; `ifdef RANDOMIZE_MEM_INIT for (initvar = 0; initvar < 1; initvar = initvar+1) _T_burst[initvar] = _RAND_4[1:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_1 = _RAND_5[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if(_T_id__T_10_en & _T_id__T_10_mask) begin _T_id[_T_id__T_10_addr] <= _T_id__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] end if(_T_addr__T_10_en & _T_addr__T_10_mask) begin _T_addr[_T_addr__T_10_addr] <= _T_addr__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] end if(_T_len__T_10_en & _T_len__T_10_mask) begin _T_len[_T_len__T_10_addr] <= _T_len__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] end if(_T_size__T_10_en & _T_size__T_10_mask) begin _T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] end if(_T_burst__T_10_en & _T_burst__T_10_mask) begin _T_burst[_T_burst__T_10_addr] <= _T_burst__T_10_data; // @[Decoupled.scala 215:24:freechips.rocketchip.system.TinyConfig.fir@129483.4] end if (reset) begin _T_1 <= 1'h0; end else begin if (_T_11) begin if (_T_3) begin if (io_deq_ready) begin _T_1 <= 1'h0; end else begin _T_1 <= _T_6; end end else begin _T_1 <= _T_6; end end end end endmodule module AXI4Fragmenter_1( // @[:freechips.rocketchip.system.TinyConfig.fir@129682.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@129683.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@129684.4] output auto_in_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [11:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_in_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [31:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [3:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_in_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_in_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [11:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_in_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_in_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [31:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_in_r_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [11:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_aw_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [31:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [3:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_b_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output [11:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_ar_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] output auto_out_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [31:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_r_bits_user, // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] input auto_out_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@129685.4] ); wire Queue_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [3:0] Queue_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [11:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [7:0] Queue_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [1:0] Queue_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [3:0] Queue_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [11:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [7:0] Queue_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire [1:0] Queue_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] wire Queue_1_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_1_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_1_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_1_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [3:0] Queue_1_io_enq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [11:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [1:0] Queue_1_io_enq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_1_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_1_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [3:0] Queue_1_io_deq_bits_id; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [11:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] wire Queue_2_clock; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_reset; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_enq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_enq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire [31:0] Queue_2_io_enq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire [3:0] Queue_2_io_enq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_enq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_deq_ready; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_deq_valid; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire [31:0] Queue_2_io_deq_bits_data; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire [3:0] Queue_2_io_deq_bits_strb; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] wire Queue_2_io_deq_bits_last; // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] reg _T_4; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@129724.4] reg [31:0] _RAND_0; reg [11:0] _T_5; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@129725.4] reg [31:0] _RAND_1; reg [7:0] _T_6; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.TinyConfig.fir@129726.4] reg [31:0] _RAND_2; wire [7:0] _T_2_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129717.4] wire [7:0] _T_7; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@129727.4] wire [11:0] _T_2_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129718.4] wire [11:0] _T_8; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@129728.4] wire [1:0] _T_2_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129715.4] wire _T_50; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@129770.4] wire [2:0] _T_2_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129716.4] wire [15:0] _T_59; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@129779.4] wire [15:0] _GEN_48; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129780.4] wire [15:0] _T_61; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129781.4] wire [15:0] _T_62; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@129782.4] wire [22:0] _GEN_49; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129783.4] wire [22:0] _T_63; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129783.4] wire [14:0] _T_64; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@129784.4] wire _T_66; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@129788.4] wire [15:0] _GEN_50; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129790.6] wire [15:0] _T_67; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129790.6] wire [11:0] _T_68; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@129791.6] wire [14:0] _GEN_51; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129792.6] wire [14:0] _T_69; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129792.6] wire [14:0] _T_70; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@129793.6] wire [15:0] _GEN_52; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129794.6] wire [15:0] _T_71; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129794.6] wire [15:0] _GEN_0; // @[Fragmenter.scala 101:59:freechips.rocketchip.system.TinyConfig.fir@129789.4] wire [15:0] _GEN_1; // @[Fragmenter.scala 104:60:freechips.rocketchip.system.TinyConfig.fir@129798.4] wire _T_73; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@129801.4] wire [11:0] _T_75; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@129807.4] wire [8:0] _T_77; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@129809.4] wire [1:0] _T_78; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@129810.4] wire [1:0] _T_79; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@129811.4] wire [11:0] _GEN_53; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129812.4] wire [11:0] _T_80; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129812.4] wire _T_2_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129720.4] wire _T_82; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129815.4] wire _T_83; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@129817.6] wire [8:0] _GEN_54; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129820.6] wire [8:0] _T_85; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129821.6] wire [15:0] _GEN_3; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129816.4] wire [8:0] _GEN_4; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129816.4] reg _T_88; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@129852.4] reg [31:0] _RAND_3; reg [11:0] _T_89; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.TinyConfig.fir@129853.4] reg [31:0] _RAND_4; reg [7:0] _T_90; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.TinyConfig.fir@129854.4] reg [31:0] _RAND_5; wire [7:0] _T_86_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129845.4] wire [7:0] _T_91; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@129855.4] wire [11:0] _T_86_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129846.4] wire [11:0] _T_92; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@129856.4] wire [1:0] _T_86_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129843.4] wire _T_134; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@129898.4] wire [2:0] _T_86_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129844.4] wire [15:0] _T_143; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@129907.4] wire [15:0] _GEN_59; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129908.4] wire [15:0] _T_145; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129909.4] wire [15:0] _T_146; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@129910.4] wire [22:0] _GEN_60; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129911.4] wire [22:0] _T_147; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129911.4] wire [14:0] _T_148; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@129912.4] wire _T_150; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@129916.4] wire [15:0] _GEN_61; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129918.6] wire [15:0] _T_151; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129918.6] wire [11:0] _T_152; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@129919.6] wire [14:0] _GEN_62; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129920.6] wire [14:0] _T_153; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129920.6] wire [14:0] _T_154; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@129921.6] wire [15:0] _GEN_63; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129922.6] wire [15:0] _T_155; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129922.6] wire [15:0] _GEN_5; // @[Fragmenter.scala 101:59:freechips.rocketchip.system.TinyConfig.fir@129917.4] wire [15:0] _GEN_6; // @[Fragmenter.scala 104:60:freechips.rocketchip.system.TinyConfig.fir@129926.4] wire _T_157; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@129929.4] reg [8:0] _T_182; // @[Fragmenter.scala 162:30:freechips.rocketchip.system.TinyConfig.fir@129992.4] reg [31:0] _RAND_6; wire _T_183; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.TinyConfig.fir@129993.4] reg _T_171; // @[Fragmenter.scala 148:35:freechips.rocketchip.system.TinyConfig.fir@129968.4] reg [31:0] _RAND_7; wire _T_178; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.TinyConfig.fir@129984.4] wire _T_179; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.TinyConfig.fir@129985.4] wire [11:0] _T_159; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@129935.4] wire [8:0] _T_161; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@129937.4] wire [1:0] _T_162; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@129938.4] wire [1:0] _T_163; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@129939.4] wire [11:0] _GEN_64; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129940.4] wire [11:0] _T_164; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129940.4] wire _T_86_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129848.4] wire _T_166; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129943.4] wire _T_167; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@129945.6] wire [8:0] _GEN_65; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129948.6] wire [8:0] _T_169; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129949.6] wire [15:0] _GEN_8; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129944.4] wire [8:0] _GEN_9; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129944.4] wire _T_180; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.TinyConfig.fir@129987.4] wire _T_181; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.TinyConfig.fir@129988.4] wire _T_174; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@129973.4] wire _T_177; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.TinyConfig.fir@129982.4] wire _T_175; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129977.4] wire [8:0] _T_184; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.TinyConfig.fir@129994.4] wire [8:0] _T_185; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.TinyConfig.fir@129995.4] wire _T_186; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.TinyConfig.fir@129996.4] wire _T_170_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129960.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129964.4] wire _T_197; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@130013.4] wire _T_198; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.TinyConfig.fir@130014.4] wire _T_199; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.TinyConfig.fir@130015.4] wire _T_187; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129997.4] wire [8:0] _GEN_66; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@129998.4] wire [8:0] _T_189; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@129999.4] wire _T_191; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.TinyConfig.fir@130002.4] wire _T_192; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.TinyConfig.fir@130003.4] wire _T_193; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.TinyConfig.fir@130004.4] wire _T_195; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130006.4] wire _T_196; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130007.4] wire _T_203; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.TinyConfig.fir@130023.4] wire _T_170_bits_last; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129960.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129961.4] wire _T_204; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.TinyConfig.fir@130024.4] wire _T_205; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.TinyConfig.fir@130025.4] wire _T_206; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.TinyConfig.fir@130026.4] wire _T_208; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130028.4] wire _T_209; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130029.4] wire _T_214; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.TinyConfig.fir@130042.4] wire _T_215; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.TinyConfig.fir@130043.4] reg [1:0] _T_217_0; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_8; reg [1:0] _T_217_1; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_9; reg [1:0] _T_217_2; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_10; reg [1:0] _T_217_3; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_11; reg [1:0] _T_217_4; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_12; reg [1:0] _T_217_5; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_13; reg [1:0] _T_217_6; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_14; reg [1:0] _T_217_7; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_15; reg [1:0] _T_217_8; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_16; reg [1:0] _T_217_9; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_17; reg [1:0] _T_217_10; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_18; reg [1:0] _T_217_11; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_19; reg [1:0] _T_217_12; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_20; reg [1:0] _T_217_13; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_21; reg [1:0] _T_217_14; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_22; reg [1:0] _T_217_15; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.TinyConfig.fir@130063.4] reg [31:0] _RAND_23; wire [1:0] _GEN_13; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_14; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_15; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_16; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_17; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_18; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_19; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_20; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_21; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_22; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_23; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_24; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_25; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_26; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [1:0] _GEN_27; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] wire [15:0] _T_220; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@130067.4] wire _T_222; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130069.4] wire _T_223; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130070.4] wire _T_224; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130071.4] wire _T_225; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130072.4] wire _T_226; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130073.4] wire _T_227; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130074.4] wire _T_228; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130075.4] wire _T_229; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130076.4] wire _T_230; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130077.4] wire _T_231; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130078.4] wire _T_232; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130079.4] wire _T_233; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130080.4] wire _T_234; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130081.4] wire _T_235; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130082.4] wire _T_236; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130083.4] wire _T_237; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130084.4] wire _T_238; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@130085.4] wire _T_239; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130086.4] wire [1:0] _T_240; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130088.6] wire _T_243; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130093.4] wire [1:0] _T_244; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130095.6] wire _T_247; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130100.4] wire [1:0] _T_248; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130102.6] wire _T_251; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130107.4] wire [1:0] _T_252; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130109.6] wire _T_255; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130114.4] wire [1:0] _T_256; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130116.6] wire _T_259; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130121.4] wire [1:0] _T_260; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130123.6] wire _T_263; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130128.4] wire [1:0] _T_264; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130130.6] wire _T_267; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130135.4] wire [1:0] _T_268; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130137.6] wire _T_271; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130142.4] wire [1:0] _T_272; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130144.6] wire _T_275; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130149.4] wire [1:0] _T_276; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130151.6] wire _T_279; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130156.4] wire [1:0] _T_280; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130158.6] wire _T_283; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130163.4] wire [1:0] _T_284; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130165.6] wire _T_287; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130170.4] wire [1:0] _T_288; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130172.6] wire _T_291; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130177.4] wire [1:0] _T_292; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130179.6] wire _T_295; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130184.4] wire [1:0] _T_296; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130186.6] wire _T_299; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130191.4] wire [1:0] _T_300; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130193.6] Queue_49 Queue ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129696.4] .clock(Queue_clock), .reset(Queue_reset), .io_enq_ready(Queue_io_enq_ready), .io_enq_valid(Queue_io_enq_valid), .io_enq_bits_id(Queue_io_enq_bits_id), .io_enq_bits_addr(Queue_io_enq_bits_addr), .io_enq_bits_len(Queue_io_enq_bits_len), .io_enq_bits_size(Queue_io_enq_bits_size), .io_enq_bits_burst(Queue_io_enq_bits_burst), .io_deq_ready(Queue_io_deq_ready), .io_deq_valid(Queue_io_deq_valid), .io_deq_bits_id(Queue_io_deq_bits_id), .io_deq_bits_addr(Queue_io_deq_bits_addr), .io_deq_bits_len(Queue_io_deq_bits_len), .io_deq_bits_size(Queue_io_deq_bits_size), .io_deq_bits_burst(Queue_io_deq_bits_burst) ); Queue_49 Queue_1 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129824.4] .clock(Queue_1_clock), .reset(Queue_1_reset), .io_enq_ready(Queue_1_io_enq_ready), .io_enq_valid(Queue_1_io_enq_valid), .io_enq_bits_id(Queue_1_io_enq_bits_id), .io_enq_bits_addr(Queue_1_io_enq_bits_addr), .io_enq_bits_len(Queue_1_io_enq_bits_len), .io_enq_bits_size(Queue_1_io_enq_bits_size), .io_enq_bits_burst(Queue_1_io_enq_bits_burst), .io_deq_ready(Queue_1_io_deq_ready), .io_deq_valid(Queue_1_io_deq_valid), .io_deq_bits_id(Queue_1_io_deq_bits_id), .io_deq_bits_addr(Queue_1_io_deq_bits_addr), .io_deq_bits_len(Queue_1_io_deq_bits_len), .io_deq_bits_size(Queue_1_io_deq_bits_size), .io_deq_bits_burst(Queue_1_io_deq_bits_burst) ); Queue_17 Queue_2 ( // @[Decoupled.scala 294:21:freechips.rocketchip.system.TinyConfig.fir@129952.4] .clock(Queue_2_clock), .reset(Queue_2_reset), .io_enq_ready(Queue_2_io_enq_ready), .io_enq_valid(Queue_2_io_enq_valid), .io_enq_bits_data(Queue_2_io_enq_bits_data), .io_enq_bits_strb(Queue_2_io_enq_bits_strb), .io_enq_bits_last(Queue_2_io_enq_bits_last), .io_deq_ready(Queue_2_io_deq_ready), .io_deq_valid(Queue_2_io_deq_valid), .io_deq_bits_data(Queue_2_io_deq_bits_data), .io_deq_bits_strb(Queue_2_io_deq_bits_strb), .io_deq_bits_last(Queue_2_io_deq_bits_last) ); assign _T_2_bits_len = Queue_io_deq_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129717.4] assign _T_7 = _T_4 ? _T_6 : _T_2_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@129727.4] assign _T_2_bits_addr = Queue_io_deq_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129718.4] assign _T_8 = _T_4 ? _T_5 : _T_2_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@129728.4] assign _T_2_bits_burst = Queue_io_deq_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129715.4] assign _T_50 = _T_2_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@129770.4] assign _T_2_bits_size = Queue_io_deq_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129716.4] assign _T_59 = 16'h1 << _T_2_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@129779.4] assign _GEN_48 = {{4'd0}, _T_8}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129780.4] assign _T_61 = _GEN_48 + _T_59; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129781.4] assign _T_62 = {_T_2_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@129782.4] assign _GEN_49 = {{7'd0}, _T_62}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129783.4] assign _T_63 = _GEN_49 << _T_2_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129783.4] assign _T_64 = _T_63[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@129784.4] assign _T_66 = _T_2_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@129788.4] assign _GEN_50 = {{1'd0}, _T_64}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129790.6] assign _T_67 = _T_61 & _GEN_50; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129790.6] assign _T_68 = ~ _T_2_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@129791.6] assign _GEN_51 = {{3'd0}, _T_68}; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129792.6] assign _T_69 = _GEN_51 | _T_64; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129792.6] assign _T_70 = ~ _T_69; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@129793.6] assign _GEN_52 = {{1'd0}, _T_70}; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129794.6] assign _T_71 = _T_67 | _GEN_52; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129794.6] assign _GEN_0 = _T_66 ? _T_71 : _T_61; // @[Fragmenter.scala 101:59:freechips.rocketchip.system.TinyConfig.fir@129789.4] assign _GEN_1 = _T_50 ? {{4'd0}, _T_2_bits_addr} : _GEN_0; // @[Fragmenter.scala 104:60:freechips.rocketchip.system.TinyConfig.fir@129798.4] assign _T_73 = 8'h0 == _T_7; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@129801.4] assign _T_75 = ~ _T_8; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@129807.4] assign _T_77 = 9'h3 << _T_2_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@129809.4] assign _T_78 = _T_77[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@129810.4] assign _T_79 = ~ _T_78; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@129811.4] assign _GEN_53 = {{10'd0}, _T_79}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129812.4] assign _T_80 = _T_75 | _GEN_53; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129812.4] assign _T_2_valid = Queue_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129710.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129720.4] assign _T_82 = auto_out_ar_ready & _T_2_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129815.4] assign _T_83 = _T_73 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@129817.6] assign _GEN_54 = {{1'd0}, _T_7}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129820.6] assign _T_85 = _GEN_54 - 9'h1; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129821.6] assign _GEN_3 = _T_82 ? _GEN_1 : {{4'd0}, _T_5}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129816.4] assign _GEN_4 = _T_82 ? _T_85 : {{1'd0}, _T_6}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129816.4] assign _T_86_bits_len = Queue_1_io_deq_bits_len; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129845.4] assign _T_91 = _T_88 ? _T_90 : _T_86_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.TinyConfig.fir@129855.4] assign _T_86_bits_addr = Queue_1_io_deq_bits_addr; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129846.4] assign _T_92 = _T_88 ? _T_89 : _T_86_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.TinyConfig.fir@129856.4] assign _T_86_bits_burst = Queue_1_io_deq_bits_burst; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129843.4] assign _T_134 = _T_86_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.TinyConfig.fir@129898.4] assign _T_86_bits_size = Queue_1_io_deq_bits_size; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129844.4] assign _T_143 = 16'h1 << _T_86_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.TinyConfig.fir@129907.4] assign _GEN_59 = {{4'd0}, _T_92}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129908.4] assign _T_145 = _GEN_59 + _T_143; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.TinyConfig.fir@129909.4] assign _T_146 = {_T_86_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.TinyConfig.fir@129910.4] assign _GEN_60 = {{7'd0}, _T_146}; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129911.4] assign _T_147 = _GEN_60 << _T_86_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.TinyConfig.fir@129911.4] assign _T_148 = _T_147[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.TinyConfig.fir@129912.4] assign _T_150 = _T_86_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.TinyConfig.fir@129916.4] assign _GEN_61 = {{1'd0}, _T_148}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129918.6] assign _T_151 = _T_145 & _GEN_61; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.TinyConfig.fir@129918.6] assign _T_152 = ~ _T_86_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.TinyConfig.fir@129919.6] assign _GEN_62 = {{3'd0}, _T_152}; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129920.6] assign _T_153 = _GEN_62 | _T_148; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.TinyConfig.fir@129920.6] assign _T_154 = ~ _T_153; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.TinyConfig.fir@129921.6] assign _GEN_63 = {{1'd0}, _T_154}; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129922.6] assign _T_155 = _T_151 | _GEN_63; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.TinyConfig.fir@129922.6] assign _GEN_5 = _T_150 ? _T_155 : _T_145; // @[Fragmenter.scala 101:59:freechips.rocketchip.system.TinyConfig.fir@129917.4] assign _GEN_6 = _T_134 ? {{4'd0}, _T_86_bits_addr} : _GEN_5; // @[Fragmenter.scala 104:60:freechips.rocketchip.system.TinyConfig.fir@129926.4] assign _T_157 = 8'h0 == _T_91; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.TinyConfig.fir@129929.4] assign _T_183 = _T_182 == 9'h0; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.TinyConfig.fir@129993.4] assign _T_178 = _T_183 | _T_171; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.TinyConfig.fir@129984.4] assign _T_179 = auto_out_aw_ready & _T_178; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.TinyConfig.fir@129985.4] assign _T_159 = ~ _T_92; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.TinyConfig.fir@129935.4] assign _T_161 = 9'h3 << _T_86_bits_size; // @[package.scala 189:77:freechips.rocketchip.system.TinyConfig.fir@129937.4] assign _T_162 = _T_161[1:0]; // @[package.scala 189:82:freechips.rocketchip.system.TinyConfig.fir@129938.4] assign _T_163 = ~ _T_162; // @[package.scala 189:46:freechips.rocketchip.system.TinyConfig.fir@129939.4] assign _GEN_64 = {{10'd0}, _T_163}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129940.4] assign _T_164 = _T_159 | _GEN_64; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.TinyConfig.fir@129940.4] assign _T_86_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129838.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129848.4] assign _T_166 = _T_179 & _T_86_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129943.4] assign _T_167 = _T_157 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.TinyConfig.fir@129945.6] assign _GEN_65 = {{1'd0}, _T_91}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129948.6] assign _T_169 = _GEN_65 - 9'h1; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.TinyConfig.fir@129949.6] assign _GEN_8 = _T_166 ? _GEN_6 : {{4'd0}, _T_89}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129944.4] assign _GEN_9 = _T_166 ? _T_169 : {{1'd0}, _T_90}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.TinyConfig.fir@129944.4] assign _T_180 = _T_171 == 1'h0; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.TinyConfig.fir@129987.4] assign _T_181 = _T_86_valid & _T_180; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.TinyConfig.fir@129988.4] assign _T_174 = _T_181 & _T_183; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.TinyConfig.fir@129973.4] assign _T_177 = _T_86_valid & _T_178; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.TinyConfig.fir@129982.4] assign _T_175 = auto_out_aw_ready & _T_177; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129977.4] assign _T_184 = _T_181 ? 9'h1 : 9'h0; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.TinyConfig.fir@129994.4] assign _T_185 = _T_183 ? _T_184 : _T_182; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.TinyConfig.fir@129995.4] assign _T_186 = _T_185 == 9'h1; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.TinyConfig.fir@129996.4] assign _T_170_valid = Queue_2_io_deq_valid; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129960.4 Decoupled.scala 317:15:freechips.rocketchip.system.TinyConfig.fir@129964.4] assign _T_197 = _T_183 == 1'h0; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.TinyConfig.fir@130013.4] assign _T_198 = _T_197 | _T_181; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.TinyConfig.fir@130014.4] assign _T_199 = _T_170_valid & _T_198; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.TinyConfig.fir@130015.4] assign _T_187 = auto_out_w_ready & _T_199; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@129997.4] assign _GEN_66 = {{8'd0}, _T_187}; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@129998.4] assign _T_189 = _T_185 - _GEN_66; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.TinyConfig.fir@129999.4] assign _T_191 = _T_187 == 1'h0; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.TinyConfig.fir@130002.4] assign _T_192 = _T_185 != 9'h0; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.TinyConfig.fir@130003.4] assign _T_193 = _T_191 | _T_192; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.TinyConfig.fir@130004.4] assign _T_195 = _T_193 | reset; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130006.4] assign _T_196 = _T_195 == 1'h0; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130007.4] assign _T_203 = _T_199 == 1'h0; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.TinyConfig.fir@130023.4] assign _T_170_bits_last = Queue_2_io_deq_bits_last; // @[Decoupled.scala 315:19:freechips.rocketchip.system.TinyConfig.fir@129960.4 Decoupled.scala 316:14:freechips.rocketchip.system.TinyConfig.fir@129961.4] assign _T_204 = _T_170_bits_last == 1'h0; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.TinyConfig.fir@130024.4] assign _T_205 = _T_203 | _T_204; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.TinyConfig.fir@130025.4] assign _T_206 = _T_205 | _T_186; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.TinyConfig.fir@130026.4] assign _T_208 = _T_206 | reset; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130028.4] assign _T_209 = _T_208 == 1'h0; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130029.4] assign _T_214 = auto_out_b_bits_user == 1'h0; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.TinyConfig.fir@130042.4] assign _T_215 = auto_in_b_ready | _T_214; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.TinyConfig.fir@130043.4] assign _GEN_13 = 4'h1 == auto_out_b_bits_id ? _T_217_1 : _T_217_0; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_14 = 4'h2 == auto_out_b_bits_id ? _T_217_2 : _GEN_13; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_15 = 4'h3 == auto_out_b_bits_id ? _T_217_3 : _GEN_14; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_16 = 4'h4 == auto_out_b_bits_id ? _T_217_4 : _GEN_15; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_17 = 4'h5 == auto_out_b_bits_id ? _T_217_5 : _GEN_16; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_18 = 4'h6 == auto_out_b_bits_id ? _T_217_6 : _GEN_17; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_19 = 4'h7 == auto_out_b_bits_id ? _T_217_7 : _GEN_18; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_20 = 4'h8 == auto_out_b_bits_id ? _T_217_8 : _GEN_19; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_21 = 4'h9 == auto_out_b_bits_id ? _T_217_9 : _GEN_20; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_22 = 4'ha == auto_out_b_bits_id ? _T_217_10 : _GEN_21; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_23 = 4'hb == auto_out_b_bits_id ? _T_217_11 : _GEN_22; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_24 = 4'hc == auto_out_b_bits_id ? _T_217_12 : _GEN_23; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_25 = 4'hd == auto_out_b_bits_id ? _T_217_13 : _GEN_24; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_26 = 4'he == auto_out_b_bits_id ? _T_217_14 : _GEN_25; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _GEN_27 = 4'hf == auto_out_b_bits_id ? _T_217_15 : _GEN_26; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.TinyConfig.fir@130064.4] assign _T_220 = 16'h1 << auto_out_b_bits_id; // @[OneHot.scala 65:12:freechips.rocketchip.system.TinyConfig.fir@130067.4] assign _T_222 = _T_220[0]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130069.4] assign _T_223 = _T_220[1]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130070.4] assign _T_224 = _T_220[2]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130071.4] assign _T_225 = _T_220[3]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130072.4] assign _T_226 = _T_220[4]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130073.4] assign _T_227 = _T_220[5]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130074.4] assign _T_228 = _T_220[6]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130075.4] assign _T_229 = _T_220[7]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130076.4] assign _T_230 = _T_220[8]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130077.4] assign _T_231 = _T_220[9]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130078.4] assign _T_232 = _T_220[10]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130079.4] assign _T_233 = _T_220[11]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130080.4] assign _T_234 = _T_220[12]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130081.4] assign _T_235 = _T_220[13]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130082.4] assign _T_236 = _T_220[14]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130083.4] assign _T_237 = _T_220[15]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.TinyConfig.fir@130084.4] assign _T_238 = _T_215 & auto_out_b_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.TinyConfig.fir@130085.4] assign _T_239 = _T_222 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130086.4] assign _T_240 = _T_217_0 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130088.6] assign _T_243 = _T_223 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130093.4] assign _T_244 = _T_217_1 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130095.6] assign _T_247 = _T_224 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130100.4] assign _T_248 = _T_217_2 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130102.6] assign _T_251 = _T_225 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130107.4] assign _T_252 = _T_217_3 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130109.6] assign _T_255 = _T_226 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130114.4] assign _T_256 = _T_217_4 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130116.6] assign _T_259 = _T_227 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130121.4] assign _T_260 = _T_217_5 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130123.6] assign _T_263 = _T_228 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130128.4] assign _T_264 = _T_217_6 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130130.6] assign _T_267 = _T_229 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130135.4] assign _T_268 = _T_217_7 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130137.6] assign _T_271 = _T_230 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130142.4] assign _T_272 = _T_217_8 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130144.6] assign _T_275 = _T_231 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130149.4] assign _T_276 = _T_217_9 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130151.6] assign _T_279 = _T_232 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130156.4] assign _T_280 = _T_217_10 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130158.6] assign _T_283 = _T_233 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130163.4] assign _T_284 = _T_217_11 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130165.6] assign _T_287 = _T_234 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130170.4] assign _T_288 = _T_217_12 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130172.6] assign _T_291 = _T_235 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130177.4] assign _T_292 = _T_217_13 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130179.6] assign _T_295 = _T_236 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130184.4] assign _T_296 = _T_217_14 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130186.6] assign _T_299 = _T_237 & _T_238; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.TinyConfig.fir@130191.4] assign _T_300 = _T_217_15 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.TinyConfig.fir@130193.6] assign auto_in_aw_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_w_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_b_valid = auto_out_b_valid & auto_out_b_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_b_bits_resp = auto_out_b_bits_resp | _GEN_27; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_ar_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_in_r_bits_last = auto_out_r_bits_last & auto_out_r_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.TinyConfig.fir@129695.4] assign auto_out_aw_valid = _T_86_valid & _T_178; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_aw_bits_addr = ~ _T_164; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_aw_bits_user = 8'h0 == _T_91; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_w_valid = _T_170_valid & _T_198; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_w_bits_data = Queue_2_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_w_bits_strb = Queue_2_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_w_bits_last = _T_185 == 9'h1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_b_ready = auto_in_b_ready | _T_214; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_ar_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_ar_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_ar_bits_addr = ~ _T_80; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_ar_bits_user = 8'h0 == _T_7; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@129694.4] assign Queue_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129697.4] assign Queue_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129698.4] assign Queue_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129699.4] assign Queue_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129708.4] assign Queue_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129707.4] assign Queue_io_enq_bits_len = auto_in_ar_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129706.4] assign Queue_io_enq_bits_size = auto_in_ar_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129705.4] assign Queue_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129704.4] assign Queue_io_deq_ready = auto_out_ar_ready & _T_73; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129721.4] assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129825.4] assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129826.4] assign Queue_1_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129827.4] assign Queue_1_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129836.4] assign Queue_1_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129835.4] assign Queue_1_io_enq_bits_len = auto_in_aw_bits_len; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129834.4] assign Queue_1_io_enq_bits_size = auto_in_aw_bits_size; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129833.4] assign Queue_1_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129832.4] assign Queue_1_io_deq_ready = _T_179 & _T_157; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129849.4] assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@129953.4] assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@129954.4] assign Queue_2_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 295:22:freechips.rocketchip.system.TinyConfig.fir@129955.4] assign Queue_2_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129958.4] assign Queue_2_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129957.4] assign Queue_2_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 296:21:freechips.rocketchip.system.TinyConfig.fir@129956.4] assign Queue_2_io_deq_ready = auto_out_w_ready & _T_198; // @[Decoupled.scala 318:15:freechips.rocketchip.system.TinyConfig.fir@129965.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE `endif `ifdef RANDOMIZE_REG_INIT `define RANDOMIZE `endif `ifdef RANDOMIZE_MEM_INIT `define RANDOMIZE `endif `ifndef RANDOM `define RANDOM $random `endif `ifdef RANDOMIZE_MEM_INIT integer initvar; `endif initial begin `ifdef RANDOMIZE `ifdef INIT_RANDOM `INIT_RANDOM `endif `ifndef VERILATOR `ifdef RANDOMIZE_DELAY #`RANDOMIZE_DELAY begin end `else #0.002 begin end `endif `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; _T_4 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; _T_5 = _RAND_1[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; _T_6 = _RAND_2[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; _T_88 = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_4 = {1{`RANDOM}}; _T_89 = _RAND_4[11:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_5 = {1{`RANDOM}}; _T_90 = _RAND_5[7:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_6 = {1{`RANDOM}}; _T_182 = _RAND_6[8:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_7 = {1{`RANDOM}}; _T_171 = _RAND_7[0:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_8 = {1{`RANDOM}}; _T_217_0 = _RAND_8[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_9 = {1{`RANDOM}}; _T_217_1 = _RAND_9[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_10 = {1{`RANDOM}}; _T_217_2 = _RAND_10[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_11 = {1{`RANDOM}}; _T_217_3 = _RAND_11[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_12 = {1{`RANDOM}}; _T_217_4 = _RAND_12[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_13 = {1{`RANDOM}}; _T_217_5 = _RAND_13[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_14 = {1{`RANDOM}}; _T_217_6 = _RAND_14[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_15 = {1{`RANDOM}}; _T_217_7 = _RAND_15[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_16 = {1{`RANDOM}}; _T_217_8 = _RAND_16[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_17 = {1{`RANDOM}}; _T_217_9 = _RAND_17[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_18 = {1{`RANDOM}}; _T_217_10 = _RAND_18[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_19 = {1{`RANDOM}}; _T_217_11 = _RAND_19[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_20 = {1{`RANDOM}}; _T_217_12 = _RAND_20[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_21 = {1{`RANDOM}}; _T_217_13 = _RAND_21[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_22 = {1{`RANDOM}}; _T_217_14 = _RAND_22[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_23 = {1{`RANDOM}}; _T_217_15 = _RAND_23[1:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end always @(posedge clock) begin if (reset) begin _T_4 <= 1'h0; end else begin if (_T_82) begin _T_4 <= _T_83; end end _T_5 <= _GEN_3[11:0]; _T_6 <= _GEN_4[7:0]; if (reset) begin _T_88 <= 1'h0; end else begin if (_T_166) begin _T_88 <= _T_167; end end _T_89 <= _GEN_8[11:0]; _T_90 <= _GEN_9[7:0]; if (reset) begin _T_182 <= 9'h0; end else begin _T_182 <= _T_189; end if (reset) begin _T_171 <= 1'h0; end else begin if (_T_175) begin _T_171 <= 1'h0; end else begin if (_T_174) begin _T_171 <= 1'h1; end end end if (reset) begin _T_217_0 <= 2'h0; end else begin if (_T_239) begin if (auto_out_b_bits_user) begin _T_217_0 <= 2'h0; end else begin _T_217_0 <= _T_240; end end end if (reset) begin _T_217_1 <= 2'h0; end else begin if (_T_243) begin if (auto_out_b_bits_user) begin _T_217_1 <= 2'h0; end else begin _T_217_1 <= _T_244; end end end if (reset) begin _T_217_2 <= 2'h0; end else begin if (_T_247) begin if (auto_out_b_bits_user) begin _T_217_2 <= 2'h0; end else begin _T_217_2 <= _T_248; end end end if (reset) begin _T_217_3 <= 2'h0; end else begin if (_T_251) begin if (auto_out_b_bits_user) begin _T_217_3 <= 2'h0; end else begin _T_217_3 <= _T_252; end end end if (reset) begin _T_217_4 <= 2'h0; end else begin if (_T_255) begin if (auto_out_b_bits_user) begin _T_217_4 <= 2'h0; end else begin _T_217_4 <= _T_256; end end end if (reset) begin _T_217_5 <= 2'h0; end else begin if (_T_259) begin if (auto_out_b_bits_user) begin _T_217_5 <= 2'h0; end else begin _T_217_5 <= _T_260; end end end if (reset) begin _T_217_6 <= 2'h0; end else begin if (_T_263) begin if (auto_out_b_bits_user) begin _T_217_6 <= 2'h0; end else begin _T_217_6 <= _T_264; end end end if (reset) begin _T_217_7 <= 2'h0; end else begin if (_T_267) begin if (auto_out_b_bits_user) begin _T_217_7 <= 2'h0; end else begin _T_217_7 <= _T_268; end end end if (reset) begin _T_217_8 <= 2'h0; end else begin if (_T_271) begin if (auto_out_b_bits_user) begin _T_217_8 <= 2'h0; end else begin _T_217_8 <= _T_272; end end end if (reset) begin _T_217_9 <= 2'h0; end else begin if (_T_275) begin if (auto_out_b_bits_user) begin _T_217_9 <= 2'h0; end else begin _T_217_9 <= _T_276; end end end if (reset) begin _T_217_10 <= 2'h0; end else begin if (_T_279) begin if (auto_out_b_bits_user) begin _T_217_10 <= 2'h0; end else begin _T_217_10 <= _T_280; end end end if (reset) begin _T_217_11 <= 2'h0; end else begin if (_T_283) begin if (auto_out_b_bits_user) begin _T_217_11 <= 2'h0; end else begin _T_217_11 <= _T_284; end end end if (reset) begin _T_217_12 <= 2'h0; end else begin if (_T_287) begin if (auto_out_b_bits_user) begin _T_217_12 <= 2'h0; end else begin _T_217_12 <= _T_288; end end end if (reset) begin _T_217_13 <= 2'h0; end else begin if (_T_291) begin if (auto_out_b_bits_user) begin _T_217_13 <= 2'h0; end else begin _T_217_13 <= _T_292; end end end if (reset) begin _T_217_14 <= 2'h0; end else begin if (_T_295) begin if (auto_out_b_bits_user) begin _T_217_14 <= 2'h0; end else begin _T_217_14 <= _T_296; end end end if (reset) begin _T_217_15 <= 2'h0; end else begin if (_T_299) begin if (auto_out_b_bits_user) begin _T_217_15 <= 2'h0; end else begin _T_217_15 <= _T_300; end end end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_196) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:167 assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible\n"); // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130009.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_196) begin $fatal; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.TinyConfig.fir@130010.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_209) begin $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:176 assert (!out.w.valid || !in_w.bits.last || w_last)\n"); // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130031.6] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_209) begin $fatal; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.TinyConfig.fir@130032.6] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module SimAXIMem( // @[:freechips.rocketchip.system.TinyConfig.fir@130198.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@130199.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@130200.4] output io_axi4_0_aw_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_aw_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [3:0] io_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [11:0] io_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [7:0] io_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [2:0] io_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [1:0] io_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output io_axi4_0_w_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_w_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [31:0] io_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [3:0] io_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_b_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output io_axi4_0_b_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output [3:0] io_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output [1:0] io_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output io_axi4_0_ar_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_ar_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [3:0] io_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [11:0] io_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [7:0] io_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [2:0] io_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input [1:0] io_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] input io_axi4_0_r_ready, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output io_axi4_0_r_valid, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output [3:0] io_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output [31:0] io_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output [1:0] io_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] output io_axi4_0_r_bits_last // @[:freechips.rocketchip.system.TinyConfig.fir@130202.4] ); wire srams_clock; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_reset; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_aw_ready; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_aw_valid; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [3:0] srams_auto_in_aw_bits_id; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [11:0] srams_auto_in_aw_bits_addr; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_aw_bits_user; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_w_ready; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_w_valid; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [31:0] srams_auto_in_w_bits_data; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [3:0] srams_auto_in_w_bits_strb; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_b_ready; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_b_valid; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [3:0] srams_auto_in_b_bits_id; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [1:0] srams_auto_in_b_bits_resp; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_b_bits_user; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_ar_ready; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_ar_valid; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [3:0] srams_auto_in_ar_bits_id; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [11:0] srams_auto_in_ar_bits_addr; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_ar_bits_user; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_r_ready; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_r_valid; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [3:0] srams_auto_in_r_bits_id; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [31:0] srams_auto_in_r_bits_data; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire [1:0] srams_auto_in_r_bits_resp; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire srams_auto_in_r_bits_user; // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] wire axi4xbar_clock; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_reset; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_aw_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_aw_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_in_aw_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [11:0] axi4xbar_auto_in_aw_bits_addr; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [7:0] axi4xbar_auto_in_aw_bits_len; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [2:0] axi4xbar_auto_in_aw_bits_size; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_in_aw_bits_burst; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_w_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_w_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [31:0] axi4xbar_auto_in_w_bits_data; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_in_w_bits_strb; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_w_bits_last; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_b_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_b_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_in_b_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_in_b_bits_resp; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_ar_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_ar_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_in_ar_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [11:0] axi4xbar_auto_in_ar_bits_addr; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [7:0] axi4xbar_auto_in_ar_bits_len; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [2:0] axi4xbar_auto_in_ar_bits_size; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_in_ar_bits_burst; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_r_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_r_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_in_r_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [31:0] axi4xbar_auto_in_r_bits_data; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_in_r_bits_resp; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_in_r_bits_last; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_aw_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_aw_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_out_aw_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [11:0] axi4xbar_auto_out_aw_bits_addr; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [7:0] axi4xbar_auto_out_aw_bits_len; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [2:0] axi4xbar_auto_out_aw_bits_size; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_out_aw_bits_burst; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_w_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_w_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [31:0] axi4xbar_auto_out_w_bits_data; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_out_w_bits_strb; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_w_bits_last; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_b_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_b_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_out_b_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_out_b_bits_resp; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_ar_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_ar_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_out_ar_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [11:0] axi4xbar_auto_out_ar_bits_addr; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [7:0] axi4xbar_auto_out_ar_bits_len; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [2:0] axi4xbar_auto_out_ar_bits_size; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_out_ar_bits_burst; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_r_ready; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_r_valid; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [3:0] axi4xbar_auto_out_r_bits_id; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [31:0] axi4xbar_auto_out_r_bits_data; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire [1:0] axi4xbar_auto_out_r_bits_resp; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4xbar_auto_out_r_bits_last; // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] wire axi4buf_clock; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_reset; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_in_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [11:0] axi4buf_auto_in_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_aw_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [31:0] axi4buf_auto_in_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_in_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_w_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_in_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [1:0] axi4buf_auto_in_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_b_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_in_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [11:0] axi4buf_auto_in_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_ar_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_in_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [31:0] axi4buf_auto_in_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [1:0] axi4buf_auto_in_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_r_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_in_r_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_out_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [11:0] axi4buf_auto_out_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_aw_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [31:0] axi4buf_auto_out_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_out_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_out_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [1:0] axi4buf_auto_out_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_b_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_out_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [11:0] axi4buf_auto_out_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_ar_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [3:0] axi4buf_auto_out_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [31:0] axi4buf_auto_out_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire [1:0] axi4buf_auto_out_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4buf_auto_out_r_bits_user; // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] wire axi4frag_clock; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_reset; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_in_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [11:0] axi4frag_auto_in_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [7:0] axi4frag_auto_in_aw_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [2:0] axi4frag_auto_in_aw_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_in_aw_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [31:0] axi4frag_auto_in_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_in_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_in_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_in_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_in_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [11:0] axi4frag_auto_in_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [7:0] axi4frag_auto_in_ar_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [2:0] axi4frag_auto_in_ar_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_in_ar_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_in_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [31:0] axi4frag_auto_in_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_in_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_in_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_out_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [11:0] axi4frag_auto_out_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_aw_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [31:0] axi4frag_auto_out_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_out_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_out_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_out_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_b_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_out_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [11:0] axi4frag_auto_out_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_ar_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [3:0] axi4frag_auto_out_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [31:0] axi4frag_auto_out_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire [1:0] axi4frag_auto_out_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_r_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] wire axi4frag_auto_out_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] AXI4RAM srams ( // @[Ports.scala 221:69:freechips.rocketchip.system.TinyConfig.fir@130208.4] .clock(srams_clock), .reset(srams_reset), .auto_in_aw_ready(srams_auto_in_aw_ready), .auto_in_aw_valid(srams_auto_in_aw_valid), .auto_in_aw_bits_id(srams_auto_in_aw_bits_id), .auto_in_aw_bits_addr(srams_auto_in_aw_bits_addr), .auto_in_aw_bits_user(srams_auto_in_aw_bits_user), .auto_in_w_ready(srams_auto_in_w_ready), .auto_in_w_valid(srams_auto_in_w_valid), .auto_in_w_bits_data(srams_auto_in_w_bits_data), .auto_in_w_bits_strb(srams_auto_in_w_bits_strb), .auto_in_b_ready(srams_auto_in_b_ready), .auto_in_b_valid(srams_auto_in_b_valid), .auto_in_b_bits_id(srams_auto_in_b_bits_id), .auto_in_b_bits_resp(srams_auto_in_b_bits_resp), .auto_in_b_bits_user(srams_auto_in_b_bits_user), .auto_in_ar_ready(srams_auto_in_ar_ready), .auto_in_ar_valid(srams_auto_in_ar_valid), .auto_in_ar_bits_id(srams_auto_in_ar_bits_id), .auto_in_ar_bits_addr(srams_auto_in_ar_bits_addr), .auto_in_ar_bits_user(srams_auto_in_ar_bits_user), .auto_in_r_ready(srams_auto_in_r_ready), .auto_in_r_valid(srams_auto_in_r_valid), .auto_in_r_bits_id(srams_auto_in_r_bits_id), .auto_in_r_bits_data(srams_auto_in_r_bits_data), .auto_in_r_bits_resp(srams_auto_in_r_bits_resp), .auto_in_r_bits_user(srams_auto_in_r_bits_user) ); AXI4Xbar axi4xbar ( // @[Xbar.scala 211:30:freechips.rocketchip.system.TinyConfig.fir@130214.4] .clock(axi4xbar_clock), .reset(axi4xbar_reset), .auto_in_aw_ready(axi4xbar_auto_in_aw_ready), .auto_in_aw_valid(axi4xbar_auto_in_aw_valid), .auto_in_aw_bits_id(axi4xbar_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4xbar_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4xbar_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4xbar_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4xbar_auto_in_aw_bits_burst), .auto_in_w_ready(axi4xbar_auto_in_w_ready), .auto_in_w_valid(axi4xbar_auto_in_w_valid), .auto_in_w_bits_data(axi4xbar_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4xbar_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4xbar_auto_in_w_bits_last), .auto_in_b_ready(axi4xbar_auto_in_b_ready), .auto_in_b_valid(axi4xbar_auto_in_b_valid), .auto_in_b_bits_id(axi4xbar_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4xbar_auto_in_b_bits_resp), .auto_in_ar_ready(axi4xbar_auto_in_ar_ready), .auto_in_ar_valid(axi4xbar_auto_in_ar_valid), .auto_in_ar_bits_id(axi4xbar_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4xbar_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4xbar_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4xbar_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4xbar_auto_in_ar_bits_burst), .auto_in_r_ready(axi4xbar_auto_in_r_ready), .auto_in_r_valid(axi4xbar_auto_in_r_valid), .auto_in_r_bits_id(axi4xbar_auto_in_r_bits_id), .auto_in_r_bits_data(axi4xbar_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4xbar_auto_in_r_bits_resp), .auto_in_r_bits_last(axi4xbar_auto_in_r_bits_last), .auto_out_aw_ready(axi4xbar_auto_out_aw_ready), .auto_out_aw_valid(axi4xbar_auto_out_aw_valid), .auto_out_aw_bits_id(axi4xbar_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4xbar_auto_out_aw_bits_addr), .auto_out_aw_bits_len(axi4xbar_auto_out_aw_bits_len), .auto_out_aw_bits_size(axi4xbar_auto_out_aw_bits_size), .auto_out_aw_bits_burst(axi4xbar_auto_out_aw_bits_burst), .auto_out_w_ready(axi4xbar_auto_out_w_ready), .auto_out_w_valid(axi4xbar_auto_out_w_valid), .auto_out_w_bits_data(axi4xbar_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4xbar_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4xbar_auto_out_w_bits_last), .auto_out_b_ready(axi4xbar_auto_out_b_ready), .auto_out_b_valid(axi4xbar_auto_out_b_valid), .auto_out_b_bits_id(axi4xbar_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4xbar_auto_out_b_bits_resp), .auto_out_ar_ready(axi4xbar_auto_out_ar_ready), .auto_out_ar_valid(axi4xbar_auto_out_ar_valid), .auto_out_ar_bits_id(axi4xbar_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4xbar_auto_out_ar_bits_addr), .auto_out_ar_bits_len(axi4xbar_auto_out_ar_bits_len), .auto_out_ar_bits_size(axi4xbar_auto_out_ar_bits_size), .auto_out_ar_bits_burst(axi4xbar_auto_out_ar_bits_burst), .auto_out_r_ready(axi4xbar_auto_out_r_ready), .auto_out_r_valid(axi4xbar_auto_out_r_valid), .auto_out_r_bits_id(axi4xbar_auto_out_r_bits_id), .auto_out_r_bits_data(axi4xbar_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4xbar_auto_out_r_bits_resp), .auto_out_r_bits_last(axi4xbar_auto_out_r_bits_last) ); AXI4Buffer_1 axi4buf ( // @[Buffer.scala 58:29:freechips.rocketchip.system.TinyConfig.fir@130220.4] .clock(axi4buf_clock), .reset(axi4buf_reset), .auto_in_aw_ready(axi4buf_auto_in_aw_ready), .auto_in_aw_valid(axi4buf_auto_in_aw_valid), .auto_in_aw_bits_id(axi4buf_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4buf_auto_in_aw_bits_addr), .auto_in_aw_bits_user(axi4buf_auto_in_aw_bits_user), .auto_in_w_ready(axi4buf_auto_in_w_ready), .auto_in_w_valid(axi4buf_auto_in_w_valid), .auto_in_w_bits_data(axi4buf_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4buf_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4buf_auto_in_w_bits_last), .auto_in_b_ready(axi4buf_auto_in_b_ready), .auto_in_b_valid(axi4buf_auto_in_b_valid), .auto_in_b_bits_id(axi4buf_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4buf_auto_in_b_bits_resp), .auto_in_b_bits_user(axi4buf_auto_in_b_bits_user), .auto_in_ar_ready(axi4buf_auto_in_ar_ready), .auto_in_ar_valid(axi4buf_auto_in_ar_valid), .auto_in_ar_bits_id(axi4buf_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4buf_auto_in_ar_bits_addr), .auto_in_ar_bits_user(axi4buf_auto_in_ar_bits_user), .auto_in_r_ready(axi4buf_auto_in_r_ready), .auto_in_r_valid(axi4buf_auto_in_r_valid), .auto_in_r_bits_id(axi4buf_auto_in_r_bits_id), .auto_in_r_bits_data(axi4buf_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4buf_auto_in_r_bits_resp), .auto_in_r_bits_user(axi4buf_auto_in_r_bits_user), .auto_in_r_bits_last(axi4buf_auto_in_r_bits_last), .auto_out_aw_ready(axi4buf_auto_out_aw_ready), .auto_out_aw_valid(axi4buf_auto_out_aw_valid), .auto_out_aw_bits_id(axi4buf_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4buf_auto_out_aw_bits_addr), .auto_out_aw_bits_user(axi4buf_auto_out_aw_bits_user), .auto_out_w_ready(axi4buf_auto_out_w_ready), .auto_out_w_valid(axi4buf_auto_out_w_valid), .auto_out_w_bits_data(axi4buf_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4buf_auto_out_w_bits_strb), .auto_out_b_ready(axi4buf_auto_out_b_ready), .auto_out_b_valid(axi4buf_auto_out_b_valid), .auto_out_b_bits_id(axi4buf_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4buf_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4buf_auto_out_b_bits_user), .auto_out_ar_ready(axi4buf_auto_out_ar_ready), .auto_out_ar_valid(axi4buf_auto_out_ar_valid), .auto_out_ar_bits_id(axi4buf_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4buf_auto_out_ar_bits_addr), .auto_out_ar_bits_user(axi4buf_auto_out_ar_bits_user), .auto_out_r_ready(axi4buf_auto_out_r_ready), .auto_out_r_valid(axi4buf_auto_out_r_valid), .auto_out_r_bits_id(axi4buf_auto_out_r_bits_id), .auto_out_r_bits_data(axi4buf_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4buf_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4buf_auto_out_r_bits_user) ); AXI4Fragmenter_1 axi4frag ( // @[Fragmenter.scala 205:30:freechips.rocketchip.system.TinyConfig.fir@130226.4] .clock(axi4frag_clock), .reset(axi4frag_reset), .auto_in_aw_ready(axi4frag_auto_in_aw_ready), .auto_in_aw_valid(axi4frag_auto_in_aw_valid), .auto_in_aw_bits_id(axi4frag_auto_in_aw_bits_id), .auto_in_aw_bits_addr(axi4frag_auto_in_aw_bits_addr), .auto_in_aw_bits_len(axi4frag_auto_in_aw_bits_len), .auto_in_aw_bits_size(axi4frag_auto_in_aw_bits_size), .auto_in_aw_bits_burst(axi4frag_auto_in_aw_bits_burst), .auto_in_w_ready(axi4frag_auto_in_w_ready), .auto_in_w_valid(axi4frag_auto_in_w_valid), .auto_in_w_bits_data(axi4frag_auto_in_w_bits_data), .auto_in_w_bits_strb(axi4frag_auto_in_w_bits_strb), .auto_in_w_bits_last(axi4frag_auto_in_w_bits_last), .auto_in_b_ready(axi4frag_auto_in_b_ready), .auto_in_b_valid(axi4frag_auto_in_b_valid), .auto_in_b_bits_id(axi4frag_auto_in_b_bits_id), .auto_in_b_bits_resp(axi4frag_auto_in_b_bits_resp), .auto_in_ar_ready(axi4frag_auto_in_ar_ready), .auto_in_ar_valid(axi4frag_auto_in_ar_valid), .auto_in_ar_bits_id(axi4frag_auto_in_ar_bits_id), .auto_in_ar_bits_addr(axi4frag_auto_in_ar_bits_addr), .auto_in_ar_bits_len(axi4frag_auto_in_ar_bits_len), .auto_in_ar_bits_size(axi4frag_auto_in_ar_bits_size), .auto_in_ar_bits_burst(axi4frag_auto_in_ar_bits_burst), .auto_in_r_ready(axi4frag_auto_in_r_ready), .auto_in_r_valid(axi4frag_auto_in_r_valid), .auto_in_r_bits_id(axi4frag_auto_in_r_bits_id), .auto_in_r_bits_data(axi4frag_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4frag_auto_in_r_bits_resp), .auto_in_r_bits_last(axi4frag_auto_in_r_bits_last), .auto_out_aw_ready(axi4frag_auto_out_aw_ready), .auto_out_aw_valid(axi4frag_auto_out_aw_valid), .auto_out_aw_bits_id(axi4frag_auto_out_aw_bits_id), .auto_out_aw_bits_addr(axi4frag_auto_out_aw_bits_addr), .auto_out_aw_bits_user(axi4frag_auto_out_aw_bits_user), .auto_out_w_ready(axi4frag_auto_out_w_ready), .auto_out_w_valid(axi4frag_auto_out_w_valid), .auto_out_w_bits_data(axi4frag_auto_out_w_bits_data), .auto_out_w_bits_strb(axi4frag_auto_out_w_bits_strb), .auto_out_w_bits_last(axi4frag_auto_out_w_bits_last), .auto_out_b_ready(axi4frag_auto_out_b_ready), .auto_out_b_valid(axi4frag_auto_out_b_valid), .auto_out_b_bits_id(axi4frag_auto_out_b_bits_id), .auto_out_b_bits_resp(axi4frag_auto_out_b_bits_resp), .auto_out_b_bits_user(axi4frag_auto_out_b_bits_user), .auto_out_ar_ready(axi4frag_auto_out_ar_ready), .auto_out_ar_valid(axi4frag_auto_out_ar_valid), .auto_out_ar_bits_id(axi4frag_auto_out_ar_bits_id), .auto_out_ar_bits_addr(axi4frag_auto_out_ar_bits_addr), .auto_out_ar_bits_user(axi4frag_auto_out_ar_bits_user), .auto_out_r_ready(axi4frag_auto_out_r_ready), .auto_out_r_valid(axi4frag_auto_out_r_valid), .auto_out_r_bits_id(axi4frag_auto_out_r_bits_id), .auto_out_r_bits_data(axi4frag_auto_out_r_bits_data), .auto_out_r_bits_resp(axi4frag_auto_out_r_bits_resp), .auto_out_r_bits_user(axi4frag_auto_out_r_bits_user), .auto_out_r_bits_last(axi4frag_auto_out_r_bits_last) ); assign io_axi4_0_aw_ready = axi4xbar_auto_in_aw_ready; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_w_ready = axi4xbar_auto_in_w_ready; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_b_valid = axi4xbar_auto_in_b_valid; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_b_bits_id = axi4xbar_auto_in_b_bits_id; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_b_bits_resp = axi4xbar_auto_in_b_bits_resp; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_ar_ready = axi4xbar_auto_in_ar_ready; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_r_valid = axi4xbar_auto_in_r_valid; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_r_bits_id = axi4xbar_auto_in_r_bits_id; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_r_bits_data = axi4xbar_auto_in_r_bits_data; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_r_bits_resp = axi4xbar_auto_in_r_bits_resp; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign io_axi4_0_r_bits_last = axi4xbar_auto_in_r_bits_last; // @[Ports.scala 228:71:freechips.rocketchip.system.TinyConfig.fir@130238.4] assign srams_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130212.4] assign srams_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@130213.4] assign srams_auto_in_aw_valid = axi4buf_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_aw_bits_id = axi4buf_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_aw_bits_addr = axi4buf_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_aw_bits_user = axi4buf_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_w_valid = axi4buf_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_w_bits_data = axi4buf_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_w_bits_strb = axi4buf_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_b_ready = axi4buf_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_ar_valid = axi4buf_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_ar_bits_id = axi4buf_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_ar_bits_addr = axi4buf_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_ar_bits_user = axi4buf_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign srams_auto_in_r_ready = axi4buf_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4xbar_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130218.4] assign axi4xbar_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@130219.4] assign axi4xbar_auto_in_aw_valid = io_axi4_0_aw_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_aw_bits_id = io_axi4_0_aw_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_aw_bits_addr = io_axi4_0_aw_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_aw_bits_len = io_axi4_0_aw_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_aw_bits_size = io_axi4_0_aw_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_aw_bits_burst = io_axi4_0_aw_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_w_valid = io_axi4_0_w_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_w_bits_data = io_axi4_0_w_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_w_bits_strb = io_axi4_0_w_bits_strb; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_w_bits_last = io_axi4_0_w_bits_last; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_b_ready = io_axi4_0_b_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_valid = io_axi4_0_ar_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_bits_id = io_axi4_0_ar_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_bits_addr = io_axi4_0_ar_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_bits_len = io_axi4_0_ar_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_bits_size = io_axi4_0_ar_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_ar_bits_burst = io_axi4_0_ar_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_in_r_ready = io_axi4_0_r_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130234.4] assign axi4xbar_auto_out_aw_ready = axi4frag_auto_in_aw_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_w_ready = axi4frag_auto_in_w_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_b_valid = axi4frag_auto_in_b_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_b_bits_id = axi4frag_auto_in_b_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_b_bits_resp = axi4frag_auto_in_b_bits_resp; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_ar_ready = axi4frag_auto_in_ar_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_r_valid = axi4frag_auto_in_r_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_r_bits_id = axi4frag_auto_in_r_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_r_bits_data = axi4frag_auto_in_r_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_r_bits_resp = axi4frag_auto_in_r_bits_resp; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4xbar_auto_out_r_bits_last = axi4frag_auto_in_r_bits_last; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4buf_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130224.4] assign axi4buf_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@130225.4] assign axi4buf_auto_in_aw_valid = axi4frag_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_aw_bits_id = axi4frag_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_aw_bits_addr = axi4frag_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_aw_bits_user = axi4frag_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_w_valid = axi4frag_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_w_bits_data = axi4frag_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_w_bits_strb = axi4frag_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_w_bits_last = axi4frag_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_b_ready = axi4frag_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_ar_valid = axi4frag_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_ar_bits_id = axi4frag_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_ar_bits_addr = axi4frag_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_ar_bits_user = axi4frag_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_in_r_ready = axi4frag_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4buf_auto_out_aw_ready = srams_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_w_ready = srams_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_b_valid = srams_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_b_bits_id = srams_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_b_bits_resp = srams_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_b_bits_user = srams_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_ar_ready = srams_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_r_valid = srams_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_r_bits_id = srams_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_r_bits_data = srams_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_r_bits_resp = srams_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4buf_auto_out_r_bits_user = srams_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130236.4] assign axi4frag_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130230.4] assign axi4frag_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@130231.4] assign axi4frag_auto_in_aw_valid = axi4xbar_auto_out_aw_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_aw_bits_id = axi4xbar_auto_out_aw_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_aw_bits_addr = axi4xbar_auto_out_aw_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_aw_bits_len = axi4xbar_auto_out_aw_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_aw_bits_size = axi4xbar_auto_out_aw_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_aw_bits_burst = axi4xbar_auto_out_aw_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_w_valid = axi4xbar_auto_out_w_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_w_bits_data = axi4xbar_auto_out_w_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_w_bits_strb = axi4xbar_auto_out_w_bits_strb; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_w_bits_last = axi4xbar_auto_out_w_bits_last; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_b_ready = axi4xbar_auto_out_b_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_valid = axi4xbar_auto_out_ar_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_bits_id = axi4xbar_auto_out_ar_bits_id; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_bits_addr = axi4xbar_auto_out_ar_bits_addr; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_bits_len = axi4xbar_auto_out_ar_bits_len; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_bits_size = axi4xbar_auto_out_ar_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_ar_bits_burst = axi4xbar_auto_out_ar_bits_burst; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_in_r_ready = axi4xbar_auto_out_r_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.TinyConfig.fir@130235.4] assign axi4frag_auto_out_aw_ready = axi4buf_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_w_ready = axi4buf_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_b_valid = axi4buf_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_b_bits_id = axi4buf_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_b_bits_resp = axi4buf_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_b_bits_user = axi4buf_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_ar_ready = axi4buf_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_valid = axi4buf_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_bits_id = axi4buf_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_bits_data = axi4buf_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_bits_resp = axi4buf_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_bits_user = axi4buf_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] assign axi4frag_auto_out_r_bits_last = axi4buf_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.TinyConfig.fir@130237.4] endmodule module TestHarness( // @[:freechips.rocketchip.system.TinyConfig.fir@130249.2] input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@130250.4] input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@130251.4] output io_success // @[:freechips.rocketchip.system.TinyConfig.fir@130252.4] ); wire dut_clock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_reset; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmi_req_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmi_req_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [6:0] dut_debug_clockeddmi_dmi_req_bits_addr; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_debug_clockeddmi_dmi_req_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_debug_clockeddmi_dmi_req_bits_op; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmi_resp_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmi_resp_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_debug_clockeddmi_dmi_resp_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_debug_clockeddmi_dmi_resp_bits_resp; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmiClock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_clockeddmi_dmiReset; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_ndreset; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_debug_dmactive; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_interrupts; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_aw_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_aw_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_aw_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [30:0] dut_mmio_axi4_0_aw_bits_addr; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_mmio_axi4_0_aw_bits_len; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_mmio_axi4_0_aw_bits_size; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_mmio_axi4_0_aw_bits_burst; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_aw_bits_lock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_aw_bits_cache; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_mmio_axi4_0_aw_bits_prot; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_aw_bits_qos; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_w_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_w_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_mmio_axi4_0_w_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_w_bits_strb; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_w_bits_last; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_b_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_b_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_b_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_mmio_axi4_0_b_bits_resp; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_ar_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_ar_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_ar_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [30:0] dut_mmio_axi4_0_ar_bits_addr; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_mmio_axi4_0_ar_bits_len; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_mmio_axi4_0_ar_bits_size; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_mmio_axi4_0_ar_bits_burst; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_ar_bits_lock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_ar_bits_cache; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_mmio_axi4_0_ar_bits_prot; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_ar_bits_qos; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_r_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_r_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_mmio_axi4_0_r_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_mmio_axi4_0_r_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_mmio_axi4_0_r_bits_resp; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_mmio_axi4_0_r_bits_last; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_aw_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_aw_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_aw_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_l2_frontend_bus_axi4_0_aw_bits_addr; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_aw_bits_len; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_l2_frontend_bus_axi4_0_aw_bits_size; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_l2_frontend_bus_axi4_0_aw_bits_burst; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_aw_bits_lock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_l2_frontend_bus_axi4_0_aw_bits_cache; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_l2_frontend_bus_axi4_0_aw_bits_prot; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_l2_frontend_bus_axi4_0_aw_bits_qos; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_w_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_w_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [63:0] dut_l2_frontend_bus_axi4_0_w_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_w_bits_strb; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_w_bits_last; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_b_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_b_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_b_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_l2_frontend_bus_axi4_0_b_bits_resp; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_ar_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_ar_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_ar_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [31:0] dut_l2_frontend_bus_axi4_0_ar_bits_addr; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_ar_bits_len; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_l2_frontend_bus_axi4_0_ar_bits_size; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_l2_frontend_bus_axi4_0_ar_bits_burst; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_ar_bits_lock; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_l2_frontend_bus_axi4_0_ar_bits_cache; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [2:0] dut_l2_frontend_bus_axi4_0_ar_bits_prot; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [3:0] dut_l2_frontend_bus_axi4_0_ar_bits_qos; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_r_ready; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_r_valid; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [7:0] dut_l2_frontend_bus_axi4_0_r_bits_id; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [63:0] dut_l2_frontend_bus_axi4_0_r_bits_data; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire [1:0] dut_l2_frontend_bus_axi4_0_r_bits_resp; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire dut_l2_frontend_bus_axi4_0_r_bits_last; // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] wire mmio_mem_clock; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_reset; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_aw_ready; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_aw_valid; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [3:0] mmio_mem_io_axi4_0_aw_bits_id; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [11:0] mmio_mem_io_axi4_0_aw_bits_addr; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [7:0] mmio_mem_io_axi4_0_aw_bits_len; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [2:0] mmio_mem_io_axi4_0_aw_bits_size; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [1:0] mmio_mem_io_axi4_0_aw_bits_burst; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_w_ready; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_w_valid; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [31:0] mmio_mem_io_axi4_0_w_bits_data; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [3:0] mmio_mem_io_axi4_0_w_bits_strb; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_w_bits_last; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_b_ready; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_b_valid; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [3:0] mmio_mem_io_axi4_0_b_bits_id; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [1:0] mmio_mem_io_axi4_0_b_bits_resp; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_ar_ready; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_ar_valid; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [3:0] mmio_mem_io_axi4_0_ar_bits_id; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [11:0] mmio_mem_io_axi4_0_ar_bits_addr; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [7:0] mmio_mem_io_axi4_0_ar_bits_len; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [2:0] mmio_mem_io_axi4_0_ar_bits_size; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [1:0] mmio_mem_io_axi4_0_ar_bits_burst; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_r_ready; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_r_valid; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [3:0] mmio_mem_io_axi4_0_r_bits_id; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [31:0] mmio_mem_io_axi4_0_r_bits_data; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire [1:0] mmio_mem_io_axi4_0_r_bits_resp; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire mmio_mem_io_axi4_0_r_bits_last; // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] wire SimDTM_clk; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire SimDTM_reset; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire SimDTM_debug_req_ready; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire SimDTM_debug_req_valid; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [6:0] SimDTM_debug_req_bits_addr; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [31:0] SimDTM_debug_req_bits_data; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [1:0] SimDTM_debug_req_bits_op; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire SimDTM_debug_resp_ready; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire SimDTM_debug_resp_valid; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [31:0] SimDTM_debug_resp_bits_data; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [1:0] SimDTM_debug_resp_bits_resp; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire [31:0] SimDTM_exit; // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] wire _T_8; // @[Periphery.scala 136:19:freechips.rocketchip.system.TinyConfig.fir@130306.4] wire [30:0] _GEN_0; // @[Periphery.scala 137:59:freechips.rocketchip.system.TinyConfig.fir@130308.6] wire [31:0] _T_9; // @[Periphery.scala 137:59:freechips.rocketchip.system.TinyConfig.fir@130308.6] wire _T_11; // @[Periphery.scala 137:13:freechips.rocketchip.system.TinyConfig.fir@130310.6] ExampleRocketSystem dut ( // @[TestHarness.scala 15:19:freechips.rocketchip.system.TinyConfig.fir@130257.4] .clock(dut_clock), .reset(dut_reset), .debug_clockeddmi_dmi_req_ready(dut_debug_clockeddmi_dmi_req_ready), .debug_clockeddmi_dmi_req_valid(dut_debug_clockeddmi_dmi_req_valid), .debug_clockeddmi_dmi_req_bits_addr(dut_debug_clockeddmi_dmi_req_bits_addr), .debug_clockeddmi_dmi_req_bits_data(dut_debug_clockeddmi_dmi_req_bits_data), .debug_clockeddmi_dmi_req_bits_op(dut_debug_clockeddmi_dmi_req_bits_op), .debug_clockeddmi_dmi_resp_ready(dut_debug_clockeddmi_dmi_resp_ready), .debug_clockeddmi_dmi_resp_valid(dut_debug_clockeddmi_dmi_resp_valid), .debug_clockeddmi_dmi_resp_bits_data(dut_debug_clockeddmi_dmi_resp_bits_data), .debug_clockeddmi_dmi_resp_bits_resp(dut_debug_clockeddmi_dmi_resp_bits_resp), .debug_clockeddmi_dmiClock(dut_debug_clockeddmi_dmiClock), .debug_clockeddmi_dmiReset(dut_debug_clockeddmi_dmiReset), .debug_ndreset(dut_debug_ndreset), .debug_dmactive(dut_debug_dmactive), .interrupts(dut_interrupts), .mmio_axi4_0_aw_ready(dut_mmio_axi4_0_aw_ready), .mmio_axi4_0_aw_valid(dut_mmio_axi4_0_aw_valid), .mmio_axi4_0_aw_bits_id(dut_mmio_axi4_0_aw_bits_id), .mmio_axi4_0_aw_bits_addr(dut_mmio_axi4_0_aw_bits_addr), .mmio_axi4_0_aw_bits_len(dut_mmio_axi4_0_aw_bits_len), .mmio_axi4_0_aw_bits_size(dut_mmio_axi4_0_aw_bits_size), .mmio_axi4_0_aw_bits_burst(dut_mmio_axi4_0_aw_bits_burst), .mmio_axi4_0_aw_bits_lock(dut_mmio_axi4_0_aw_bits_lock), .mmio_axi4_0_aw_bits_cache(dut_mmio_axi4_0_aw_bits_cache), .mmio_axi4_0_aw_bits_prot(dut_mmio_axi4_0_aw_bits_prot), .mmio_axi4_0_aw_bits_qos(dut_mmio_axi4_0_aw_bits_qos), .mmio_axi4_0_w_ready(dut_mmio_axi4_0_w_ready), .mmio_axi4_0_w_valid(dut_mmio_axi4_0_w_valid), .mmio_axi4_0_w_bits_data(dut_mmio_axi4_0_w_bits_data), .mmio_axi4_0_w_bits_strb(dut_mmio_axi4_0_w_bits_strb), .mmio_axi4_0_w_bits_last(dut_mmio_axi4_0_w_bits_last), .mmio_axi4_0_b_ready(dut_mmio_axi4_0_b_ready), .mmio_axi4_0_b_valid(dut_mmio_axi4_0_b_valid), .mmio_axi4_0_b_bits_id(dut_mmio_axi4_0_b_bits_id), .mmio_axi4_0_b_bits_resp(dut_mmio_axi4_0_b_bits_resp), .mmio_axi4_0_ar_ready(dut_mmio_axi4_0_ar_ready), .mmio_axi4_0_ar_valid(dut_mmio_axi4_0_ar_valid), .mmio_axi4_0_ar_bits_id(dut_mmio_axi4_0_ar_bits_id), .mmio_axi4_0_ar_bits_addr(dut_mmio_axi4_0_ar_bits_addr), .mmio_axi4_0_ar_bits_len(dut_mmio_axi4_0_ar_bits_len), .mmio_axi4_0_ar_bits_size(dut_mmio_axi4_0_ar_bits_size), .mmio_axi4_0_ar_bits_burst(dut_mmio_axi4_0_ar_bits_burst), .mmio_axi4_0_ar_bits_lock(dut_mmio_axi4_0_ar_bits_lock), .mmio_axi4_0_ar_bits_cache(dut_mmio_axi4_0_ar_bits_cache), .mmio_axi4_0_ar_bits_prot(dut_mmio_axi4_0_ar_bits_prot), .mmio_axi4_0_ar_bits_qos(dut_mmio_axi4_0_ar_bits_qos), .mmio_axi4_0_r_ready(dut_mmio_axi4_0_r_ready), .mmio_axi4_0_r_valid(dut_mmio_axi4_0_r_valid), .mmio_axi4_0_r_bits_id(dut_mmio_axi4_0_r_bits_id), .mmio_axi4_0_r_bits_data(dut_mmio_axi4_0_r_bits_data), .mmio_axi4_0_r_bits_resp(dut_mmio_axi4_0_r_bits_resp), .mmio_axi4_0_r_bits_last(dut_mmio_axi4_0_r_bits_last), .l2_frontend_bus_axi4_0_aw_ready(dut_l2_frontend_bus_axi4_0_aw_ready), .l2_frontend_bus_axi4_0_aw_valid(dut_l2_frontend_bus_axi4_0_aw_valid), .l2_frontend_bus_axi4_0_aw_bits_id(dut_l2_frontend_bus_axi4_0_aw_bits_id), .l2_frontend_bus_axi4_0_aw_bits_addr(dut_l2_frontend_bus_axi4_0_aw_bits_addr), .l2_frontend_bus_axi4_0_aw_bits_len(dut_l2_frontend_bus_axi4_0_aw_bits_len), .l2_frontend_bus_axi4_0_aw_bits_size(dut_l2_frontend_bus_axi4_0_aw_bits_size), .l2_frontend_bus_axi4_0_aw_bits_burst(dut_l2_frontend_bus_axi4_0_aw_bits_burst), .l2_frontend_bus_axi4_0_aw_bits_lock(dut_l2_frontend_bus_axi4_0_aw_bits_lock), .l2_frontend_bus_axi4_0_aw_bits_cache(dut_l2_frontend_bus_axi4_0_aw_bits_cache), .l2_frontend_bus_axi4_0_aw_bits_prot(dut_l2_frontend_bus_axi4_0_aw_bits_prot), .l2_frontend_bus_axi4_0_aw_bits_qos(dut_l2_frontend_bus_axi4_0_aw_bits_qos), .l2_frontend_bus_axi4_0_w_ready(dut_l2_frontend_bus_axi4_0_w_ready), .l2_frontend_bus_axi4_0_w_valid(dut_l2_frontend_bus_axi4_0_w_valid), .l2_frontend_bus_axi4_0_w_bits_data(dut_l2_frontend_bus_axi4_0_w_bits_data), .l2_frontend_bus_axi4_0_w_bits_strb(dut_l2_frontend_bus_axi4_0_w_bits_strb), .l2_frontend_bus_axi4_0_w_bits_last(dut_l2_frontend_bus_axi4_0_w_bits_last), .l2_frontend_bus_axi4_0_b_ready(dut_l2_frontend_bus_axi4_0_b_ready), .l2_frontend_bus_axi4_0_b_valid(dut_l2_frontend_bus_axi4_0_b_valid), .l2_frontend_bus_axi4_0_b_bits_id(dut_l2_frontend_bus_axi4_0_b_bits_id), .l2_frontend_bus_axi4_0_b_bits_resp(dut_l2_frontend_bus_axi4_0_b_bits_resp), .l2_frontend_bus_axi4_0_ar_ready(dut_l2_frontend_bus_axi4_0_ar_ready), .l2_frontend_bus_axi4_0_ar_valid(dut_l2_frontend_bus_axi4_0_ar_valid), .l2_frontend_bus_axi4_0_ar_bits_id(dut_l2_frontend_bus_axi4_0_ar_bits_id), .l2_frontend_bus_axi4_0_ar_bits_addr(dut_l2_frontend_bus_axi4_0_ar_bits_addr), .l2_frontend_bus_axi4_0_ar_bits_len(dut_l2_frontend_bus_axi4_0_ar_bits_len), .l2_frontend_bus_axi4_0_ar_bits_size(dut_l2_frontend_bus_axi4_0_ar_bits_size), .l2_frontend_bus_axi4_0_ar_bits_burst(dut_l2_frontend_bus_axi4_0_ar_bits_burst), .l2_frontend_bus_axi4_0_ar_bits_lock(dut_l2_frontend_bus_axi4_0_ar_bits_lock), .l2_frontend_bus_axi4_0_ar_bits_cache(dut_l2_frontend_bus_axi4_0_ar_bits_cache), .l2_frontend_bus_axi4_0_ar_bits_prot(dut_l2_frontend_bus_axi4_0_ar_bits_prot), .l2_frontend_bus_axi4_0_ar_bits_qos(dut_l2_frontend_bus_axi4_0_ar_bits_qos), .l2_frontend_bus_axi4_0_r_ready(dut_l2_frontend_bus_axi4_0_r_ready), .l2_frontend_bus_axi4_0_r_valid(dut_l2_frontend_bus_axi4_0_r_valid), .l2_frontend_bus_axi4_0_r_bits_id(dut_l2_frontend_bus_axi4_0_r_bits_id), .l2_frontend_bus_axi4_0_r_bits_data(dut_l2_frontend_bus_axi4_0_r_bits_data), .l2_frontend_bus_axi4_0_r_bits_resp(dut_l2_frontend_bus_axi4_0_r_bits_resp), .l2_frontend_bus_axi4_0_r_bits_last(dut_l2_frontend_bus_axi4_0_r_bits_last) ); SimAXIMem mmio_mem ( // @[Ports.scala 121:13:freechips.rocketchip.system.TinyConfig.fir@130271.4] .clock(mmio_mem_clock), .reset(mmio_mem_reset), .io_axi4_0_aw_ready(mmio_mem_io_axi4_0_aw_ready), .io_axi4_0_aw_valid(mmio_mem_io_axi4_0_aw_valid), .io_axi4_0_aw_bits_id(mmio_mem_io_axi4_0_aw_bits_id), .io_axi4_0_aw_bits_addr(mmio_mem_io_axi4_0_aw_bits_addr), .io_axi4_0_aw_bits_len(mmio_mem_io_axi4_0_aw_bits_len), .io_axi4_0_aw_bits_size(mmio_mem_io_axi4_0_aw_bits_size), .io_axi4_0_aw_bits_burst(mmio_mem_io_axi4_0_aw_bits_burst), .io_axi4_0_w_ready(mmio_mem_io_axi4_0_w_ready), .io_axi4_0_w_valid(mmio_mem_io_axi4_0_w_valid), .io_axi4_0_w_bits_data(mmio_mem_io_axi4_0_w_bits_data), .io_axi4_0_w_bits_strb(mmio_mem_io_axi4_0_w_bits_strb), .io_axi4_0_w_bits_last(mmio_mem_io_axi4_0_w_bits_last), .io_axi4_0_b_ready(mmio_mem_io_axi4_0_b_ready), .io_axi4_0_b_valid(mmio_mem_io_axi4_0_b_valid), .io_axi4_0_b_bits_id(mmio_mem_io_axi4_0_b_bits_id), .io_axi4_0_b_bits_resp(mmio_mem_io_axi4_0_b_bits_resp), .io_axi4_0_ar_ready(mmio_mem_io_axi4_0_ar_ready), .io_axi4_0_ar_valid(mmio_mem_io_axi4_0_ar_valid), .io_axi4_0_ar_bits_id(mmio_mem_io_axi4_0_ar_bits_id), .io_axi4_0_ar_bits_addr(mmio_mem_io_axi4_0_ar_bits_addr), .io_axi4_0_ar_bits_len(mmio_mem_io_axi4_0_ar_bits_len), .io_axi4_0_ar_bits_size(mmio_mem_io_axi4_0_ar_bits_size), .io_axi4_0_ar_bits_burst(mmio_mem_io_axi4_0_ar_bits_burst), .io_axi4_0_r_ready(mmio_mem_io_axi4_0_r_ready), .io_axi4_0_r_valid(mmio_mem_io_axi4_0_r_valid), .io_axi4_0_r_bits_id(mmio_mem_io_axi4_0_r_bits_id), .io_axi4_0_r_bits_data(mmio_mem_io_axi4_0_r_bits_data), .io_axi4_0_r_bits_resp(mmio_mem_io_axi4_0_r_bits_resp), .io_axi4_0_r_bits_last(mmio_mem_io_axi4_0_r_bits_last) ); SimDTM SimDTM ( // @[Periphery.scala 192:23:freechips.rocketchip.system.TinyConfig.fir@130294.4] .clk(SimDTM_clk), .reset(SimDTM_reset), .debug_req_ready(SimDTM_debug_req_ready), .debug_req_valid(SimDTM_debug_req_valid), .debug_req_bits_addr(SimDTM_debug_req_bits_addr), .debug_req_bits_data(SimDTM_debug_req_bits_data), .debug_req_bits_op(SimDTM_debug_req_bits_op), .debug_resp_ready(SimDTM_debug_resp_ready), .debug_resp_valid(SimDTM_debug_resp_valid), .debug_resp_bits_data(SimDTM_debug_resp_bits_data), .debug_resp_bits_resp(SimDTM_debug_resp_bits_resp), .exit(SimDTM_exit) ); assign _T_8 = SimDTM_exit >= 32'h2; // @[Periphery.scala 136:19:freechips.rocketchip.system.TinyConfig.fir@130306.4] assign _GEN_0 = SimDTM_exit[31:1]; // @[Periphery.scala 137:59:freechips.rocketchip.system.TinyConfig.fir@130308.6] assign _T_9 = {{1'd0}, _GEN_0}; // @[Periphery.scala 137:59:freechips.rocketchip.system.TinyConfig.fir@130308.6] assign _T_11 = reset == 1'h0; // @[Periphery.scala 137:13:freechips.rocketchip.system.TinyConfig.fir@130310.6] assign io_success = SimDTM_exit == 32'h1; // @[Periphery.scala 135:15:freechips.rocketchip.system.TinyConfig.fir@130305.4] assign dut_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130265.4] assign dut_reset = reset | dut_debug_ndreset; // @[:freechips.rocketchip.system.TinyConfig.fir@130266.4 TestHarness.scala 16:13:freechips.rocketchip.system.TinyConfig.fir@130269.4] assign dut_debug_clockeddmi_dmi_req_valid = SimDTM_debug_req_valid; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign dut_debug_clockeddmi_dmi_req_bits_addr = SimDTM_debug_req_bits_addr; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign dut_debug_clockeddmi_dmi_req_bits_data = SimDTM_debug_req_bits_data; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign dut_debug_clockeddmi_dmi_req_bits_op = SimDTM_debug_req_bits_op; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign dut_debug_clockeddmi_dmi_resp_ready = SimDTM_debug_resp_ready; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign dut_debug_clockeddmi_dmiClock = clock; // @[Periphery.scala 132:20:freechips.rocketchip.system.TinyConfig.fir@130302.4] assign dut_debug_clockeddmi_dmiReset = reset; // @[Periphery.scala 133:20:freechips.rocketchip.system.TinyConfig.fir@130303.4] assign dut_interrupts = 2'h0; // @[InterruptBus.scala 68:16:freechips.rocketchip.system.TinyConfig.fir@130270.4] assign dut_mmio_axi4_0_aw_ready = mmio_mem_io_axi4_0_aw_ready; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_w_ready = mmio_mem_io_axi4_0_w_ready; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_b_valid = mmio_mem_io_axi4_0_b_valid; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_b_bits_id = mmio_mem_io_axi4_0_b_bits_id; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_b_bits_resp = mmio_mem_io_axi4_0_b_bits_resp; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_ar_ready = mmio_mem_io_axi4_0_ar_ready; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_r_valid = mmio_mem_io_axi4_0_r_valid; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_r_bits_id = mmio_mem_io_axi4_0_r_bits_id; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_r_bits_data = mmio_mem_io_axi4_0_r_bits_data; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_r_bits_resp = mmio_mem_io_axi4_0_r_bits_resp; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_mmio_axi4_0_r_bits_last = mmio_mem_io_axi4_0_r_bits_last; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign dut_l2_frontend_bus_axi4_0_aw_valid = 1'h0; // @[Bundles.scala 85:18:freechips.rocketchip.system.TinyConfig.fir@130280.4] assign dut_l2_frontend_bus_axi4_0_aw_bits_id = 8'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_addr = 32'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_len = 8'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_size = 3'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_burst = 2'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_lock = 1'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_cache = 4'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_prot = 3'h0; assign dut_l2_frontend_bus_axi4_0_aw_bits_qos = 4'h0; assign dut_l2_frontend_bus_axi4_0_w_valid = 1'h0; // @[Bundles.scala 86:18:freechips.rocketchip.system.TinyConfig.fir@130281.4] assign dut_l2_frontend_bus_axi4_0_w_bits_data = 64'h0; assign dut_l2_frontend_bus_axi4_0_w_bits_strb = 8'h0; assign dut_l2_frontend_bus_axi4_0_w_bits_last = 1'h0; assign dut_l2_frontend_bus_axi4_0_b_ready = 1'h0; // @[Bundles.scala 88:18:freechips.rocketchip.system.TinyConfig.fir@130283.4] assign dut_l2_frontend_bus_axi4_0_ar_valid = 1'h0; // @[Bundles.scala 84:18:freechips.rocketchip.system.TinyConfig.fir@130279.4] assign dut_l2_frontend_bus_axi4_0_ar_bits_id = 8'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_addr = 32'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_len = 8'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_size = 3'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_burst = 2'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_lock = 1'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_cache = 4'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_prot = 3'h0; assign dut_l2_frontend_bus_axi4_0_ar_bits_qos = 4'h0; assign dut_l2_frontend_bus_axi4_0_r_ready = 1'h0; // @[Bundles.scala 87:18:freechips.rocketchip.system.TinyConfig.fir@130282.4] assign mmio_mem_clock = clock; // @[:freechips.rocketchip.system.TinyConfig.fir@130276.4] assign mmio_mem_reset = reset; // @[:freechips.rocketchip.system.TinyConfig.fir@130277.4] assign mmio_mem_io_axi4_0_aw_valid = dut_mmio_axi4_0_aw_valid; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_aw_bits_id = dut_mmio_axi4_0_aw_bits_id; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_aw_bits_addr = dut_mmio_axi4_0_aw_bits_addr[11:0]; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_aw_bits_len = dut_mmio_axi4_0_aw_bits_len; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_aw_bits_size = dut_mmio_axi4_0_aw_bits_size; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_aw_bits_burst = dut_mmio_axi4_0_aw_bits_burst; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_w_valid = dut_mmio_axi4_0_w_valid; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_w_bits_data = dut_mmio_axi4_0_w_bits_data; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_w_bits_strb = dut_mmio_axi4_0_w_bits_strb; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_w_bits_last = dut_mmio_axi4_0_w_bits_last; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_b_ready = dut_mmio_axi4_0_b_ready; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_valid = dut_mmio_axi4_0_ar_valid; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_bits_id = dut_mmio_axi4_0_ar_bits_id; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_bits_addr = dut_mmio_axi4_0_ar_bits_addr[11:0]; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_bits_len = dut_mmio_axi4_0_ar_bits_len; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_bits_size = dut_mmio_axi4_0_ar_bits_size; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_ar_bits_burst = dut_mmio_axi4_0_ar_bits_burst; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign mmio_mem_io_axi4_0_r_ready = dut_mmio_axi4_0_r_ready; // @[Ports.scala 121:44:freechips.rocketchip.system.TinyConfig.fir@130278.4] assign SimDTM_clk = clock; // @[Periphery.scala 129:12:freechips.rocketchip.system.TinyConfig.fir@130299.4] assign SimDTM_reset = reset; // @[Periphery.scala 130:14:freechips.rocketchip.system.TinyConfig.fir@130300.4] assign SimDTM_debug_req_ready = dut_debug_clockeddmi_dmi_req_ready; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign SimDTM_debug_resp_valid = dut_debug_clockeddmi_dmi_resp_valid; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign SimDTM_debug_resp_bits_data = dut_debug_clockeddmi_dmi_resp_bits_data; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] assign SimDTM_debug_resp_bits_resp = dut_debug_clockeddmi_dmi_resp_bits_resp; // @[Periphery.scala 131:15:freechips.rocketchip.system.TinyConfig.fir@130301.4] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T_8 & _T_11) begin $fwrite(32'h80000002,"*** FAILED *** (exit code = %d)\n",_T_9); // @[Periphery.scala 137:13:freechips.rocketchip.system.TinyConfig.fir@130312.8] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (_T_8 & _T_11) begin $fatal; // @[Periphery.scala 138:11:freechips.rocketchip.system.TinyConfig.fir@130317.8] end `ifdef STOP_COND end `endif `endif // SYNTHESIS end endmodule module data_arrays_0( input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [7:0] RW0_wdata_0, input [7:0] RW0_wdata_1, input [7:0] RW0_wdata_2, input [7:0] RW0_wdata_3, output [7:0] RW0_rdata_0, output [7:0] RW0_rdata_1, output [7:0] RW0_rdata_2, output [7:0] RW0_rdata_3, input RW0_wmask_0, input RW0_wmask_1, input RW0_wmask_2, input RW0_wmask_3 ); wire [5:0] data_arrays_0_ext_RW0_addr; wire data_arrays_0_ext_RW0_en; wire data_arrays_0_ext_RW0_clk; wire data_arrays_0_ext_RW0_wmode; wire [31:0] data_arrays_0_ext_RW0_wdata; wire [31:0] data_arrays_0_ext_RW0_rdata; wire [3:0] data_arrays_0_ext_RW0_wmask; wire [7:0] _GEN_0; wire [7:0] _GEN_1; wire [7:0] _GEN_2; wire [7:0] _GEN_3; wire [7:0] _GEN_4; wire [7:0] _GEN_5; wire [7:0] _GEN_6; wire [7:0] _GEN_7; wire [15:0] _GEN_8; wire [15:0] _GEN_9; wire _GEN_10; wire _GEN_11; wire _GEN_12; wire _GEN_13; wire [1:0] _GEN_14; wire [1:0] _GEN_15; data_arrays_0_ext data_arrays_0_ext ( .RW0_addr(data_arrays_0_ext_RW0_addr), .RW0_en(data_arrays_0_ext_RW0_en), .RW0_clk(data_arrays_0_ext_RW0_clk), .RW0_wmode(data_arrays_0_ext_RW0_wmode), .RW0_wdata(data_arrays_0_ext_RW0_wdata), .RW0_rdata(data_arrays_0_ext_RW0_rdata), .RW0_wmask(data_arrays_0_ext_RW0_wmask) ); assign data_arrays_0_ext_RW0_clk = RW0_clk; assign data_arrays_0_ext_RW0_en = RW0_en; assign data_arrays_0_ext_RW0_addr = RW0_addr; assign _GEN_0 = data_arrays_0_ext_RW0_rdata[7:0]; assign RW0_rdata_0 = $unsigned(_GEN_0); assign _GEN_1 = data_arrays_0_ext_RW0_rdata[15:8]; assign RW0_rdata_1 = $unsigned(_GEN_1); assign _GEN_2 = data_arrays_0_ext_RW0_rdata[23:16]; assign RW0_rdata_2 = $unsigned(_GEN_2); assign _GEN_3 = data_arrays_0_ext_RW0_rdata[31:24]; assign RW0_rdata_3 = $unsigned(_GEN_3); assign data_arrays_0_ext_RW0_wmode = RW0_wmode; assign _GEN_4 = $unsigned(RW0_wdata_3); assign _GEN_5 = $unsigned(RW0_wdata_2); assign _GEN_6 = $unsigned(RW0_wdata_1); assign _GEN_7 = $unsigned(RW0_wdata_0); assign _GEN_8 = {_GEN_4,_GEN_5}; assign _GEN_9 = {_GEN_6,_GEN_7}; assign data_arrays_0_ext_RW0_wdata = {_GEN_8,_GEN_9}; assign _GEN_10 = $unsigned(RW0_wmask_3); assign _GEN_11 = $unsigned(RW0_wmask_2); assign _GEN_12 = $unsigned(RW0_wmask_1); assign _GEN_13 = $unsigned(RW0_wmask_0); assign _GEN_14 = {_GEN_10,_GEN_11}; assign _GEN_15 = {_GEN_12,_GEN_13}; assign data_arrays_0_ext_RW0_wmask = {_GEN_14,_GEN_15}; endmodule module tag_array( input [1:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [24:0] RW0_wdata_0, output [24:0] RW0_rdata_0 ); wire [1:0] tag_array_ext_RW0_addr; wire tag_array_ext_RW0_en; wire tag_array_ext_RW0_clk; wire tag_array_ext_RW0_wmode; wire [24:0] tag_array_ext_RW0_wdata; wire [24:0] tag_array_ext_RW0_rdata; wire tag_array_ext_RW0_wmask; tag_array_ext tag_array_ext ( .RW0_addr(tag_array_ext_RW0_addr), .RW0_en(tag_array_ext_RW0_en), .RW0_clk(tag_array_ext_RW0_clk), .RW0_wmode(tag_array_ext_RW0_wmode), .RW0_wdata(tag_array_ext_RW0_wdata), .RW0_rdata(tag_array_ext_RW0_rdata), .RW0_wmask(tag_array_ext_RW0_wmask) ); assign tag_array_ext_RW0_clk = RW0_clk; assign tag_array_ext_RW0_en = RW0_en; assign tag_array_ext_RW0_addr = RW0_addr; assign RW0_rdata_0 = $unsigned(tag_array_ext_RW0_rdata); assign tag_array_ext_RW0_wmode = RW0_wmode; assign tag_array_ext_RW0_wdata = $unsigned(RW0_wdata_0); assign tag_array_ext_RW0_wmask = 1'h1; endmodule module data_arrays_0_0( input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [31:0] RW0_wdata_0, output [31:0] RW0_rdata_0 ); wire [5:0] data_arrays_0_0_ext_RW0_addr; wire data_arrays_0_0_ext_RW0_en; wire data_arrays_0_0_ext_RW0_clk; wire data_arrays_0_0_ext_RW0_wmode; wire [31:0] data_arrays_0_0_ext_RW0_wdata; wire [31:0] data_arrays_0_0_ext_RW0_rdata; wire data_arrays_0_0_ext_RW0_wmask; data_arrays_0_0_ext data_arrays_0_0_ext ( .RW0_addr(data_arrays_0_0_ext_RW0_addr), .RW0_en(data_arrays_0_0_ext_RW0_en), .RW0_clk(data_arrays_0_0_ext_RW0_clk), .RW0_wmode(data_arrays_0_0_ext_RW0_wmode), .RW0_wdata(data_arrays_0_0_ext_RW0_wdata), .RW0_rdata(data_arrays_0_0_ext_RW0_rdata), .RW0_wmask(data_arrays_0_0_ext_RW0_wmask) ); assign data_arrays_0_0_ext_RW0_clk = RW0_clk; assign data_arrays_0_0_ext_RW0_en = RW0_en; assign data_arrays_0_0_ext_RW0_addr = RW0_addr; assign RW0_rdata_0 = $unsigned(data_arrays_0_0_ext_RW0_rdata); assign data_arrays_0_0_ext_RW0_wmode = RW0_wmode; assign data_arrays_0_0_ext_RW0_wdata = $unsigned(RW0_wdata_0); assign data_arrays_0_0_ext_RW0_wmask = 1'h1; endmodule module mem( input [9:0] R0_addr, input R0_en, input R0_clk, output [7:0] R0_data_0, output [7:0] R0_data_1, output [7:0] R0_data_2, output [7:0] R0_data_3, input [9:0] W0_addr, input W0_en, input W0_clk, input [7:0] W0_data_0, input [7:0] W0_data_1, input [7:0] W0_data_2, input [7:0] W0_data_3, input W0_mask_0, input W0_mask_1, input W0_mask_2, input W0_mask_3 ); wire [9:0] mem_ext_R0_addr; wire mem_ext_R0_en; wire mem_ext_R0_clk; wire [31:0] mem_ext_R0_data; wire [9:0] mem_ext_W0_addr; wire mem_ext_W0_en; wire mem_ext_W0_clk; wire [31:0] mem_ext_W0_data; wire [3:0] mem_ext_W0_mask; wire [7:0] _GEN_0; wire [7:0] _GEN_1; wire [7:0] _GEN_2; wire [7:0] _GEN_3; wire [7:0] _GEN_4; wire [7:0] _GEN_5; wire [7:0] _GEN_6; wire [7:0] _GEN_7; wire [15:0] _GEN_8; wire [15:0] _GEN_9; wire _GEN_10; wire _GEN_11; wire _GEN_12; wire _GEN_13; wire [1:0] _GEN_14; wire [1:0] _GEN_15; mem_ext mem_ext ( .R0_addr(mem_ext_R0_addr), .R0_en(mem_ext_R0_en), .R0_clk(mem_ext_R0_clk), .R0_data(mem_ext_R0_data), .W0_addr(mem_ext_W0_addr), .W0_en(mem_ext_W0_en), .W0_clk(mem_ext_W0_clk), .W0_data(mem_ext_W0_data), .W0_mask(mem_ext_W0_mask) ); assign mem_ext_R0_clk = R0_clk; assign mem_ext_R0_en = R0_en; assign mem_ext_R0_addr = R0_addr; assign _GEN_0 = mem_ext_R0_data[7:0]; assign R0_data_0 = $unsigned(_GEN_0); assign _GEN_1 = mem_ext_R0_data[15:8]; assign R0_data_1 = $unsigned(_GEN_1); assign _GEN_2 = mem_ext_R0_data[23:16]; assign R0_data_2 = $unsigned(_GEN_2); assign _GEN_3 = mem_ext_R0_data[31:24]; assign R0_data_3 = $unsigned(_GEN_3); assign mem_ext_W0_clk = W0_clk; assign mem_ext_W0_en = W0_en; assign mem_ext_W0_addr = W0_addr; assign _GEN_4 = $unsigned(W0_data_3); assign _GEN_5 = $unsigned(W0_data_2); assign _GEN_6 = $unsigned(W0_data_1); assign _GEN_7 = $unsigned(W0_data_0); assign _GEN_8 = {_GEN_4,_GEN_5}; assign _GEN_9 = {_GEN_6,_GEN_7}; assign mem_ext_W0_data = {_GEN_8,_GEN_9}; assign _GEN_10 = $unsigned(W0_mask_3); assign _GEN_11 = $unsigned(W0_mask_2); assign _GEN_12 = $unsigned(W0_mask_1); assign _GEN_13 = $unsigned(W0_mask_0); assign _GEN_14 = {_GEN_10,_GEN_11}; assign _GEN_15 = {_GEN_12,_GEN_13}; assign mem_ext_W0_mask = {_GEN_14,_GEN_15}; endmodule