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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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0
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Files
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xet
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main
verilog_data-2
/
WangXuan95_FPGA-USB-Device
/
RTL
/
usb_class
Commit History
Add Batch 1 with 10 repos
ecb91a3
verified
SAIFIINDUSTRIES
commited on
7 days ago
SAIFIINDUSTRIES commited on 