Add Repo: LIV2_GottaGoFastRAM

LIV2_GottaGoFastRAM/.github/workflows/release.yml

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+name: Generate release files
+
+permissions:
+  contents: write
+on:
+  push:
+    tags:
+      - "Release_**"
+      - "Rev**"
+      - "Proto**"
+      - "proto**"
+  workflow_dispatch:
+
+jobs:
+  draft_release:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: release
+        uses: softprops/action-gh-release@v1
+        with:
+          draft: true
+          files: |
+            Binaries/*.jed

LIV2_GottaGoFastRAM/Images/wavedrom-waveforms.txt

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+# Used on wavedrom.com to generate timing diagrams
+
+{signal: [
+  {name: 'State', wave: 'xx=========x', period: 0.5, data: "0 1 2 3 4 5 6 7 0",},
+  {name: 'CLK', wave: 'P.....',},
+  {name: 'ADDR', wave: 'xxx=......xx', period: 0.5, data: "Match"},
+  {name: 'AS', wave: '1...0....1..', period:0.5},
+  {name: 'DS', wave: '1...0....1..', period:0.5},
+  {name: 'RW', wave: '0.1.........', period:0.5},
+  {name: 'BUFFER_OE', wave: '1....0...1..', period:0.5},
+  {name: 'WR', wave: '1...........', period:0.5},
+  {name: 'DATA', wave: 'x.......=.x.', period:0.5},
+  {name: 'MADDR', wave: 'x...=..=..xx',period:0.5, data: "Row Column"},
+  {name: 'RAS', wave: '1...010...1.',period:0.5},
+  {name: 'CAS', wave: '1..0.1..0.1.',period:0.5},
+],
+  head:{text:'Read Cycle', tock: 0,},
+ config: {hscale: 2}}
+
+
+{signal: [
+  {name: 'State', wave: 'xx=========x', period: 0.5, data: "0 1 2 3 4 5 6 7 0",},
+  {name: 'CLK', wave: 'P.....',},
+  {name: 'ADDR', wave: 'xxx=......xx', period: 0.5, data: "Match"},
+  {name: 'AS', wave: '1...0....1..', period:0.5},
+  {name: 'DS', wave: '1.....0..1..', period:0.5},
+  {name: 'RW', wave: '1...0.....1.', period:0.5},
+  {name: 'BUFFER_OE', wave: '1.....0..1..', period:0.5},
+  {name: 'WR', wave: '1.....0..1..', period:0.5},
+  {name: 'DATA', wave: 'x....=....xx', period:0.5},
+  {name: 'MADDR', wave: 'x...=..=..xx',period:0.5, data: "Row Column"},
+  {name: 'RAS', wave: '1...010...1.',period:0.5},
+  {name: 'CAS', wave: '1..0.1..0.1.',period:0.5},
+],
+  head:{text:'Write Cycle', tock: 0,},
+ config: {hscale: 2}}

LIV2_GottaGoFastRAM/LICENSE.md

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+CERN Open Hardware Licence v1.2 
+
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+wishes to provide a tool to foster collaboration and sharing among
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LIV2_GottaGoFastRAM/README.md

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+# GottaGoFastRAM 8MB Autoconfig Fast RAM
+
+This is an 8MB Autoconfig Fast RAM for Amiga 500/1000/2000/CDTV based on mkl's mem68k  
+It's small size allows it to be stacked on top of an ide68k board  
+Rather than use the original mem68k Abel code I have written a new memory controller in Verilog
+
+![PCB](Images/pcb.png?raw=True)
+![Assembled](Images/assembled.jpg?raw=True)
+## Table of contents
+1. [PCB Ordering](#ordering-pcbs)
+2. [Mounting Options](#mounting-options)
+3. [Cfgin/out](#cfginout)
+4. [Jumpers](#jumpers)
+5. [CDTV](#cdtv)
+6. [Timing Diagrams](#timing-diagrams)
+7. [Bill of materials](#bill-of-materials)
+8. [Known Issues](#known-issues)
+9. [Experimental firmware](#experimental-firmware)
+
+## Ordering PCBs
+I recommend ordering the PCB with a 0.6 or 0.8mm thickness if you intend on stacking with an ide68k or mouting using a DIP socket/machined pin strips.  
+If you are going to mount using the socket pins and not stacking with an ide68k I'd recommend going with the usual 1.6mm to reduce flexing.
+
+## Mounting options
+
+1. Can be soldered to the bottom of a machined pin socket/machined pin strips (will require some cutting of the dip socket to fit the caps/ferrites near the plastic)  
+<img src="Images/mounting_strip.jpg" width=300 />  
+2. Can be soldered to socket pins and stacked with an ide68k  
+<img src="Images/stacked1.jpg" width=300 />  
+<img src="Images/stacked2.jpg" width=300 />  
+
+## Cfgin/out
+These pins allow you to insert the memory module into your autoconfig chain.  
+If there are no other autoconfig devices in your system you can just leave these unconnected otherwise you will need to either connect CFGOut to the CFGin of the first device in your existing autoconfig chain, or connect CFGIn to the CFGOut pin of the last device in your existing autoconfig chain.  
+In the Amiga 2000 you can connect CFGIN to U606 Pin 8 which will add the device to the end of the chain but __NOTE: This takes up the config signal for the leftmost slot (CN601) so do NOT install a Zorro card there__
+
+You can also connect cfgin and cfgout with a jumper to disable the device temporarily
+
+## Jumpers
+J1: Cfgin pull up/down (You will probably want to leave this at default unless you know what you're doing)  
+J2-3: Bridge these if you have not fitted the buffer U4
+
+## CDTV
+The CDTV's DMAC takes up the first autoconfig slot, so if you intend to use this with a CDTV use the CDTV specific .JED file to program the CPLD
+
+If you have a Rev A or Rev B (not B1) board you will need to apply a [small mod for CDTV compatibility](https://github.com/LIV2/GottaGoFastRAM/issues/4/#issuecomment-868977723)
+
+## Timing Diagrams
+![Read Cycle](Images/read.svg?raw=True)  
+![Write Cycle](Images/write.svg?raw=True)
+
+### Bill of materials
+|Component|Location|QTY|Link|Remarks|
+|---------|--------|---|------|--------|
+|4Mx16 3V DRAM TSSOP - K4E641612D or GM71VS65163 |U3|1|-|eBay/Aliexpress etc.|
+|XC9572XL-10VQ64C|U1|1|[Mouser](https://www.mouser.se/ProductDetail/217-C9572XL-10VQG64C)<br />[DigiKey](https://www.digikey.com/short/2f7qn38b)||
+|74LVC2G17 TSSOP-6/SOT-363|U4|1|[Mouser](https://www.mouser.com/ProductDetail/771-74LVC2G17GVQ100H)<br />[DigiKey](https://www.digikey.com/short/95mn57tt) ||
+|AP2210N-3.3 SOT-23|U5|1|[Mouser](https://www.mouser.com/ProductDetail/621-AP2210N-3.3TRG1)<br />[DigiKey](https://www.digikey.com/short/30rd0zn5)|Maybe can be substituted with MCP1703AT-3302E|
+|74LVC245N TSSOP|U6,U7|2|[Mouser](https://www.mouser.com/ProductDetail/595-SN74LVC245APWRG4)<br />[DigiKey](https://www.digikey.com/short/pnq3wff3)|Can be substituted with SN74LVTH245 or SN74LVCR2245|
+|Ferrite Bead, 1206 package|FB1, FB2|2|[Mouser](https://www.mouser.com/ProductDetail/875-MI1206K601R-10)<br />[DigiKey](https://www.digikey.com/short/n4p04ctv)|Can be substituted with 0 Ohm 1206 resistors|
+|10K Resistor, 0603|R1|1|[Mouser](https://www.mouser.com/ProductDetail/603-RT0603FRD0710KL)<br />[DigiKey](https://www.digikey.com/short/nvvrt5dw)||
+|0.1uF Ceramic Capacitor, 0603|C1,4-13|11|[Mouser](https://www.mouser.com/ProductDetail/80-C603C104K5RAC3121)<br />[DigiKey](https://www.digikey.com/short/f7trtfwt)||
+|4.7uF Ceramic Capacitor, 1206|C2|1|[Mouser](https://www.mouser.com/ProductDetail/187-CL31B475KAHNFNE)<br />[DigiKey](https://www.digikey.com/short/d7mbf5nn)||
+|10uF Ceramic Capacitor, 1206|C3|1|[Mouser](https://www.mouser.com/ProductDetail/187-CL31A106MAHNNNE)<br />[DigiKey](https://www.digikey.com/short/rqt1br0q)||
+|Socket pins|Pins|64|[Aliexpress](https://www.aliexpress.com/item/32791545218.html?spm=a2g0o.productlist.0.0.6e223b55CVrXSq&algo_pvid=8fda9f5a-6e07-4dc8-9ed4-bd809bf75756&algo_expid=8fda9f5a-6e07-4dc8-9ed4-bd809bf75756-0&btsid=2100bde316043149660504011ef819&ws_ab_test=searchweb0_0,searchweb201602_,searchweb201603_)|Use these if stacking with an ide68k module|
+|64-Pin DIP socket - machined pin|Pins|1|[Mouser](https://www.mouser.com/ProductDetail/575-193964)|If not stacking with ide68k - pcb can be soldered to bottom of this flush with the plastic|
+
+## Known issues
+1. Rev A & B - Incorrect voltage supplied to U4 causes incompatibility with CDTV. Fixed in Rev B1 but you can [rework Rev A or B boards by following the instructions here](https://github.com/LIV2/GottaGoFastRAM/issues/4/#issuecomment-868977723)
+
+## Experimental Firmware
+* [AutoSnoop Firmware - Autoconfig after all other Z2 devices without any wires](https://github.com/LIV2/GottaGoFastRAM/tree/snoopy)

LIV2_GottaGoFastRAM/RTL/gottagofast.v

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+/*
+GottaGoFastRAM - 8MB Autoconfig FastRAM for Amiga 500(+)/1000/2000/CDTV
+Copyright 2020 Matthew Harlum
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Inspired by mkl's mem68k
+*/
+
+`ifndef makedefines // The defines ignored if being built by Makefile
+`define SERIAL 32'd421
+`define PRODID 8'1
+
+`define autoconfig  // If disabled RAM is always mapped to $200000-9FFFFF
+//`define cdtv      // Uncomment to build CDTV compatible version
+//`define Offer_6M  // If told to shutup when offering 8MB, offer up a 2MB and also 4MB block next (useful with an A590/2091)
+`define rev_b
+`endif
+
+module gottagofast(
+    input CLK,
+    input RESETn,
+    input CFGINn,
+    input UDSn,
+    input LDSn,
+    input ASn,
+    input RWn,
+    inout [15:12] DBUS,
+    input [23:1] ADDR,
+    output reg [11:0] MADDR,
+    output reg CFGOUTn,
+    output RASn,
+    output UCASn,
+    output LCASn,
+    output OEn,
+    output MEMWn
+    );
+
+reg reset_delayed1;
+reg reset;
+
+// Memory controller
+
+reg ram_cycle;
+reg access_ras;
+reg access_ucas;
+reg access_lcas;
+reg refresh_ras;
+reg refresh_cas;
+reg [7:0] addr_match;
+
+`ifdef autoconfig
+// Autoconfig
+localparam [15:0] mfg_id  = 16'd5194;
+localparam [7:0]  prod_id = 8'd1;
+localparam [31:0] serial = `SERIAL;
+
+wire autoconfig_cycle;
+reg shutup = 0;
+reg CFGINnr;
+reg configured;
+reg [2:0] autoconfig_state;
+reg [3:0] data_out;
+
+localparam Offer_8M = 3'b000,
+// If offering 2MB + 4MB blocks you need to offer the 2MB block first
+// This is because of a kickstart bug where the memory config overflows if there is already 2MB configured before another 4MB then 2MB is configured...
+`ifdef Offer_6M
+        Offer_2M = 3'b001,
+        Offer_4M = 3'b010,
+`else
+        Offer_4M = 3'b001,
+        Offer_2M = 3'b010,
+`endif
+        Offer_1M = 3'b011,
+        SHUTUP   = 3'b100;
+
+assign DBUS[15:12] = (RESETn & autoconfig_cycle & RWn & !ASn & !UDSn) ? data_out[3:0] : 'bZ;
+
+`ifdef cdtv
+reg cdtv_configured;
+
+assign autoconfig_cycle = (ADDR[23:16] == 8'hE8) & !CFGINnr & !shutup & cdtv_configured;
+`else
+assign autoconfig_cycle = (ADDR[23:16] == 8'hE8) & !CFGINnr & !shutup;
+`endif
+
+`ifdef cdtv
+// CDTV DMAC is first in chain.
+// So we wait until it's configured before we talk
+always @(negedge UDSn or negedge reset)
+begin
+    if (!reset) begin
+      cdtv_configured <= 1'b0;
+    end else begin
+    if (ADDR[23:16] == 8'hE8 & ADDR[8:1] == 8'h24 & !ASn & !RWn) begin
+      cdtv_configured <= 1'b1;
+    end
+  end
+end
+`endif
+
+// Register Config in/out at end of bus cycle
+always @(posedge ASn or negedge reset)
+begin
+  if (!reset) begin
+    CFGOUTn <= 1'b1;
+    CFGINnr <= 1'b1;
+  end else begin
+    CFGOUTn <= !shutup;
+    CFGINnr <= CFGINn;
+  end
+end
+
+// Offers an 8MB block first, if there's no space offer 4MB, 2MB then 1MB before giving up
+always @(posedge CLK or negedge reset)
+begin
+  if (!reset) begin
+    data_out <= 'bZ;
+  end else if (autoconfig_cycle & RWn) begin
+    case (ADDR[8:1])
+      8'h00:   data_out <= 4'b1110;
+      8'h01:
+        case (autoconfig_state)
+          Offer_8M: data_out <= 4'b0000;
+          Offer_4M: data_out <= 4'b0111;
+          Offer_2M: data_out <= 4'b0110;
+          Offer_1M: data_out <= 4'b0101;
+          default:  data_out <= 4'b0000;
+        endcase
+      8'h02:   data_out <= ~prod_id[7:4]; // Product number
+      8'h03:   data_out <= ~prod_id[3:0]; // Product number
+      8'h04:   data_out <= ~4'b1000;
+      8'h05:   data_out <= ~4'b0000;
+      8'h08:   data_out <= ~mfg_id[15:12]; // Manufacturer ID
+      8'h09:   data_out <= ~mfg_id[11:8];  // Manufacturer ID
+      8'h0A:   data_out <= ~mfg_id[7:4];   // Manufacturer ID
+      8'h0B:   data_out <= ~mfg_id[3:0];   // Manufacturer ID
+      8'h0C:   data_out <= ~serial[31:28]; // Serial number
+      8'h0D:   data_out <= ~serial[27:24]; // Serial number
+      8'h0E:   data_out <= ~serial[23:20]; // Serial number
+      8'h0F:   data_out <= ~serial[19:16]; // Serial number
+      8'h10:   data_out <= ~serial[15:12]; // Serial number
+      8'h11:   data_out <= ~serial[11:8];  // Serial number
+      8'h12:   data_out <= ~serial[7:4];   // Serial number
+      8'h13:   data_out <= ~serial[3:0];   // Serial number
+      8'h20:   data_out <= 4'b0;
+      8'h21:   data_out <= 4'b0;
+      default: data_out <= 4'hF;
+    endcase
+  end
+end
+
+always @(negedge UDSn or negedge reset)
+begin
+  if (!reset) begin
+    configured <= 1'b0;
+    shutup <= 1'b0;
+    addr_match <= 8'b00000000;
+    autoconfig_state <= Offer_8M;
+  end else if (autoconfig_cycle & !ASn & !RWn) begin
+    if (ADDR[8:1] == 8'h26) begin
+      // We've been told to shut up (not enough memory space)
+      // Try offering a smaller block
+      if (autoconfig_state >= SHUTUP-1) begin
+        // All options exhausted - time to shut up!
+        shutup <= 1;
+        autoconfig_state <= SHUTUP;
+      end else begin
+        // Offer the next smallest block
+        autoconfig_state <= autoconfig_state + 1;
+      end
+    end
+    else if (ADDR[8:1] == 8'h24) begin
+      case (autoconfig_state)
+        Offer_8M:
+          begin
+            addr_match <= 8'hFF;
+            shutup     <= 1'b1;
+          end
+        Offer_4M:
+          begin
+            case(DBUS)
+              4'h2:    addr_match <= (addr_match|8'b00001111);
+              4'h4:    addr_match <= (addr_match|8'b00111100);
+              4'h6:    addr_match <= (addr_match|8'b11110000);
+            endcase
+            shutup     <= 1'b1;
+          end
+        Offer_2M:
+          begin
+            case(DBUS)
+              4'h2:    addr_match <= (addr_match|8'b00000011);
+              4'h4:    addr_match <= (addr_match|8'b00001100);
+              4'h6:    addr_match <= (addr_match|8'b00110000);
+              4'h8:    addr_match <= (addr_match|8'b11000000);
+            endcase
+            `ifdef Offer_6M
+            autoconfig_state <= Offer_4M;
+            `else
+            shutup     <= 1'b1;
+            `endif
+          end
+        Offer_1M:
+          begin
+            case(DBUS)
+              4'h2:    addr_match <= (addr_match|8'b00000001);
+              4'h3:    addr_match <= (addr_match|8'b00000010);
+              4'h4:    addr_match <= (addr_match|8'b00000100);
+              4'h5:    addr_match <= (addr_match|8'b00001000);
+              4'h6:    addr_match <= (addr_match|8'b00010000);
+              4'h7:    addr_match <= (addr_match|8'b00100000);
+              4'h8:    addr_match <= (addr_match|8'b01000000);
+              4'h9:    addr_match <= (addr_match|8'b10000000);
+            endcase
+            shutup     <= 1'b1;
+          end
+        default:  addr_match <= 8'b0;
+      endcase
+      configured <= 1'b1;
+    end
+  end
+end
+`endif
+
+// Memory controller
+
+assign RASn  = !(access_ras | (refresh_ras & refresh_cas));
+assign UCASn = !((access_ucas) | refresh_cas);
+assign LCASn = !((access_lcas) | refresh_cas);
+`ifdef rev_b  // On Rev B OEn drives the buffers
+assign OEn   = !ram_cycle | ASn | !RESETn | (UDSn & LDSn);
+`else
+assign OEn   = !(RWn & access_ras);
+`endif
+assign MEMWn = RWn | (UDSn & LDSn);
+
+// Filter reset line by registering it
+always @(posedge CLK)
+begin
+  reset_delayed1 <= RESETn;
+  reset <= reset_delayed1;
+end
+
+// CAS before RAS refresh
+// CAS Asserted in S1 & S2
+// RAS Asserted in S2
+always @(negedge CLK or negedge reset)
+begin
+  if (!reset) begin
+    refresh_cas <= 1'b0;
+  end else begin
+    refresh_cas <= (!refresh_cas & ASn & !access_ras);
+  end
+end
+
+always @(posedge CLK or negedge reset)
+begin
+  if (!reset) begin
+    refresh_ras <= 1'b0;
+  end else begin
+    refresh_ras <= refresh_cas;
+  end
+end
+
+// Memory access
+always @(negedge CLK or negedge reset)
+begin
+  if (!reset) begin
+    ram_cycle = 1'b0;
+  end else begin
+`ifdef autoconfig
+    ram_cycle = (
+      ((ADDR[23:20] == 4'h2) & addr_match[0]) |
+      ((ADDR[23:20] == 4'h3) & addr_match[1]) |
+      ((ADDR[23:20] == 4'h4) & addr_match[2]) |
+      ((ADDR[23:20] == 4'h5) & addr_match[3]) |
+      ((ADDR[23:20] == 4'h6) & addr_match[4]) |
+      ((ADDR[23:20] == 4'h7) & addr_match[5]) |
+      ((ADDR[23:20] == 4'h8) & addr_match[6]) |
+      ((ADDR[23:20] == 4'h9) & addr_match[7])
+      ) & !ASn & configured;
+`else
+    ram_cycle = ((ADDR[23:20] >= 4'h2) & (ADDR[23:20] <= 4'h9) & !ASn);
+`endif
+  end
+end
+
+always @(posedge CLK or negedge reset)
+begin
+  if (!reset) begin
+    access_ras  <= 1'b0;
+    access_ucas <= 1'b0;
+    access_lcas <= 1'b0;
+  end else begin
+    access_ras  <= (ram_cycle & !access_ucas & !access_lcas); // Assert @ S4, Deassert @ S0
+    access_ucas <= (access_ras & !access_ucas & !UDSn);       // Assert @ S6, Deassert @ S0
+    access_lcas <= (access_ras & !access_lcas & !LDSn);       // Assert @ S6, Deassert @ S0
+  end
+end
+
+// Row/Col mux
+// Switch to ROW address at falling edge of S0
+// Switch to column address at falling edge of S4
+always @(negedge CLK)
+begin
+  if (!access_ras) begin
+    MADDR[11:0]  <= ADDR[22:11]; // Row Address
+  end else begin
+    MADDR[11:10] <= 2'b00;
+    MADDR[9:0]   <= ADDR[10:1];  // Column Address
+  end
+end
+
+endmodule

LIV2_GottaGoFastRAM/Rev_A/LICENSE.md

@@ -0,0 +1,189 @@
+CERN Open Hardware Licence v1.2 
+
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LIV2_GottaGoFastRAM/Rev_A/README.md

@@ -0,0 +1,48 @@
+# GottaGoFastRAM 8MB Autoconfig Fast RAM
+
+This is an 8MB Autoconfig Fast RAM for Amiga 500/1000/2000/CDTV based on mkl's mem68k  
+It's small size allows it to be stacked on top of an ide68k board  
+Rather than use the original mem68k Abel code I have written a new memory controller in Verilog
+
+Unfortunately the memory modules are hard to find, I was able to get some by scouring eBay for some 16/32MB simms and looking for ones pictured with the right ram modules - If you see a 16/32MB simm with 2/4 50-pin TSSOP modules then they're probably the right ones
+
+![PCB](Images/pcb.png?raw=True)
+
+## PCB Ordering
+I recommend ordering the PCB with a 0.6 or 0.8mm thickness if you intend on stacking with an ide68k or mouting using a DIP socket/machined pin strips.  
+If you are going to mount using the socket pins and not stacking with an ide68k I'd recommend going with the usual 1.6mm to reduce flexing.
+
+## Mounting options
+
+1. Can be soldered to the bottom of a machined pin socket/machined pin strips (will require some cutting of the dip socket to fit the caps/ferrites near the plastic)
+2. Can be soldered to socket pins and stacked with an ide68k
+
+## Cfgin/out
+These pins allow you to insert the memory module into your autoconfig chain.  
+If there are no other autoconfig devices in your system you can just leave these unconnected otherwise you will need to either connect CFGOut to the CFGin of the first device in your existing autoconfig chain, or connect CFGIn to the CFGOut pin of the last device in your existing autoconfig chain.  
+You can also connect cfgin and cfgout with a jumper to disable the device temporarily
+
+## Jumpers
+J1: Cfgin pull up/down (You will probably want to leave this at default unless you know what you're doing)
+J2-3: Bridge these if you have not fitted the buffer U4
+
+## CDTV
+The CDTV's DMAC takes up the first autoconfig slot, so if you intend to use this with a CDTV use the CDTV specific .JED file to program the CPLD
+
+## Timing Diagrams
+![Read Cycle](Images/read.svg?raw=True)  
+![Write Cycle](Images/write.svg?raw=True)
+
+### Bill of materials
+|Component|Location|QTY|Link|Remarks|
+|---------|--------|---|------|--------|
+|4Mx16 5V DRAM - KM416C4100|U3|1|-|Look for 16MB SIMMs on eBay which show only 2 tssop package RAMs|
+|XC9572XL-10VQ64C|U1|1|[Mouser](https://www.mouser.se/ProductDetail/217-C9572XL-10VQG64C)||
+|74LVC2G17|U4|1|[Mouser](https://www.mouser.com/ProductDetail/771-74LVC2G17GVQ100H)||
+|AP2210N-3.3|U5|1|[Mouser](https://www.mouser.com/ProductDetail/621-AP2210N-3.3TRG1)||
+|Ferrite Bead, 1206 package|FB1, FB2|2|[Mouser](https://www.mouser.com/ProductDetail/875-MI1206K601R-10)||
+|0.1uF Ceramic Capacitor, 0603|C1,4-11|9|[Mouser](https://www.mouser.com/ProductDetail/80-C603C104K5RAC3121)||
+|4.7uF Ceramic Capacitor, 1206|C2,C12|2|[Mouser](https://www.mouser.com/ProductDetail/791-1206X475K160CT)||
+|10uF Ceramic Capacitor, 1206|C3|1|[Mouser](https://www.mouser.com/ProductDetail/80-C1206C106K4R)||
+|Socket pins|Pins|64|[Aliexpress](https://www.aliexpress.com/item/32791545218.html?spm=a2g0o.productlist.0.0.6e223b55CVrXSq&algo_pvid=8fda9f5a-6e07-4dc8-9ed4-bd809bf75756&algo_expid=8fda9f5a-6e07-4dc8-9ed4-bd809bf75756-0&btsid=2100bde316043149660504011ef819&ws_ab_test=searchweb0_0,searchweb201602_,searchweb201603_)|Use these if stacking with an ide68k module|
+|64-Pin DIP socket - machined pin|Pins|1|[Mouser](https://www.mouser.com/ProductDetail/575-193964)|If not stacking with ide68k - pcb can be soldered to bottom of this flush with the plastic|