Add Repo: JulianKemmerer_PipelineC-Graphics (part 3)

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_5d63f80d.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.11576640182364978]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_5d63f80d is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_5d63f80d;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_5d63f80d is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_6069a755.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.5562525118778798]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_6069a755 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_6069a755;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_6069a755 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_6311c908.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.5678295901123974]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_6311c908 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_6311c908;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_6311c908 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_6714f46f.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.6810226061500695]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_6714f46f is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_6714f46f;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_6714f46f is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_7a9d37b4.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.9182325763810695]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_7a9d37b4 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_7a9d37b4;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_7a9d37b4 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_90050f10.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.1152079015212119]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_90050f10 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_90050f10;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_90050f10 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_99330d44.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.2348636325861179]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_99330d44 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_99330d44;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_99330d44 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_9dd07569.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.15168850763451094]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_9dd07569 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_9dd07569;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_9dd07569 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_a1537cdf.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.26444763121346143]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_a1537cdf is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_a1537cdf;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_a1537cdf is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_b301c8f8.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.913779941137985]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_b301c8f8 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_b301c8f8;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_b301c8f8 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_bc6abea1.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.6265334308652049]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_bc6abea1 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_bc6abea1;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_bc6abea1 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_d539089d.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.5735088492977638]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_d539089d is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_d539089d;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_d539089d is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_de1df097.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.05038321464128472]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_de1df097 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_de1df097;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_de1df097 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_f964e092.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.0870864205394118]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_f964e092 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_f964e092;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_f964e092 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_fbfd5db3.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.8434226410733904]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_fbfd5db3 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_fbfd5db3;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_fbfd5db3 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint1_t_uint1_t_1CLK_feab4394.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.48734493891662395]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint1_t_uint1_t_1CLK_feab4394 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(0 downto 0);
+ iffalse : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end MUX_uint1_t_uint1_t_uint1_t_1CLK_feab4394;
+architecture arch of MUX_uint1_t_uint1_t_uint1_t_1CLK_feab4394 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(0 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(0 downto 0);
+  iffalse : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint21_t_uint21_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint21_t_uint21_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(20 downto 0);
+ iffalse : in unsigned(20 downto 0);
+ return_output : out unsigned(20 downto 0));
+end MUX_uint1_t_uint21_t_uint21_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint21_t_uint21_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(20 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(20 downto 0);
+  iffalse : unsigned(20 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint22_t_uint22_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint22_t_uint22_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(21 downto 0);
+ iffalse : in unsigned(21 downto 0);
+ return_output : out unsigned(21 downto 0));
+end MUX_uint1_t_uint22_t_uint22_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint22_t_uint22_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(21 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(21 downto 0);
+  iffalse : unsigned(21 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint23_t_uint23_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint23_t_uint23_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(22 downto 0);
+ iffalse : in unsigned(22 downto 0);
+ return_output : out unsigned(22 downto 0));
+end MUX_uint1_t_uint23_t_uint23_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint23_t_uint23_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(22 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(22 downto 0);
+  iffalse : unsigned(22 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint2_t_uint2_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint2_t_uint2_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(1 downto 0);
+ iffalse : in unsigned(1 downto 0);
+ return_output : out unsigned(1 downto 0));
+end MUX_uint1_t_uint2_t_uint2_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint2_t_uint2_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(1 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(1 downto 0);
+  iffalse : unsigned(1 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint32_t_uint32_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint32_t_uint32_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(31 downto 0);
+ iffalse : in unsigned(31 downto 0);
+ return_output : out unsigned(31 downto 0));
+end MUX_uint1_t_uint32_t_uint32_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint32_t_uint32_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(31 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(31 downto 0);
+  iffalse : unsigned(31 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint36_t_uint36_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint36_t_uint36_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(35 downto 0);
+ iffalse : in unsigned(35 downto 0);
+ return_output : out unsigned(35 downto 0));
+end MUX_uint1_t_uint36_t_uint36_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint36_t_uint36_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(35 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(35 downto 0);
+  iffalse : unsigned(35 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint3_t_uint3_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint3_t_uint3_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(2 downto 0);
+ iffalse : in unsigned(2 downto 0);
+ return_output : out unsigned(2 downto 0));
+end MUX_uint1_t_uint3_t_uint3_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint3_t_uint3_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(2 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(2 downto 0);
+  iffalse : unsigned(2 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint4_t_uint4_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint4_t_uint4_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(3 downto 0);
+ iffalse : in unsigned(3 downto 0);
+ return_output : out unsigned(3 downto 0));
+end MUX_uint1_t_uint4_t_uint4_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint4_t_uint4_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(3 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(3 downto 0);
+  iffalse : unsigned(3 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint5_t_uint5_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint5_t_uint5_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(4 downto 0);
+ iffalse : in unsigned(4 downto 0);
+ return_output : out unsigned(4 downto 0));
+end MUX_uint1_t_uint5_t_uint5_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint5_t_uint5_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(4 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(4 downto 0);
+  iffalse : unsigned(4 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_0CLK_de264c78.vhd

@@ -0,0 +1,94 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_0CLK_de264c78 is
+port(
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_0CLK_de264c78;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_0048e4e7.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.06468329695495262]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_0048e4e7 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_0048e4e7;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_0048e4e7 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_0865ab4c.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.6272647041159]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_0865ab4c is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_0865ab4c;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_0865ab4c is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_16883554.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.9899393287764648]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_16883554 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_16883554;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_16883554 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_1b6c3041.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.27769258299894467]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_1b6c3041 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_1b6c3041;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_1b6c3041 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_27b2954a.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.7067499178175534]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_27b2954a is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_27b2954a;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_27b2954a is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_2f798d40.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.21917685941228532]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_2f798d40 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_2f798d40;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_2f798d40 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_46e601b3.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.6487348736303374]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_46e601b3 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_46e601b3;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_46e601b3 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_5a5c4ba6.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.9812577506097568]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_5a5c4ba6 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_5a5c4ba6;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_5a5c4ba6 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_60a0f81c.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.8744222795891725]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_60a0f81c is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_60a0f81c;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_60a0f81c is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_632d7826.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.08357877746286822]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_632d7826 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_632d7826;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_632d7826 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_95a2cf47.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.30922642183112053]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_95a2cf47 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_95a2cf47;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_95a2cf47 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_97dd14d7.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.05979962904785528]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_97dd14d7 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_97dd14d7;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_97dd14d7 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_9bab4883.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.6264664838418639]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_9bab4883 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_9bab4883;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_9bab4883 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_a9a2737d.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.7476129023434017]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_a9a2737d is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_a9a2737d;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_a9a2737d is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_c45bae38.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.726845996601681]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_c45bae38 is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_c45bae38;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_c45bae38 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_dd78bbdc.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.4289326583992761]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_dd78bbdc is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_dd78bbdc;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_dd78bbdc is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_f7fa3caf.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.3757685994908663]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_f7fa3caf is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_f7fa3caf;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_f7fa3caf is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/MUX_uint1_t_uint8_t_uint8_t_1CLK_fc57febd.vhd

@@ -0,0 +1,132 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.16124828203108071]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity MUX_uint1_t_uint8_t_uint8_t_1CLK_fc57febd is
+port(
+ clk : in std_logic;
+ cond : in unsigned(0 downto 0);
+ iftrue : in unsigned(7 downto 0);
+ iffalse : in unsigned(7 downto 0);
+ return_output : out unsigned(7 downto 0));
+end MUX_uint1_t_uint8_t_uint8_t_1CLK_fc57febd;
+architecture arch of MUX_uint1_t_uint8_t_uint8_t_1CLK_fc57febd is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+  
+  return_output : unsigned(7 downto 0);
+  cond : unsigned(0 downto 0);
+  iftrue : unsigned(7 downto 0);
+  iffalse : unsigned(7 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ cond,
+ iftrue,
+ iffalse,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.cond := cond;
+   read_pipe.iftrue := iftrue;
+   read_pipe.iffalse := iffalse;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Assign output based on range for this stage
+      if write_pipe.cond=1 then
+        write_pipe.return_output := write_pipe.iftrue;
+      else
+        write_pipe.return_output := write_pipe.iffalse;
+      end if;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78.vhd

@@ -0,0 +1,84 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78 is
+port(
+ expr : in std_logic_vector(22 downto 0);
+ return_output : out std_logic_vector(22 downto 0));
+end UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78;
+architecture arch of UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+
+  return_output : std_logic_vector(22 downto 0);
+  expr : std_logic_vector(22 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.expr := expr;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      -- Same value
+      write_pipe.return_output := write_pipe.expr; 
+      -- With left most sign bit inverted
+      write_pipe.return_output(write_pipe.return_output'left) := not write_pipe.expr(write_pipe.expr'left);
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NEGATE_float_8_14_t_1CLK_2e182bc4.vhd

@@ -0,0 +1,122 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: [0.43327790074151423]
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity UNARY_OP_NEGATE_float_8_14_t_1CLK_2e182bc4 is
+port(
+ clk : in std_logic;
+ expr : in std_logic_vector(22 downto 0);
+ return_output : out std_logic_vector(22 downto 0));
+end UNARY_OP_NEGATE_float_8_14_t_1CLK_2e182bc4;
+architecture arch of UNARY_OP_NEGATE_float_8_14_t_1CLK_2e182bc4 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 1;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+
+  return_output : std_logic_vector(22 downto 0);
+  expr : std_logic_vector(22 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+   
+  -- Type holding all manually (not auto generated in pipelining) registers for this function
+  --  RAW HDL pipeline, user state regs
+  type manual_registers_t is record
+    raw_hdl_pipeline : raw_hdl_register_pipeline_t; 
+  end record;
+  
+-- Function to null out manual regs 
+function manual_registers_NULL return manual_registers_t is
+ variable rv : manual_registers_t;
+  begin
+
+  return rv;
+end function;
+
+-- Manual (not auto pipeline) registers and signals for this function
+signal manual_registers : manual_registers_t;
+signal manual_registers_r : manual_registers_t := manual_registers_NULL;
+
+
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr,
+ -- Registers
+ manual_registers_r)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Raw hdl REGS
+ -- Default read raw hdl regs once per clock
+ read_raw_hdl_pipeline_regs := manual_registers_r.raw_hdl_pipeline;
+ -- Default write contents of raw hdl regs
+ write_raw_hdl_pipeline_regs := read_raw_hdl_pipeline_regs;
+  
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.expr := expr;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 1 then
+      -- Same value
+      write_pipe.return_output := write_pipe.expr; 
+      -- With left most sign bit inverted
+      write_pipe.return_output(write_pipe.return_output'left) := not write_pipe.expr(write_pipe.expr'left);
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ manual_registers.raw_hdl_pipeline <= write_raw_hdl_pipeline_regs;
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+-- Register comb signals
+process(clk) is
+begin
+ if rising_edge(clk) then
+
+     manual_registers_r <= manual_registers;
+ end if;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NEGATE_int16_t_0CLK_23f04728.vhd

@@ -0,0 +1,117 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 2
+entity UNARY_OP_NEGATE_int16_t_0CLK_23f04728 is
+port(
+ expr : in signed(15 downto 0);
+ return_output : out signed(16 downto 0));
+end UNARY_OP_NEGATE_int16_t_0CLK_23f04728;
+architecture arch of UNARY_OP_NEGATE_int16_t_0CLK_23f04728 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+-- All of the wires/regs in function
+-- Each function instance gets signals
+-- UNARY_OP_NOT[UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea]
+signal UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr : unsigned(16 downto 0);
+signal UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output : unsigned(16 downto 0);
+
+-- BIN_OP_PLUS[UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8]
+signal BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left : unsigned(16 downto 0);
+signal BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right : unsigned(0 downto 0);
+signal BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output : unsigned(17 downto 0);
+
+
+begin
+
+-- SUBMODULE INSTANCES 
+-- UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea
+UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea : entity work.UNARY_OP_NOT_uint17_t_0CLK_de264c78 port map (
+UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr,
+UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output);
+
+-- BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8
+BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8 : entity work.BIN_OP_PLUS_uint17_t_uint1_t_0CLK_de264c78 port map (
+BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left,
+BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right,
+BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output);
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr,
+ -- All submodule outputs
+ UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output,
+ BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output)
+is 
+ -- All of the wires in function
+ variable VAR_CLOCK_ENABLE : unsigned(0 downto 0);
+ variable VAR_expr : signed(15 downto 0);
+ variable VAR_return_output : signed(16 downto 0);
+ variable VAR_x_wide : unsigned(16 downto 0);
+ variable VAR_x_wide_UNARY_OP_NEGATE_int16_t_c_l10_c3_f061 : unsigned(16 downto 0);
+ variable VAR_x_wide_neg : unsigned(16 downto 0);
+ variable VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr : unsigned(16 downto 0);
+ variable VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output : unsigned(16 downto 0);
+ variable VAR_x_neg_wide_plus1 : unsigned(16 downto 0);
+ variable VAR_x_neg_wide_plus1_UNARY_OP_NEGATE_int16_t_c_l16_c3_dac4 : unsigned(16 downto 0);
+ variable VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left : unsigned(16 downto 0);
+ variable VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right : unsigned(0 downto 0);
+ variable VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output : unsigned(17 downto 0);
+ variable VAR_rv : signed(16 downto 0);
+ variable VAR_rv_UNARY_OP_NEGATE_int16_t_c_l19_c3_3714 : signed(16 downto 0);
+begin
+ -- Constants and things derived from constants alone
+     -- Submodule level 0
+     VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right := to_unsigned(1, 1);
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+   if STAGE = 0 then
+     -- Mux in inputs
+     VAR_expr := expr;
+
+     -- Submodule level 0
+     VAR_x_wide_UNARY_OP_NEGATE_int16_t_c_l10_c3_f061 := unsigned(std_logic_vector(resize(VAR_expr,17)));
+     VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr := VAR_x_wide_UNARY_OP_NEGATE_int16_t_c_l10_c3_f061;
+     -- UNARY_OP_NOT[UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea] LATENCY=0
+     -- Inputs
+     UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr <= VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_expr;
+     -- Outputs
+     VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output := UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output;
+
+     -- Submodule level 1
+     VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left := VAR_UNARY_OP_NOT_UNARY_OP_NEGATE_int16_t_c_l13_c17_63ea_return_output;
+     -- BIN_OP_PLUS[UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8] LATENCY=0
+     -- Inputs
+     BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left <= VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_left;
+     BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right <= VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_right;
+     -- Outputs
+     VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output := BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output;
+
+     -- Submodule level 2
+     VAR_x_neg_wide_plus1_UNARY_OP_NEGATE_int16_t_c_l16_c3_dac4 := resize(VAR_BIN_OP_PLUS_UNARY_OP_NEGATE_int16_t_c_l16_c22_b5b8_return_output, 17);
+     VAR_rv_UNARY_OP_NEGATE_int16_t_c_l19_c3_3714 := signed(std_logic_vector(resize(VAR_x_neg_wide_plus1_UNARY_OP_NEGATE_int16_t_c_l16_c3_dac4, 17)));
+     VAR_return_output := VAR_rv_UNARY_OP_NEGATE_int16_t_c_l19_c3_3714;
+     -- Last stage of pipeline return wire to return port/reg
+     return_output <= VAR_return_output;
+   end if;
+ end loop;
+
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NOT_uint16_t_0CLK_de264c78.vhd

@@ -0,0 +1,83 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity UNARY_OP_NOT_uint16_t_0CLK_de264c78 is
+port(
+ expr : in unsigned(15 downto 0);
+ return_output : out unsigned(15 downto 0));
+end UNARY_OP_NOT_uint16_t_0CLK_de264c78;
+architecture arch of UNARY_OP_NOT_uint16_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+
+  expr_resized : unsigned(15 downto 0);
+  return_output : unsigned(15 downto 0);
+  expr : unsigned(15 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.expr := expr;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      write_pipe.expr_resized := resize(write_pipe.expr, 16);
+      write_pipe.return_output := not write_pipe.expr_resized;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NOT_uint17_t_0CLK_de264c78.vhd

@@ -0,0 +1,83 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity UNARY_OP_NOT_uint17_t_0CLK_de264c78 is
+port(
+ expr : in unsigned(16 downto 0);
+ return_output : out unsigned(16 downto 0));
+end UNARY_OP_NOT_uint17_t_0CLK_de264c78;
+architecture arch of UNARY_OP_NOT_uint17_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+
+  expr_resized : unsigned(16 downto 0);
+  return_output : unsigned(16 downto 0);
+  expr : unsigned(16 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.expr := expr;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      write_pipe.expr_resized := resize(write_pipe.expr, 17);
+      write_pipe.return_output := not write_pipe.expr_resized;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;

JulianKemmerer_PipelineC-Graphics/vhd/all_vhdl_files/UNARY_OP_NOT_uint1_t_0CLK_de264c78.vhd

@@ -0,0 +1,83 @@
+-- Timing params:
+--   Fixed?: False
+--   Pipeline Slices: []
+--   Input regs?: False
+--   Output regs?: False
+library std;
+use std.textio.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+use work.c_structs_pkg.all;
+-- Submodules: 0
+entity UNARY_OP_NOT_uint1_t_0CLK_de264c78 is
+port(
+ expr : in unsigned(0 downto 0);
+ return_output : out unsigned(0 downto 0));
+end UNARY_OP_NOT_uint1_t_0CLK_de264c78;
+architecture arch of UNARY_OP_NOT_uint1_t_0CLK_de264c78 is
+-- Types and such
+-- Declarations
+attribute mark_debug : string;
+constant PIPELINE_LATENCY : integer := 0;
+
+-- One struct to represent this modules variables
+type raw_hdl_variables_t is record
+ -- All of the wires in function
+
+  expr_resized : unsigned(0 downto 0);
+  return_output : unsigned(0 downto 0);
+  expr : unsigned(0 downto 0);
+end record;
+
+-- Type for this modules register pipeline
+type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t;
+  
+begin
+
+
+
+-- Combinatorial process for pipeline stages
+process (
+ -- Inputs
+ expr)
+is 
+ -- Read and write variables to do register transfers per clock
+ -- from the previous to next stage
+ variable read_pipe : raw_hdl_variables_t;
+ variable write_pipe : raw_hdl_variables_t;
+
+ -- This modules self pipeline registers read once per clock
+ variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+ variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t;
+  begin
+
+ -- Loop to construct simultaneous register transfers for each of the pipeline stages
+ -- LATENCY=0 is combinational Logic
+ for STAGE in 0 to PIPELINE_LATENCY loop
+  -- Input to first stage are inputs to function
+  if STAGE=0 then
+   -- Mux in inputs
+   read_pipe.expr := expr;
+  else
+   -- Default read from previous stage
+   read_pipe := read_raw_hdl_pipeline_regs(STAGE-1);
+  end if;
+  -- Default write contents of previous stage
+  write_pipe := read_pipe;
+
+
+    if STAGE = 0 then
+      write_pipe.expr_resized := resize(write_pipe.expr, 1);
+      write_pipe.return_output := not write_pipe.expr_resized;
+    end if;     
+    -- Write to stage reg
+  write_raw_hdl_pipeline_regs(STAGE) := write_pipe;
+ end loop;
+
+ -- Last stage of pipeline return wire to return port/reg
+ return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output;
+end process;
+
+end arch;